RE: [PATCH v6 7/7] irqchip: s3c24xx: add devicetree support
Rob Herring wrote: > > On 03/26/2013 05:10 PM, Heiko Stübner wrote: > > Add the necessary code to initialize the interrupt controller > > thru devicetree data using the irqchip infrastructure. > > > > Signed-off-by: Heiko Stuebner > > Acked-by: Rob Herring > Rob, thanks for your ack. Applied with your ack. - Kukjin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 7/7] irqchip: s3c24xx: add devicetree support
On 03/26/2013 05:10 PM, Heiko Stübner wrote:
> Add the necessary code to initialize the interrupt controller
> thru devicetree data using the irqchip infrastructure.
>
> Signed-off-by: Heiko Stuebner
Acked-by: Rob Herring
> ---
> .../interrupt-controller/samsung,s3c24xx-irq.txt | 53 +
> drivers/irqchip/irq-s3c24xx.c | 231
> +++-
> 2 files changed, 278 insertions(+), 6 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
>
> diff --git
> a/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
>
> b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
> new file mode 100644
> index 000..c54c5a9
> --- /dev/null
> +++
> b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
> @@ -0,0 +1,53 @@
> +Samsung S3C24XX Interrupt Controllers
> +
> +The S3C24XX SoCs contain a custom set of interrupt controllers providing a
> +varying number of interrupt sources. The set consists of a main- and sub-
> +controller and on newer SoCs even a second main controller.
> +
> +Required properties:
> +- compatible: Compatible property value should be "samsung,s3c2410-irq"
> + for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and
> later.
> +
> +- reg: Physical base address of the controller and length of memory mapped
> + region.
> +
> +- interrupt-controller : Identifies the node as an interrupt controller
> +
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> + interrupt source. The value shall be 4 and interrupt descriptor shall
> + have the following format:
> +
> +
> + ctrl_num contains the controller to use:
> + - 0 ... main controller
> + - 1 ... sub controller
> + - 2 ... second main controller on s3c2416 and s3c2450
> + parent_irq contains the parent bit in the main controller and will be
> + ignored in main controllers
> + ctrl_irq contains the interrupt bit of the controller
> + type contains the trigger type to use
> +
> +Example:
> +
> + interrupt-controller@4a00 {
> + compatible = "samsung,s3c2410-irq";
> + reg = <0x4a00 0x100>;
> + interrupt-controller;
> + #interrupt-cells=<4>;
> + };
> +
> + [...]
> +
> + serial@5000 {
> + compatible = "samsung,s3c2410-uart";
> + reg = <0x5000 0x4000>;
> + interrupt-parent = <&subintc>;
> + interrupts = <1 28 0 4>, <1 28 1 4>;
> + };
> +
> + rtc@5700 {
> + compatible = "samsung,s3c2410-rtc";
> + reg = <0x5700 0x100>;
> + interrupt-parent = <&intc>;
> + interrupts = <0 30 0 3>, <0 8 0 3>;
> + };
> diff --git a/drivers/irqchip/irq-s3c24xx.c b/drivers/irqchip/irq-s3c24xx.c
> index 02b82db..5e40b34 100644
> --- a/drivers/irqchip/irq-s3c24xx.c
> +++ b/drivers/irqchip/irq-s3c24xx.c
> @@ -25,6 +25,9 @@
> #include
> #include
> #include
> +#include
> +#include
> +#include
>
> #include
> #include
> @@ -36,6 +39,8 @@
> #include
> #include
>
> +#include "irqchip.h"
> +
> #define S3C_IRQTYPE_NONE 0
> #define S3C_IRQTYPE_EINT 1
> #define S3C_IRQTYPE_EDGE 2
> @@ -94,7 +99,10 @@ static void s3c_irq_mask(struct irq_data *data)
> if (parent_intc) {
> parent_data = &parent_intc->irqs[irq_data->parent_irq];
>
> - /* check to see if we need to mask the parent IRQ */
> + /* check to see if we need to mask the parent IRQ
> + * The parent_irq is always in main_intc, so the hwirq
> + * for find_mapping does not need an offset in any case.
> + */
> if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
> irqno = irq_find_mapping(parent_intc->domain,
>irq_data->parent_irq);
> @@ -294,10 +302,18 @@ static void s3c_irq_demux(unsigned int irq, struct
> irq_desc *desc)
> {
> struct irq_chip *chip = irq_desc_get_chip(desc);
> struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
> + struct s3c_irq_intc *intc = irq_data->intc;
> struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
> unsigned long src;
> unsigned long msk;
> unsigned int n;
> + unsigned int offset;
> +
> + /* we're using individual domains for the non-dt case
> + * and one big domain for the dt case where the subintc
> + * starts at hwirq number 32.
> + */
> + offset = (intc->domain->of_node) ? 32 : 0;
>
> chained_irq_enter(chip, desc);
>
> @@ -310,14 +326,15 @@ static void s3c_irq_demux(unsigned int irq, struct
> irq_desc *desc)
> while (src) {
> n = __ffs(src);
> src &= ~(1 << n);
> - generic_handle_irq(irq_find_mapping(sub_intc->domain, n
[PATCH v6 7/7] irqchip: s3c24xx: add devicetree support
Add the necessary code to initialize the interrupt controller
thru devicetree data using the irqchip infrastructure.
Signed-off-by: Heiko Stuebner
---
.../interrupt-controller/samsung,s3c24xx-irq.txt | 53 +
drivers/irqchip/irq-s3c24xx.c | 231 +++-
2 files changed, 278 insertions(+), 6 deletions(-)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
new file mode 100644
index 000..c54c5a9
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
@@ -0,0 +1,53 @@
+Samsung S3C24XX Interrupt Controllers
+
+The S3C24XX SoCs contain a custom set of interrupt controllers providing a
+varying number of interrupt sources. The set consists of a main- and sub-
+controller and on newer SoCs even a second main controller.
+
+Required properties:
+- compatible: Compatible property value should be "samsung,s3c2410-irq"
+ for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.
+
+- reg: Physical base address of the controller and length of memory mapped
+ region.
+
+- interrupt-controller : Identifies the node as an interrupt controller
+
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 4 and interrupt descriptor shall
+ have the following format:
+
+
+ ctrl_num contains the controller to use:
+ - 0 ... main controller
+ - 1 ... sub controller
+ - 2 ... second main controller on s3c2416 and s3c2450
+ parent_irq contains the parent bit in the main controller and will be
+ ignored in main controllers
+ ctrl_irq contains the interrupt bit of the controller
+ type contains the trigger type to use
+
+Example:
+
+ interrupt-controller@4a00 {
+ compatible = "samsung,s3c2410-irq";
+ reg = <0x4a00 0x100>;
+ interrupt-controller;
+ #interrupt-cells=<4>;
+ };
+
+ [...]
+
+ serial@5000 {
+ compatible = "samsung,s3c2410-uart";
+ reg = <0x5000 0x4000>;
+ interrupt-parent = <&subintc>;
+ interrupts = <1 28 0 4>, <1 28 1 4>;
+ };
+
+ rtc@5700 {
+ compatible = "samsung,s3c2410-rtc";
+ reg = <0x5700 0x100>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 30 0 3>, <0 8 0 3>;
+ };
diff --git a/drivers/irqchip/irq-s3c24xx.c b/drivers/irqchip/irq-s3c24xx.c
index 02b82db..5e40b34 100644
--- a/drivers/irqchip/irq-s3c24xx.c
+++ b/drivers/irqchip/irq-s3c24xx.c
@@ -25,6 +25,9 @@
#include
#include
#include
+#include
+#include
+#include
#include
#include
@@ -36,6 +39,8 @@
#include
#include
+#include "irqchip.h"
+
#define S3C_IRQTYPE_NONE 0
#define S3C_IRQTYPE_EINT 1
#define S3C_IRQTYPE_EDGE 2
@@ -94,7 +99,10 @@ static void s3c_irq_mask(struct irq_data *data)
if (parent_intc) {
parent_data = &parent_intc->irqs[irq_data->parent_irq];
- /* check to see if we need to mask the parent IRQ */
+ /* check to see if we need to mask the parent IRQ
+* The parent_irq is always in main_intc, so the hwirq
+* for find_mapping does not need an offset in any case.
+*/
if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
irqno = irq_find_mapping(parent_intc->domain,
irq_data->parent_irq);
@@ -294,10 +302,18 @@ static void s3c_irq_demux(unsigned int irq, struct
irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
+ struct s3c_irq_intc *intc = irq_data->intc;
struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
unsigned long src;
unsigned long msk;
unsigned int n;
+ unsigned int offset;
+
+ /* we're using individual domains for the non-dt case
+* and one big domain for the dt case where the subintc
+* starts at hwirq number 32.
+*/
+ offset = (intc->domain->of_node) ? 32 : 0;
chained_irq_enter(chip, desc);
@@ -310,14 +326,15 @@ static void s3c_irq_demux(unsigned int irq, struct
irq_desc *desc)
while (src) {
n = __ffs(src);
src &= ~(1 << n);
- generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
+ irq = irq_find_mapping(sub_intc->domain, offset + n);
+ generic_handle_irq(irq);
}
chained_irq_exit(chip, desc);
}
static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
-
