Re: [PATCH] clk: samsung: exynos7: Add required clock tree for UFS
Hello,
On Sat, Aug 29, 2015 at 2:23 PM, Krzysztof Kozlowski
wrote:
> 2015-08-28 18:28 GMT+09:00 Alim Akhtar :
>> Adding required mux/div/gate clocks for UFS controller
>> present on Exynos7.
>>
>> Signed-off-by: Alim Akhtar
>> ---
>> This patch has a dependency on [1]
>> [1]->
>> https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg46122.html
>>
>> drivers/clk/samsung/clk-exynos7.c | 117
>> +++
>> include/dt-bindings/clock/exynos7-clk.h | 34 +++--
>> 2 files changed, 146 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos7.c
>> b/drivers/clk/samsung/clk-exynos7.c
>> index 380608b..069af8c 100644
>> --- a/drivers/clk/samsung/clk-exynos7.c
>> +++ b/drivers/clk/samsung/clk-exynos7.c
>> @@ -35,6 +35,7 @@
>> #define DIV_TOPC1 0x0604
>> #define DIV_TOPC3 0x060C
>> #define ENABLE_ACLK_TOPC1 0x0804
>> +#define ENABLE_SCLK_TOPC1 0x0A04
>>
>> static struct samsung_fixed_factor_clock topc_fixed_factor_clks[]
>> __initdata = {
>> FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
>> @@ -143,6 +144,15 @@ static struct samsung_pll_rate_table
>> pll1460x_24mhz_tbl[] __initdata = {
>> static struct samsung_gate_clock topc_gate_clks[] __initdata = {
>> GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
>> ENABLE_ACLK_TOPC1, 20, 0, 0),
>> +
>> + GATE(SCLK_MFC_PLL_B, "dout_sclk_mfc_pll_b", "dout_sclk_mfc_pll",
>> + ENABLE_SCLK_TOPC1, 17, 0, 0),
>> + GATE(SCLK_MFC_PLL_A, "dout_sclk_mfc_pll_a", "dout_sclk_mfc_pll",
>> + ENABLE_SCLK_TOPC1, 16, 0, 0),
>> + GATE(SCLK_BUS1_PLL_B, "dout_sclk_bus1_pll_b", "dout_sclk_bus1_pll",
>> + ENABLE_SCLK_TOPC1, 13, 0, 0),
>> + GATE(SCLK_BUS1_PLL_B, "dout_sclk_bus1_pll_a", "dout_sclk_bus1_pll",
>> + ENABLE_SCLK_TOPC1, 12, 0, 0),
>
> 1. s/SCLK_BUS1_PLL_B/SCLK_BUS1_PLL_A/?
> 2. Why have they name prefixed with "dout"? These are gates, not dividers.
>
well right, went again over the whole clock file and looks like there
are other GATE clocks will starts with _dout_ prefix,
let me send another sets of patches will clean/rename these clock to
match the user manual, so that it will be easy for review.
Thanks for pointing it out.
>> };
>>
>> static struct samsung_pll_clock topc_pll_clks[] __initdata = {
>> @@ -433,12 +443,21 @@ static struct samsung_mux_clock top1_mux_clks[]
>> __initdata = {
>> MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24,
>> 2),
>> MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28,
>> 2),
>>
>> + MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1,
>> + MUX_SEL_TOP1_FSYS0, 0, 2),
>> MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16,
>> 2),
>> MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
>> MUX_SEL_TOP1_FSYS0, 28, 2),
>>
>> + MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1,
>> + MUX_SEL_TOP1_FSYS1, 0, 2),
>> + MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1,
>> + MUX_SEL_TOP1_FSYS1, 16, 2),
>> +
>> MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0,
>> 2),
>> MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12,
>> 2),
>> + MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1,
>> + MUX_SEL_TOP1_FSYS11, 24, 2),
>> };
>>
>> static struct samsung_div_clock top1_div_clks[] __initdata = {
>> @@ -447,6 +466,13 @@ static struct samsung_div_clock top1_div_clks[]
>> __initdata = {
>> DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200",
>> "mout_aclk_fsys0_200",
>> DIV_TOP13, 28, 4),
>>
>> + DIV(DOUT_SCLK_PHY_FSYS1, "dout_sclk_phy_fsys1",
>> + "mout_sclk_phy_fsys1", DIV_TOP1_FSYS1, 0, 6),
>> +
>> + DIV(DOUT_SCLK_UFSUNIPRO20, "dout_sclk_ufsunipro20",
>> + "mout_sclk_ufsunipro20",
>> + DIV_TOP1_FSYS1, 16, 6),
>> +
>> DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
>> DIV_TOP1_FSYS0, 16, 10),
>> DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
>> @@ -456,6 +482,9 @@ static struct samsung_div_clock top1_div_clks[]
>> __initdata = {
>> DIV_TOP1_FSYS11, 0, 10),
>> DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
>> DIV_TOP1_FSYS11, 12, 10),
>> +
>> + DIV(DOUT_SCLK_PHY_FSYS1_26M, "dout_sclk_phy_fsys1_26m",
>> + "mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6),
>> };
>>
>> static struct samsung_gate_clock top1_gate_clks[] __initdata = {
>> @@ -464,10 +493,20 @@ static struct samsung_gate_clock top1_gate_clks[]
>> __initdata = {
>> GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
>> ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
>>
>> + GATE(CLK_SCLK_PHY_FSYS1, "sclk_phy_fsys1", "dout_sclk_phy_fsy
Re: [PATCH] clk: samsung: exynos7: Add required clock tree for UFS
2015-08-28 18:28 GMT+09:00 Alim Akhtar :
> Adding required mux/div/gate clocks for UFS controller
> present on Exynos7.
>
> Signed-off-by: Alim Akhtar
> ---
> This patch has a dependency on [1]
> [1]->
> https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg46122.html
>
> drivers/clk/samsung/clk-exynos7.c | 117
> +++
> include/dt-bindings/clock/exynos7-clk.h | 34 +++--
> 2 files changed, 146 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos7.c
> b/drivers/clk/samsung/clk-exynos7.c
> index 380608b..069af8c 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -35,6 +35,7 @@
> #define DIV_TOPC1 0x0604
> #define DIV_TOPC3 0x060C
> #define ENABLE_ACLK_TOPC1 0x0804
> +#define ENABLE_SCLK_TOPC1 0x0A04
>
> static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata
> = {
> FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
> @@ -143,6 +144,15 @@ static struct samsung_pll_rate_table
> pll1460x_24mhz_tbl[] __initdata = {
> static struct samsung_gate_clock topc_gate_clks[] __initdata = {
> GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
> ENABLE_ACLK_TOPC1, 20, 0, 0),
> +
> + GATE(SCLK_MFC_PLL_B, "dout_sclk_mfc_pll_b", "dout_sclk_mfc_pll",
> + ENABLE_SCLK_TOPC1, 17, 0, 0),
> + GATE(SCLK_MFC_PLL_A, "dout_sclk_mfc_pll_a", "dout_sclk_mfc_pll",
> + ENABLE_SCLK_TOPC1, 16, 0, 0),
> + GATE(SCLK_BUS1_PLL_B, "dout_sclk_bus1_pll_b", "dout_sclk_bus1_pll",
> + ENABLE_SCLK_TOPC1, 13, 0, 0),
> + GATE(SCLK_BUS1_PLL_B, "dout_sclk_bus1_pll_a", "dout_sclk_bus1_pll",
> + ENABLE_SCLK_TOPC1, 12, 0, 0),
1. s/SCLK_BUS1_PLL_B/SCLK_BUS1_PLL_A/?
2. Why have they name prefixed with "dout"? These are gates, not dividers.
> };
>
> static struct samsung_pll_clock topc_pll_clks[] __initdata = {
> @@ -433,12 +443,21 @@ static struct samsung_mux_clock top1_mux_clks[]
> __initdata = {
> MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
> MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
>
> + MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1,
> + MUX_SEL_TOP1_FSYS0, 0, 2),
> MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),
> MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
> MUX_SEL_TOP1_FSYS0, 28, 2),
>
> + MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1,
> + MUX_SEL_TOP1_FSYS1, 0, 2),
> + MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1,
> + MUX_SEL_TOP1_FSYS1, 16, 2),
> +
> MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),
> MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12,
> 2),
> + MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1,
> + MUX_SEL_TOP1_FSYS11, 24, 2),
> };
>
> static struct samsung_div_clock top1_div_clks[] __initdata = {
> @@ -447,6 +466,13 @@ static struct samsung_div_clock top1_div_clks[]
> __initdata = {
> DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
> DIV_TOP13, 28, 4),
>
> + DIV(DOUT_SCLK_PHY_FSYS1, "dout_sclk_phy_fsys1",
> + "mout_sclk_phy_fsys1", DIV_TOP1_FSYS1, 0, 6),
> +
> + DIV(DOUT_SCLK_UFSUNIPRO20, "dout_sclk_ufsunipro20",
> + "mout_sclk_ufsunipro20",
> + DIV_TOP1_FSYS1, 16, 6),
> +
> DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
> DIV_TOP1_FSYS0, 16, 10),
> DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
> @@ -456,6 +482,9 @@ static struct samsung_div_clock top1_div_clks[]
> __initdata = {
> DIV_TOP1_FSYS11, 0, 10),
> DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
> DIV_TOP1_FSYS11, 12, 10),
> +
> + DIV(DOUT_SCLK_PHY_FSYS1_26M, "dout_sclk_phy_fsys1_26m",
> + "mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6),
> };
>
> static struct samsung_gate_clock top1_gate_clks[] __initdata = {
> @@ -464,10 +493,20 @@ static struct samsung_gate_clock top1_gate_clks[]
> __initdata = {
> GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
> ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
>
> + GATE(CLK_SCLK_PHY_FSYS1, "sclk_phy_fsys1", "dout_sclk_phy_fsys1",
> + ENABLE_SCLK_TOP1_FSYS1, 0, CLK_SET_RATE_PARENT, 0),
> +
> + GATE(CLK_SCLK_UFSUNIPRO20, "sclk_ufsunipro20",
> "dout_sclk_ufsunipro20",
> + ENABLE_SCLK_TOP1_FSYS1, 16, CLK_SET_RATE_PARENT, 0),
> +
> GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
> ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
> ENABLE_SCLK_TOP1_FSYS11, 12,
Re: [PATCH] clk: samsung: exynos7: Add required clock tree for UFS
Hi, On 08/28/2015 03:36 PM, Krzysztof Kozlowski wrote: 2015-08-28 18:28 GMT+09:00 Alim Akhtar : Adding required mux/div/gate clocks for UFS controller present on Exynos7. Signed-off-by: Alim Akhtar --- This patch has a dependency on [1] [1]-> https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg46122.html Hi, I just noticed that you did not send this and previous patches to proper mailing list and to all of maintainers. You missed linux-...@vger.kernel.org and Stephen Boyd. Please use script/get_maintainers. It will print all necessary addresses. Thanks for pointing this out, I will add them. Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] clk: samsung: exynos7: Add required clock tree for UFS
2015-08-28 18:28 GMT+09:00 Alim Akhtar : > Adding required mux/div/gate clocks for UFS controller > present on Exynos7. > > Signed-off-by: Alim Akhtar > --- > This patch has a dependency on [1] > [1]-> > https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg46122.html Hi, I just noticed that you did not send this and previous patches to proper mailing list and to all of maintainers. You missed linux-...@vger.kernel.org and Stephen Boyd. Please use script/get_maintainers. It will print all necessary addresses. Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
