Re: [PATCH v3 5/6] irqchip: s3c24xx: add devicetree support

2013-03-18 Thread Rob Herring
On 03/17/2013 08:07 AM, Heiko Stübner wrote:
 Add the necessary code to initialize the interrupt controller
 thru devicetree data using the irqchip infrastructure.
 
 On dt machines the eint-type interrupts in the main interrupt controller
 get mapped as regular edge-types, as their wakeup and interrupt type
 properties will be handled by the upcoming pinctrl driver.
 
 Signed-off-by: Heiko Stuebner he...@sntech.de
 ---
  .../interrupt-controller/samsung,s3c24xx-irq.txt   |   54 +
  drivers/irqchip/irq-s3c24xx.c  |  222 
 
  2 files changed, 276 insertions(+), 0 deletions(-)
  create mode 100644 
 Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
 
 diff --git 
 a/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
  
 b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
 new file mode 100644
 index 000..be5dead
 --- /dev/null
 +++ 
 b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
 @@ -0,0 +1,54 @@
 +Samsung S3C24XX Interrupt Controllers
 +
 +The S3C24XX SoCs contain a custom set of interrupt controllers providing a
 +varying number of interrupt sources. The set consists of a main- and sub-
 +controller and on newer SoCs even a second main controller.
 +
 +Required properties:
 +- compatible: Compatible property value should be one of 
 samsung,s3c2410-irq,
 +  samsung,s3c2412-irq, samsung,s3c2416-irq, samsung,s3c2440-irq,
 +  samsung,s3c2442-irq, samsung,s3c2443-irq depending on the SoC variant.
 +
 +- reg: Physical base address of the controller and length of memory mapped
 +  region.
 +
 +- interrupt-controller : Identifies the node as an interrupt controller
 +
 +Sub-controllers as child nodes:
 +  The interrupt controllers that should be referenced by device nodes are
 +  represented by child nodes. Valid names are intc, subintc and intc2.
 +  The interrupt values in device nodes are then mapped directly to the
 +  bit-numbers of the pending register of the named interrupt controller.
 +
 +Required properties:
 +- interrupt-controller : Identifies the node as an interrupt controller
 +
 +- #interrupt-cells : Specifies the number of cells needed to encode an
 +  interrupt source. The value shall be 2.
 +
 +Example:
 +
 + interrupt-controller@4a00 {
 + compatible = samsung,s3c2416-irq;
 + reg = 0x4a00 0x100;
 + interrupt-controller;
 +
 + intc:intc {
 + interrupt-controller;
 + #interrupt-cells = 2;
 + };
 +
 + subintc:subintc {
 + interrupt-controller;
 + #interrupt-cells = 2;
 + };
 + };
 +
 + [...]
 +
 + serial@5000 {
 + compatible = samsung,s3c2410-uart;
 + reg = 0x5000 0x4000;
 + interrupt-parent = subintc;
 + interrupts = 0 0, 1 0;
 + };
 diff --git a/drivers/irqchip/irq-s3c24xx.c b/drivers/irqchip/irq-s3c24xx.c
 index 1eba289..55cb363 100644
 --- a/drivers/irqchip/irq-s3c24xx.c
 +++ b/drivers/irqchip/irq-s3c24xx.c
 @@ -25,6 +25,9 @@
  #include linux/ioport.h
  #include linux/device.h
  #include linux/irqdomain.h
 +#include linux/of.h
 +#include linux/of_irq.h
 +#include linux/of_address.h
  
  #include asm/exception.h
  #include asm/mach/irq.h
 @@ -36,6 +39,8 @@
  #include plat/regs-irqtype.h
  #include plat/pm.h
  
 +#include irqchip.h
 +
  #define S3C_IRQTYPE_NONE 0
  #define S3C_IRQTYPE_EINT 1
  #define S3C_IRQTYPE_EDGE 2
 @@ -380,6 +385,10 @@ static int s3c24xx_irq_map(struct irq_domain *h, 
 unsigned int virq,
  
   parent_intc = intc-parent;
  
 + /* on dt platforms the extints get handled by the pinctrl driver */
 + if (h-of_node  irq_data-type == S3C_IRQTYPE_EINT)
 + irq_data-type = S3C_IRQTYPE_EDGE;
 +
   /* set handler and flags */
   switch (irq_data-type) {
   case S3C_IRQTYPE_NONE:
 @@ -1104,3 +1113,216 @@ void __init s3c2443_init_irq(void)
   s3c24xx_init_intc(NULL, init_s3c2443subint[0], main_intc, 0x4a18);
  }
  #endif
 +
 +#ifdef CONFIG_OF
 +struct s3c24xx_irq_of_ctrl {
 + char*name;
 + unsigned long   offset;
 + struct s3c_irq_data *irq_data;
 + struct s3c_irq_intc **handle;
 + struct s3c_irq_intc **parent;
 +};
 +
 +#define S3C24XX_IRQCTRL(n, o, d, h, p)   \
 +{\
 + .name   = n,\
 + .offset = o,\
 + .irq_data   = d,\
 + .handle = h,\
 + .parent = p,\
 +}
 +
 +struct s3c24xx_irq_of_data {
 + struct s3c24xx_irq_of_ctrl  *irq_ctrl;
 + int num_ctrl;
 +};
 +
 +#ifdef CONFIG_CPU_S3C2410
 +static struct 

Re: [PATCH v3 5/6] irqchip: s3c24xx: add devicetree support

2013-03-17 Thread Heiko Stübner
Am Sonntag, 17. März 2013, 14:07:58 schrieb Heiko Stübner:
 Add the necessary code to initialize the interrupt controller
 thru devicetree data using the irqchip infrastructure.
 
 On dt machines the eint-type interrupts in the main interrupt controller
 get mapped as regular edge-types, as their wakeup and interrupt type
 properties will be handled by the upcoming pinctrl driver.
 
 Signed-off-by: Heiko Stuebner he...@sntech.de
 ---
  .../interrupt-controller/samsung,s3c24xx-irq.txt   |   54 +
  drivers/irqchip/irq-s3c24xx.c  |  222
  2 files changed, 276 insertions(+), 0 deletions(-)
  create mode 100644
 Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq
 .txt
 
 diff --git
 a/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-i
 rq.txt
 b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-i
 rq.txt new file mode 100644
 index 000..be5dead
 --- /dev/null
 +++
 b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-i
 rq.txt @@ -0,0 +1,54 @@
 +Samsung S3C24XX Interrupt Controllers
 +
 +The S3C24XX SoCs contain a custom set of interrupt controllers providing a
 +varying number of interrupt sources. The set consists of a main- and sub-
 +controller and on newer SoCs even a second main controller.
 +
 +Required properties:
 +- compatible: Compatible property value should be one of
 samsung,s3c2410-irq, +  samsung,s3c2412-irq, samsung,s3c2416-irq,
 samsung,s3c2440-irq, +  samsung,s3c2442-irq, samsung,s3c2443-irq
 depending on the SoC variant. +
 +- reg: Physical base address of the controller and length of memory mapped
 +  region.
 +
 +- interrupt-controller : Identifies the node as an interrupt controller
 +
 +Sub-controllers as child nodes:
 +  The interrupt controllers that should be referenced by device nodes are
 +  represented by child nodes. Valid names are intc, subintc and intc2.
 +  The interrupt values in device nodes are then mapped directly to the
 +  bit-numbers of the pending register of the named interrupt controller.
 +
 +Required properties:
 +- interrupt-controller : Identifies the node as an interrupt controller
 +
 +- #interrupt-cells : Specifies the number of cells needed to encode an
 +  interrupt source. The value shall be 2.

just noticed, that with the eint handling moving to the pinctrl driver, there 
are no interrupt trigger settings to be made here anymore, so this can 
probably move to xlate_onecell and #interrupt-cells to 1.
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