subject:"Re\: \[PATCH v5 5\/5\] clk\/exynos5260\: add clock file for exynos5260"

Re: [PATCH v5 5/5] clk/exynos5260: add clock file for exynos5260

2014-03-23 Thread Rahul Sharma

On 13 March 2014 18:40, Tomasz Figa t.f...@samsung.com wrote:
 On 12.03.2014 15:56, Rahul Sharma wrote:

 Add support for exynos5260 clocks in clock driver.

 Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
 Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
 ---
   drivers/clk/samsung/Makefile |1 +
   drivers/clk/samsung/clk-exynos5260.c | 1805
 ++
   drivers/clk/samsung/clk-exynos5260.h |  448 +
   3 files changed, 2254 insertions(+)
   create mode 100644 drivers/clk/samsung/clk-exynos5260.c
   create mode 100644 drivers/clk/samsung/clk-exynos5260.h


 [snip]


 diff --git a/drivers/clk/samsung/clk-exynos5260.c
 b/drivers/clk/samsung/clk-exynos5260.c
 new file mode 100644
 index 000..f72ad6a
 --- /dev/null
 +++ b/drivers/clk/samsung/clk-exynos5260.c


 [snip]


 +struct samsung_gate_clock aud_gate_clks[] __initdata = {
 +   GATE(AUD_CLK_AUD_UART, clk_aud_uart, dout_aclk_aud_131,
 +   EN_IP_AUD, 4, 0, 0),
 +   GATE(AUD_CLK_PCM, clk_pcm, dout_aclk_aud_131, EN_IP_AUD, 3, 0,
 0),
 +   GATE(AUD_CLK_I2S, clk_i2s, dout_aclk_aud_131, EN_IP_AUD, 2, 0,
 0),
 +   GATE(AUD_CLK_DMAC, clk_dmac, dout_aclk_aud_131,
 +   EN_IP_AUD, 1, 0, 0),
 +   GATE(0, clk_sramc, dout_aclk_aud_131, EN_IP_AUD, 0, 0, 0),
 +
 +   GATE(AUD_SCLK_AUD_UART, sclk_aud_uart, dout_sclk_aud_uart,
 +   EN_SCLK_AUD, 2, CLK_SET_RATE_PARENT, 0),
 +   GATE(AUD_SCLK_PCM, sclk_aud_pcm, dout_sclk_aud_pcm,
 +   EN_SCLK_AUD, 1, CLK_SET_RATE_PARENT, 0),
 +   GATE(AUD_SCLK_I2S, sclk_aud_i2s, dout_sclk_aud_i2s,
 +   EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0),


 Please keep the clocks sorted by the register offsets ascending as well, to
 match the order in UM.

 [snip]


 +
 +struct samsung_mux_clock disp_mux_clks[] __initdata = {
 +   MUX(0, mout_sclk_hdmi_spdif, mout_sclk_hdmi_spdif_p,
 +   MUX_SEL_DISP4, 4, 2),
 +
 +   MUX(0, mout_sclk_dsim1_tx_clk_esc_clk_user,
 +   mout_sclk_dsim1_tx_clk_esc_clk_user_p,
 +   MUX_SEL_DISP2, 28, 1),


 Ditto.

 [snip]


 +struct samsung_gate_clock disp_gate_clks[] __initdata = {
 +   GATE(DISP_CLK_SMMU_TV, clk_smmu3_tv, mout_aclk_disp_222_user,
 +   EN_IP_DISP, 25, 0, 0),
 +   GATE(DISP_CLK_SMMU_FIMD1M1, clk_smmu3_fimd1m1,
 +   mout_aclk_disp_222_user,
 +   EN_IP_DISP, 23, 0, 0),
 +   GATE(DISP_CLK_SMMU_FIMD1M0, clk_smmu3_fimd1m0,
 +   mout_aclk_disp_222_user,
 +   EN_IP_DISP, 22, 0, 0),
 +   GATE(0, clk_pixel_mixer, mout_aclk_disp_222_user,
 +   EN_IP_DISP, 13, CLK_IGNORE_UNUSED, 0),
 +   GATE(0, clk_pixel_disp, mout_aclk_disp_222_user,
 +   EN_IP_DISP, 12, CLK_IGNORE_UNUSED, 0),
 +   GATE(DISP_CLK_MIXER, clk_mixer, mout_aclk_disp_222_user,
 +   EN_IP_DISP, 11, 0, 0),
 +   GATE(DISP_CLK_MIPIPHY, clk_mipi_dphy, mout_aclk_disp_222_user,
 +   EN_IP_DISP, 10, 0, 0),
 +   GATE(DISP_CLK_HDMIPHY, clk_hdmiphy, mout_aclk_disp_222_user,
 +   EN_IP_DISP, 9, 0, 0),
 +   GATE(DISP_CLK_HDMI, clk_hdmi, mout_aclk_disp_222_user,
 +   EN_IP_DISP, 8, 0, 0),
 +   GATE(DISP_CLK_FIMD1, clk_fimd1, mout_aclk_disp_222_user,
 +   EN_IP_DISP, 7, 0, 0),
 +   GATE(DISP_CLK_DSIM1, clk_dsim1, mout_aclk_disp_222_user,
 +   EN_IP_DISP, 6, 0, 0),
 +   GATE(DISP_CLK_DPPHY, clk_dptx_phy, mout_aclk_disp_222_user,
 +   EN_IP_DISP, 5, 0, 0),
 +   GATE(DISP_CLK_DP, clk_dptx_link, mout_aclk_disp_222_user,
 +   EN_IP_DISP, 4, 0, 0),
 +   GATE(DISP_SCLK_PIXEL, sclk_hdmi_phy_pixel_clki,
 +   dout_sclk_hdmi_phy_pixel_clki,
 +   EN_SCLK_DISP0, 29, CLK_SET_RATE_PARENT, 0),
 +   GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, sclk_hdmi_link_i_pixel,
 +   mout_phyclk_hdmi_phy_pixel_clko_user,
 +   EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0),


 Ditto.

 [snip]


 +struct samsung_gate_clock fsys_gate_clks[] __initdata = {
 +   GATE(FSYS_CLK_TSI, clk_tsi, dout_aclk_fsys_200,
 +   EN_IP_FSYS, 20, 0, 0),
 +   GATE(FSYS_CLK_USBLINK, clk_usblink, dout_aclk_fsys_200,
 +   EN_IP_FSYS, 18, 0, 0),
 +   GATE(FSYS_CLK_USBHOST20, clk_usbhost20, dout_aclk_fsys_200,
 +   EN_IP_FSYS, 15, 0, 0),
 +   GATE(FSYS_CLK_USBDRD30, clk_usbdrd30, dout_aclk_fsys_200,
 +   EN_IP_FSYS, 14, 0, 0),
 +   GATE(FSYS_CLK_SROMC, clk_sromc, dout_aclk_fsys_200,
 +   EN_IP_FSYS, 13, 0, 0),
 +   GATE(FSYS_CLK_PDMA, clk_pdma, dout_aclk_fsys_200,
 +   EN_IP_FSYS, 9, 0, 0),
 +

Re: [PATCH v5 5/5] clk/exynos5260: add clock file for exynos5260

2014-03-13 Thread Tomasz Figa


On 12.03.2014 15:56, Rahul Sharma wrote:

Add support for exynos5260 clocks in clock driver.

Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
---
  drivers/clk/samsung/Makefile |1 +
  drivers/clk/samsung/clk-exynos5260.c | 1805 ++
  drivers/clk/samsung/clk-exynos5260.h |  448 +
  3 files changed, 2254 insertions(+)
  create mode 100644 drivers/clk/samsung/clk-exynos5260.c
  create mode 100644 drivers/clk/samsung/clk-exynos5260.h


[snip]


diff --git a/drivers/clk/samsung/clk-exynos5260.c 
b/drivers/clk/samsung/clk-exynos5260.c
new file mode 100644
index 000..f72ad6a
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5260.c


[snip]


+struct samsung_gate_clock aud_gate_clks[] __initdata = {
+   GATE(AUD_CLK_AUD_UART, clk_aud_uart, dout_aclk_aud_131,
+   EN_IP_AUD, 4, 0, 0),
+   GATE(AUD_CLK_PCM, clk_pcm, dout_aclk_aud_131, EN_IP_AUD, 3, 0, 0),
+   GATE(AUD_CLK_I2S, clk_i2s, dout_aclk_aud_131, EN_IP_AUD, 2, 0, 0),
+   GATE(AUD_CLK_DMAC, clk_dmac, dout_aclk_aud_131,
+   EN_IP_AUD, 1, 0, 0),
+   GATE(0, clk_sramc, dout_aclk_aud_131, EN_IP_AUD, 0, 0, 0),
+
+   GATE(AUD_SCLK_AUD_UART, sclk_aud_uart, dout_sclk_aud_uart,
+   EN_SCLK_AUD, 2, CLK_SET_RATE_PARENT, 0),
+   GATE(AUD_SCLK_PCM, sclk_aud_pcm, dout_sclk_aud_pcm,
+   EN_SCLK_AUD, 1, CLK_SET_RATE_PARENT, 0),
+   GATE(AUD_SCLK_I2S, sclk_aud_i2s, dout_sclk_aud_i2s,
+   EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0),


Please keep the clocks sorted by the register offsets ascending as well, 
to match the order in UM.


[snip]


+
+struct samsung_mux_clock disp_mux_clks[] __initdata = {
+   MUX(0, mout_sclk_hdmi_spdif, mout_sclk_hdmi_spdif_p,
+   MUX_SEL_DISP4, 4, 2),
+
+   MUX(0, mout_sclk_dsim1_tx_clk_esc_clk_user,
+   mout_sclk_dsim1_tx_clk_esc_clk_user_p,
+   MUX_SEL_DISP2, 28, 1),


Ditto.

[snip]


+struct samsung_gate_clock disp_gate_clks[] __initdata = {
+   GATE(DISP_CLK_SMMU_TV, clk_smmu3_tv, mout_aclk_disp_222_user,
+   EN_IP_DISP, 25, 0, 0),
+   GATE(DISP_CLK_SMMU_FIMD1M1, clk_smmu3_fimd1m1,
+   mout_aclk_disp_222_user,
+   EN_IP_DISP, 23, 0, 0),
+   GATE(DISP_CLK_SMMU_FIMD1M0, clk_smmu3_fimd1m0,
+   mout_aclk_disp_222_user,
+   EN_IP_DISP, 22, 0, 0),
+   GATE(0, clk_pixel_mixer, mout_aclk_disp_222_user,
+   EN_IP_DISP, 13, CLK_IGNORE_UNUSED, 0),
+   GATE(0, clk_pixel_disp, mout_aclk_disp_222_user,
+   EN_IP_DISP, 12, CLK_IGNORE_UNUSED, 0),
+   GATE(DISP_CLK_MIXER, clk_mixer, mout_aclk_disp_222_user,
+   EN_IP_DISP, 11, 0, 0),
+   GATE(DISP_CLK_MIPIPHY, clk_mipi_dphy, mout_aclk_disp_222_user,
+   EN_IP_DISP, 10, 0, 0),
+   GATE(DISP_CLK_HDMIPHY, clk_hdmiphy, mout_aclk_disp_222_user,
+   EN_IP_DISP, 9, 0, 0),
+   GATE(DISP_CLK_HDMI, clk_hdmi, mout_aclk_disp_222_user,
+   EN_IP_DISP, 8, 0, 0),
+   GATE(DISP_CLK_FIMD1, clk_fimd1, mout_aclk_disp_222_user,
+   EN_IP_DISP, 7, 0, 0),
+   GATE(DISP_CLK_DSIM1, clk_dsim1, mout_aclk_disp_222_user,
+   EN_IP_DISP, 6, 0, 0),
+   GATE(DISP_CLK_DPPHY, clk_dptx_phy, mout_aclk_disp_222_user,
+   EN_IP_DISP, 5, 0, 0),
+   GATE(DISP_CLK_DP, clk_dptx_link, mout_aclk_disp_222_user,
+   EN_IP_DISP, 4, 0, 0),
+   GATE(DISP_SCLK_PIXEL, sclk_hdmi_phy_pixel_clki,
+   dout_sclk_hdmi_phy_pixel_clki,
+   EN_SCLK_DISP0, 29, CLK_SET_RATE_PARENT, 0),
+   GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, sclk_hdmi_link_i_pixel,
+   mout_phyclk_hdmi_phy_pixel_clko_user,
+   EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0),


Ditto.

[snip]


+struct samsung_gate_clock fsys_gate_clks[] __initdata = {
+   GATE(FSYS_CLK_TSI, clk_tsi, dout_aclk_fsys_200,
+   EN_IP_FSYS, 20, 0, 0),
+   GATE(FSYS_CLK_USBLINK, clk_usblink, dout_aclk_fsys_200,
+   EN_IP_FSYS, 18, 0, 0),
+   GATE(FSYS_CLK_USBHOST20, clk_usbhost20, dout_aclk_fsys_200,
+   EN_IP_FSYS, 15, 0, 0),
+   GATE(FSYS_CLK_USBDRD30, clk_usbdrd30, dout_aclk_fsys_200,
+   EN_IP_FSYS, 14, 0, 0),
+   GATE(FSYS_CLK_SROMC, clk_sromc, dout_aclk_fsys_200,
+   EN_IP_FSYS, 13, 0, 0),
+   GATE(FSYS_CLK_PDMA, clk_pdma, dout_aclk_fsys_200,
+   EN_IP_FSYS, 9, 0, 0),
+   GATE(FSYS_CLK_MMC2, clk_mmc2, dout_aclk_fsys_200,
+   EN_IP_FSYS, 8, 0, 0),
+   GATE(FSYS_CLK_MMC1, clk_mmc1, dout_aclk_fsys_200,
+

Re: [PATCH v5 5/5] clk/exynos5260: add clock file for exynos5260

Re: [PATCH v5 5/5] clk/exynos5260: add clock file for exynos5260

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