Re: [PATCH 1/5] scsi: ufs: move the ufshcd_hba_stop to ufshcd.c
Tested-by: Maya Erez me...@codeaurora.org
Looks good. Reviewed-by: Subhash Jadavani subha...@codeaurora.org
On 4/24/2013 9:36 PM, Seungwon Jeon wrote:
Move the ufshcd_hba_stop from header file.
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
drivers/scsi/ufs/ufshcd.c |9 +
drivers/scsi/ufs/ufshcd.h |9 -
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 60fd40c..41b9639 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -285,6 +285,15 @@ static inline void ufshcd_hba_start(struct ufs_hba
*hba)
}
/**
+ * ufshcd_hba_stop - Send controller to reset state
+ * @hba: per adapter instance
+ */
+static inline void ufshcd_hba_stop(struct ufs_hba *hba)
+{
+writel(CONTROLLER_DISABLE, (hba-mmio_base + REG_CONTROLLER_ENABLE));
+}
+
+/**
* ufshcd_is_hba_active - Get controller state
* @hba: per adapter instance
*
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 6b99a42..1680394 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -190,13 +190,4 @@ int ufshcd_init(struct device *, struct ufs_hba **
, void __iomem * ,
unsigned int);
void ufshcd_remove(struct ufs_hba *);
-/**
- * ufshcd_hba_stop - Send controller to reset state
- * @hba: per adapter instance
- */
-static inline void ufshcd_hba_stop(struct ufs_hba *hba)
-{
-writel(CONTROLLER_DISABLE, (hba-mmio_base + REG_CONTROLLER_ENABLE));
-}
-
#endif /* End of Header */
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Maya Erez
QUALCOMM ISRAEL, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
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Re: [PATCH 2/5] scsi: ufs: wrap the i/o access operations
Tested-by: Maya Erez me...@codeaurora.org I also tend to agree with Sujit on the order of the wrappers parameters. Thanks, Maya On 4/26/2013 10:36 AM, Seungwon Jeon wrote: Hi, On Thursday, April 25, 2013, Sujit Reddy Thumma wrote: On 4/24/2013 9:36 PM, Seungwon Jeon wrote: Simplify operations with hiding mmio_base. Signed-off-by: Seungwon Jeon tgih@samsung.com --- drivers/scsi/ufs/ufshcd.c | 106 +++-- drivers/scsi/ufs/ufshcd.h |5 ++ 2 files changed, 49 insertions(+), 62 deletions(-) diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index 1680394..6728450 100644 --- a/drivers/scsi/ufs/ufshcd.h +++ b/drivers/scsi/ufs/ufshcd.h @@ -190,4 +190,9 @@ int ufshcd_init(struct device *, struct ufs_hba ** , void __iomem * , unsigned int); void ufshcd_remove(struct ufs_hba *); +#define ufshcd_writel(hba, reg, val) \ Let this be consistent with writel() arguments - val as second arg and reg as third? You got a point there. When considering an array of arguments in two functions and value part can be some long expression, I think it seems more coherent. ufshcd_readl(hba, reg); ufshcd_writel(hba, reg, val); How about keeping these? I somehow tend to agree with what Sujit suggested. Its good to be consitent with writel() for better code readability. Thanks, Seungwon Jeon + writel((val), (hba)-mmio_base + (reg)) +#define ufshcd_readl(hba, reg)\ + readl((hba)-mmio_base + (reg)) + #endif /* End of Header */ -- Regards, Sujit -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- Maya Erez QUALCOMM ISRAEL, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/5] scsi: ufs: amend interrupt configuration
Tested-by: Maya Erez me...@codeaurora.org
Patch looks good but one minor comment below.
On 4/24/2013 9:36 PM, Seungwon Jeon wrote:
It makes interrupt setting more flexible especially
for disabling. And wrong bit mask is fixed for ver 1.0.
[17:16] is added for mask.
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
drivers/scsi/ufs/ufshcd.c | 86
-
drivers/scsi/ufs/ufshcd.h |4 +-
drivers/scsi/ufs/ufshci.h |5 ++-
3 files changed, 66 insertions(+), 29 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index b6c19b0..efe2256 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -35,6 +35,10 @@
#include ufshcd.h
+#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
+ UTP_TASK_REQ_COMPL |\
+ UFSHCD_ERROR_MASK)
+
I don't see any use of this macro in this patch. could you please remove
it or move it to the patch-set where its really being used.
enum {
UFSHCD_MAX_CHANNEL = 0,
UFSHCD_MAX_ID = 1,
@@ -64,6 +68,20 @@ enum {
};
/**
+ * ufshcd_get_intr_mask - Get the interrupt bit mask
+ * @hba - Pointer to adapter instance
+ *
+ * Returns interrupt bit mask per version
+ */
+static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
+{
+if (hba-ufs_version == UFSHCI_VERSION_10)
+return INTERRUPT_MASK_ALL_VER_10;
+else
+return INTERRUPT_MASK_ALL_VER_11;
+}
+
+/**
* ufshcd_get_ufs_version - Get the UFS version supported by the HBA
* @hba - Pointer to adapter instance
*
@@ -397,25 +415,45 @@ static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
}
/**
- * ufshcd_int_config - enable/disable interrupts
+ * ufshcd_enable_intr - enable interrupts
* @hba: per adapter instance
- * @option: interrupt option
+ * @intrs: interrupt bits
*/
-static void ufshcd_int_config(struct ufs_hba *hba, u32 option)
+static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
{
-switch (option) {
-case UFSHCD_INT_ENABLE:
-ufshcd_writel(hba, REG_INTERRUPT_ENABLE, hba-int_enable_mask);
-break;
-case UFSHCD_INT_DISABLE:
-if (hba-ufs_version == UFSHCI_VERSION_10)
-ufshcd_writel(hba, REG_INTERRUPT_ENABLE,
- INTERRUPT_DISABLE_MASK_10);
-else
-ufshcd_writel(hba, REG_INTERRUPT_ENABLE,
- INTERRUPT_DISABLE_MASK_11);
-break;
+u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
+
+if (hba-ufs_version == UFSHCI_VERSION_10) {
+u32 rw;
+rw = set INTERRUPT_MASK_RW_VER_10;
+set = rw | ((set ^ intrs) intrs);
+} else {
+set |= intrs;
+}
+
+ufshcd_writel(hba, REG_INTERRUPT_ENABLE, set);
+}
+
+/**
+ * ufshcd_disable_intr - disable interrupts
+ * @hba: per adapter instance
+ * @intrs: interrupt bits
+ */
+static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
+{
+u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
+
+if (hba-ufs_version == UFSHCI_VERSION_10) {
+u32 rw;
+rw = (set INTERRUPT_MASK_RW_VER_10)
+~(intrs INTERRUPT_MASK_RW_VER_10);
+set = rw | ((set intrs) ~INTERRUPT_MASK_RW_VER_10);
+
+} else {
+set = ~intrs;
}
+
+ufshcd_writel(hba, REG_INTERRUPT_ENABLE, set);
}
/**
@@ -717,8 +755,7 @@ static int ufshcd_dme_link_startup(struct ufs_hba
*hba)
uic_cmd-argument3 = 0;
/* enable UIC related interrupts */
-hba-int_enable_mask |= UIC_COMMAND_COMPL;
-ufshcd_int_config(hba, UFSHCD_INT_ENABLE);
+ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
/* sending UIC commands to controller */
ufshcd_send_uic_command(hba, uic_cmd);
@@ -765,13 +802,9 @@ static int ufshcd_make_hba_operational(struct
ufs_hba *hba)
}
/* Enable required interrupts */
-hba-int_enable_mask |= (UTP_TRANSFER_REQ_COMPL |
- UIC_ERROR |
- UTP_TASK_REQ_COMPL |
- DEVICE_FATAL_ERROR |
- CONTROLLER_FATAL_ERROR |
- SYSTEM_BUS_FATAL_ERROR);
-ufshcd_int_config(hba, UFSHCD_INT_ENABLE);
+ufshcd_enable_intr(hba, UTP_TRANSFER_REQ_COMPL | UIC_ERROR |
+ UTP_TASK_REQ_COMPL | DEVICE_FATAL_ERROR |
+ CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR);
/* Configure interrupt aggregation */
ufshcd_config_int_aggr(hba, INT_AGGR_CONFIG);
@@ -1578,7 +1611,7 @@ static void ufshcd_hba_free(struct ufs_hba *hba)
void ufshcd_remove(struct ufs_hba *hba)
{
/* disable interrupts */
-ufshcd_int_config(hba, UFSHCD_INT_DISABLE);
+
Re: [PATCH 5/5] scsi: ufs: add dme operations
Tested-by: Maya Erez me...@codeaurora.org Add uic command operations including DME_XXX series. Signed-off-by: Seungwon Jeon tgih@samsung.com --- drivers/scsi/ufs/ufs-attrs.h | 129 drivers/scsi/ufs/ufshcd.c| 220 +- drivers/scsi/ufs/ufshcd.h| 55 +++ drivers/scsi/ufs/ufshci.h| 19 4 files changed, 422 insertions(+), 1 deletions(-) create mode 100644 drivers/scsi/ufs/ufs-attrs.h diff --git a/drivers/scsi/ufs/ufs-attrs.h b/drivers/scsi/ufs/ufs-attrs.h new file mode 100644 index 000..562bb49 --- /dev/null +++ b/drivers/scsi/ufs/ufs-attrs.h @@ -0,0 +1,129 @@ +/* + * drivers/scsi/ufs/ufs-attrs.h + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _UFS_ATTRS_H_ +#define _UFS_ATTRS_H_ + +/* + * PHY Adpater attributes + */ +#define PA_ACTIVETXDATALANES 0x1560 +#define PA_ACTIVERXDATALANES 0x1580 +#define PA_TXTRAILINGCLOCKS 0x1564 +#define PA_PHY_TYPE 0x1500 +#define PA_AVAILTXDATALANES 0x1520 +#define PA_AVAILRXDATALANES 0x1540 +#define PA_MINRXTRAILINGCLOCKS 0x1543 +#define PA_TXPWRSTATUS 0x1567 +#define PA_RXPWRSTATUS 0x1582 +#define PA_TXFORCECLOCK 0x1562 +#define PA_TXPWRMODE 0x1563 +#define PA_LEGACYDPHYESCDL 0x1570 +#define PA_MAXTXSPEEDFAST0x1521 +#define PA_MAXTXSPEEDSLOW0x1522 +#define PA_MAXRXSPEEDFAST0x1541 +#define PA_MAXRXSPEEDSLOW0x1542 +#define PA_TXLINKSTARTUPHS 0x1544 +#define PA_TXSPEEDFAST 0x1565 +#define PA_TXSPEEDSLOW 0x1566 +#define PA_REMOTEVERINFO 0x15A0 +#define PA_TXGEAR0x1568 +#define PA_TXTERMINATION 0x1569 +#define PA_HSSERIES 0x156A +#define PA_PWRMODE 0x1571 +#define PA_RXGEAR0x1583 +#define PA_RXTERMINATION 0x1584 +#define PA_MAXRXPWMGEAR 0x1586 +#define PA_MAXRXHSGEAR 0x1587 +#define PA_RXHSUNTERMCAP 0x15A5 +#define PA_RXLSTERMCAP 0x15A6 +#define PA_PACPREQTIMEOUT0x1590 +#define PA_PACPREQEOBTIMEOUT 0x1591 +#define PA_LOCALVERINFO 0x15A9 +#define PA_TACTIVATE 0x15A8 +#define PA_PACPFRAMECOUNT0x15C0 +#define PA_PACPERRORCOUNT0x15C1 +#define PA_PHYTESTCONTROL0x15C2 +#define PA_PWRMODEUSERDATA0 0x15B0 +#define PA_PWRMODEUSERDATA1 0x15B1 +#define PA_PWRMODEUSERDATA2 0x15B2 +#define PA_PWRMODEUSERDATA3 0x15B3 +#define PA_PWRMODEUSERDATA4 0x15B4 +#define PA_PWRMODEUSERDATA5 0x15B5 +#define PA_PWRMODEUSERDATA6 0x15B6 +#define PA_PWRMODEUSERDATA7 0x15B7 +#define PA_PWRMODEUSERDATA8 0x15B8 +#define PA_PWRMODEUSERDATA9 0x15B9 +#define PA_PWRMODEUSERDATA10 0x15BA +#define PA_PWRMODEUSERDATA11 0x15BB +#define PA_CONNECTEDTXDATALANE 0x1561 +#define PA_CONNECTEDRXDATALANE 0x1581 +#define PA_LOGICALLANEMAP0x15A1 +#define PA_SLEEPNOCONFIGTIME 0x15A2 +#define PA_STALLNOCONFIGTIME 0x15A3 +#define PA_SAVECONFIGTIME0x15A4 + +/* + * Data Link Layer Attributes + */ +#define DL_TC0TXFCTHRESHOLD 0x2040 +#define DL_FC0PROTTIMEOUTVAL 0x2041 +#define DL_TC0REPLAYTIMEOUTVAL 0x2042 +#define DL_AFC0REQTIMEOUTVAL 0x2043 +#define DL_AFC0CREDITTHRESHOLD 0x2044 +#define DL_TC0OUTACKTHRESHOLD0x2045 +#define DL_TC1TXFCTHRESHOLD 0x2060 +#define DL_FC1PROTTIMEOUTVAL 0x2061 +#define DL_TC1REPLAYTIMEOUTVAL 0x2062 +#define DL_AFC1REQTIMEOUTVAL 0x2063 +#define DL_AFC1CREDITTHRESHOLD 0x2064 +#define DL_TC1OUTACKTHRESHOLD0x2065 +#define DL_TXPREEMPTIONCAP 0x2000 +#define DL_TC0TXMAXSDUSIZE 0x2001 +#define DL_TC0RXINITCREDITVAL0x2002 +#define DL_TC0TXBUFFERSIZE 0x2005 +#define DL_PEERTC0PRESENT0x2046 +#define DL_PEERTC0RXINITCREVAL 0x2047 +#define DL_TC1TXMAXSDUSIZE 0x2003 +#define DL_TC1RXINITCREDITVAL0x2004 +#define DL_TC1TXBUFFERSIZE 0x2006 +#define DL_PEERTC1PRESENT0x2066 +#define DL_PEERTC1RXINITCREVAL 0x2067 + +/* + * Network Layer Attributes + */ +#define N_DEVICEID 0x3000 +#define N_DEVICEID_VALID 0x3001 +#define N_TC0TXMAXSDUSIZE0x3020 +#define N_TC1TXMAXSDUSIZE0x3021 + +/* + * Transport Layer Attributes + */ +#define T_NUMCPORTS 0x4000 +#define T_NUMTESTFEATURES0x4001 +#define T_CONNECTIONSTATE0x4020 +#define T_PEERDEVICEID 0x4021 +#define T_PEERCPORTID0x4022 +#define T_TRAFFICCLASS 0x4023 +#define T_PROTOCOLID 0x4024 +#define T_CPORTFLAGS 0x4025 +#define T_TXTOKENVALUE 0x4026 +#define T_RXTOKENVALUE 0x4027
Re: [PATCH] checkpatch: Make camelcase test --strict and less noisy
On Thu, Apr 11, 2013 at 07:45:03AM -0700, Joe Perches wrote:
CamelCase tests are a bit noisy against certain
types of code acceptable to some kernel developers.
Make the test applicable only with --strict.
Do not bleat a message on nominally acceptable
CamelCase uses that are separated by an _ like
drm_core_has_MTRR.
Signed-off-by: Joe Perches j...@perches.com
---
scripts/checkpatch.pl | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 3fb6d86..97226fb 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2937,12 +2937,12 @@ sub process {
while ($line =~ m{($Constant|$Lval)}g) {
my $var = $1;
if ($var !~ /$Constant/
- $var =~ /[A-Z]\w*[a-z]|[a-z]\w*[A-Z]/
+ $var =~ /[A-Z][a-z]|[a-z][A-Z]/
$var !~
/^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/
!defined $camelcase{$var}) {
$camelcase{$var} = 1;
- WARN(CAMELCASE,
- Avoid CamelCase: $var\n . $herecurr);
+ CHK(CAMELCASE,
+ Avoid CamelCase: $var\n . $herecurr);
Yep, this is better.
James?
--
Regards/Gruss,
Boris.
Sent from a fat crate under my desk. Formatting is fine.
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Re: [PATCH 10/21] [SCSI] nsp32: use mdelay instead of large udelay constants
On Mon, 2013-04-29 at 15:21 +0200, Arnd Bergmann wrote: On Friday 26 April 2013, Masanori Goto wrote: 2013/4/25 Arnd Bergmann a...@arndb.de ARM cannot handle udelay for more than 2 miliseconds, so we should use mdelay instead for those. Singed-off-by: GOTO Masanori go...@debian.or.jp Thanks. I assume you mean Acked-by, not Singed-off as in burnt or Signed-off as a notification that you have applied it to your own git tree. I'll keep the patch with an your Acked-by line in my tree unless James wants to apply to the scsi tree. I can, certainly. I'll be sending the first scsi set today, but I'll be doing another one for just before the close of the merge window. Goto-san, while I have your attention, is the nsp_cs driver orphaned? I know it's not your driver, but you did once work with its author (YOKOTA Hiroshi yok...@netlab.is.tsukuba.ac.jp) and I'm trying to get some cleanup on the static functions in the header files. Thanks, James -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V4] scsi: ufs: add support for query requests
Add support for sending UFS query requests through tagged command
queuing. This design allows queuing query requests in any open slot
along with other SCSI commands. In this way there is no need to
save a slot in the requests queue and decrease its size.
A query request is posing to a SCSI command to use native flow. But
unlike normal SCSI command flow, the data and response fields are
filled in UFS host data structure instead of passing as arguments
while queuing into SCSI mlqueue (mid-layer SCSI queue, the requests
from this queue are submitted to the device queue). As per specification
only one query request is allowed to be processed by device. Hence a
mutex lock for protecting data and response fields (hba-query.request and
hba-query.response) needs to be held while query request is in
progress.
The API for submitting a query request is ufs_query_request() in
ufshcd.c. This function is responsible for:
1. Obtaining the SCSI device from the host
2. Keeping the query mutex to prevent multiple queries
3. Storing the required data for sending a query request in ufs_hba
4. Queuing a SCSI vendor specific command to trigger a query request
in the UFS driver.
The callers of ufs_query_request() are expected to fill the query
command data fields and are to provide an allocated response field
for the driver to fill response fields after request completion.
The request and response upiu is extended in a union to enable using the
same data structure, both for command upiu and query request upiu.
The query request flow is separated from the scsi command flow in:
1. Preparing the request
2. Validating response (error) codes
3. Copying data (only used for descriptor read/write query requests)
4. Copying response/sense
Data error can't be handled in the scsi command native flow. Hence,
we pass the code as without a change back to the submitting layer.
UPIU (UFS Protocol Information Unit) size is increased to 512 bytes
from 128. The UPIU header and the transaction specific fields (SCSI
command or Query Request OSF - Op-code Specific Fields) are 32 bytes
together, the rest is used to transfer extra request data (such as
descriptor in query requests). In order to accommodate the largest
descriptor in the UFS spec (256 bytes) we need to increase the UPIU
size.
Signed-off-by: Dolev Raviv dra...@codeaurora.org
---
changes for v4:
- Removed un-necessary inline modifiers
- Fixed return values to SCSI layer on completion
changes for v3:
- Reworked validating response UPIU
- Removed redundant NULL pointer checks
changes for v2:
- Moved ufs_query_request to ufshcd.c and removed ufs_core.c
- Addressed Santosh's comments
diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig
index 35faf24..82417d6 100644
--- a/drivers/scsi/ufs/Kconfig
+++ b/drivers/scsi/ufs/Kconfig
@@ -35,6 +35,7 @@
config SCSI_UFSHCD
tristate Universal Flash Storage Controller Driver Core
depends on SCSI
+ default y
---help---
This selects the support for UFS devices in Linux, say Y and make
sure that you know the name of your UFS host adapter (the card
diff --git a/drivers/scsi/ufs/ufs.h b/drivers/scsi/ufs/ufs.h
index 139bc06..086ff03 100644
--- a/drivers/scsi/ufs/ufs.h
+++ b/drivers/scsi/ufs/ufs.h
@@ -36,10 +36,20 @@
#ifndef _UFS_H
#define _UFS_H
+#include linux/mutex.h
+#include linux/types.h
+
#define MAX_CDB_SIZE 16
+#define GENERAL_UPIU_REQUEST_SIZE 32
+#define UPIU_HEADER_DATA_SEGMENT_MAX_SIZE ((ALIGNED_UPIU_SIZE) - \
+ (GENERAL_UPIU_REQUEST_SIZE))
+#define QUERY_OSF_SIZE ((GENERAL_UPIU_REQUEST_SIZE) - \
+ (sizeof(struct utp_upiu_header)))
+#define UFS_QUERY_RESERVED_SCSI_CMD 0xCC
+#define UFS_QUERY_CMD_SIZE 10
#define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
- ((byte3 24) | (byte2 16) |\
+ cpu_to_be32((byte3 24) | (byte2 16) |\
(byte1 8) | (byte0))
/*
@@ -62,7 +72,7 @@ enum {
UPIU_TRANSACTION_COMMAND= 0x01,
UPIU_TRANSACTION_DATA_OUT = 0x02,
UPIU_TRANSACTION_TASK_REQ = 0x04,
- UPIU_TRANSACTION_QUERY_REQ = 0x26,
+ UPIU_TRANSACTION_QUERY_REQ = 0x16,
};
/* UTP UPIU Transaction Codes Target to Initiator */
@@ -73,6 +83,7 @@ enum {
UPIU_TRANSACTION_TASK_RSP = 0x24,
UPIU_TRANSACTION_READY_XFER = 0x31,
UPIU_TRANSACTION_QUERY_RSP = 0x36,
+ UPIU_TRANSACTION_REJECT_UPIU= 0x3F,
};
/* UPIU Read/Write flags */
@@ -90,6 +101,12 @@ enum {
UPIU_TASK_ATTR_ACA = 0x03,
};
+/* UPIU Query request function */
+enum {
+ UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01,
+ UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81,
+};
+
/* UTP QUERY Transaction Specific Fields OpCode */
enum {
UPIU_QUERY_OPCODE_NOP = 0x0,
@@ -103,6 +120,21 @@ enum {
Re: [PATCH 2/5] bnx2fc: Include chip number in the symbolic name
On Fri, 2013-03-08 at 13:28 -0800, Bhanu Prakash Gollapudi wrote: +#ifndef PCI_DEVICE_ID_NX2_57710 +#define PCI_DEVICE_ID_NX2_57710 0x164e +#endif +#ifndef PCI_DEVICE_ID_NX2_57711 +#define PCI_DEVICE_ID_NX2_57711 0x164f +#endif +#ifndef PCI_DEVICE_ID_NX2_57712 +#define PCI_DEVICE_ID_NX2_57712 0x1662 +#endif +#ifndef PCI_DEVICE_ID_NX2_57712_MF +#define PCI_DEVICE_ID_NX2_57712_MF 0x1663 +#endif +#ifndef PCI_DEVICE_ID_NX2_57712_VF +#define PCI_DEVICE_ID_NX2_57712_VF 0x166f +#endif +#ifndef PCI_DEVICE_ID_NX2_57800 +#define PCI_DEVICE_ID_NX2_57800 0x168a +#endif +#ifndef PCI_DEVICE_ID_NX2_57800_MF +#define PCI_DEVICE_ID_NX2_57800_MF 0x16a5 +#endif +#ifndef PCI_DEVICE_ID_NX2_57800_VF +#define PCI_DEVICE_ID_NX2_57800_VF 0x16a9 +#endif +#ifndef PCI_DEVICE_ID_NX2_57810 +#define PCI_DEVICE_ID_NX2_57810 0x168e +#endif +#ifndef PCI_DEVICE_ID_NX2_57810_MF +#define PCI_DEVICE_ID_NX2_57810_MF 0x16ae +#endif +#ifndef PCI_DEVICE_ID_NX2_57810_VF +#define PCI_DEVICE_ID_NX2_57810_VF 0x16af +#endif +#ifndef PCI_DEVICE_ID_NX2_57840 +#define PCI_DEVICE_ID_NX2_57840 0x168d +#endif +#ifndef PCI_DEVICE_ID_NX2_57840_MF +#define PCI_DEVICE_ID_NX2_57840_MF 0x16a4 +#endif +#ifndef PCI_DEVICE_ID_NX2_57840_VF +#define PCI_DEVICE_ID_NX2_57840_VF 0x16ad +#endif +#ifndef PCI_DEVICE_ID_NX2_57840_2_20 +#define PCI_DEVICE_ID_NX2_57840_2_20 0x16a2 +#endif +#ifndef PCI_DEVICE_ID_NX2_57840_4_10 +#define PCI_DEVICE_ID_NX2_57840_4_10 0x16a1 +#endif This doesn't belong in your header file. Most of the IDs are already in pci_ids.h; I added the few which weren't. James -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] bnx2fc: Include chip number in the symbolic name
On 05/01/2013 05:39 PM, James Bottomley wrote: On Fri, 2013-03-08 at 13:28 -0800, Bhanu Prakash Gollapudi wrote: +#ifndef PCI_DEVICE_ID_NX2_57710 +#define PCI_DEVICE_ID_NX2_577100x164e +#endif +#ifndef PCI_DEVICE_ID_NX2_57711 +#define PCI_DEVICE_ID_NX2_577110x164f +#endif +#ifndef PCI_DEVICE_ID_NX2_57712 +#define PCI_DEVICE_ID_NX2_577120x1662 +#endif +#ifndef PCI_DEVICE_ID_NX2_57712_MF +#define PCI_DEVICE_ID_NX2_57712_MF 0x1663 +#endif +#ifndef PCI_DEVICE_ID_NX2_57712_VF +#define PCI_DEVICE_ID_NX2_57712_VF 0x166f +#endif +#ifndef PCI_DEVICE_ID_NX2_57800 +#define PCI_DEVICE_ID_NX2_578000x168a +#endif +#ifndef PCI_DEVICE_ID_NX2_57800_MF +#define PCI_DEVICE_ID_NX2_57800_MF 0x16a5 +#endif +#ifndef PCI_DEVICE_ID_NX2_57800_VF +#define PCI_DEVICE_ID_NX2_57800_VF 0x16a9 +#endif +#ifndef PCI_DEVICE_ID_NX2_57810 +#define PCI_DEVICE_ID_NX2_578100x168e +#endif +#ifndef PCI_DEVICE_ID_NX2_57810_MF +#define PCI_DEVICE_ID_NX2_57810_MF 0x16ae +#endif +#ifndef PCI_DEVICE_ID_NX2_57810_VF +#define PCI_DEVICE_ID_NX2_57810_VF 0x16af +#endif +#ifndef PCI_DEVICE_ID_NX2_57840 +#define PCI_DEVICE_ID_NX2_578400x168d +#endif +#ifndef PCI_DEVICE_ID_NX2_57840_MF +#define PCI_DEVICE_ID_NX2_57840_MF 0x16a4 +#endif +#ifndef PCI_DEVICE_ID_NX2_57840_VF +#define PCI_DEVICE_ID_NX2_57840_VF 0x16ad +#endif +#ifndef PCI_DEVICE_ID_NX2_57840_2_20 +#define PCI_DEVICE_ID_NX2_57840_2_20 0x16a2 +#endif +#ifndef PCI_DEVICE_ID_NX2_57840_4_10 +#define PCI_DEVICE_ID_NX2_57840_4_10 0x16a1 +#endif This doesn't belong in your header file. Most of the IDs are already in pci_ids.h; I added the few which weren't. I had to add these since some of them were not there in pci_ids.h yet. If you have retained a few that are not in pci_ids.h file, it fine with me. Thanks, Bhanu James -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/5] bnx2fc: Bumped version to 1.0.14
On Fri, 2013-03-08 at 15:53 -0800, Bhanu Prakash Gollapudi wrote: On 03/08/2013 01:28 PM, Bhanu Prakash Gollapudi wrote: Signed-off-by: Bhanu Prakash Gollapudi bprak...@broadcom.com --- drivers/scsi/bnx2fc/bnx2fc.h |2 +- drivers/scsi/bnx2fc/bnx2fc_fcoe.c |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/bnx2fc/bnx2fc.h b/drivers/scsi/bnx2fc/bnx2fc.h index 676dba3..1ece6e9 100644 --- a/drivers/scsi/bnx2fc/bnx2fc.h +++ b/drivers/scsi/bnx2fc/bnx2fc.h @@ -64,7 +64,7 @@ #include bnx2fc_constants.h #define BNX2FC_NAME bnx2fc -#define BNX2FC_VERSION 1.0.13 +#define BNX2FC_VERSION 1.0.14 #define PFX bnx2fc: diff --git a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c index 1e852d6..9ab62da 100644 --- a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c +++ b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c @@ -22,7 +22,7 @@ DEFINE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu); #define DRV_MODULE_NAME bnx2fc #define DRV_MODULE_VERSIONBNX2FC_VERSION -#define DRV_MODULE_RELDATE Dec 21, 2012 +#define DRV_MODULE_RELDATE Mar 08, 2012 James, I realized there was a typo in the date - 2012 instead of 2013. Please apply this patch instead. Sorry for the inconvenience. Signed-off-by: Bhanu Prakash Gollapudi bprak...@broadcom.com --- drivers/scsi/bnx2fc/bnx2fc.h |2 +- drivers/scsi/bnx2fc/bnx2fc_fcoe.c |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/bnx2fc/bnx2fc.h b/drivers/scsi/bnx2fc/bnx2fc.h index 676dba3..1ece6e9 100644 --- a/drivers/scsi/bnx2fc/bnx2fc.h +++ b/drivers/scsi/bnx2fc/bnx2fc.h @@ -64,7 +64,7 @@ #include bnx2fc_constants.h #define BNX2FC_NAMEbnx2fc -#define BNX2FC_VERSION1.0.13 +#define BNX2FC_VERSION1.0.14 #define PFXbnx2fc: diff --git a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c index 1e852d6..9ab62da 100644 --- a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c +++ b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c @@ -22,7 +22,7 @@ DEFINE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu); #define DRV_MODULE_NAMEbnx2fc #define DRV_MODULE_VERSIONBNX2FC_VERSION -#define DRV_MODULE_RELDATEDec 21, 2012 +#define DRV_MODULE_RELDATEMar 08, 2013 This doesn't actually apply ... your mailer has converted tabs to spaces. Since it's only a couple of lines, I fixed it up by hand this time ... James -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 0/4] Patchset to use PCLMULQDQ to accelerate CRC-T10DIF checksum computation
Currently the CRC-T10DIF checksum is computed using a generic table lookup algorithm. By switching the checksum to PCLMULQDQ based computation, we can speedup the computation by 8x for checksumming 512 bytes and even more for larger buffer size. This will improve performance of SCSI drivers turning on the CRC-T10IDF checksum. In our SSD based experiments, we have seen increase disk throughput by 3.5x with T10DIF for 512 byte block size. This patch set provides the x86_64 routine using PCLMULQDQ instruction and switches the crc_t10dif library function to use the faster PCLMULQDQ based routine when available. Tim v3 1. Update the crct10dif crypto transform used in the crct10dif library in a safe way. 2. Load the accelerated t10dif transform for the x86_64 cpus that support it. 3. Added generic crct10dif crypto transform. v2 1. Get rid of unnecessary xmm registers save and restore and fix ENDPROC position in PCLMULQDQ version of crc t10dif computation. 2. Fix URL to paper reference of CRC computation with PCLMULQDQ. 3. Add one additional tcrypt test case to exercise more code paths through crc t10dif computation. 4. Fix config dependencies of CRYPTO_CRCT10DIF. Thanks to Herbert Xu, Matthew Wilcox and Jussi Kivilinna who reviewed the patches and Keith Busch for testing version 1 of the patch set. Tim Chen (4): Wrap crc_t10dif function all to use crypto transform framework Accelerated CRC T10 DIF computation with PCLMULQDQ instruction Glue code to cast accelerated CRCT10DIF assembly as a crypto transform Simple correctness and speed test for CRCT10DIF hash arch/x86/crypto/Makefile| 2 + arch/x86/crypto/crct10dif-pcl-asm_64.S | 643 arch/x86/crypto/crct10dif-pclmul_glue.c | 157 crypto/Kconfig | 20 + crypto/Makefile | 1 + crypto/crct10dif.c | 126 +++ crypto/tcrypt.c | 8 + crypto/testmgr.c| 10 + crypto/testmgr.h| 33 ++ include/linux/crc-t10dif.h | 5 + lib/crc-t10dif.c| 95 - 11 files changed, 1098 insertions(+), 2 deletions(-) create mode 100644 arch/x86/crypto/crct10dif-pcl-asm_64.S create mode 100644 arch/x86/crypto/crct10dif-pclmul_glue.c create mode 100644 crypto/crct10dif.c -- 1.7.11.7 -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/4] Wrap crc_t10dif function all to use crypto transform framework
When CRC T10 DIF is calculated using the crypto transform framework, we
wrap the crc_t10dif function call to utilize it. This allows us to
take advantage of any accelerated CRC T10 DIF transform that is
plugged into the crypto framework.
Signed-off-by: Tim Chen tim.c.c...@linux.intel.com
---
crypto/Kconfig | 9
crypto/Makefile| 1 +
crypto/crct10dif.c | 126 +
include/linux/crc-t10dif.h | 5 ++
lib/crc-t10dif.c | 95 +-
5 files changed, 234 insertions(+), 2 deletions(-)
create mode 100644 crypto/crct10dif.c
diff --git a/crypto/Kconfig b/crypto/Kconfig
index 0e7a237..17b78e4 100644
--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -376,6 +376,15 @@ config CRYPTO_CRC32_PCLMUL
which will enable any routine to use the CRC-32-IEEE 802.3 checksum
and gain better performance as compared with the table implementation.
+config CRYPTO_CRCT10DIF
+ tristate CRCT10DIF algorithm
+ depends on CRC_T10DIF
+ select CRYPTO_HASH
+ help
+ CRC T10 Data Integrity Field computation is being cast as
+ a crypto transform. This allows for faster crc t10 diff
+ transforms to be used if they are available.
+
config CRYPTO_GHASH
tristate GHASH digest algorithm
select CRYPTO_GF128MUL
diff --git a/crypto/Makefile b/crypto/Makefile
index a8e9b0f..62af87d 100644
--- a/crypto/Makefile
+++ b/crypto/Makefile
@@ -83,6 +83,7 @@ obj-$(CONFIG_CRYPTO_ZLIB) += zlib.o
obj-$(CONFIG_CRYPTO_MICHAEL_MIC) += michael_mic.o
obj-$(CONFIG_CRYPTO_CRC32C) += crc32c.o
obj-$(CONFIG_CRYPTO_CRC32) += crc32.o
+obj-$(CONFIG_CRYPTO_CRCT10DIF) += crct10dif.o
obj-$(CONFIG_CRYPTO_AUTHENC) += authenc.o authencesn.o
obj-$(CONFIG_CRYPTO_LZO) += lzo.o
obj-$(CONFIG_CRYPTO_842) += 842.o
diff --git a/crypto/crct10dif.c b/crypto/crct10dif.c
new file mode 100644
index 000..246af93
--- /dev/null
+++ b/crypto/crct10dif.c
@@ -0,0 +1,126 @@
+/*
+ * Cryptographic API.
+ *
+ * T10 Data Integrity Field CRC16 Crypto Transform
+ *
+ * Copyright (C) 2013 Intel Corporation
+ * Author: Tim Chen tim.c.c...@linux.intel.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+#include linux/types.h
+#include linux/module.h
+#include linux/crc-t10dif.h
+#include crypto/internal/hash.h
+#include linux/init.h
+#include linux/string.h
+#include linux/kernel.h
+
+struct chksum_desc_ctx {
+ __u16 crc;
+};
+
+/*
+ * Steps through buffer one byte at at time, calculates reflected
+ * crc using table.
+ */
+
+static int chksum_init(struct shash_desc *desc)
+{
+ struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
+
+ ctx-crc = 0;
+
+ return 0;
+}
+
+static int chksum_update(struct shash_desc *desc, const u8 *data,
+unsigned int length)
+{
+ struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
+
+ ctx-crc = crc_t10dif_generic(ctx-crc, data, length);
+ return 0;
+}
+
+static int chksum_final(struct shash_desc *desc, u8 *out)
+{
+ struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
+
+ *(__u16 *)out = ctx-crc;
+ return 0;
+}
+
+static int __chksum_finup(__u16 *crcp, const u8 *data, unsigned int len,
+ u8 *out)
+{
+ *(__u16 *)out = crc_t10dif_generic(*crcp, data, len);
+ return 0;
+}
+
+static int chksum_finup(struct shash_desc *desc, const u8 *data,
+ unsigned int len, u8 *out)
+{
+ struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
+
+ return __chksum_finup(ctx-crc, data, len, out);
+}
+
+static int chksum_digest(struct shash_desc *desc, const u8 *data,
+unsigned int length, u8 *out)
+{
+ struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
+
+ return __chksum_finup(ctx-crc, data, length, out);
+}
+
+static struct shash_alg alg = {
+ .digestsize = CRC_T10DIF_DIGEST_SIZE,
+ .init = chksum_init,
+ .update = chksum_update,
+ .final = chksum_final,
+ .finup = chksum_finup,
+ .digest = chksum_digest,
+ .descsize = sizeof(struct chksum_desc_ctx),
+
[PATCH v3 3/4] Glue code to cast accelerated CRCT10DIF assembly as a crypto transform
Glue code that plugs the PCLMULQDQ accelerated CRC T10 DIF hash into the
crypto framework. The config CRYPTO_CRCT10DIF_PCLMUL should be turned
on to enable the feature. The crc_t10dif crypto library function will
use this faster algorithm when crct10dif_pclmul module is loaded.
Signed-off-by: Tim Chen tim.c.c...@linux.intel.com
---
arch/x86/crypto/Makefile| 2 +
arch/x86/crypto/crct10dif-pclmul_glue.c | 157
crypto/Kconfig | 11 +++
3 files changed, 170 insertions(+)
create mode 100644 arch/x86/crypto/crct10dif-pclmul_glue.c
diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile
index 03cd731..d544a66 100644
--- a/arch/x86/crypto/Makefile
+++ b/arch/x86/crypto/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CRYPTO_SHA1_SSSE3) += sha1-ssse3.o
obj-$(CONFIG_CRYPTO_CRC32_PCLMUL) += crc32-pclmul.o
obj-$(CONFIG_CRYPTO_SHA256_SSSE3) += sha256-ssse3.o
obj-$(CONFIG_CRYPTO_SHA512_SSSE3) += sha512-ssse3.o
+obj-$(CONFIG_CRYPTO_CRCT10DIF_PCLMUL) += crct10dif-pclmul.o
# These modules require assembler to support AVX.
ifeq ($(avx_supported),yes)
@@ -70,3 +71,4 @@ crc32c-intel-$(CONFIG_64BIT) += crc32c-pcl-intel-asm_64.o
crc32-pclmul-y := crc32-pclmul_asm.o crc32-pclmul_glue.o
sha256-ssse3-y := sha256-ssse3-asm.o sha256-avx-asm.o sha256-avx2-asm.o
sha256_ssse3_glue.o
sha512-ssse3-y := sha512-ssse3-asm.o sha512-avx-asm.o sha512-avx2-asm.o
sha512_ssse3_glue.o
+crct10dif-pclmul-y := crct10dif-pcl-asm_64.o crct10dif-pclmul_glue.o
diff --git a/arch/x86/crypto/crct10dif-pclmul_glue.c
b/arch/x86/crypto/crct10dif-pclmul_glue.c
new file mode 100644
index 000..3c0abd3
--- /dev/null
+++ b/arch/x86/crypto/crct10dif-pclmul_glue.c
@@ -0,0 +1,157 @@
+/*
+ * Cryptographic API.
+ *
+ * T10 Data Integrity Field CRC16 Crypto Transform using PCLMULQDQ Instructions
+ *
+ * Copyright (C) 2013 Intel Corporation
+ * Author: Tim Chen tim.c.c...@linux.intel.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+#include linux/types.h
+#include linux/module.h
+#include linux/crc-t10dif.h
+#include crypto/internal/hash.h
+#include linux/init.h
+#include linux/string.h
+#include linux/kernel.h
+#include asm/i387.h
+#include asm/cpufeature.h
+#include asm/cpu_device_id.h
+
+asmlinkage __u16 crc_t10dif_pcl(__u16 crc, const unsigned char *buf,
+ size_t len);
+
+struct chksum_desc_ctx {
+ __u16 crc;
+};
+
+/*
+ * Steps through buffer one byte at at time, calculates reflected
+ * crc using table.
+ */
+
+static int chksum_init(struct shash_desc *desc)
+{
+ struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
+
+ ctx-crc = 0;
+
+ return 0;
+}
+
+static int chksum_update(struct shash_desc *desc, const u8 *data,
+unsigned int length)
+{
+ struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
+
+ if (irq_fpu_usable()) {
+ kernel_fpu_begin();
+ ctx-crc = crc_t10dif_pcl(ctx-crc, data, length);
+ kernel_fpu_end();
+ } else
+ ctx-crc = crc_t10dif_generic(ctx-crc, data, length);
+ return 0;
+}
+
+static int chksum_final(struct shash_desc *desc, u8 *out)
+{
+ struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
+
+ *(__u16 *)out = ctx-crc;
+ return 0;
+}
+
+static int __chksum_finup(__u16 *crcp, const u8 *data, unsigned int len,
+ u8 *out)
+{
+ if (irq_fpu_usable()) {
+ kernel_fpu_begin();
+ *(__u16 *)out = crc_t10dif_pcl(*crcp, data, len);
+ kernel_fpu_end();
+ } else
+ *(__u16 *)out = crc_t10dif_generic(*crcp, data, len);
+ return 0;
+}
+
+static int chksum_finup(struct shash_desc *desc, const u8 *data,
+ unsigned int len, u8 *out)
+{
+ struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
+
+ return __chksum_finup(ctx-crc, data, len, out);
+}
+
+static int chksum_digest(struct shash_desc *desc, const u8 *data,
+unsigned int length, u8 *out)
+{
+ struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
+
+ return __chksum_finup(ctx-crc, data, length, out);
+}
+
+static struct shash_alg alg = {
+ .digestsize =
[PATCH v3 4/4] Simple correctness and speed test for CRCT10DIF hash
These are simple tests to do sanity check of CRC T10 DIF hash. The
correctness of the transform can be checked with the command
modprobe tcrypt mode=47
The speed of the transform can be evaluated with the command
modprobe tcrypt mode=320
Set the cpu frequency to constant and turn turbo off when running the
speed test so the frequency governor will not tweak the frequency and
affects the measurements.
Signed-off-by: Tim Chen tim.c.c...@linux.intel.com
---
crypto/tcrypt.c | 8
crypto/testmgr.c | 10 ++
crypto/testmgr.h | 33 +
3 files changed, 51 insertions(+)
diff --git a/crypto/tcrypt.c b/crypto/tcrypt.c
index 24ea7df..5e95722 100644
--- a/crypto/tcrypt.c
+++ b/crypto/tcrypt.c
@@ -1174,6 +1174,10 @@ static int do_test(int m)
ret += tcrypt_test(ghash);
break;
+ case 47:
+ ret += tcrypt_test(crct10dif);
+ break;
+
case 100:
ret += tcrypt_test(hmac(md5));
break;
@@ -1498,6 +1502,10 @@ static int do_test(int m)
test_hash_speed(crc32c, sec, generic_hash_speed_template);
if (mode 300 mode 400) break;
+ case 320:
+ test_hash_speed(crct10dif, sec, generic_hash_speed_template);
+ if (mode 300 mode 400) break;
+
case 399:
break;
diff --git a/crypto/testmgr.c b/crypto/testmgr.c
index 3807084..b165316 100644
--- a/crypto/testmgr.c
+++ b/crypto/testmgr.c
@@ -1944,6 +1944,16 @@ static const struct alg_test_desc alg_test_descs[] = {
}
}
}, {
+ .alg = crct10dif,
+ .test = alg_test_hash,
+ .fips_allowed = 1,
+ .suite = {
+ .hash = {
+ .vecs = crct10dif_tv_template,
+ .count = CRCT10DIF_TEST_VECTORS
+ }
+ }
+ }, {
.alg = cryptd(__driver-cbc-aes-aesni),
.test = alg_test_null,
.fips_allowed = 1,
diff --git a/crypto/testmgr.h b/crypto/testmgr.h
index d503660..56916d0 100644
--- a/crypto/testmgr.h
+++ b/crypto/testmgr.h
@@ -450,6 +450,39 @@ static struct hash_testvec rmd320_tv_template[] = {
}
};
+#define CRCT10DIF_TEST_VECTORS 3
+static struct hash_testvec crct10dif_tv_template[] = {
+ {
+ .plaintext = abc,
+ .psize = 3,
+#ifdef __LITTLE_ENDIAN
+ .digest = \x3b\x44,
+#else
+ .digest = \x44\x3b,
+#endif
+ }, {
+ .plaintext = 1234567890123456789012345678901234567890
+123456789012345678901234567890123456789,
+ .psize = 79,
+#ifdef __LITTLE_ENDIAN
+ .digest = \x70\x4b,
+#else
+ .digest = \x4b\x70,
+#endif
+ }, {
+ .plaintext =
+ abcd,
+ .psize = 56,
+#ifdef __LITTLE_ENDIAN
+ .digest = \xe3\x9c,
+#else
+ .digest = \x9c\xe3,
+#endif
+ .np = 2,
+ .tap= { 28, 28 }
+ }
+};
+
/*
* SHA1 test vectors from from FIPS PUB 180-1
* Long vector from CAVS 5.0
--
1.7.11.7
--
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[PATCH v3 2/4] Accelerated CRC T10 DIF computation with PCLMULQDQ instruction
This is the x86_64 CRC T10 DIF transform accelerated with the PCLMULQDQ instructions. Details discussing the implementation can be found in the paper: Fast CRC Computation for Generic Polynomials Using PCLMULQDQ Instruction http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf Signed-off-by: Tim Chen tim.c.c...@linux.intel.com --- arch/x86/crypto/crct10dif-pcl-asm_64.S | 643 + 1 file changed, 643 insertions(+) create mode 100644 arch/x86/crypto/crct10dif-pcl-asm_64.S diff --git a/arch/x86/crypto/crct10dif-pcl-asm_64.S b/arch/x86/crypto/crct10dif-pcl-asm_64.S new file mode 100644 index 000..35e9756 --- /dev/null +++ b/arch/x86/crypto/crct10dif-pcl-asm_64.S @@ -0,0 +1,643 @@ + +# Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions +# +# Copyright (c) 2013, Intel Corporation +# +# Authors: +# Erdinc Ozturk erdinc.ozt...@intel.com +# Vinodh Gopal vinodh.go...@intel.com +# James Guilford james.guilf...@intel.com +# Tim Chen tim.c.c...@linux.intel.com +# +# This software is available to you under a choice of one of two +# licenses. You may choose to be licensed under the terms of the GNU +# General Public License (GPL) Version 2, available from the file +# COPYING in the main directory of this source tree, or the +# OpenIB.org BSD license below: +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the +# distribution. +# +# * Neither the name of the Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# +# THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION AS IS AND ANY +# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# Function API: +# UINT16 crc_t10dif_pcl( +# UINT16 init_crc, //initial CRC value, 16 bits +# const unsigned char *buf, //buffer pointer to calculate CRC on +# UINT64 len //buffer length in bytes (64-bit data) +# ); +# +# Reference paper titled Fast CRC Computation for Generic +# Polynomials Using PCLMULQDQ Instruction +# URL: http://www.intel.com/content/dam/www/public/us/en/documents +# /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf +# +# + +#include linux/linkage.h + +.text + +#definearg1 %rdi +#definearg2 %rsi +#definearg3 %rdx + +#definearg1_low32 %edi + +ENTRY(crc_t10dif_pcl) +.align 16 + + # adjust the 16-bit initial_crc value, scale it to 32 bits + shl $16, arg1_low32 + + # Allocate Stack Space + mov %rsp, %rcx + sub $16*2, %rsp + # align stack to 16 byte boundary + and $~(0x10 - 1), %rsp + + # check if smaller than 256 + cmp $256, arg3 + + # for sizes less than 128, we can't fold 64B at a time... + jl _less_than_128 + + + # load the initial crc value + movdarg1_low32, %xmm10 # initial crc + + # crc value does not need to be byte-reflected, but it needs + # to be moved to the high part of the register. + # because data will be byte-reflected and will align with + # initial crc at correct place. + pslldq $12, %xmm10 + + movdqa SHUF_MASK(%rip), %xmm11 + # receive the initial 64B data, xor the initial crc value + movdqu 16*0(arg2), %xmm0 + movdqu 16*1(arg2), %xmm1 + movdqu 16*2(arg2), %xmm2 + movdqu 16*3(arg2), %xmm3 + movdqu 16*4(arg2), %xmm4 + movdqu 16*5(arg2), %xmm5 + movdqu 16*6(arg2), %xmm6 + movdqu 16*7(arg2), %xmm7 + + pshufb %xmm11,
Re: [PATCH v2 1/4] Wrap crc_t10dif function all to use crypto transform framework
On Tue, 2013-04-30 at 11:27 +0800, Herbert Xu wrote: On Mon, Apr 29, 2013 at 01:40:30PM -0700, Tim Chen wrote: If I allocate the transform under the mod init instead, how can I make sure that the fast version is already registered if I have it compiled in? It is not clear to me how that's done looking at the libcrc32c code. This is only an issue when everything is built-in to the kernel. In that case we could make the crc implementations register at a point earlier than device_initcall, but no earlier than subsys_initcall since that's where cryptomgr sits. I've spun version 3 of this patch series to address the concerns about version 2. The patches are sent separately. Thanks. Tim -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/5] bnx2fc: Bumped version to 1.0.14
On 05/01/2013 06:05 PM, James Bottomley wrote: On Fri, 2013-03-08 at 15:53 -0800, Bhanu Prakash Gollapudi wrote: On 03/08/2013 01:28 PM, Bhanu Prakash Gollapudi wrote: Signed-off-by: Bhanu Prakash Gollapudi bprak...@broadcom.com --- drivers/scsi/bnx2fc/bnx2fc.h |2 +- drivers/scsi/bnx2fc/bnx2fc_fcoe.c |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/bnx2fc/bnx2fc.h b/drivers/scsi/bnx2fc/bnx2fc.h index 676dba3..1ece6e9 100644 --- a/drivers/scsi/bnx2fc/bnx2fc.h +++ b/drivers/scsi/bnx2fc/bnx2fc.h @@ -64,7 +64,7 @@ #include bnx2fc_constants.h #define BNX2FC_NAME bnx2fc -#define BNX2FC_VERSION 1.0.13 +#define BNX2FC_VERSION 1.0.14 #define PFX bnx2fc: diff --git a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c index 1e852d6..9ab62da 100644 --- a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c +++ b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c @@ -22,7 +22,7 @@ DEFINE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu); #define DRV_MODULE_NAME bnx2fc #define DRV_MODULE_VERSION BNX2FC_VERSION -#define DRV_MODULE_RELDATE Dec 21, 2012 +#define DRV_MODULE_RELDATE Mar 08, 2012 James, I realized there was a typo in the date - 2012 instead of 2013. Please apply this patch instead. Sorry for the inconvenience. Signed-off-by: Bhanu Prakash Gollapudi bprak...@broadcom.com --- drivers/scsi/bnx2fc/bnx2fc.h |2 +- drivers/scsi/bnx2fc/bnx2fc_fcoe.c |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/bnx2fc/bnx2fc.h b/drivers/scsi/bnx2fc/bnx2fc.h index 676dba3..1ece6e9 100644 --- a/drivers/scsi/bnx2fc/bnx2fc.h +++ b/drivers/scsi/bnx2fc/bnx2fc.h @@ -64,7 +64,7 @@ #include bnx2fc_constants.h #define BNX2FC_NAMEbnx2fc -#define BNX2FC_VERSION1.0.13 +#define BNX2FC_VERSION1.0.14 #define PFXbnx2fc: diff --git a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c index 1e852d6..9ab62da 100644 --- a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c +++ b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c @@ -22,7 +22,7 @@ DEFINE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu); #define DRV_MODULE_NAMEbnx2fc #define DRV_MODULE_VERSIONBNX2FC_VERSION -#define DRV_MODULE_RELDATEDec 21, 2012 +#define DRV_MODULE_RELDATEMar 08, 2013 This doesn't actually apply ... your mailer has converted tabs to spaces. Since it's only a couple of lines, I fixed it up by hand this time ... James Thanks for taking care of this, James. Bhanu -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 4/5] scsi: ufs: rework link start-up process
On Tuesday, April 30, 2013, Sujit Reddy Thumma wrote:
On 4/30/2013 12:03 PM, Seungwon Jeon wrote:
On Monday, April 29, 2013, Sujit Reddy Thumma wrote:
On 4/29/2013 3:54 PM, Seungwon Jeon wrote:
On Monday, April 29, 2013, Sujit Reddy Thumma wrote:
On 4/26/2013 10:44 AM, Seungwon Jeon wrote:
On Thursday, April 25, 2013 , Sujit Reddy Thumma wrote:
On 4/24/2013 9:36 PM, Seungwon Jeon wrote:
Link start-up requires long time with multiphase handshakes
between UFS host and device. This affects driver's probe time.
This patch let link start-up run asynchronously.
And completion time of uic command is defined to avoid a
permanent wait.
I have similar patch posted few days back scsi: ufs: Generalize UFS
Interconnect Layer (UIC) command support which does a bit more (mutex,
error handling) than what is done here. Can that be used/improved?
I completed to check your patch to compare it now.
Though it's just my thought, the patch I sent is more intuitive on the
whole.
Considering other dme operations which I have introduced, it looks like
matched.
There are lot of code duplications you might want to minimize building a
DME command.
Of course, you may disagree.
But I think the part of mutex is needed. It's a good point.
In case of error handling, I didn't catch nothing special.
Rather, handling link lost case is not proper.
When ufs host meets link lost status, it should start with dme_reset
not retried dme_linkstartup.
In section 7.2.1 (Host Controller Initialization) of JESD223A UFS HCI
v1.1 specification I find this -
6. Sent DME_LINKSTARTUP command to start the link startup procedure
9. Check value of HCS.DP and make sure that there is a device attached
to the Link. If presence of a device is detected, go to step 10;
otherwise, resend the DME_LINKSTARTUP command after IS.ULLS has been set
to 1 (Go to step 6). IS.ULLS equal 1 indicates that the UFS Device is
ready for a link startup.
Going by the spec. just retrying with DME_LINKSTARTUP is correct.
Yes, as you quoted above, HCI standard mentions that.
Also, the following is mentioned.
UIC Link Lost Status (ULLS) corresponds to the UniPro DME_LINKLOST.ind
I just referred unipro specification.
When DME_LINKLOST.ind is generated, this affects the Link is put in the
LinkLost state.
Unipro spec says that DME User must apply a DME_RESET to redo the boot
sequence.
If there is misunderstood meaning and I have something to miss, we can
discuss more.
Please let me know.
Yes, it looks like the two specs. are conflicting each other. I guess we
need to take this to Jedec for clarification. Meanwhile, to be on safe
side can we add a retry mechanism that does ufshcd_hba_enable() before
sending DME_LINKSTARTUP again? This way we can be sure that the
DME_RESET and DME_ENABLE is taken care by the host reset itself.
Yes, If the latter case is applied, 'ufshcd_hba_enable' will be start entry
for retry.
Further, IS.ULLS could be handled through the interrupt instead of polling
for retry mechanism?
Agree, but the interrupt handling will be tailored for two things - 1)
bootup case where scsi_scan_host is not yet called. 2) the case where
link lost occurred after a long time after bootup where there is no need
to do scsi_scan_host again.
Yes, it could be another patch.
In addition, it doesn't say what happens if IS.ULLS never sets to 1.
Probably, the case which never happens.
And it would be good if link start-up procedure is done in separate
process, not in driver probe.
True.
If it's all right with you, I'd like to update lock mechanism for uic
command.
I can add your signed-off. Please let me know your opinion.
I would like to get a third opinion as both the patches needs
modifications.
Some comments below:
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
drivers/scsi/ufs/ufshcd.c | 114
+---
drivers/scsi/ufs/ufshcd.h |6 ++-
2 files changed, 89 insertions(+), 31 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index efe2256..76ff332 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -38,6 +38,7 @@
#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
UTP_TASK_REQ_COMPL |\
UFSHCD_ERROR_MASK)
+#define UIC_CMD_TIMEOUT 100
enum {
UFSHCD_MAX_CHANNEL = 0,
@@ -357,13 +358,15 @@ static inline void
ufshcd_hba_capabilities(struct ufs_hba *hba)
}
/**
- * ufshcd_send_uic_command - Send UIC commands to unipro layers
+ * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
* @hba: per adapter instance
* @uic_command: UIC command
*/
static inline void
-ufshcd_send_uic_command(struct ufs_hba *hba,
