Re: [PATCH 3/3] scsi:ufs:add hi3660 ufs driver code
On Sat, Jun 10, 2017 at 9:21 AM, butao wrote:
> add hi3660 ufs driver code
>
> Signed-off-by: Geng Jianfeng
> Signed-off-by: Bu Tao
> Signed-off-by: Zang Leigang
> Signed-off-by: Yu Jianfeng
> ---
> drivers/scsi/ufs/Kconfig | 8 +
> drivers/scsi/ufs/Makefile | 1 +
> drivers/scsi/ufs/ufs-hi3660.c | 715
> ++
> drivers/scsi/ufs/ufs-hi3660.h | 170 ++
> 4 files changed, 894 insertions(+)
> mode change 100644 => 100755 drivers/scsi/ufs/Kconfig
> mode change 100644 => 100755 drivers/scsi/ufs/Makefile
> create mode 100755 drivers/scsi/ufs/ufs-hi3660.c
> create mode 100755 drivers/scsi/ufs/ufs-hi3660.h
mode 755? Err.
>
> diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig
> old mode 100644
> new mode 100755
> index e27b4d4e6ae2..119604ea0aae
> --- a/drivers/scsi/ufs/Kconfig
> +++ b/drivers/scsi/ufs/Kconfig
> @@ -80,6 +80,14 @@ config SCSI_UFSHCD_PLATFORM
>
> If unsure, say N.
>
> +config SCSI_UFS_HI3660
> + tristate "Hisilicon Hi3660 UFS controller platform driver"
> + depends on (ARCH_HISI || COMPILE_TEST) && SCSI_UFSHCD_PLATFORM
> + help
> + This selects the Hisilicon HI3660 additions to UFSHCD platform
> driver.
> +
> + If unsure, say N.
> +
Please also add "SCSI_UFS_HI3660=y" into arch/arm64/configs/defconfig,
and submit as a separate patch.
-Guodong
> config SCSI_UFS_DWC_TC_PLATFORM
> tristate "DesignWare platform support using a G210 Test Chip"
> depends on SCSI_UFSHCD_PLATFORM
> diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile
> old mode 100644
> new mode 100755
> index 6e77cb0bfee9..ae880189f018
> --- a/drivers/scsi/ufs/Makefile
> +++ b/drivers/scsi/ufs/Makefile
> @@ -2,6 +2,7 @@
> obj-$(CONFIG_SCSI_UFS_DWC_TC_PCI) += tc-dwc-g210-pci.o ufshcd-dwc.o
> tc-dwc-g210.o
> obj-$(CONFIG_SCSI_UFS_DWC_TC_PLATFORM) += tc-dwc-g210-pltfrm.o ufshcd-dwc.o
> tc-dwc-g210.o
> obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o
> +obj-$(CONFIG_SCSI_UFS_HI3660) += ufs-hi3660.o
> obj-$(CONFIG_SCSI_UFSHCD) += ufshcd.o
> obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o
> obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o
> diff --git a/drivers/scsi/ufs/ufs-hi3660.c b/drivers/scsi/ufs/ufs-hi3660.c
> new file mode 100755
> index ..ccbcb01f6863
> --- /dev/null
> +++ b/drivers/scsi/ufs/ufs-hi3660.c
> @@ -0,0 +1,715 @@
> +/*
> + * Copyright (c) 2016-2017 Linaro Ltd.
> + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "ufshcd.h"
> +#include "ufshcd-pltfrm.h"
> +#include "unipro.h"
> +#include "ufs-hi3660.h"
> +#include "ufshci.h"
> +
> +static int ufs_hi3660_check_hibern8(struct ufs_hba *hba)
> +{
> + int err;
> + u32 tx_fsm_val_0;
> + u32 tx_fsm_val_1;
> + unsigned long timeout = jiffies +
> msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
> +
> + do {
> + err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
> 0),
> + &tx_fsm_val_0);
> + err |= ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
> 1),
> + &tx_fsm_val_1);
> + if (err || (tx_fsm_val_0 == TX_FSM_HIBERN8 && tx_fsm_val_1 ==
> TX_FSM_HIBERN8))
> + break;
> +
> + /* sleep for max. 200us */
> + usleep_range(100, 200);
> + } while (time_before(jiffies, timeout));
> +
> + /*
> +* we might have scheduled out for long during polling so
> +* check the state again.
> +*/
> + if (time_after(jiffies, timeout)) {
> + err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
> 0),
> +&tx_fsm_val_0);
> + err |= ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
> 1),
> +&tx_fsm_val_1);
> + }
> +
> + if (err) {
> + dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
> + __func__, err);
> + } else if (tx_fsm_val_0 != TX_FSM_HIBERN8 || tx_fsm_val_1 !=
> TX_FSM_HIBERN8) {
> + err = -1;
> + dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d,
> lane1 = %d\n",
> + __func__, tx_fsm_val_0, tx_fsm_val_1);
> + }
> +
> + return err;
> +}
> +
> +static void ufs_hi3660_clk_init(struct ufs_hba *hba)
> +{
> + struct ufs_hi3660_host *host = ufshcd_get_variant(hba);
> +
> + ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_
Re: [PATCH 2/3] scsi:ufs:add ufs node&reset property for hi3660
Bu Tao,
One other issue: the 'sender' of your patchset is "butao". For
upstreaming purpose, it is recommended to use your full name, in
"first name" + "Surname" format. In your case, you need to specify it
in your commit message:
$ git commit --amend --author="Bu Tao "
You may also want to add that to your .gitconfig to save your future effort.
[user]
name = Bu Tao
email = bu...@hisilicon.com
-Guodong
On Sat, Jun 10, 2017 at 10:44 AM, Guodong Xu wrote:
> Bu Tao,
>
> 1. Subject line of this patch goes something like "arm64: dts: hi3660:
> add ufs support xxx"
>
> 2. Have you run "./scripts/get_maintainer.pl *.patch" to get the
> correct maintainers to include into your patch review?
> I don't think so. Because this is a dts change, however in your
> email's to/ cc/, there is no DTS reviewers being included. Please fix
> that and resend.
>
> 3. I suppose before sending your patchset, you already tested it
> against tip kernel. For example, where your dts change can be applied?
> If they apply to my dts patchset [1], please mention it in your commit
> message. If they don't, then please tell us where.
>
> [1]. http://www.spinics.net/lists/devicetree/msg178303.html
>
> 4. Re-send, send them as "git format-patch -v2".
>
> -Guodong
>
> On Sat, Jun 10, 2017 at 9:20 AM, butao wrote:
>> add ufs node for hi3660
>>
>> Signed-off-by: Bu Tao
>> ---
>> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 20
>> 1 file changed, 20 insertions(+)
>> mode change 100644 => 100755 arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> old mode 100644
>> new mode 100755
>> index 3983086bd67b..4ba9cec43d94
>> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> @@ -141,6 +141,26 @@
>> #size-cells = <2>;
>> ranges;
>>
>> +ufs: ufs@ff3b {
>> +compatible = "jedec,ufs-1.1",
>> "hisilicon,hi3660-ufs";
>> +reg = <0x0 0xff3b 0x0 0x1000>, /* 0: HCI
>> standard */
>> + <0x0 0xff3b1000 0x0 0x1000>; /* 1: UFS
>> SYS CTRL */
>> +interrupt-parent = <&gic>;
>> +interrupts = <0 278 4>;
>> +clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
>> + <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
>> +clock-names = "clk_ref", "clk_phy";
>> +freq-table-hz = <0 0>, <0 0>;
>> +resets = <&crg_rst 0x84 12>, /* offset:
>> 0x84; bit: 12 */
>> + <&crg_rst 0x84 7>;/* offset:
>> 0x84; bit: 7 */
>> +reset-names = "rst", "assert";
>> +ufs-hi3660-use-rate-B;
>> +ufs-hi3660-broken-fastauto;
>> +ufs-hi3660-use-HS-GEAR3;
>> +ufs-hi3660-broken-clk-gate-bypass;
>> +status = "ok";
>> +};
>> +
>> fixed_uart5: fixed_19_2M {
>> compatible = "fixed-clock";
>> #clock-cells = <0>;
>> --
>> 2.11.GIT
>>
Re: [PATCH 2/3] scsi:ufs:add ufs node&reset property for hi3660
On Sat, Jun 10, 2017 at 9:20 AM, butao wrote:
> add ufs node for hi3660
>
> Signed-off-by: Bu Tao
> ---
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 20
> 1 file changed, 20 insertions(+)
> mode change 100644 => 100755 arch/arm64/boot/dts/hisilicon/hi3660.dtsi
Mode change 755? Err.
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> old mode 100644
> new mode 100755
> index 3983086bd67b..4ba9cec43d94
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -141,6 +141,26 @@
> #size-cells = <2>;
> ranges;
>
> +ufs: ufs@ff3b {
> +compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs";
> +reg = <0x0 0xff3b 0x0 0x1000>, /* 0: HCI
> standard */
> + <0x0 0xff3b1000 0x0 0x1000>; /* 1: UFS
> SYS CTRL */
> +interrupt-parent = <&gic>;
> +interrupts = <0 278 4>;
> +clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
> + <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
> +clock-names = "clk_ref", "clk_phy";
> +freq-table-hz = <0 0>, <0 0>;
> +resets = <&crg_rst 0x84 12>, /* offset:
> 0x84; bit: 12 */
> + <&crg_rst 0x84 7>;/* offset:
> 0x84; bit: 7 */
> +reset-names = "rst", "assert";
> +ufs-hi3660-use-rate-B;
> +ufs-hi3660-broken-fastauto;
> +ufs-hi3660-use-HS-GEAR3;
> +ufs-hi3660-broken-clk-gate-bypass;
> +status = "ok";
> +};
> +
> fixed_uart5: fixed_19_2M {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> --
> 2.11.GIT
>
Re: [PATCH 2/3] scsi:ufs:add ufs node&reset property for hi3660
Bu Tao,
1. Subject line of this patch goes something like "arm64: dts: hi3660:
add ufs support xxx"
2. Have you run "./scripts/get_maintainer.pl *.patch" to get the
correct maintainers to include into your patch review?
I don't think so. Because this is a dts change, however in your
email's to/ cc/, there is no DTS reviewers being included. Please fix
that and resend.
3. I suppose before sending your patchset, you already tested it
against tip kernel. For example, where your dts change can be applied?
If they apply to my dts patchset [1], please mention it in your commit
message. If they don't, then please tell us where.
[1]. http://www.spinics.net/lists/devicetree/msg178303.html
4. Re-send, send them as "git format-patch -v2".
-Guodong
On Sat, Jun 10, 2017 at 9:20 AM, butao wrote:
> add ufs node for hi3660
>
> Signed-off-by: Bu Tao
> ---
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 20
> 1 file changed, 20 insertions(+)
> mode change 100644 => 100755 arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> old mode 100644
> new mode 100755
> index 3983086bd67b..4ba9cec43d94
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -141,6 +141,26 @@
> #size-cells = <2>;
> ranges;
>
> +ufs: ufs@ff3b {
> +compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs";
> +reg = <0x0 0xff3b 0x0 0x1000>, /* 0: HCI
> standard */
> + <0x0 0xff3b1000 0x0 0x1000>; /* 1: UFS
> SYS CTRL */
> +interrupt-parent = <&gic>;
> +interrupts = <0 278 4>;
> +clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
> + <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
> +clock-names = "clk_ref", "clk_phy";
> +freq-table-hz = <0 0>, <0 0>;
> +resets = <&crg_rst 0x84 12>, /* offset:
> 0x84; bit: 12 */
> + <&crg_rst 0x84 7>;/* offset:
> 0x84; bit: 7 */
> +reset-names = "rst", "assert";
> +ufs-hi3660-use-rate-B;
> +ufs-hi3660-broken-fastauto;
> +ufs-hi3660-use-HS-GEAR3;
> +ufs-hi3660-broken-clk-gate-bypass;
> +status = "ok";
> +};
> +
> fixed_uart5: fixed_19_2M {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> --
> 2.11.GIT
>
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[PATCH 2/3] scsi:ufs:add ufs node&reset property for hi3660
add ufs node for hi3660
Signed-off-by: Bu Tao
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 20
1 file changed, 20 insertions(+)
mode change 100644 => 100755 arch/arm64/boot/dts/hisilicon/hi3660.dtsi
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
old mode 100644
new mode 100755
index 3983086bd67b..4ba9cec43d94
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -141,6 +141,26 @@
#size-cells = <2>;
ranges;
+ufs: ufs@ff3b {
+compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs";
+reg = <0x0 0xff3b 0x0 0x1000>, /* 0: HCI
standard */
+ <0x0 0xff3b1000 0x0 0x1000>; /* 1: UFS SYS
CTRL */
+interrupt-parent = <&gic>;
+interrupts = <0 278 4>;
+clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
+clock-names = "clk_ref", "clk_phy";
+freq-table-hz = <0 0>, <0 0>;
+resets = <&crg_rst 0x84 12>, /* offset:
0x84; bit: 12 */
+ <&crg_rst 0x84 7>;/* offset:
0x84; bit: 7 */
+reset-names = "rst", "assert";
+ufs-hi3660-use-rate-B;
+ufs-hi3660-broken-fastauto;
+ufs-hi3660-use-HS-GEAR3;
+ufs-hi3660-broken-clk-gate-bypass;
+status = "ok";
+};
+
fixed_uart5: fixed_19_2M {
compatible = "fixed-clock";
#clock-cells = <0>;
--
2.11.GIT
[PATCH 3/3] scsi:ufs:add hi3660 ufs driver code
add hi3660 ufs driver code
Signed-off-by: Geng Jianfeng
Signed-off-by: Bu Tao
Signed-off-by: Zang Leigang
Signed-off-by: Yu Jianfeng
---
drivers/scsi/ufs/Kconfig | 8 +
drivers/scsi/ufs/Makefile | 1 +
drivers/scsi/ufs/ufs-hi3660.c | 715 ++
drivers/scsi/ufs/ufs-hi3660.h | 170 ++
4 files changed, 894 insertions(+)
mode change 100644 => 100755 drivers/scsi/ufs/Kconfig
mode change 100644 => 100755 drivers/scsi/ufs/Makefile
create mode 100755 drivers/scsi/ufs/ufs-hi3660.c
create mode 100755 drivers/scsi/ufs/ufs-hi3660.h
diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig
old mode 100644
new mode 100755
index e27b4d4e6ae2..119604ea0aae
--- a/drivers/scsi/ufs/Kconfig
+++ b/drivers/scsi/ufs/Kconfig
@@ -80,6 +80,14 @@ config SCSI_UFSHCD_PLATFORM
If unsure, say N.
+config SCSI_UFS_HI3660
+ tristate "Hisilicon Hi3660 UFS controller platform driver"
+ depends on (ARCH_HISI || COMPILE_TEST) && SCSI_UFSHCD_PLATFORM
+ help
+ This selects the Hisilicon HI3660 additions to UFSHCD platform driver.
+
+ If unsure, say N.
+
config SCSI_UFS_DWC_TC_PLATFORM
tristate "DesignWare platform support using a G210 Test Chip"
depends on SCSI_UFSHCD_PLATFORM
diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile
old mode 100644
new mode 100755
index 6e77cb0bfee9..ae880189f018
--- a/drivers/scsi/ufs/Makefile
+++ b/drivers/scsi/ufs/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_SCSI_UFS_DWC_TC_PCI) += tc-dwc-g210-pci.o ufshcd-dwc.o
tc-dwc-g210.o
obj-$(CONFIG_SCSI_UFS_DWC_TC_PLATFORM) += tc-dwc-g210-pltfrm.o ufshcd-dwc.o
tc-dwc-g210.o
obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o
+obj-$(CONFIG_SCSI_UFS_HI3660) += ufs-hi3660.o
obj-$(CONFIG_SCSI_UFSHCD) += ufshcd.o
obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o
obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o
diff --git a/drivers/scsi/ufs/ufs-hi3660.c b/drivers/scsi/ufs/ufs-hi3660.c
new file mode 100755
index ..ccbcb01f6863
--- /dev/null
+++ b/drivers/scsi/ufs/ufs-hi3660.c
@@ -0,0 +1,715 @@
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "ufshcd.h"
+#include "ufshcd-pltfrm.h"
+#include "unipro.h"
+#include "ufs-hi3660.h"
+#include "ufshci.h"
+
+static int ufs_hi3660_check_hibern8(struct ufs_hba *hba)
+{
+ int err;
+ u32 tx_fsm_val_0;
+ u32 tx_fsm_val_1;
+ unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
+
+ do {
+ err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),
+ &tx_fsm_val_0);
+ err |= ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
1),
+ &tx_fsm_val_1);
+ if (err || (tx_fsm_val_0 == TX_FSM_HIBERN8 && tx_fsm_val_1 ==
TX_FSM_HIBERN8))
+ break;
+
+ /* sleep for max. 200us */
+ usleep_range(100, 200);
+ } while (time_before(jiffies, timeout));
+
+ /*
+* we might have scheduled out for long during polling so
+* check the state again.
+*/
+ if (time_after(jiffies, timeout)) {
+ err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),
+&tx_fsm_val_0);
+ err |= ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
1),
+&tx_fsm_val_1);
+ }
+
+ if (err) {
+ dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
+ __func__, err);
+ } else if (tx_fsm_val_0 != TX_FSM_HIBERN8 || tx_fsm_val_1 !=
TX_FSM_HIBERN8) {
+ err = -1;
+ dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1
= %d\n",
+ __func__, tx_fsm_val_0, tx_fsm_val_1);
+ }
+
+ return err;
+}
+
+static void ufs_hi3660_clk_init(struct ufs_hba *hba)
+{
+ struct ufs_hi3660_host *host = ufshcd_get_variant(hba);
+
+ ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
+ if (ufs_sys_ctrl_readl(host, PHY_CLK_CTRL) & BIT_SYSCTRL_REF_CLOCK_EN)
+ mdelay(1);
+ /* use abb clk */
+ ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_SRC_SEl, UFS_SYSCTRL);
+ ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_ISO_EN, PHY_ISO_EN);
+ /* open mphy ref clk */
+ ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
+}
+
+static void ufs_hi3660_soc_init(struct ufs_hba *hba)
+{
+
[PATCH 1/3] scsi:ufs:add AHIT for hi3660 ufs
add Auto-Hibernate Idle Timer value for hi3660 ufs
Signed-off-by: Bu Tao
Signed-off-by: Geng Jianfeng
Signed-off-by: Zang Leigang
Signed-off-by: Yu Jianfeng
---
drivers/scsi/ufs/ufshci.h | 3 +++
1 file changed, 3 insertions(+)
mode change 100644 => 100755 drivers/scsi/ufs/ufshci.h
diff --git a/drivers/scsi/ufs/ufshci.h b/drivers/scsi/ufs/ufshci.h
old mode 100644
new mode 100755
index f60145d4a66e..5ab9dfe4280e
--- a/drivers/scsi/ufs/ufshci.h
+++ b/drivers/scsi/ufs/ufshci.h
@@ -151,6 +151,9 @@ enum {
CONTROLLER_FATAL_ERROR |\
SYSTEM_BUS_FATAL_ERROR)
+/* AHIT - Auto-Hibernate Idle Timer */
+#define UFS_AHIT_AH8ITV_MASK 0x3FF
+
/* HCS - Host Controller Status 30h */
#define DEVICE_PRESENT UFS_BIT(0)
#define UTP_TRANSFER_REQ_LIST_READYUFS_BIT(1)
--
2.11.GIT
Re: [PATCH 01/15] qla2xxx: Combine Active command arrays.
Hi Bart,
> On Jun 7, 2017, at 3:45 PM, Bart Van Assche
> wrote:
>
> On Wed, 2017-06-07 at 14:43 -0700, Himanshu Madhani wrote:
>> +enum {
>> +TYPE_SRB,
>> +TYPE_TGT_CMD,
>> +};
>> +
>> typedef struct srb {
>> +/*
>> + * Do not move cmd_type field, it needs to
>> + * line up with qla_tgt_cmd->cmd_type
>> + */
>> +uint8_t cmd_type;
>> +uint8_t pad[3];
>> atomic_t ref_count;
>> struct fc_port *fcport;
>> struct scsi_qla_host *vha;
>
> [ ... ]
>
>> struct qla_tgt_cmd {
>> +/*
>> + * Do not move cmd_type field. it needs to line up with srb->cmd_type
>> + */
>> +uint8_t cmd_type;
>> +uint8_t pad[7];
>> struct se_cmd se_cmd;
>> struct fc_port *sess;
>> int state;
>
> Hello Quinn and Himanshu,
>
> Sorry but this is really inelegant. Have you considered the following?
> - Keep the existing srb and qla_tgt_cmd data structures.
> - Introduce a new data structure with enum cmd_type as the first member and
> a union of struct srb and struct qla_tgt_cmd as the second member.
> - Use __attribute__((aligned(...))) to express alignment requirements instead
> of explicitly inserting padding bytes.
>
> With that approach no casts are needed to convert a pointer to the new data
> structure into a struct srb or struct qla_tgt_cmd pointer - all that will be
> needed is to take the address of the appropriate member of the union.
>
> Thanks,
>
> Bart.
We are working on addressing this review comment. We’ll send it as a separate
patch once we run through our regression test cycle.
Thanks,
- Himanshu
Re: [PATCH 2/3] target: Add TARGET_SCF_LOOKUP_LUN_FROM_TAG support for ABORT_TASK
On 06/08/17 22:52, Nicholas A. Bellinger wrote: > Because qla2xxx doesn't reuse tags, it's not a problem since it's the > only consumer of TARGET_SCF_LOOKUP_LUN_FROM_TAG. Hello Nic, Can you clarify this? Since all target drivers and also the target core use a finite number of bits to represent tags, tags *will* be reused sooner or later. Bart.
patch "scsi: ibmvscsi_tgt: remove use of class_attrs" added to driver-core-next
This is a note to let you know that I've just added the patch titled
scsi: ibmvscsi_tgt: remove use of class_attrs
to my driver-core git tree which can be found at
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git
in the driver-core-next branch.
The patch will show up in the next release of the linux-next tree
(usually sometime within the next 24 hours during the week.)
The patch will also be merged in the next major kernel release
during the merge window.
If you have any questions about this process, please let me know.
>From f62014fcb9e4af6267dce6e3bf5dc40fdc58f255 Mon Sep 17 00:00:00 2001
From: Greg Kroah-Hartman
Date: Thu, 8 Jun 2017 10:12:37 +0200
Subject: scsi: ibmvscsi_tgt: remove use of class_attrs
The class_attrs pointer is going away and it's not even being used in
this driver, so just remove it entirely.
Acked-by: "Bryant G. Ly"
Cc: Michael Cyr
Cc: "James E.J. Bottomley"
Cc: "Martin K. Petersen"
Cc:
Cc:
Signed-off-by: Greg Kroah-Hartman
---
drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c
b/drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c
index d390325c99ec..b480878e3258 100644
--- a/drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c
+++ b/drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c
@@ -3915,10 +3915,6 @@ static const struct target_core_fabric_ops ibmvscsis_ops
= {
static void ibmvscsis_dev_release(struct device *dev) {};
-static struct class_attribute ibmvscsis_class_attrs[] = {
- __ATTR_NULL,
-};
-
static struct device_attribute dev_attr_system_id =
__ATTR(system_id, S_IRUGO, system_id_show, NULL);
@@ -3938,7 +3934,6 @@ ATTRIBUTE_GROUPS(ibmvscsis_dev);
static struct class ibmvscsis_class = {
.name = "ibmvscsis",
.dev_release= ibmvscsis_dev_release,
- .class_attrs= ibmvscsis_class_attrs,
.dev_groups = ibmvscsis_dev_groups,
};
--
2.13.1
Re: [PATCH] scsi: qla2xxx: fix printk format string warning on 32-bit
Hi Arnd,
> On Jun 9, 2017, at 3:46 AM, Arnd Bergmann wrote:
>
> On 32-bit architectures, we using %lx to print a size_t causes a harmless
> warning:
>
> qla2xxx/qla_init.c: In function 'qla24xx_load_risc_flash':
> qla2xxx/qla_init.c:6407:7: error: format '%lx' expects argument of type 'long
> unsigned int', but argument 5 has type 'unsigned int' [-Werror=format=]
> qla2xxx/qla_init.c: In function 'qla24xx_load_risc_blob':
> qla2xxx/qla_init.c:6709:7: error: format '%lx' expects argument of type 'long
> unsigned int', but argument 5 has type 'unsigned int' [-Werror=format=]
>
> The correct format string is %zx.
>
> Fixes: 0f110b54d157 ("scsi: qla2xxx: Retain loop test for fwdump length
> exceeding buffer length")
> Signed-off-by: Arnd Bergmann
> ---
> drivers/scsi/qla2xxx/qla_init.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
> index 436968ad4484..730e7fe4344a 100644
> --- a/drivers/scsi/qla2xxx/qla_init.c
> +++ b/drivers/scsi/qla2xxx/qla_init.c
> @@ -6404,7 +6404,7 @@ qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t
> *srisc_addr,
> "-> template size %x bytes\n", dlen);
> if (dlen > risc_size * sizeof(*dcode)) {
> ql_log(ql_log_warn, vha, 0x0167,
> - "Failed fwdump template exceeds array by %lx bytes\n",
> + "Failed fwdump template exceeds array by %zx bytes\n",
> (size_t)(dlen - risc_size * sizeof(*dcode)));
> goto default_template;
> }
> @@ -6706,7 +6706,7 @@ qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t
> *srisc_addr)
> "-> template size %x bytes\n", dlen);
> if (dlen > risc_size * sizeof(*fwcode)) {
> ql_log(ql_log_warn, vha, 0x0177,
> - "Failed fwdump template exceeds array by %lx bytes\n",
> + "Failed fwdump template exceeds array by %zx bytes\n",
> (size_t)(dlen - risc_size * sizeof(*fwcode)));
> goto default_template;
> }
> --
> 2.9.0
>
I had posted patch already to fix this
https://patchwork.kernel.org/patch/9769981/
Thanks,
- Himanshu
[PATCH v5 17/23] scsi: hisi_sas: add v3 code to send ATA frame
From: Xiang Chen
Add code to prepare ATA frame for v3 hw
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 106 +
1 file changed, 106 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 515f50c..30c103b 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -171,8 +171,11 @@
#define CMD_HDR_CMD_OFF29
#define CMD_HDR_CMD_MSK(0x7 << CMD_HDR_CMD_OFF)
/* dw1 */
+#define CMD_HDR_UNCON_CMD_OFF 3
#define CMD_HDR_DIR_OFF5
#define CMD_HDR_DIR_MSK(0x3 << CMD_HDR_DIR_OFF)
+#define CMD_HDR_RESET_OFF 7
+#define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
#define CMD_HDR_VDTL_OFF 10
#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
#define CMD_HDR_FRAME_TYPE_OFF 11
@@ -182,6 +185,8 @@
/* dw2 */
#define CMD_HDR_CFL_OFF0
#define CMD_HDR_CFL_MSK(0x1ff << CMD_HDR_CFL_OFF)
+#define CMD_HDR_NCQ_TAG_OFF10
+#define CMD_HDR_NCQ_TAG_MSK(0x1f << CMD_HDR_NCQ_TAG_OFF)
#define CMD_HDR_MRFL_OFF 15
#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
#define CMD_HDR_SG_MOD_OFF 24
@@ -260,6 +265,11 @@ enum {
#define DIR_TO_DEVICE 2
#define DIR_RESERVED 3
+#define CMD_IS_UNCONSTRAINT(cmd) \
+ ((cmd == ATA_CMD_READ_LOG_EXT) || \
+ (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \
+ (cmd == ATA_CMD_DEV_RESET))
+
static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
{
void __iomem *regs = hisi_hba->regs + off;
@@ -725,6 +735,101 @@ static int prep_smp_v3_hw(struct hisi_hba *hisi_hba,
return rc;
}
+static int get_ncq_tag_v3_hw(struct sas_task *task, u32 *tag)
+{
+ struct ata_queued_cmd *qc = task->uldd_task;
+
+ if (qc) {
+ if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
+ qc->tf.command == ATA_CMD_FPDMA_READ) {
+ *tag = qc->tag;
+ return 1;
+ }
+ }
+ return 0;
+}
+
+static int prep_ata_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_slot *slot)
+{
+ struct sas_task *task = slot->task;
+ struct domain_device *device = task->dev;
+ struct domain_device *parent_dev = device->parent;
+ struct hisi_sas_device *sas_dev = device->lldd_dev;
+ struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
+ struct asd_sas_port *sas_port = device->port;
+ struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
+ u8 *buf_cmd;
+ int has_data = 0, rc = 0, hdr_tag = 0;
+ u32 dw1 = 0, dw2 = 0;
+
+ hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
+ if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
+ hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
+ else
+ hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
+
+ switch (task->data_dir) {
+ case DMA_TO_DEVICE:
+ has_data = 1;
+ dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
+ break;
+ case DMA_FROM_DEVICE:
+ has_data = 1;
+ dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
+ break;
+ default:
+ dw1 &= ~CMD_HDR_DIR_MSK;
+ }
+
+ if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
+ (task->ata_task.fis.control & ATA_SRST))
+ dw1 |= 1 << CMD_HDR_RESET_OFF;
+
+ dw1 |= (hisi_sas_get_ata_protocol(
+ task->ata_task.fis.command, task->data_dir))
+ << CMD_HDR_FRAME_TYPE_OFF;
+ dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
+
+ if (CMD_IS_UNCONSTRAINT(task->ata_task.fis.command))
+ dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
+
+ hdr->dw1 = cpu_to_le32(dw1);
+
+ /* dw2 */
+ if (task->ata_task.use_ncq && get_ncq_tag_v3_hw(task, &hdr_tag)) {
+ task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
+ dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
+ }
+
+ dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
+ 2 << CMD_HDR_SG_MOD_OFF;
+ hdr->dw2 = cpu_to_le32(dw2);
+
+ /* dw3 */
+ hdr->transfer_tags = cpu_to_le32(slot->idx);
+
+ if (has_data) {
+ rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
+ slot->n_elem);
+ if (rc)
+ return rc;
+ }
+
+ hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
+ hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
+ hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
+
+ buf_cmd = slot->comma
[PATCH v5 21/23] scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error
From: Xiang Chen For ECC 1bit error, logic can recover it, so we only print a warning. For ECC multi-bit and AXI bus fatal error, we panic. Note: once v3 hw controller reset support is added, the panic will be replaced by a controller reset, like v2 hw. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 394 + 1 file changed, 394 insertions(+) diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 3cd4b9a..63a74a0 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -51,7 +51,39 @@ #define CFG_SET_ABORTED_IPTT_OFF 0 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) #define CFG_1US_TIMER_TRSH 0xcc +#define HGC_LM_DFX_STATUS2 0x128 +#define HGC_LM_DFX_STATUS2_IOSTLIST_OFF0 +#define HGC_LM_DFX_STATUS2_IOSTLIST_MSK(0xfff <<\ + HGC_LM_DFX_STATUS2_IOSTLIST_OFF) +#define HGC_LM_DFX_STATUS2_ITCTLIST_OFF12 +#define HGC_LM_DFX_STATUS2_ITCTLIST_MSK(0x7ff <<\ + HGC_LM_DFX_STATUS2_ITCTLIST_OFF) +#define HGC_CQE_ECC_ADDR 0x13c +#define HGC_CQE_ECC_1B_ADDR_OFF0 +#define HGC_CQE_ECC_1B_ADDR_MSK(0x3f << HGC_CQE_ECC_1B_ADDR_OFF) +#define HGC_CQE_ECC_MB_ADDR_OFF8 +#define HGC_CQE_ECC_MB_ADDR_MSK(0x3f << HGC_CQE_ECC_MB_ADDR_OFF) +#define HGC_IOST_ECC_ADDR 0x140 +#define HGC_IOST_ECC_1B_ADDR_OFF 0 +#define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF) +#define HGC_IOST_ECC_MB_ADDR_OFF 16 +#define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF) +#define HGC_DQE_ECC_ADDR 0x144 +#define HGC_DQE_ECC_1B_ADDR_OFF0 +#define HGC_DQE_ECC_1B_ADDR_MSK(0xfff << HGC_DQE_ECC_1B_ADDR_OFF) +#define HGC_DQE_ECC_MB_ADDR_OFF16 +#define HGC_DQE_ECC_MB_ADDR_MSK(0xfff << HGC_DQE_ECC_MB_ADDR_OFF) #define CHNL_INT_STATUS0x148 +#define HGC_ITCT_ECC_ADDR 0x150 +#define HGC_ITCT_ECC_1B_ADDR_OFF 0 +#define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << HGC_ITCT_ECC_1B_ADDR_OFF) +#define HGC_ITCT_ECC_MB_ADDR_OFF 16 +#define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << HGC_ITCT_ECC_MB_ADDR_OFF) +#define HGC_AXI_FIFO_ERR_INFO 0x154 +#define AXI_ERR_INFO_OFF 0 +#define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) +#define FIFO_ERR_INFO_OFF 8 +#define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) #define INT_COAL_EN0x19c #define OQ_INT_COAL_TIME 0x1a0 #define OQ_INT_COAL_CNT0x1a4 @@ -85,6 +117,26 @@ #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) #define SAS_ECC_INTR 0x1e8 #define SAS_ECC_INTR_MSK 0x1ec +#define SAS_ECC_INTR_DQE_ECC_1B_OFF0 +#define SAS_ECC_INTR_DQE_ECC_MB_OFF1 +#define SAS_ECC_INTR_IOST_ECC_1B_OFF 2 +#define SAS_ECC_INTR_IOST_ECC_MB_OFF 3 +#define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4 +#define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5 +#define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6 +#define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7 +#define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 8 +#define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 9 +#define SAS_ECC_INTR_CQE_ECC_1B_OFF10 +#define SAS_ECC_INTR_CQE_ECC_MB_OFF11 +#define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12 +#define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13 +#define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14 +#define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15 +#define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16 +#define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17 +#define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18 +#define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19 #define HGC_ERR_STAT_EN0x238 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 @@ -98,6 +150,20 @@ #define COMPL_Q_0_DEPTH0x4e8 #define COMPL_Q_0_WR_PTR 0x4ec #define COMPL_Q_0_RD_PTR 0x4f0 +#define HGC_RXM_DFX_STATUS14 0xae8 +#define HGC_RXM_DFX_STATUS14_MEM0_OFF 0 +#define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff <<\ + HGC_RXM_DFX_STATUS14_MEM0_OFF) +#define HGC_RXM_DFX_STATUS14_MEM1_OFF 9 +#define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff <<\ + HGC_RXM_DFX_STATUS14_MEM1_OFF) +#define HGC_RXM_DFX_STATUS14_MEM2_OFF 18 +#define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff <<\ + HGC_RXM_DFX_STATUS14_MEM2_OFF) +#d
[PATCH v5 08/23] scsi: hisi_sas: create hisi_sas_get_fw_info()
Move the functionality to retrieve the fw info into
a dedicated device type-agnostic function,
hisi_sas_get_fw_info().
The reasoning is that this function will be required
for future pci-based platforms.
Also add some debug logs for failure.
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sas.h | 1 +
drivers/scsi/hisi_sas/hisi_sas_main.c | 107 ++
2 files changed, 71 insertions(+), 37 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 84cac98..c1f6669 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -371,6 +371,7 @@ struct hisi_sas_command_table_ssp {
extern void hisi_sas_sata_done(struct sas_task *task,
struct hisi_sas_slot *slot);
extern int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag);
+extern int hisi_sas_get_fw_info(struct hisi_hba *hisi_hba);
extern int hisi_sas_probe(struct platform_device *pdev,
const struct hisi_sas_hw *ops);
extern int hisi_sas_remove(struct platform_device *pdev);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c
b/drivers/scsi/hisi_sas/hisi_sas_main.c
index ff033bd..1a6adf7 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -1725,66 +1725,99 @@ static void hisi_sas_rst_work_handler(struct
work_struct *work)
hisi_sas_controller_reset(hisi_hba);
}
-static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev,
- const struct hisi_sas_hw *hw)
+int hisi_sas_get_fw_info(struct hisi_hba *hisi_hba)
{
- struct resource *res;
- struct Scsi_Host *shost;
- struct hisi_hba *hisi_hba;
- struct device *dev = &pdev->dev;
- struct device_node *np = pdev->dev.of_node;
+ struct device *dev = hisi_hba->dev;
+ struct platform_device *pdev = hisi_hba->platform_dev;
+ struct device_node *np = pdev ? pdev->dev.of_node : NULL;
struct clk *refclk;
- shost = scsi_host_alloc(&hisi_sas_sht, sizeof(*hisi_hba));
- if (!shost) {
- dev_err(dev, "scsi host alloc failed\n");
- return NULL;
- }
- hisi_hba = shost_priv(shost);
-
- INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
- hisi_hba->hw = hw;
- hisi_hba->platform_dev = pdev;
- hisi_hba->dev = dev;
- hisi_hba->shost = shost;
- SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
-
- init_timer(&hisi_hba->timer);
-
if (device_property_read_u8_array(dev, "sas-addr", hisi_hba->sas_addr,
- SAS_ADDR_SIZE))
- goto err_out;
+ SAS_ADDR_SIZE)) {
+ dev_err(dev, "could not get property sas-addr\n");
+ return -ENOENT;
+ }
if (np) {
+ /*
+* These properties are only required for platform device-based
+* controller with DT firmware.
+*/
hisi_hba->ctrl = syscon_regmap_lookup_by_phandle(np,
"hisilicon,sas-syscon");
- if (IS_ERR(hisi_hba->ctrl))
- goto err_out;
+ if (IS_ERR(hisi_hba->ctrl)) {
+ dev_err(dev, "could not get syscon\n");
+ return -ENOENT;
+ }
if (device_property_read_u32(dev, "ctrl-reset-reg",
-&hisi_hba->ctrl_reset_reg))
- goto err_out;
+&hisi_hba->ctrl_reset_reg)) {
+ dev_err(dev,
+ "could not get property ctrl-reset-reg\n");
+ return -ENOENT;
+ }
if (device_property_read_u32(dev, "ctrl-reset-sts-reg",
-&hisi_hba->ctrl_reset_sts_reg))
- goto err_out;
+&hisi_hba->ctrl_reset_sts_reg)) {
+ dev_err(dev,
+ "could not get property ctrl-reset-sts-reg\n");
+ return -ENOENT;
+ }
if (device_property_read_u32(dev, "ctrl-clock-ena-reg",
-&hisi_hba->ctrl_clock_ena_reg))
- goto err_out;
+&hisi_hba->ctrl_clock_ena_reg)) {
+ dev_err(dev,
+ "could not get property ctrl-clock-ena-reg\n");
+ return -ENOENT;
+ }
}
- refclk = devm_clk_get(&pdev->dev, NULL);
+ refclk = devm_clk_get(dev, NULL);
if (IS_ERR(refclk))
dev_dbg(dev, "no ref clk property\n");
else
[PATCH v5 22/23] scsi: hisi_sas: add v3 code to fill some more hw function pointers
From: Xiang Chen
Add code to fill the interface of phy_hard_reset, phy_get_max_linkrate,
and phy enable/disable.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 39 ++
1 file changed, 39 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 63a74a0..3688051 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -195,6 +195,8 @@
#define TXID_AUTO (PORT_BASE + 0xb8)
#define CT3_OFF1
#define CT3_MSK(0x1 << CT3_OFF)
+#define TX_HARDRST_OFF 2
+#define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
#define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
@@ -664,6 +666,14 @@ static void enable_phy_v3_hw(struct hisi_hba *hisi_hba,
int phy_no)
hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
}
+static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
+
+ cfg &= ~PHY_CFG_ENA_MSK;
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
+}
+
static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
{
config_id_frame_v3_hw(hisi_hba, phy_no);
@@ -671,6 +681,11 @@ static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int
phy_no)
enable_phy_v3_hw(hisi_hba, phy_no);
}
+static void stop_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ disable_phy_v3_hw(hisi_hba, phy_no);
+}
+
static void start_phys_v3_hw(struct hisi_hba *hisi_hba)
{
int i;
@@ -679,6 +694,26 @@ static void start_phys_v3_hw(struct hisi_hba *hisi_hba)
start_phy_v3_hw(hisi_hba, i);
}
+static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
+ u32 txid_auto;
+
+ stop_phy_v3_hw(hisi_hba, phy_no);
+ if (phy->identify.device_type == SAS_END_DEVICE) {
+ txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
+ hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
+ txid_auto | TX_HARDRST_MSK);
+ }
+ msleep(100);
+ start_phy_v3_hw(hisi_hba, phy_no);
+}
+
+enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
+{
+ return SAS_LINK_RATE_12_0_GBPS;
+}
+
static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
{
start_phys_v3_hw(hisi_hba);
@@ -1967,6 +2002,10 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
.start_delivery = start_delivery_v3_hw,
.slot_complete = slot_complete_v3_hw,
.phys_init = phys_init_v3_hw,
+ .phy_enable = enable_phy_v3_hw,
+ .phy_disable = disable_phy_v3_hw,
+ .phy_hard_reset = phy_hard_reset_v3_hw,
+ .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
};
static struct Scsi_Host *
--
1.9.1
[PATCH v5 12/23] scsi: hisi_sas: add v3 hw PHY init
From: Xiang Chen
Add code to configure PHYs for v3 hw.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 127 -
1 file changed, 126 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 1a5eae6..5580250 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -19,6 +19,10 @@
#define ITCT_BASE_ADDR_HI 0x14
#define IO_BROKEN_MSG_ADDR_LO 0x18
#define IO_BROKEN_MSG_ADDR_HI 0x1c
+#define PHY_CONTEXT0x20
+#define PHY_STATE 0x24
+#define PHY_PORT_NUM_MA0x28
+#define PHY_CONN_RATE 0x30
#define AXI_AHB_CLK_CFG0x3c
#define AXI_USER1 0x48
#define AXI_USER2 0x4c
@@ -42,6 +46,7 @@
#define CFG_SET_ABORTED_IPTT_OFF 0
#define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
#define CFG_1US_TIMER_TRSH 0xcc
+#define CHNL_INT_STATUS0x148
#define INT_COAL_EN0x19c
#define OQ_INT_COAL_TIME 0x1a0
#define OQ_INT_COAL_CNT0x1a4
@@ -68,9 +73,11 @@
#define ENT_INT_SRC_MSK1 0x1c4
#define ENT_INT_SRC_MSK2 0x1c8
#define ENT_INT_SRC_MSK3 0x1cc
+#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
#define CHNL_PHYUPDOWN_INT_MSK 0x1d0
#define CHNL_ENT_INT_MSK 0x1d4
#define HGC_COM_INT_MSK0x1d8
+#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
#define SAS_ECC_INTR 0x1e8
#define SAS_ECC_INTR_MSK 0x1ec
#define HGC_ERR_STAT_EN0x238
@@ -91,11 +98,33 @@
/* phy registers requiring init */
#define PORT_BASE (0x2000)
+#define PHY_CFG(PORT_BASE + 0x0)
+#define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
+#define PHY_CFG_ENA_OFF0
+#define PHY_CFG_ENA_MSK(0x1 << PHY_CFG_ENA_OFF)
+#define PHY_CFG_DC_OPT_OFF 2
+#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
#define PHY_CTRL (PORT_BASE + 0x14)
#define PHY_CTRL_RESET_OFF 0
#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
#define SL_CFG (PORT_BASE + 0x84)
+#define SL_CONTROL (PORT_BASE + 0x94)
+#define SL_CONTROL_NOTIFY_EN_OFF 0
+#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
+#define SL_CTA_OFF 17
+#define SL_CTA_MSK (0x1 << SL_CTA_OFF)
+#define TX_ID_DWORD0 (PORT_BASE + 0x9c)
+#define TX_ID_DWORD1 (PORT_BASE + 0xa0)
+#define TX_ID_DWORD2 (PORT_BASE + 0xa4)
+#define TX_ID_DWORD3 (PORT_BASE + 0xa8)
+#define TX_ID_DWORD4 (PORT_BASE + 0xaC)
+#define TX_ID_DWORD5 (PORT_BASE + 0xb0)
+#define TX_ID_DWORD6 (PORT_BASE + 0xb4)
+#define TXID_AUTO (PORT_BASE + 0xb8)
+#define CT3_OFF1
+#define CT3_MSK(0x1 << CT3_OFF)
+#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
#define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
#define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
@@ -136,6 +165,13 @@ struct hisi_sas_complete_v3_hdr {
};
#define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
+#define HISI_SAS_MSI_COUNT_V3_HW 32
+
+enum {
+ HISI_SAS_PHY_PHY_UPDOWN,
+ HISI_SAS_PHY_CHNL_INT,
+ HISI_SAS_PHY_INT_NR
+};
static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
{
@@ -152,6 +188,14 @@ static void hisi_sas_phy_write32(struct hisi_hba
*hisi_hba, int phy_no,
writel(val, regs);
}
+static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
+ int phy_no, u32 off)
+{
+ void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
+
+ return readl(regs);
+}
+
static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
{
int i;
@@ -266,6 +310,45 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
upper_32_bits(hisi_hba->initial_fis_dma));
}
+static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
+
+ cfg &= ~PHY_CFG_DC_OPT_MSK;
+ cfg |= 1 << PHY_CFG_DC_OPT_OFF;
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
+}
+
+static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
[PATCH v5 07/23] scsi: hisi_sas: add pci_dev in hisi_hba struct
Since hip08 SAS controller is based on pci device, add hisi_hba.pci_dev
for hip08 (will be v3), and also rename hisi_hba.pdev to .platform_dev
for clarity.
In addition, for common code which wants to reference the controller
device struct, add hisi_hba.dev, and change the common code to use
it.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas.h | 6 -
drivers/scsi/hisi_sas/hisi_sas_main.c | 36 ++--
drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 28 +++---
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 44 +-
4 files changed, 59 insertions(+), 55 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 19c6ffd..84cac98 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -196,7 +197,10 @@ struct hisi_hba {
/* This must be the first element, used by SHOST_TO_SAS_HA */
struct sas_ha_struct *p;
- struct platform_device *pdev;
+ struct platform_device *platform_dev;
+ struct pci_dev *pci_dev;
+ struct device *dev;
+
void __iomem *regs;
struct regmap *ctrl;
u32 ctrl_reset_reg;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c
b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 5e84314..ff033bd 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -168,7 +168,7 @@ void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba,
struct sas_task *task,
{
if (task) {
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct domain_device *device = task->dev;
struct hisi_sas_device *sas_dev = device->lldd_dev;
@@ -245,7 +245,7 @@ static void hisi_sas_slot_abort(struct work_struct *work)
struct scsi_cmnd *cmnd = task->uldd_task;
struct hisi_sas_tmf_task tmf_task;
struct scsi_lun lun;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int tag = abort_slot->idx;
unsigned long flags;
@@ -279,7 +279,7 @@ static int hisi_sas_task_prep(struct sas_task *task, struct
hisi_sas_dq
struct hisi_sas_slot *slot;
struct hisi_sas_cmd_hdr *cmd_hdr_base;
struct asd_sas_port *sas_port = device->port;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int dlvry_queue_slot, dlvry_queue, n_elem = 0, rc, slot_idx;
unsigned long flags;
@@ -449,7 +449,7 @@ static int hisi_sas_task_exec(struct sas_task *task, gfp_t
gfp_flags,
u32 pass = 0;
unsigned long flags;
struct hisi_hba *hisi_hba = dev_to_hisi_hba(task->dev);
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct domain_device *device = task->dev;
struct hisi_sas_device *sas_dev = device->lldd_dev;
struct hisi_sas_dq *dq = sas_dev->dq;
@@ -544,7 +544,7 @@ static int hisi_sas_dev_found(struct domain_device *device)
struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
struct domain_device *parent_dev = device->parent;
struct hisi_sas_device *sas_dev;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
if (hisi_hba->hw->alloc_dev)
sas_dev = hisi_hba->hw->alloc_dev(device);
@@ -729,7 +729,7 @@ static void hisi_sas_dev_gone(struct domain_device *device)
{
struct hisi_sas_device *sas_dev = device->lldd_dev;
struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int dev_id = sas_dev->device_id;
dev_info(dev, "found dev[%d:%x] is gone\n",
@@ -812,7 +812,7 @@ static int hisi_sas_exec_internal_tmf_task(struct
domain_device *device,
{
struct hisi_sas_device *sas_dev = device->lldd_dev;
struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct sas_task *task;
int res, retry;
@@ -929,7 +929,7 @@ static int hisi_sas_softreset_ata_disk(struct domain_device
*device)
struct ata_link *link;
int rc = TMF_RESP_FUNC_FAILED;
struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int s = sizeof(struct host_to_dev_fis);
unsigned long flags;
@@ -987,7 +987,7 @@ static int hisi_sas_controller_reset(struct hisi_hba
*hisi_hba)
return -1;
if (!test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) {
- struct device *dev = &hisi_hba->pdev->dev;
+
[PATCH v5 02/23] scsi: hisi_sas: define hisi_sas_device.device_id as int
Currently hisi_sas_device.device_id is a u64. This can create a
problem in selecting the queue for a device, in that this code
does a 64b division on device id. For some 32b systems, 64b division
is slow and the lib reference must be explicitly included.
The device id does not need to be 64b in size, so, as a solution,
just make as an int.
Also, struct hisi_sas_device elements are re-ordered to improve
packing efficiency.
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sas.h | 8
drivers/scsi/hisi_sas/hisi_sas_main.c | 10 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 4e28f32..b4e96fa9 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -107,15 +107,15 @@ struct hisi_sas_dq {
};
struct hisi_sas_device {
- enum sas_device_typedev_type;
struct hisi_hba *hisi_hba;
struct domain_device*sas_device;
+ struct list_headlist;
u64 attached_phy;
- u64 device_id;
atomic64_t running_req;
- struct list_headlist;
- u8 dev_status;
+ enum sas_device_typedev_type;
+ int device_id;
int sata_idx;
+ u8 dev_status;
};
struct hisi_sas_slot {
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c
b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 3605d28..54e0cf2 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -209,7 +209,7 @@ static int hisi_sas_task_prep(struct sas_task *task, struct
hisi_hba *hisi_hba,
if (DEV_IS_GONE(sas_dev)) {
if (sas_dev)
- dev_info(dev, "task prep: device %llu not ready\n",
+ dev_info(dev, "task prep: device %d not ready\n",
sas_dev->device_id);
else
dev_info(dev, "task prep: device %016llx not ready\n",
@@ -627,9 +627,9 @@ static void hisi_sas_dev_gone(struct domain_device *device)
struct hisi_sas_device *sas_dev = device->lldd_dev;
struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
struct device *dev = &hisi_hba->pdev->dev;
- u64 dev_id = sas_dev->device_id;
+ int dev_id = sas_dev->device_id;
- dev_info(dev, "found dev[%lld:%x] is gone\n",
+ dev_info(dev, "found dev[%d:%x] is gone\n",
sas_dev->device_id, sas_dev->dev_type);
hisi_sas_internal_task_abort(hisi_hba, device,
@@ -1082,7 +1082,7 @@ static int hisi_sas_lu_reset(struct domain_device
*device, u8 *lun)
}
out:
if (rc != TMF_RESP_FUNC_COMPLETE)
- dev_err(dev, "lu_reset: for device[%llx]:rc= %d\n",
+ dev_err(dev, "lu_reset: for device[%d]:rc= %d\n",
sas_dev->device_id, rc);
return rc;
}
@@ -1129,7 +1129,7 @@ static int hisi_sas_query_task(struct sas_task *task)
}
static int
-hisi_sas_internal_abort_task_exec(struct hisi_hba *hisi_hba, u64 device_id,
+hisi_sas_internal_abort_task_exec(struct hisi_hba *hisi_hba, int device_id,
struct sas_task *task, int abort_flag,
int task_tag)
{
--
1.9.1
[PATCH v5 10/23] scsi: hisi_sas: add initialisation for v3 pci-based controller
Add the code to initialise the controller which is based on pci
device in hisi_sas_v3_hw.c
The core controller routines are still in hisi_sas_main.c; some
common initialisation functions are also exported from
hisi_sas_main.c
For pci-based controller, the device properties, like
phy count and sas address are read from the firmware,
same as platform device-based controller.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas.h | 6 ++
drivers/scsi/hisi_sas/hisi_sas_main.c | 18 ++--
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 154 +
3 files changed, 172 insertions(+), 6 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index c1f6669..e89f6ae 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -366,6 +366,12 @@ struct hisi_sas_command_table_ssp {
struct hisi_sas_command_table_stp stp;
};
+extern struct scsi_transport_template *hisi_sas_stt;
+extern struct scsi_host_template *hisi_sas_sht;
+
+extern void hisi_sas_init_add(struct hisi_hba *hisi_hba);
+extern int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost);
+extern void hisi_sas_free(struct hisi_hba *hisi_hba);
extern u8 hisi_sas_get_ata_protocol(u8 cmd, int direction);
extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port);
extern void hisi_sas_sata_done(struct sas_task *task,
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c
b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 1a6adf7..92b7068 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -1472,9 +1472,10 @@ void hisi_sas_rescan_topology(struct hisi_hba *hisi_hba,
u32 old_state,
}
EXPORT_SYMBOL_GPL(hisi_sas_rescan_topology);
-static struct scsi_transport_template *hisi_sas_stt;
+struct scsi_transport_template *hisi_sas_stt;
+EXPORT_SYMBOL_GPL(hisi_sas_stt);
-static struct scsi_host_template hisi_sas_sht = {
+static struct scsi_host_template _hisi_sas_sht = {
.module = THIS_MODULE,
.name = DRV_NAME,
.queuecommand = sas_queuecommand,
@@ -1494,6 +1495,8 @@ void hisi_sas_rescan_topology(struct hisi_hba *hisi_hba,
u32 old_state,
.target_destroy = sas_target_destroy,
.ioctl = sas_ioctl,
};
+struct scsi_host_template *hisi_sas_sht = &_hisi_sas_sht;
+EXPORT_SYMBOL_GPL(hisi_sas_sht);
static struct sas_domain_function_template hisi_sas_transport_ops = {
.lldd_dev_found = hisi_sas_dev_found,
@@ -1541,7 +1544,7 @@ void hisi_sas_init_mem(struct hisi_hba *hisi_hba)
}
EXPORT_SYMBOL_GPL(hisi_sas_init_mem);
-static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
+int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
{
struct device *dev = hisi_hba->dev;
int i, s, max_command_entries = hisi_hba->hw->max_command_entries;
@@ -1660,8 +1663,9 @@ static int hisi_sas_alloc(struct hisi_hba *hisi_hba,
struct Scsi_Host *shost)
err_out:
return -ENOMEM;
}
+EXPORT_SYMBOL_GPL(hisi_sas_alloc);
-static void hisi_sas_free(struct hisi_hba *hisi_hba)
+void hisi_sas_free(struct hisi_hba *hisi_hba)
{
struct device *dev = hisi_hba->dev;
int i, s, max_command_entries = hisi_hba->hw->max_command_entries;
@@ -1716,6 +1720,7 @@ static void hisi_sas_free(struct hisi_hba *hisi_hba)
if (hisi_hba->wq)
destroy_workqueue(hisi_hba->wq);
}
+EXPORT_SYMBOL_GPL(hisi_sas_free);
static void hisi_sas_rst_work_handler(struct work_struct *work)
{
@@ -1801,7 +1806,7 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct
platform_device *pdev,
struct hisi_hba *hisi_hba;
struct device *dev = &pdev->dev;
- shost = scsi_host_alloc(&hisi_sas_sht, sizeof(*hisi_hba));
+ shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba));
if (!shost) {
dev_err(dev, "scsi host alloc failed\n");
return NULL;
@@ -1843,7 +1848,7 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct
platform_device *pdev,
return NULL;
}
-static void hisi_sas_init_add(struct hisi_hba *hisi_hba)
+void hisi_sas_init_add(struct hisi_hba *hisi_hba)
{
int i;
@@ -1852,6 +1857,7 @@ static void hisi_sas_init_add(struct hisi_hba *hisi_hba)
hisi_hba->sas_addr,
SAS_ADDR_SIZE);
}
+EXPORT_SYMBOL_GPL(hisi_sas_init_add);
int hisi_sas_probe(struct platform_device *pdev,
const struct hisi_sas_hw *hw)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index cf72577..e9a9fb0 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -11,14 +11,168 @@
#include "hisi_sas.h"
#define DRV_NAME "hisi_sas_v3_hw"
+static const struct hisi_sas_hw hisi_sas_v3_hw = {
+}
[PATCH v5 01/23] scsi: hisi_sas: fix timeout check in hisi_sas_internal_task_abort()
From: Xiang Chen
We need to check for timeout before task status, or the task will be
mistook as completed internal abort command.
Also add protection for sas_task.task_state_flags in
hisi_sas_tmf_timedout().
Signed-off-by: Xiang Chen
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sas_main.c | 25 +
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c
b/drivers/scsi/hisi_sas/hisi_sas_main.c
index f720d3c..3605d28 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -691,8 +691,13 @@ static void hisi_sas_task_done(struct sas_task *task)
static void hisi_sas_tmf_timedout(unsigned long data)
{
struct sas_task *task = (struct sas_task *)data;
+ unsigned long flags;
+
+ spin_lock_irqsave(&task->task_state_lock, flags);
+ if (!(task->task_state_flags & SAS_TASK_STATE_DONE))
+ task->task_state_flags |= SAS_TASK_STATE_ABORTED;
+ spin_unlock_irqrestore(&task->task_state_lock, flags);
- task->task_state_flags |= SAS_TASK_STATE_ABORTED;
complete(&task->slow_task->completion);
}
@@ -1247,6 +1252,17 @@ static int hisi_sas_query_task(struct sas_task *task)
wait_for_completion(&task->slow_task->completion);
res = TMF_RESP_FUNC_FAILED;
+ /* Internal abort timed out */
+ if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
+ if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
+ struct hisi_sas_slot *slot = task->lldd_task;
+
+ if (slot)
+ slot->task = NULL;
+ dev_err(dev, "internal task abort: timeout.\n");
+ }
+ }
+
if (task->task_status.resp == SAS_TASK_COMPLETE &&
task->task_status.stat == TMF_RESP_FUNC_COMPLETE) {
res = TMF_RESP_FUNC_COMPLETE;
@@ -1259,13 +1275,6 @@ static int hisi_sas_query_task(struct sas_task *task)
goto exit;
}
- /* Internal abort timed out */
- if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
- if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
- dev_err(dev, "internal task abort: timeout.\n");
- }
- }
-
exit:
dev_dbg(dev, "internal task abort: task to dev %016llx task=%p "
"resp: 0x%x sts 0x%x\n",
--
1.9.1
[PATCH v5 23/23] scsi: hisi_sas: modify internal abort dev flow for v3 hw
From: Xiang Chen
There is a change for abort dev for v3 hw: add registers to configure
unaborted iptt for a device, and then inform this to logic.
Signed-off-by: Xiang Chen
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sas.h | 2 ++
drivers/scsi/hisi_sas/hisi_sas_main.c | 15 +++
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 28
3 files changed, 45 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index e89f6ae..4fc2308 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -188,6 +188,8 @@ struct hisi_sas_hw {
void (*free_device)(struct hisi_hba *hisi_hba,
struct hisi_sas_device *dev);
int (*get_wideport_bitmap)(struct hisi_hba *hisi_hba, int port_id);
+ void (*dereg_device)(struct hisi_hba *hisi_hba,
+ struct domain_device *device);
int (*soft_reset)(struct hisi_hba *hisi_hba);
int max_command_entries;
int complete_hdr_size;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c
b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 92b7068..c4cefa88 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -725,6 +725,13 @@ static void hisi_sas_release_tasks(struct hisi_hba
*hisi_hba)
}
}
+static void hisi_sas_dereg_device(struct hisi_hba *hisi_hba,
+ struct domain_device *device)
+{
+ if (hisi_hba->hw->dereg_device)
+ hisi_hba->hw->dereg_device(hisi_hba, device);
+}
+
static void hisi_sas_dev_gone(struct domain_device *device)
{
struct hisi_sas_device *sas_dev = device->lldd_dev;
@@ -738,6 +745,8 @@ static void hisi_sas_dev_gone(struct domain_device *device)
hisi_sas_internal_task_abort(hisi_hba, device,
HISI_SAS_INT_ABT_DEV, 0);
+ hisi_sas_dereg_device(hisi_hba, device);
+
hisi_hba->hw->free_device(hisi_hba, sas_dev);
device->lldd_dev = NULL;
memset(sas_dev, 0, sizeof(*sas_dev));
@@ -1069,6 +1078,7 @@ static int hisi_sas_abort_task(struct sas_task *task)
if (task->dev->dev_type == SAS_SATA_DEV) {
hisi_sas_internal_task_abort(hisi_hba, device,
HISI_SAS_INT_ABT_DEV, 0);
+ hisi_sas_dereg_device(hisi_hba, device);
rc = hisi_sas_softreset_ata_disk(device);
}
} else if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SMP) {
@@ -1135,6 +1145,10 @@ static int hisi_sas_I_T_nexus_reset(struct domain_device
*device)
return TMF_RESP_FUNC_FAILED;
sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
+ hisi_sas_internal_task_abort(hisi_hba, device,
+ HISI_SAS_INT_ABT_DEV, 0);
+ hisi_sas_dereg_device(hisi_hba, device);
+
rc = hisi_sas_debug_I_T_nexus_reset(device);
if (rc == TMF_RESP_FUNC_COMPLETE) {
@@ -1162,6 +1176,7 @@ static int hisi_sas_lu_reset(struct domain_device
*device, u8 *lun)
HISI_SAS_INT_ABT_DEV, 0);
if (rc == TMF_RESP_FUNC_FAILED)
goto out;
+ hisi_sas_dereg_device(hisi_hba, device);
phy = sas_get_local_phy(device);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 3688051..6494388 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -50,6 +50,10 @@
#define CFG_ABT_SET_QUERY_IPTT 0xd4
#define CFG_SET_ABORTED_IPTT_OFF 0
#define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
+#define CFG_SET_ABORTED_EN_OFF 12
+#define CFG_ABT_SET_IPTT_DONE 0xd8
+#define CFG_ABT_SET_IPTT_DONE_OFF 0
+#define HGC_IOMB_PROC1_STATUS 0x104
#define CFG_1US_TIMER_TRSH 0xcc
#define HGC_LM_DFX_STATUS2 0x128
#define HGC_LM_DFX_STATUS2_IOSTLIST_OFF0
@@ -651,6 +655,29 @@ static void free_device_v3_hw(struct hisi_hba *hisi_hba,
}
}
+static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
+ struct domain_device *device)
+{
+ struct hisi_sas_slot *slot, *slot2;
+ struct hisi_sas_device *sas_dev = device->lldd_dev;
+ u32 cfg_abt_set_query_iptt;
+
+ cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
+ CFG_ABT_SET_QUERY_IPTT);
+ list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
+ cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
+ cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
+ (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
+ hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
+ cfg_abt_set_query
[PATCH v5 05/23] scsi: hisi_sas: relocate sata_done_v2_hw()
From: Xiang Chen
Relocate get_ata_protocol() to a common location, as future hw
versions will require it.
Also rename with "hisi_sas_" prefix for consistency.
Signed-off-by: Xiang Chen
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sas.h | 2 ++
drivers/scsi/hisi_sas/hisi_sas_main.c | 15 +++
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 18 ++
3 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index a50c699..1dcdf66 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -364,6 +364,8 @@ struct hisi_sas_command_table_ssp {
extern u8 hisi_sas_get_ata_protocol(u8 cmd, int direction);
extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port);
+extern void hisi_sas_sata_done(struct sas_task *task,
+ struct hisi_sas_slot *slot);
extern int hisi_sas_probe(struct platform_device *pdev,
const struct hisi_sas_hw *ops);
extern int hisi_sas_remove(struct platform_device *pdev);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c
b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 08e33e8..a7ba73b9 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -82,6 +82,21 @@ u8 hisi_sas_get_ata_protocol(u8 cmd, int direction)
}
EXPORT_SYMBOL_GPL(hisi_sas_get_ata_protocol);
+void hisi_sas_sata_done(struct sas_task *task,
+ struct hisi_sas_slot *slot)
+{
+ struct task_status_struct *ts = &task->task_status;
+ struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf;
+ struct dev_to_host_fis *d2h = slot->status_buffer +
+ sizeof(struct hisi_sas_err_record);
+
+ resp->frame_len = sizeof(struct dev_to_host_fis);
+ memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis));
+
+ ts->buf_valid_size = sizeof(*resp);
+}
+EXPORT_SYMBOL_GPL(hisi_sas_sata_done);
+
static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device)
{
return device->port->ha->lldd_ha;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
index d9314c4..fdd7019 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
@@ -1683,20 +1683,6 @@ static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
return 0;
}
-static void sata_done_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
- struct hisi_sas_slot *slot)
-{
- struct task_status_struct *ts = &task->task_status;
- struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf;
- struct dev_to_host_fis *d2h = slot->status_buffer +
- sizeof(struct hisi_sas_err_record);
-
- resp->frame_len = sizeof(struct dev_to_host_fis);
- memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis));
-
- ts->buf_valid_size = sizeof(*resp);
-}
-
#define TRANS_TX_ERR 0
#define TRANS_RX_ERR 1
#define DMA_TX_ERR 2
@@ -2189,7 +2175,7 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
break;
}
}
- sata_done_v2_hw(hisi_hba, task, slot);
+ hisi_sas_sata_done(task, slot);
}
break;
default:
@@ -2317,7 +2303,7 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
{
ts->stat = SAM_STAT_GOOD;
- sata_done_v2_hw(hisi_hba, task, slot);
+ hisi_sas_sata_done(task, slot);
break;
}
default:
--
1.9.1
[PATCH v5 06/23] scsi: hisi_sas: relocate get_ncq_tag_v2_hw()
From: Xiang Chen
Relocate get_ncq_tag_v2_hw() to a common location, as
future hw versions will require it.
Also rename with "hisi_sas_" prefix for consistency.
Signed-off-by: Xiang Chen
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sas.h | 1 +
drivers/scsi/hisi_sas/hisi_sas_main.c | 15 +++
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 16 +---
3 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 1dcdf66..19c6ffd 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -366,6 +366,7 @@ struct hisi_sas_command_table_ssp {
extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port);
extern void hisi_sas_sata_done(struct sas_task *task,
struct hisi_sas_slot *slot);
+extern int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag);
extern int hisi_sas_probe(struct platform_device *pdev,
const struct hisi_sas_hw *ops);
extern int hisi_sas_remove(struct platform_device *pdev);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c
b/drivers/scsi/hisi_sas/hisi_sas_main.c
index a7ba73b9..5e84314 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -97,6 +97,21 @@ void hisi_sas_sata_done(struct sas_task *task,
}
EXPORT_SYMBOL_GPL(hisi_sas_sata_done);
+int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag)
+{
+ struct ata_queued_cmd *qc = task->uldd_task;
+
+ if (qc) {
+ if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
+ qc->tf.command == ATA_CMD_FPDMA_READ) {
+ *tag = qc->tag;
+ return 1;
+ }
+ }
+ return 0;
+}
+EXPORT_SYMBOL_GPL(hisi_sas_get_ncq_tag);
+
static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device)
{
return device->port->ha->lldd_ha;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
index fdd7019..9cc5435 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
@@ -2332,20 +2332,6 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
return sts;
}
-static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag)
-{
- struct ata_queued_cmd *qc = task->uldd_task;
-
- if (qc) {
- if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
- qc->tf.command == ATA_CMD_FPDMA_READ) {
- *tag = qc->tag;
- return 1;
- }
- }
- return 0;
-}
-
static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
struct hisi_sas_slot *slot)
{
@@ -2393,7 +2379,7 @@ static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
hdr->dw1 = cpu_to_le32(dw1);
/* dw2 */
- if (task->ata_task.use_ncq && get_ncq_tag_v2_hw(task, &hdr_tag)) {
+ if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
}
--
1.9.1
[PATCH v5 09/23] scsi: hisi_sas: add skeleton v3 hw driver
Add skeleton driver for v3 hw in hisi_sas_v3_hw.c
File hisi_sas_v3_hw.c will serve 2 purposes:
- probing and initialisation of the controller based on pci device
- hw layer for v3-based controllers
The controller design is quite similar to v2 hw in hip07.
However key differences include:
-All v2 hw bugs are fixed (hopefully), so workarounds are not
required
-support for device deregistration
-some interrupt modifications
-configurable max device support
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/Kconfig | 10 +++-
drivers/scsi/hisi_sas/Makefile | 1 +
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 47 ++
3 files changed, 57 insertions(+), 1 deletion(-)
create mode 100644 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
diff --git a/drivers/scsi/hisi_sas/Kconfig b/drivers/scsi/hisi_sas/Kconfig
index 374a329..d42f29a 100644
--- a/drivers/scsi/hisi_sas/Kconfig
+++ b/drivers/scsi/hisi_sas/Kconfig
@@ -6,4 +6,12 @@ config SCSI_HISI_SAS
select BLK_DEV_INTEGRITY
depends on ATA
help
- This driver supports HiSilicon's SAS HBA
+ This driver supports HiSilicon's SAS HBA, including support
based
+ on platform device
+
+config SCSI_HISI_SAS_PCI
+ tristate "HiSilicon SAS on PCI bus"
+ depends on SCSI_HISI_SAS
+ depends on PCI
+ help
+ This driver supports HiSilicon's SAS HBA based on PCI device
diff --git a/drivers/scsi/hisi_sas/Makefile b/drivers/scsi/hisi_sas/Makefile
index c6d3a1b..24623f2 100644
--- a/drivers/scsi/hisi_sas/Makefile
+++ b/drivers/scsi/hisi_sas/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_SCSI_HISI_SAS)+= hisi_sas_main.o
obj-$(CONFIG_SCSI_HISI_SAS)+= hisi_sas_v1_hw.o hisi_sas_v2_hw.o
+obj-$(CONFIG_SCSI_HISI_SAS_PCI)+= hisi_sas_v3_hw.o
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
new file mode 100644
index 000..cf72577
--- /dev/null
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2017 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include "hisi_sas.h"
+#define DRV_NAME "hisi_sas_v3_hw"
+
+static int
+hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ return 0;
+}
+
+static void hisi_sas_v3_remove(struct pci_dev *pdev)
+{
+}
+
+enum {
+ /* instances of the controller */
+ hip08,
+};
+
+static const struct pci_device_id sas_v3_pci_table[] = {
+ { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
+ {}
+};
+
+static struct pci_driver sas_v3_pci_driver = {
+ .name = DRV_NAME,
+ .id_table = sas_v3_pci_table,
+ .probe = hisi_sas_v3_probe,
+ .remove = hisi_sas_v3_remove,
+};
+
+module_pci_driver(sas_v3_pci_driver);
+
+MODULE_VERSION(DRV_VERSION);
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Garry ");
+MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci
device");
+MODULE_ALIAS("platform:" DRV_NAME);
--
1.9.1
[PATCH v5 20/23] scsi: hisi_sas: add get_wideport_bitmap_v3_hw()
From: Xiang Chen
Add code for interface get_wideport_bitmap.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index ef5c158..3cd4b9a 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -629,6 +629,18 @@ static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int
phy_no)
hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
}
+static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
+{
+ int i, bitmap = 0;
+ u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
+
+ for (i = 0; i < hisi_hba->n_phy; i++)
+ if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
+ bitmap |= 1 << i;
+
+ return bitmap;
+}
+
/**
* The callpath to this function and upto writing the write
* queue pointer should be safe from interruption.
@@ -1550,6 +1562,7 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
.hw_init = hisi_sas_v3_init,
.setup_itct = setup_itct_v3_hw,
.max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
+ .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
.free_device = free_device_v3_hw,
.sl_notify = sl_notify_v3_hw,
--
1.9.1
[PATCH v5 16/23] scsi: hisi_sas: add v3 code to send SMP frame
From: Xiang Chen
Add code to prepare SMP frame.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 74 ++
1 file changed, 74 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index c869aca..515f50c 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -186,6 +186,9 @@
#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
#define CMD_HDR_SG_MOD_OFF 24
#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
+/* dw3 */
+#define CMD_HDR_IPTT_OFF 0
+#define CMD_HDR_IPTT_MSK (0x << CMD_HDR_IPTT_OFF)
/* dw6 */
#define CMD_HDR_DIF_SGL_LEN_OFF0
#define CMD_HDR_DIF_SGL_LEN_MSK(0x <<
CMD_HDR_DIF_SGL_LEN_OFF)
@@ -652,6 +655,76 @@ static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
return 0;
}
+static int prep_smp_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_slot *slot)
+{
+ struct sas_task *task = slot->task;
+ struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
+ struct domain_device *device = task->dev;
+ struct device *dev = hisi_hba->dev;
+ struct hisi_sas_port *port = slot->port;
+ struct scatterlist *sg_req, *sg_resp;
+ struct hisi_sas_device *sas_dev = device->lldd_dev;
+ dma_addr_t req_dma_addr;
+ unsigned int req_len, resp_len;
+ int elem, rc;
+
+ /*
+* DMA-map SMP request, response buffers
+*/
+ /* req */
+ sg_req = &task->smp_task.smp_req;
+ elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
+ if (!elem)
+ return -ENOMEM;
+ req_len = sg_dma_len(sg_req);
+ req_dma_addr = sg_dma_address(sg_req);
+
+ /* resp */
+ sg_resp = &task->smp_task.smp_resp;
+ elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
+ if (!elem) {
+ rc = -ENOMEM;
+ goto err_out_req;
+ }
+ resp_len = sg_dma_len(sg_resp);
+ if ((req_len & 0x3) || (resp_len & 0x3)) {
+ rc = -EINVAL;
+ goto err_out_resp;
+ }
+
+ /* create header */
+ /* dw0 */
+ hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
+ (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
+ (2 << CMD_HDR_CMD_OFF)); /* smp */
+
+ /* map itct entry */
+ hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
+ (1 << CMD_HDR_FRAME_TYPE_OFF) |
+ (DIR_NO_DATA << CMD_HDR_DIR_OFF));
+
+ /* dw2 */
+ hdr->dw2 = cpu_to_le32req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
+ (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
+ CMD_HDR_MRFL_OFF));
+
+ hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
+
+ hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
+ hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
+
+ return 0;
+
+err_out_resp:
+ dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
+DMA_FROM_DEVICE);
+err_out_req:
+ dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
+DMA_TO_DEVICE);
+ return rc;
+}
+
static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
{
int i, res = 0;
@@ -1225,6 +1298,7 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
.sl_notify = sl_notify_v3_hw,
.prep_ssp = prep_ssp_v3_hw,
+ .prep_smp = prep_smp_v3_hw,
.get_free_slot = get_free_slot_v3_hw,
.start_delivery = start_delivery_v3_hw,
.slot_complete = slot_complete_v3_hw,
--
1.9.1
[PATCH v5 19/23] scsi: hisi_sas: add v3 code to send internal abort command
From: Xiang Chen
Add code to prepare internal abort command.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index b9ab24d..ef5c158 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -165,6 +165,10 @@
/* HW dma structures */
/* Delivery queue header */
/* dw0 */
+#define CMD_HDR_ABORT_FLAG_OFF 0
+#define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
+#define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
+#define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
#define CMD_HDR_RESP_REPORT_OFF5
#define CMD_HDR_RESP_REPORT_MSK(0x1 << CMD_HDR_RESP_REPORT_OFF)
#define CMD_HDR_TLR_CTRL_OFF 6
@@ -204,6 +208,11 @@
#define CMD_HDR_DIF_SGL_LEN_MSK(0x <<
CMD_HDR_DIF_SGL_LEN_OFF)
#define CMD_HDR_DATA_SGL_LEN_OFF 16
#define CMD_HDR_DATA_SGL_LEN_MSK (0x << CMD_HDR_DATA_SGL_LEN_OFF)
+/* dw7 */
+#define CMD_HDR_ADDR_MODE_SEL_OFF 15
+#define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
+#define CMD_HDR_ABORT_IPTT_OFF 16
+#define CMD_HDR_ABORT_IPTT_MSK (0x << CMD_HDR_ABORT_IPTT_OFF)
/* Completion header */
/* dw0 */
@@ -942,6 +951,34 @@ static int prep_ata_v3_hw(struct hisi_hba *hisi_hba,
return 0;
}
+static int prep_abort_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_slot *slot,
+ int device_id, int abort_flag, int tag_to_abort)
+{
+ struct sas_task *task = slot->task;
+ struct domain_device *dev = task->dev;
+ struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
+ struct hisi_sas_port *port = slot->port;
+
+ /* dw0 */
+ hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
+ (port->id << CMD_HDR_PORT_OFF) |
+ ((dev_is_sata(dev) ? 1:0)
+ << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
+ (abort_flag
+<< CMD_HDR_ABORT_FLAG_OFF));
+
+ /* dw1 */
+ hdr->dw1 = cpu_to_le32(device_id
+ << CMD_HDR_DEV_ID_OFF);
+
+ /* dw7 */
+ hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
+ hdr->transfer_tags = cpu_to_le32(slot->idx);
+
+ return 0;
+}
+
static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
{
int i, res = 0;
@@ -1519,6 +1556,7 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
.prep_ssp = prep_ssp_v3_hw,
.prep_smp = prep_smp_v3_hw,
.prep_stp = prep_ata_v3_hw,
+ .prep_abort = prep_abort_v3_hw,
.get_free_slot = get_free_slot_v3_hw,
.start_delivery = start_delivery_v3_hw,
.slot_complete = slot_complete_v3_hw,
--
1.9.1
[PATCH v5 15/23] scsi: hisi_sas: add v3 code to send SSP frame
From: Xiang Chen
Add code to prepare SSP frame and deliver it to hardware.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 208 +
1 file changed, 208 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 4869b73..c869aca 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -157,6 +157,41 @@
#define SL_RX_BCAST_CHK_MSK(PORT_BASE + 0x2c0)
#define PHYCTRL_OOB_RESTART_MSK(PORT_BASE + 0x2c4)
+/* HW dma structures */
+/* Delivery queue header */
+/* dw0 */
+#define CMD_HDR_RESP_REPORT_OFF5
+#define CMD_HDR_RESP_REPORT_MSK(0x1 << CMD_HDR_RESP_REPORT_OFF)
+#define CMD_HDR_TLR_CTRL_OFF 6
+#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
+#define CMD_HDR_PORT_OFF 18
+#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
+#define CMD_HDR_PRIORITY_OFF 27
+#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
+#define CMD_HDR_CMD_OFF29
+#define CMD_HDR_CMD_MSK(0x7 << CMD_HDR_CMD_OFF)
+/* dw1 */
+#define CMD_HDR_DIR_OFF5
+#define CMD_HDR_DIR_MSK(0x3 << CMD_HDR_DIR_OFF)
+#define CMD_HDR_VDTL_OFF 10
+#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
+#define CMD_HDR_FRAME_TYPE_OFF 11
+#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
+#define CMD_HDR_DEV_ID_OFF 16
+#define CMD_HDR_DEV_ID_MSK (0x << CMD_HDR_DEV_ID_OFF)
+/* dw2 */
+#define CMD_HDR_CFL_OFF0
+#define CMD_HDR_CFL_MSK(0x1ff << CMD_HDR_CFL_OFF)
+#define CMD_HDR_MRFL_OFF 15
+#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
+#define CMD_HDR_SG_MOD_OFF 24
+#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
+/* dw6 */
+#define CMD_HDR_DIF_SGL_LEN_OFF0
+#define CMD_HDR_DIF_SGL_LEN_MSK(0x <<
CMD_HDR_DIF_SGL_LEN_OFF)
+#define CMD_HDR_DATA_SGL_LEN_OFF 16
+#define CMD_HDR_DATA_SGL_LEN_MSK (0x << CMD_HDR_DATA_SGL_LEN_OFF)
+
/* Completion header */
/* dw0 */
#define CMPLT_HDR_CMPLT_OFF0
@@ -217,6 +252,11 @@ enum {
HISI_SAS_PHY_INT_NR
};
+#define DIR_NO_DATA 0
+#define DIR_TO_INI 1
+#define DIR_TO_DEVICE 2
+#define DIR_RESERVED 3
+
static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
{
void __iomem *regs = hisi_hba->regs + off;
@@ -224,6 +264,13 @@ static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32
off)
return readl(regs);
}
+static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
+{
+ void __iomem *regs = hisi_hba->regs + off;
+
+ return readl_relaxed(regs);
+}
+
static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
{
void __iomem *regs = hisi_hba->regs + off;
@@ -448,6 +495,163 @@ static void sl_notify_v3_hw(struct hisi_hba *hisi_hba,
int phy_no)
hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
}
+/**
+ * The callpath to this function and upto writing the write
+ * queue pointer should be safe from interruption.
+ */
+static int
+get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
+{
+ struct device *dev = hisi_hba->dev;
+ int queue = dq->id;
+ u32 r, w;
+
+ w = dq->wr_point;
+ r = hisi_sas_read32_relaxed(hisi_hba,
+ DLVRY_Q_0_RD_PTR + (queue * 0x14));
+ if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
+ dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
+ queue, r, w);
+ return -EAGAIN;
+ }
+
+ return 0;
+}
+
+static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
+{
+ struct hisi_hba *hisi_hba = dq->hisi_hba;
+ int dlvry_queue = dq->slot_prep->dlvry_queue;
+ int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
+
+ dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
+ hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
+dq->wr_point);
+}
+
+static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_slot *slot,
+ struct hisi_sas_cmd_hdr *hdr,
+ struct scatterlist *scatter,
+ int n_elem)
+{
+ struct device *dev = hisi_hba->dev;
+ struct scatterlist *sg;
+ int i;
+
+ if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
+ dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
+ n_elem);
+ return -EINVAL;
+ }
+
+ slot->sge_page = dma_pool_all
[PATCH v5 18/23] scsi: hisi_sas: add v3 code for itct setup and free
From: Xiang Chen
Add code to itct setup and free for v3 hw.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 114 +
1 file changed, 114 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 30c103b..b9ab24d 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -24,6 +24,11 @@
#define PHY_PORT_NUM_MA0x28
#define PHY_CONN_RATE 0x30
#define AXI_AHB_CLK_CFG0x3c
+#define ITCT_CLR 0x44
+#define ITCT_CLR_EN_OFF16
+#define ITCT_CLR_EN_MSK(0x1 << ITCT_CLR_EN_OFF)
+#define ITCT_DEV_OFF 0
+#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
#define AXI_USER1 0x48
#define AXI_USER2 0x4c
#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
@@ -226,6 +231,26 @@
#define CMPLT_HDR_IO_IN_TARGET_OFF 17
#define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
+/* ITCT header */
+/* qw0 */
+#define ITCT_HDR_DEV_TYPE_OFF 0
+#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
+#define ITCT_HDR_VALID_OFF 2
+#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
+#define ITCT_HDR_MCR_OFF 5
+#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
+#define ITCT_HDR_VLN_OFF 9
+#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
+#define ITCT_HDR_SMP_TIMEOUT_OFF 16
+#define ITCT_HDR_AWT_CONTINUE_OFF 25
+#define ITCT_HDR_PORT_ID_OFF 28
+#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
+/* qw2 */
+#define ITCT_HDR_INLT_OFF 0
+#define ITCT_HDR_INLT_MSK (0xULL << ITCT_HDR_INLT_OFF)
+#define ITCT_HDR_RTOLT_OFF 48
+#define ITCT_HDR_RTOLT_MSK (0xULL << ITCT_HDR_RTOLT_OFF)
+
struct hisi_sas_complete_v3_hdr {
__le32 dw0;
__le32 dw1;
@@ -460,6 +485,93 @@ static void config_id_frame_v3_hw(struct hisi_hba
*hisi_hba, int phy_no)
__swab32(identify_buffer[5]));
}
+static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
+struct hisi_sas_device *sas_dev)
+{
+ struct domain_device *device = sas_dev->sas_device;
+ struct device *dev = hisi_hba->dev;
+ u64 qw0, device_id = sas_dev->device_id;
+ struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
+ struct domain_device *parent_dev = device->parent;
+ struct asd_sas_port *sas_port = device->port;
+ struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
+
+ memset(itct, 0, sizeof(*itct));
+
+ /* qw0 */
+ qw0 = 0;
+ switch (sas_dev->dev_type) {
+ case SAS_END_DEVICE:
+ case SAS_EDGE_EXPANDER_DEVICE:
+ case SAS_FANOUT_EXPANDER_DEVICE:
+ qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
+ break;
+ case SAS_SATA_DEV:
+ case SAS_SATA_PENDING:
+ if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
+ qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
+ else
+ qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
+ break;
+ default:
+ dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
+sas_dev->dev_type);
+ }
+
+ qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
+ (device->linkrate << ITCT_HDR_MCR_OFF) |
+ (1 << ITCT_HDR_VLN_OFF) |
+ (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
+ (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
+ (port->id << ITCT_HDR_PORT_ID_OFF));
+ itct->qw0 = cpu_to_le64(qw0);
+
+ /* qw1 */
+ memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
+ itct->sas_addr = __swab64(itct->sas_addr);
+
+ /* qw2 */
+ if (!dev_is_sata(device))
+ itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
+ (0x1ULL << ITCT_HDR_RTOLT_OFF));
+}
+
+static void free_device_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_device *sas_dev)
+{
+ u64 dev_id = sas_dev->device_id;
+ struct device *dev = hisi_hba->dev;
+ struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
+ u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
+
+ /* clear the itct interrupt state */
+ if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
+ENT_INT_SRC3_ITC_INT_MSK);
+
+ /* clear the itct table*/
+ reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
+ reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT
[PATCH v5 14/23] scsi: hisi_sas: add v3 cq interrupt handler
From: Xiang Chen
Add v3 cq interrupt handler slot_complete_v3_hw().
Note: The slot error handling needs to be further
refined in the future to examine all fields
in the error record, and handle appropriately,
instead of current solution - just report
SAS_OPEN_REJECT.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 340 +
1 file changed, 340 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 3065252..4869b73 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -157,6 +157,32 @@
#define SL_RX_BCAST_CHK_MSK(PORT_BASE + 0x2c0)
#define PHYCTRL_OOB_RESTART_MSK(PORT_BASE + 0x2c4)
+/* Completion header */
+/* dw0 */
+#define CMPLT_HDR_CMPLT_OFF0
+#define CMPLT_HDR_CMPLT_MSK(0x3 << CMPLT_HDR_CMPLT_OFF)
+#define CMPLT_HDR_ERROR_PHASE_OFF 2
+#define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
+#define CMPLT_HDR_RSPNS_XFRD_OFF 10
+#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
+#define CMPLT_HDR_ERX_OFF 12
+#define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
+#define CMPLT_HDR_ABORT_STAT_OFF 13
+#define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
+/* abort_stat */
+#define STAT_IO_NOT_VALID 0x1
+#define STAT_IO_NO_DEVICE 0x2
+#define STAT_IO_COMPLETE 0x3
+#define STAT_IO_ABORTED0x4
+/* dw1 */
+#define CMPLT_HDR_IPTT_OFF 0
+#define CMPLT_HDR_IPTT_MSK (0x << CMPLT_HDR_IPTT_OFF)
+#define CMPLT_HDR_DEV_ID_OFF 16
+#define CMPLT_HDR_DEV_ID_MSK (0x << CMPLT_HDR_DEV_ID_OFF)
+/* dw3 */
+#define CMPLT_HDR_IO_IN_TARGET_OFF 17
+#define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
+
struct hisi_sas_complete_v3_hdr {
__le32 dw0;
__le32 dw1;
@@ -164,6 +190,24 @@ struct hisi_sas_complete_v3_hdr {
__le32 dw3;
};
+struct hisi_sas_err_record_v3 {
+ /* dw0 */
+ __le32 trans_tx_fail_type;
+
+ /* dw1 */
+ __le32 trans_rx_fail_type;
+
+ /* dw2 */
+ __le16 dma_tx_err_type;
+ __le16 sipc_rx_err_type;
+
+ /* dw3 */
+ __le32 dma_rx_err_type;
+};
+
+#define RX_DATA_LEN_UNDERFLOW_OFF 6
+#define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
+
#define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
#define HISI_SAS_MSI_COUNT_V3_HW 32
@@ -625,11 +669,275 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void
*p)
return IRQ_HANDLED;
}
+static void
+slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
+ struct hisi_sas_slot *slot)
+{
+ struct task_status_struct *ts = &task->task_status;
+ struct hisi_sas_complete_v3_hdr *complete_queue =
+ hisi_hba->complete_hdr[slot->cmplt_queue];
+ struct hisi_sas_complete_v3_hdr *complete_hdr =
+ &complete_queue[slot->cmplt_queue_slot];
+ struct hisi_sas_err_record_v3 *record = slot->status_buffer;
+ u32 dma_rx_err_type = record->dma_rx_err_type;
+ u32 trans_tx_fail_type = record->trans_tx_fail_type;
+
+ switch (task->task_proto) {
+ case SAS_PROTOCOL_SSP:
+ if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
+ ts->residual = trans_tx_fail_type;
+ ts->stat = SAS_DATA_UNDERRUN;
+ } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
+ ts->stat = SAS_QUEUE_FULL;
+ slot->abort = 1;
+ } else {
+ ts->stat = SAS_OPEN_REJECT;
+ ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
+ }
+ break;
+ case SAS_PROTOCOL_SATA:
+ case SAS_PROTOCOL_STP:
+ case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
+ if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
+ ts->residual = trans_tx_fail_type;
+ ts->stat = SAS_DATA_UNDERRUN;
+ } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
+ ts->stat = SAS_PHY_DOWN;
+ slot->abort = 1;
+ } else {
+ ts->stat = SAS_OPEN_REJECT;
+ ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
+ }
+ hisi_sas_sata_done(task, slot);
+ break;
+ case SAS_PROTOCOL_SMP:
+ ts->stat = SAM_STAT_CHECK_CONDITION;
+ break;
+ default:
+ break;
+ }
+}
+
+static int
+slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
+{
+ struct sas_task *task = slot->task;
+ struct hisi_
[PATCH v5 11/23] scsi: hisi_sas: add v3 hw init
From: Xiang Chen Add code to initialise v3 hardware. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 277 + 1 file changed, 277 insertions(+) diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index e9a9fb0..1a5eae6 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -11,7 +11,283 @@ #include "hisi_sas.h" #define DRV_NAME "hisi_sas_v3_hw" +/* global registers need init*/ +#define DLVRY_QUEUE_ENABLE 0x0 +#define IOST_BASE_ADDR_LO 0x8 +#define IOST_BASE_ADDR_HI 0xc +#define ITCT_BASE_ADDR_LO 0x10 +#define ITCT_BASE_ADDR_HI 0x14 +#define IO_BROKEN_MSG_ADDR_LO 0x18 +#define IO_BROKEN_MSG_ADDR_HI 0x1c +#define AXI_AHB_CLK_CFG0x3c +#define AXI_USER1 0x48 +#define AXI_USER2 0x4c +#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 +#define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c +#define SATA_INITI_D2H_STORE_ADDR_LO 0x60 +#define SATA_INITI_D2H_STORE_ADDR_HI 0x64 +#define CFG_MAX_TAG0x68 +#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL0x84 +#define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 +#define HGC_GET_ITV_TIME 0x90 +#define DEVICE_MSG_WORK_MODE 0x94 +#define OPENA_WT_CONTI_TIME0x9c +#define I_T_NEXUS_LOSS_TIME0xa0 +#define MAX_CON_TIME_LIMIT_TIME0xa4 +#define BUS_INACTIVE_LIMIT_TIME0xa8 +#define REJECT_TO_OPEN_LIMIT_TIME 0xac +#define CFG_AGING_TIME 0xbc +#define HGC_DFX_CFG2 0xc0 +#define CFG_ABT_SET_QUERY_IPTT 0xd4 +#define CFG_SET_ABORTED_IPTT_OFF 0 +#define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) +#define CFG_1US_TIMER_TRSH 0xcc +#define INT_COAL_EN0x19c +#define OQ_INT_COAL_TIME 0x1a0 +#define OQ_INT_COAL_CNT0x1a4 +#define ENT_INT_COAL_TIME 0x1a8 +#define ENT_INT_COAL_CNT 0x1ac +#define OQ_INT_SRC 0x1b0 +#define OQ_INT_SRC_MSK 0x1b4 +#define ENT_INT_SRC1 0x1b8 +#define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 +#define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) +#define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 +#define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) +#define ENT_INT_SRC2 0x1bc +#define ENT_INT_SRC3 0x1c0 +#define ENT_INT_SRC3_WP_DEPTH_OFF 8 +#define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 +#define ENT_INT_SRC3_RP_DEPTH_OFF 10 +#define ENT_INT_SRC3_AXI_OFF 11 +#define ENT_INT_SRC3_FIFO_OFF 12 +#define ENT_INT_SRC3_LM_OFF14 +#define ENT_INT_SRC3_ITC_INT_OFF 15 +#define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) +#define ENT_INT_SRC3_ABT_OFF 16 +#define ENT_INT_SRC_MSK1 0x1c4 +#define ENT_INT_SRC_MSK2 0x1c8 +#define ENT_INT_SRC_MSK3 0x1cc +#define CHNL_PHYUPDOWN_INT_MSK 0x1d0 +#define CHNL_ENT_INT_MSK 0x1d4 +#define HGC_COM_INT_MSK0x1d8 +#define SAS_ECC_INTR 0x1e8 +#define SAS_ECC_INTR_MSK 0x1ec +#define HGC_ERR_STAT_EN0x238 +#define DLVRY_Q_0_BASE_ADDR_LO 0x260 +#define DLVRY_Q_0_BASE_ADDR_HI 0x264 +#define DLVRY_Q_0_DEPTH0x268 +#define DLVRY_Q_0_WR_PTR 0x26c +#define DLVRY_Q_0_RD_PTR 0x270 +#define HYPER_STREAM_ID_EN_CFG 0xc80 +#define OQ0_INT_SRC_MSK0xc90 +#define COMPL_Q_0_BASE_ADDR_LO 0x4e0 +#define COMPL_Q_0_BASE_ADDR_HI 0x4e4 +#define COMPL_Q_0_DEPTH0x4e8 +#define COMPL_Q_0_WR_PTR 0x4ec +#define COMPL_Q_0_RD_PTR 0x4f0 +#define AWQOS_AWCACHE_CFG 0xc84 +#define ARQOS_ARCACHE_CFG 0xc88 + +/* phy registers requiring init */ +#define PORT_BASE (0x2000) +#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) +#define PHY_CTRL (PORT_BASE + 0x14) +#define PHY_CTRL_RESET_OFF 0 +#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) +#define SL_CFG (PORT_BASE + 0x84) +#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) +#define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) +#define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) +#define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) +#define CHL_INT0 (PORT_BASE + 0x1b4) +#define CHL_INT0_HOTPLUG_TOUT_OFF 0 +#define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL
[PATCH v5 00/23] hisi_sas: hip08 support
This patchset adds support for the HiSilicon SAS controller in the hip08 chipset. The key difference compared to earlier chipsets is that the controller is an integrated PCI endpoint in hip08. As such, the controller is a pci device (not a platform device, like v2 hw in hip07). The driver is refactored so it can support both platform and pci device-based controllers. New hw layer file hisi_sas_v3_hw.c is added for v3 hw support, which also includes pci device proving and initialisation. Common functionality is still in hisi_sas_main.c, along with platform device probing and initialization. As for the patches, (ignoring #1-3) the first few reorganise some functions from v2 hw.c into main.c, as they are required for v3 hw. Then support is added for pci device-based controller in subsequent patches. And then hip08 support is added in the final patches. Difference to v4 series: -report SAS_DATA_UNDERRUN to libsas for underflow Differences to v3 series: - Addressed Christoph's comments, including: - remove msi disable in probe, and improve irq registration and deregistration - remove hisi_sas_is_rw_cmd() to check underflow, and use scsi_cmnd underflow field instead Differences to v2 series: - Add patch to change hisi_sas_device.device_id size - Add device dq pointer - Remove hisi_sas_v3_hw prototype in v3 driver - Add explicit comment in hisi_sas_get_fw_info() Differences to v1 series: - Addressed Arnd's comments, including: - read sas address from device node DSD under PCI host bridge - add comment in fatal axi error patch commit log regarding controller reset - eliminate hisi_sas_pci_init.c, and move functionality into hisi_sas_v3_hw.c, eliminating one layer of indirection John Garry (5): scsi: hisi_sas: define hisi_sas_device.device_id as int scsi: hisi_sas: add pci_dev in hisi_hba struct scsi: hisi_sas: create hisi_sas_get_fw_info() scsi: hisi_sas: add skeleton v3 hw driver scsi: hisi_sas: add initialisation for v3 pci-based controller Xiang Chen (18): scsi: hisi_sas: fix timeout check in hisi_sas_internal_task_abort() scsi: hisi_sas: optimise the usage of hisi_hba.lock scsi: hisi_sas: relocate get_ata_protocol() scsi: hisi_sas: relocate sata_done_v2_hw() scsi: hisi_sas: relocate get_ncq_tag_v2_hw() scsi: hisi_sas: add v3 hw init scsi: hisi_sas: add v3 hw PHY init scsi: hisi_sas: add phy up/down/bcast and channel ISR scsi: hisi_sas: add v3 cq interrupt handler scsi: hisi_sas: add v3 code to send SSP frame scsi: hisi_sas: add v3 code to send SMP frame scsi: hisi_sas: add v3 code to send ATA frame scsi: hisi_sas: add v3 code for itct setup and free scsi: hisi_sas: add v3 code to send internal abort command scsi: hisi_sas: add get_wideport_bitmap_v3_hw() scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error scsi: hisi_sas: add v3 code to fill some more hw function pointers scsi: hisi_sas: modify internal abort dev flow for v3 hw drivers/scsi/hisi_sas/Kconfig | 10 +- drivers/scsi/hisi_sas/Makefile |1 + drivers/scsi/hisi_sas/hisi_sas.h | 42 +- drivers/scsi/hisi_sas/hisi_sas_main.c | 355 +++-- drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 51 +- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 179 +-- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 2240 7 files changed, 2613 insertions(+), 265 deletions(-) create mode 100644 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c -- 1.9.1
[PATCH v5 04/23] scsi: hisi_sas: relocate get_ata_protocol()
From: Xiang Chen
Relocate get_ata_protocol() to a common location, as future
hw versions will require it.
Also rename with "hisi_sas_" prefix for consistency.
Signed-off-by: Xiang Chen
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sas.h | 7
drivers/scsi/hisi_sas/hisi_sas_main.c | 59 ++
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 67 +-
3 files changed, 68 insertions(+), 65 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 68ba7bd..a50c699 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -46,6 +46,12 @@
((type == SAS_EDGE_EXPANDER_DEVICE) || \
(type == SAS_FANOUT_EXPANDER_DEVICE))
+#define HISI_SAS_SATA_PROTOCOL_NONDATA 0x1
+#define HISI_SAS_SATA_PROTOCOL_PIO 0x2
+#define HISI_SAS_SATA_PROTOCOL_DMA 0x4
+#define HISI_SAS_SATA_PROTOCOL_FPDMA 0x8
+#define HISI_SAS_SATA_PROTOCOL_ATAPI 0x10
+
struct hisi_hba;
enum {
@@ -356,6 +362,7 @@ struct hisi_sas_command_table_ssp {
struct hisi_sas_command_table_stp stp;
};
+extern u8 hisi_sas_get_ata_protocol(u8 cmd, int direction);
extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port);
extern int hisi_sas_probe(struct platform_device *pdev,
const struct hisi_sas_hw *ops);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c
b/drivers/scsi/hisi_sas/hisi_sas_main.c
index b247220..08e33e8 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -23,6 +23,65 @@ static int hisi_sas_debug_issue_ssp_tmf(struct domain_device
*device,
int abort_flag, int tag);
static int hisi_sas_softreset_ata_disk(struct domain_device *device);
+u8 hisi_sas_get_ata_protocol(u8 cmd, int direction)
+{
+ switch (cmd) {
+ case ATA_CMD_FPDMA_WRITE:
+ case ATA_CMD_FPDMA_READ:
+ case ATA_CMD_FPDMA_RECV:
+ case ATA_CMD_FPDMA_SEND:
+ case ATA_CMD_NCQ_NON_DATA:
+ return HISI_SAS_SATA_PROTOCOL_FPDMA;
+
+ case ATA_CMD_DOWNLOAD_MICRO:
+ case ATA_CMD_ID_ATA:
+ case ATA_CMD_PMP_READ:
+ case ATA_CMD_READ_LOG_EXT:
+ case ATA_CMD_PIO_READ:
+ case ATA_CMD_PIO_READ_EXT:
+ case ATA_CMD_PMP_WRITE:
+ case ATA_CMD_WRITE_LOG_EXT:
+ case ATA_CMD_PIO_WRITE:
+ case ATA_CMD_PIO_WRITE_EXT:
+ return HISI_SAS_SATA_PROTOCOL_PIO;
+
+ case ATA_CMD_DSM:
+ case ATA_CMD_DOWNLOAD_MICRO_DMA:
+ case ATA_CMD_PMP_READ_DMA:
+ case ATA_CMD_PMP_WRITE_DMA:
+ case ATA_CMD_READ:
+ case ATA_CMD_READ_EXT:
+ case ATA_CMD_READ_LOG_DMA_EXT:
+ case ATA_CMD_READ_STREAM_DMA_EXT:
+ case ATA_CMD_TRUSTED_RCV_DMA:
+ case ATA_CMD_TRUSTED_SND_DMA:
+ case ATA_CMD_WRITE:
+ case ATA_CMD_WRITE_EXT:
+ case ATA_CMD_WRITE_FUA_EXT:
+ case ATA_CMD_WRITE_QUEUED:
+ case ATA_CMD_WRITE_LOG_DMA_EXT:
+ case ATA_CMD_WRITE_STREAM_DMA_EXT:
+ return HISI_SAS_SATA_PROTOCOL_DMA;
+
+ case ATA_CMD_CHK_POWER:
+ case ATA_CMD_DEV_RESET:
+ case ATA_CMD_EDD:
+ case ATA_CMD_FLUSH:
+ case ATA_CMD_FLUSH_EXT:
+ case ATA_CMD_VERIFY:
+ case ATA_CMD_VERIFY_EXT:
+ case ATA_CMD_SET_FEATURES:
+ case ATA_CMD_STANDBY:
+ case ATA_CMD_STANDBYNOW1:
+ return HISI_SAS_SATA_PROTOCOL_NONDATA;
+ default:
+ if (direction == DMA_NONE)
+ return HISI_SAS_SATA_PROTOCOL_NONDATA;
+ return HISI_SAS_SATA_PROTOCOL_PIO;
+ }
+}
+EXPORT_SYMBOL_GPL(hisi_sas_get_ata_protocol);
+
static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device)
{
return device->port->ha->lldd_ha;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
index 2607aac..d9314c4 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
@@ -554,12 +554,6 @@ enum {
#define DIR_TO_DEVICE 2
#define DIR_RESERVED 3
-#define SATA_PROTOCOL_NONDATA 0x1
-#define SATA_PROTOCOL_PIO 0x2
-#define SATA_PROTOCOL_DMA 0x4
-#define SATA_PROTOCOL_FPDMA0x8
-#define SATA_PROTOCOL_ATAPI0x10
-
#define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
err_phase == 0x4 || err_phase == 0x8 ||\
err_phase == 0x6 || err_phase == 0xa)
@@ -2352,64 +2346,6 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
return sts;
}
-static u8 get_ata_protocol(u8 cmd, int direction)
-{
- switch (cmd) {
- case ATA_CMD_FPDMA_WRITE:
- case ATA_CMD_FPDMA_READ:
- case ATA_CMD_FPDMA_RECV:
- case ATA_CMD_FPDMA_SEND:
- case ATA_CMD_NCQ_NON_DATA:
- return SATA_PROTOCOL_FPDMA;
-
- case ATA_CMD_DOWNLOAD_MICRO:
- case
[PATCH v5 03/23] scsi: hisi_sas: optimise the usage of hisi_hba.lock
From: Xiang Chen
Currently hisi_hba.lock is locked to deliver and receive a
command to/from any hw queue. This causes much
contention at high data-rates.
To boost performance, lock on a per queue basis for
sending and receiving commands to/from hw.
Certain critical regions still need to be locked in the delivery
and completion stages with hisi_hba.lock.
New element hisi_sas_device.dq is added to store the delivery
queue for a device, so it does not need to be needlessly
re-calculated for every task.
Signed-off-by: Xiang Chen
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sas.h | 9 ++---
drivers/scsi/hisi_sas/hisi_sas_main.c | 61 +++---
drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 23 +
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 34 +--
4 files changed, 71 insertions(+), 56 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index b4e96fa9..68ba7bd 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -102,6 +102,8 @@ struct hisi_sas_cq {
struct hisi_sas_dq {
struct hisi_hba *hisi_hba;
+ struct hisi_sas_slot*slot_prep;
+ spinlock_t lock;
int wr_point;
int id;
};
@@ -109,6 +111,7 @@ struct hisi_sas_dq {
struct hisi_sas_device {
struct hisi_hba *hisi_hba;
struct domain_device*sas_device;
+ struct hisi_sas_dq *dq;
struct list_headlist;
u64 attached_phy;
atomic64_t running_req;
@@ -154,9 +157,8 @@ struct hisi_sas_hw {
struct domain_device *device);
struct hisi_sas_device *(*alloc_dev)(struct domain_device *device);
void (*sl_notify)(struct hisi_hba *hisi_hba, int phy_no);
- int (*get_free_slot)(struct hisi_hba *hisi_hba, u32 dev_id,
- int *q, int *s);
- void (*start_delivery)(struct hisi_hba *hisi_hba);
+ int (*get_free_slot)(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq);
+ void (*start_delivery)(struct hisi_sas_dq *dq);
int (*prep_ssp)(struct hisi_hba *hisi_hba,
struct hisi_sas_slot *slot, int is_tmf,
struct hisi_sas_tmf_task *tmf);
@@ -217,7 +219,6 @@ struct hisi_hba {
struct hisi_sas_port port[HISI_SAS_MAX_PHYS];
int queue_count;
- struct hisi_sas_slot*slot_prep;
struct dma_pool *sge_page_pool;
struct hisi_sas_device devices[HISI_SAS_MAX_DEVICES];
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c
b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 54e0cf2..b247220 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -179,10 +179,11 @@ static void hisi_sas_slot_abort(struct work_struct *work)
task->task_done(task);
}
-static int hisi_sas_task_prep(struct sas_task *task, struct hisi_hba *hisi_hba,
- int is_tmf, struct hisi_sas_tmf_task *tmf,
- int *pass)
+static int hisi_sas_task_prep(struct sas_task *task, struct hisi_sas_dq
+ *dq, int is_tmf, struct hisi_sas_tmf_task *tmf,
+ int *pass)
{
+ struct hisi_hba *hisi_hba = dq->hisi_hba;
struct domain_device *device = task->dev;
struct hisi_sas_device *sas_dev = device->lldd_dev;
struct hisi_sas_port *port;
@@ -240,18 +241,24 @@ static int hisi_sas_task_prep(struct sas_task *task,
struct hisi_hba *hisi_hba,
} else
n_elem = task->num_scatter;
+ spin_lock_irqsave(&hisi_hba->lock, flags);
if (hisi_hba->hw->slot_index_alloc)
rc = hisi_hba->hw->slot_index_alloc(hisi_hba, &slot_idx,
device);
else
rc = hisi_sas_slot_index_alloc(hisi_hba, &slot_idx);
- if (rc)
+ if (rc) {
+ spin_unlock_irqrestore(&hisi_hba->lock, flags);
goto err_out;
- rc = hisi_hba->hw->get_free_slot(hisi_hba, sas_dev->device_id,
- &dlvry_queue, &dlvry_queue_slot);
+ }
+ spin_unlock_irqrestore(&hisi_hba->lock, flags);
+
+ rc = hisi_hba->hw->get_free_slot(hisi_hba, dq);
if (rc)
goto err_out_tag;
+ dlvry_queue = dq->id;
+ dlvry_queue_slot = dq->wr_point;
slot = &hisi_hba->slot_info[slot_idx];
memset(slot, 0, sizeof(struct hisi_sas_slot));
@@ -316,7 +323,7 @@ static int hisi_sas_task_prep(struct sas_task *task, struct
hisi_hba *hisi_hba,
task->task_state_flags |= SAS_TASK_AT_INITIATOR;
spin_unlock_irqrestore(&task->task_state_lock, flags);
- hisi_hba->slot_prep = slot;
+ dq->slot_prep = slot;
atomic64_inc(&sas_dev->running_req);
++(*pass);
@@ -354,19 +361,22 @@ static int hisi_sas_task_exec(struct sas_task *task,
gfp_t gfp
[PATCH v5 13/23] scsi: hisi_sas: add phy up/down/bcast and channel ISR
From: Xiang Chen
Add code to initialise interrupts and add some interrupt handlers.
Also add function hisi_sas_v3_destroy_irqs() to clean-up
irqs upon module unloading.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 283 +
1 file changed, 283 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 5580250..3065252 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -173,6 +173,13 @@ enum {
HISI_SAS_PHY_INT_NR
};
+static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
+{
+ void __iomem *regs = hisi_hba->regs + off;
+
+ return readl(regs);
+}
+
static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
{
void __iomem *regs = hisi_hba->regs + off;
@@ -397,6 +404,269 @@ static void sl_notify_v3_hw(struct hisi_hba *hisi_hba,
int phy_no)
hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
}
+static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
+{
+ int i, res = 0;
+ u32 context, port_id, link_rate, hard_phy_linkrate;
+ struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
+ struct asd_sas_phy *sas_phy = &phy->sas_phy;
+ struct device *dev = hisi_hba->dev;
+
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
+
+ port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
+ port_id = (port_id >> (4 * phy_no)) & 0xf;
+ link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
+ link_rate = (link_rate >> (phy_no * 4)) & 0xf;
+
+ if (port_id == 0xf) {
+ dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
+ res = IRQ_NONE;
+ goto end;
+ }
+ sas_phy->linkrate = link_rate;
+ hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
+ HARD_PHY_LINKRATE);
+ phy->maximum_linkrate = hard_phy_linkrate & 0xf;
+ phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
+ phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
+
+ /* Check for SATA dev */
+ context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
+ if (context & (1 << phy_no)) {
+ struct hisi_sas_initial_fis *initial_fis;
+ struct dev_to_host_fis *fis;
+ u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
+
+ dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
+ initial_fis = &hisi_hba->initial_fis[phy_no];
+ fis = &initial_fis->fis;
+ sas_phy->oob_mode = SATA_OOB_MODE;
+ attached_sas_addr[0] = 0x50;
+ attached_sas_addr[7] = phy_no;
+ memcpy(sas_phy->attached_sas_addr,
+ attached_sas_addr,
+ SAS_ADDR_SIZE);
+ memcpy(sas_phy->frame_rcvd, fis,
+ sizeof(struct dev_to_host_fis));
+ phy->phy_type |= PORT_TYPE_SATA;
+ phy->identify.device_type = SAS_SATA_DEV;
+ phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
+ phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
+ } else {
+ u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
+ struct sas_identify_frame *id =
+ (struct sas_identify_frame *)frame_rcvd;
+
+ dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
+ for (i = 0; i < 6; i++) {
+ u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
+ RX_IDAF_DWORD0 + (i * 4));
+ frame_rcvd[i] = __swab32(idaf);
+ }
+ sas_phy->oob_mode = SAS_OOB_MODE;
+ memcpy(sas_phy->attached_sas_addr,
+ &id->sas_addr,
+ SAS_ADDR_SIZE);
+ phy->phy_type |= PORT_TYPE_SAS;
+ phy->identify.device_type = id->dev_type;
+ phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
+ if (phy->identify.device_type == SAS_END_DEVICE)
+ phy->identify.target_port_protocols =
+ SAS_PROTOCOL_SSP;
+ else if (phy->identify.device_type != SAS_PHY_UNUSED)
+ phy->identify.target_port_protocols =
+ SAS_PROTOCOL_SMP;
+ }
+
+ phy->port_id = port_id;
+ phy->phy_attached = 1;
+ queue_work(hisi_hba->wq, &phy->phyup_ws);
+
+end:
+ hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
+CHL_INT0_SL_PHY_ENABLE_MSK);
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
+
+ return res;
+}
+
+static int phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
+{
+
[PATCH] scsi: qla2xxx: fix printk format string warning on 32-bit
On 32-bit architectures, we using %lx to print a size_t causes a harmless
warning:
qla2xxx/qla_init.c: In function 'qla24xx_load_risc_flash':
qla2xxx/qla_init.c:6407:7: error: format '%lx' expects argument of type 'long
unsigned int', but argument 5 has type 'unsigned int' [-Werror=format=]
qla2xxx/qla_init.c: In function 'qla24xx_load_risc_blob':
qla2xxx/qla_init.c:6709:7: error: format '%lx' expects argument of type 'long
unsigned int', but argument 5 has type 'unsigned int' [-Werror=format=]
The correct format string is %zx.
Fixes: 0f110b54d157 ("scsi: qla2xxx: Retain loop test for fwdump length
exceeding buffer length")
Signed-off-by: Arnd Bergmann
---
drivers/scsi/qla2xxx/qla_init.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
index 436968ad4484..730e7fe4344a 100644
--- a/drivers/scsi/qla2xxx/qla_init.c
+++ b/drivers/scsi/qla2xxx/qla_init.c
@@ -6404,7 +6404,7 @@ qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t
*srisc_addr,
"-> template size %x bytes\n", dlen);
if (dlen > risc_size * sizeof(*dcode)) {
ql_log(ql_log_warn, vha, 0x0167,
- "Failed fwdump template exceeds array by %lx bytes\n",
+ "Failed fwdump template exceeds array by %zx bytes\n",
(size_t)(dlen - risc_size * sizeof(*dcode)));
goto default_template;
}
@@ -6706,7 +6706,7 @@ qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t
*srisc_addr)
"-> template size %x bytes\n", dlen);
if (dlen > risc_size * sizeof(*fwcode)) {
ql_log(ql_log_warn, vha, 0x0177,
- "Failed fwdump template exceeds array by %lx bytes\n",
+ "Failed fwdump template exceeds array by %zx bytes\n",
(size_t)(dlen - risc_size * sizeof(*fwcode)));
goto default_template;
}
--
2.9.0
patch "scsi: ibmvscsi_tgt: remove use of class_attrs" added to driver-core-testing
This is a note to let you know that I've just added the patch titled
scsi: ibmvscsi_tgt: remove use of class_attrs
to my driver-core git tree which can be found at
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git
in the driver-core-testing branch.
The patch will show up in the next release of the linux-next tree
(usually sometime within the next 24 hours during the week.)
The patch will be merged to the driver-core-next branch sometime soon,
after it passes testing, and the merge window is open.
If you have any questions about this process, please let me know.
>From f62014fcb9e4af6267dce6e3bf5dc40fdc58f255 Mon Sep 17 00:00:00 2001
From: Greg Kroah-Hartman
Date: Thu, 8 Jun 2017 10:12:37 +0200
Subject: scsi: ibmvscsi_tgt: remove use of class_attrs
The class_attrs pointer is going away and it's not even being used in
this driver, so just remove it entirely.
Acked-by: "Bryant G. Ly"
Cc: Michael Cyr
Cc: "James E.J. Bottomley"
Cc: "Martin K. Petersen"
Cc:
Cc:
Signed-off-by: Greg Kroah-Hartman
---
drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c
b/drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c
index d390325c99ec..b480878e3258 100644
--- a/drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c
+++ b/drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c
@@ -3915,10 +3915,6 @@ static const struct target_core_fabric_ops ibmvscsis_ops
= {
static void ibmvscsis_dev_release(struct device *dev) {};
-static struct class_attribute ibmvscsis_class_attrs[] = {
- __ATTR_NULL,
-};
-
static struct device_attribute dev_attr_system_id =
__ATTR(system_id, S_IRUGO, system_id_show, NULL);
@@ -3938,7 +3934,6 @@ ATTRIBUTE_GROUPS(ibmvscsis_dev);
static struct class ibmvscsis_class = {
.name = "ibmvscsis",
.dev_release= ibmvscsis_dev_release,
- .class_attrs= ibmvscsis_class_attrs,
.dev_groups = ibmvscsis_dev_groups,
};
--
2.13.1
Re: [PATCH] configfs: Fix race between create_link and configfs_rmdir
On Thu, 2017-06-08 at 07:34 -0500, Bryant G. Ly wrote: > > Thanks Nic, > > > > applied to the configfs-for-next tree. I'm not entirely sure if we > > should bother adding this to 4.12 or if it hits rarely enough? > > > It hits for us pretty often when we have a GPFS setup with 10 hosts and 1k+ > vms. > > That is how we discovered the bug in the first place. > Using a DATERA workload with 1K unique multi-tenant backend devices and 1K unique iscsi-target IQNs per node, I've never tripped across this particular bug.. However, our userspace built atop rtslib is enforcing tenant shutdown of individual rmdir(2) of /sys/kernel/config/target/$FABRIC/$WWN/$TPGT/, before rmdir(2) of /sys/kernel/config/target/core/$HBA/$DEV/ occurs. Based on Bryant's original backtrace with targetcli, it looks like the Novalink user-space is not enforcing this requirement across user-space processes doing fabric port symlink and backend device shutdown. That said it probably doesn't need a special v4.12-rc PULL, but based on Bryant's feedback it certainly does deserve a stable CC'.
