[PATCH 01/10] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
From: Seungwon Jeon
This patch introduces Exynos UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/samsung-phy.txt| 22 ++
drivers/phy/Kconfig|7 +
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos-ufs.c | 277
drivers/phy/phy-exynos-ufs.h | 73 ++
drivers/phy/phy-exynos7-ufs.h | 89 +++
include/linux/phy/phy-exynos-ufs.h | 107
7 files changed, 576 insertions(+)
create mode 100644 drivers/phy/phy-exynos-ufs.c
create mode 100644 drivers/phy/phy-exynos-ufs.h
create mode 100644 drivers/phy/phy-exynos7-ufs.h
create mode 100644 include/linux/phy/phy-exynos-ufs.h
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 60c6f2a..1abe2c4 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -174,3 +174,25 @@ Example:
usbdrdphy0 = &usb3_phy0;
usbdrdphy1 = &usb3_phy1;
};
+
+Samsung Exynos7 soc serise UFS PHY Controller
+-
+
+UFS PHY nodes are defined to describe on-chip UFS Physical layer controllers.
+Each UFS PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible list, contains "samsung,exynos7-ufs-phy"
+- reg : offset and length of the UFS PHY register set;
+- reg-names : reg name(s) must be 'phy-pma';
+- #phy-cells : must be zero
+- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
+
+Example:
+ ufs_phy: ufs-phy@0x15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 6b8dd16..7449376 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -358,4 +358,11 @@ config PHY_BRCMSTB_SATA
Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
Likely useful only with CONFIG_SATA_BRCMSTB enabled.
+config PHY_EXYNOS_UFS
+ tristate "EXYNOS SoC series UFS PHY driver"
+ depends on OF && ARCH_EXYNOS
+ select GENERIC_PHY
+ help
+ Support for UFS PHY on Samsung EXYNOS chipsets.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f344e1b..7a36818 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -45,3 +45,4 @@ obj-$(CONFIG_PHY_QCOM_UFS)+= phy-qcom-ufs-qmp-14nm.o
obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
obj-$(CONFIG_PHY_PISTACHIO_USB)+= phy-pistachio-usb.o
+obj-$(CONFIG_PHY_EXYNOS_UFS) += phy-exynos-ufs.o
diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
new file mode 100644
index 000..840375d
--- /dev/null
+++ b/drivers/phy/phy-exynos-ufs.c
@@ -0,0 +1,277 @@
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "phy-exynos-ufs.h"
+
+#define for_each_phy_lane(phy, i) \
+ for (i = 0; i < (phy)->lane_cnt; i++)
+#define for_each_phy_cfg(cfg) \
+ for (; (cfg)->id; (cfg)++)
+
+#define phy_pma_writel(phy, val, reg) \
+ writel((val), (phy)->reg_pma + (reg))
+#define phy_pma_readl(phy, reg) \
+ readl((phy)->reg_pma + (reg))
+
+#define PHY_DEF_LANE_CNT 1
+
+static inline struct exynos_ufs_phy *get_exynos_ufs_phy(struct phy *phy)
+{
+ return (struct exynos_ufs_phy *)phy_get_drvdata(phy);
+}
+
+static void exynos_ufs_phy_config(struct exynos_ufs_phy *phy,
+ const struct exynos_ufs_phy_cfg *cfg, u8 lane)
+{
+ enum {LANE_0, LANE_1}; /* lane index */
+
+ switch (lane) {
+ case LANE_0:
+ phy_pma_writel(phy, cfg->val, cfg->off_0);
+ break;
+ case LANE_1:
+ if (cfg->id == PHY_TRSV_BLK)
+ phy_pma_write
[PATCH 04/10] scsi: ufs: add quirk not to allow reset of interrupt aggregation
From: Seungwon Jeon
Some host controller supports interrupt aggregation, but doesn't
allow to reset counter and timer by s/w.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |3 ++-
drivers/scsi/ufs/ufshcd.h |6 ++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index b441a39..35380aa 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -3204,7 +3204,8 @@ static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
* false interrupt if device completes another request after resetting
* aggregation and before reading the DB.
*/
- if (ufshcd_is_intr_aggr_allowed(hba))
+ if (ufshcd_is_intr_aggr_allowed(hba) &&
+ !(hba->quirks & UFSHCI_QUIRK_BROKEN_RESET_INTR_AGGR))
ufshcd_reset_intr_aggr(hba);
tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 24245c9..7986a54 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -471,6 +471,12 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLRUFS_BIT(7)
+ /*
+* This quirk needs to be enabled if host controller doesn't allow
+* that the interrupt aggregation timer and counter are reset by s/w.
+*/
+ #define UFSHCI_QUIRK_BROKEN_RESET_INTR_AGGR UFS_BIT(8)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH 09/10] scsi: ufs: return value of pwr_change_notify
From: Seungwon Jeon
Behavior of the "powwer mode change" contains vendor specific
operation known as pwr_change_notify. This change adds return
for pwr_change_notify to find success or failure.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 8982da9..142a927 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2579,14 +2579,18 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
dev_err(hba->dev,
"%s: power mode change failed %d\n", __func__, ret);
} else {
- if (hba->vops && hba->vops->pwr_change_notify)
- hba->vops->pwr_change_notify(hba,
- POST_CHANGE, NULL, pwr_mode);
+ if (hba->vops && hba->vops->pwr_change_notify) {
+ ret = hba->vops->pwr_change_notify(hba,
+ POST_CHANGE, NULL, pwr_mode);
+ if (ret)
+ goto out;
+ }
memcpy(&hba->pwr_info, pwr_mode,
sizeof(struct ufs_pa_layer_attr));
}
+out:
return ret;
}
@@ -2601,14 +2605,18 @@ int ufshcd_config_pwr_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr final_params = { 0 };
int ret;
- if (hba->vops && hba->vops->pwr_change_notify)
- hba->vops->pwr_change_notify(hba,
-PRE_CHANGE, desired_pwr_mode, &final_params);
- else
+ if (hba->vops && hba->vops->pwr_change_notify) {
+ ret = hba->vops->pwr_change_notify(hba,
+ PRE_CHANGE, desired_pwr_mode, &final_params);
+ if (ret)
+ goto out;
+ } else {
memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
+ }
ret = ufshcd_change_power_mode(hba, &final_params);
+out:
return ret;
}
EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
--
1.7.10.4
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[PATCH 06/10] scsi: ufs: add specific callback for nexus type
From: Seungwon Jeon
Some host controller needs nexus type information for handling
command. This change adds specific callback function to support
vendor's implementation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |6 ++
drivers/scsi/ufs/ufshcd.h |6 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index bb143ac..bc27f5e 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1377,6 +1377,8 @@ static int ufshcd_queuecommand(struct Scsi_Host *host,
struct scsi_cmnd *cmd)
/* issue command to the controller */
spin_lock_irqsave(hba->host->host_lock, flags);
+ if (hba->vops && hba->vops->specify_nexus_t_xfer_req)
+ hba->vops->specify_nexus_t_xfer_req(hba, tag, lrbp->cmd);
ufshcd_send_command(hba, tag);
out_unlock:
spin_unlock_irqrestore(hba->host->host_lock, flags);
@@ -1577,6 +1579,8 @@ static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
hba->dev_cmd.complete = &wait;
spin_lock_irqsave(hba->host->host_lock, flags);
+ if (hba->vops && hba->vops->specify_nexus_t_xfer_req)
+ hba->vops->specify_nexus_t_xfer_req(hba, tag, lrbp->cmd);
ufshcd_send_command(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
@@ -3848,6 +3852,8 @@ static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int
lun_id, int task_id,
task_req_upiup->input_param2 = cpu_to_be32(task_id);
/* send command to the controller */
+ if (hba->vops && hba->vops->specify_nexus_t_tm_req)
+ hba->vops->specify_nexus_t_tm_req(hba, free_slot, tm_function);
__set_bit(free_slot, &hba->outstanding_tasks);
ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index f4ad3df..0b7dde0 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -257,6 +257,9 @@ struct ufs_pwr_mode_info {
* @pwr_change_notify: called before and after a power mode change
* is carried out to allow vendor spesific capabilities
* to be set.
+ * @specify_nexus_t_xfer_req:
+ * @specify_nexus_t_tm_req: called before command is issued to allow vendor
+ * specific handling to be set for nexus type.
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
*/
@@ -273,6 +276,9 @@ struct ufs_hba_variant_ops {
int (*pwr_change_notify)(struct ufs_hba *,
bool, struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+ void(*specify_nexus_t_xfer_req)(struct ufs_hba *,
+ int, struct scsi_cmnd *);
+ void(*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
int (*resume)(struct ufs_hba *, enum ufs_pm_op);
};
--
1.7.10.4
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[PATCH 03/10] scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
From: Seungwon Jeon
In the right behavior, setting the bit to '0' indicates clear and
'1' indicates no change. If host contoller handles this the other way,
UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR can be used.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 20 ++--
drivers/scsi/ufs/ufshcd.h |5 +
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index f882bf0..b441a39 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -358,7 +358,23 @@ static inline void ufshcd_put_tm_slot(struct ufs_hba *hba,
int slot)
*/
static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
{
- ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos),
REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+}
+
+/**
+ * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
+ * @hba: per adapter instance
+ * @pos: position of the bit to be cleared
+ */
+static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
+{
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
}
/**
@@ -3691,7 +3707,7 @@ static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int
tag)
goto out;
spin_lock_irqsave(hba->host->host_lock, flags);
- ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
+ ufshcd_utmrl_clear(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
/* poll for max. 1 sec to clear door bell register by h/w */
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 1fa5ac1..24245c9 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -466,6 +466,11 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_BROKEN_UTRDUFS_BIT(6)
+ /*
+* Cleaer handling for transfer/task request list is just opposite.
+*/
+ #define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLRUFS_BIT(7)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH 05/10] scsi: ufs: add quirk to enable host controller without hce
From: Seungwon Jeon
Some host controller doesn't support host controller enable via HCE.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 76 +++--
drivers/scsi/ufs/ufshcd.h |5 +++
2 files changed, 79 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 35380aa..bb143ac 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2106,6 +2106,52 @@ static int ufshcd_dme_link_startup(struct ufs_hba *hba)
"dme-link-startup: error code %d\n", ret);
return ret;
}
+/**
+ * ufshcd_dme_reset - UIC command for DME_RESET
+ * @hba: per adapter instance
+ *
+ * DME_RESET command is issued in order to reset UniPro stack.
+ * This function now deal with cold reset.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_reset(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_RESET;
+
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
+
+/**
+ * ufshcd_dme_enable - UIC command for DME_ENABLE
+ * @hba: per adapter instance
+ *
+ * DME_ENABLE command is issued in order to enable UniPro stack.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_enable(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_ENABLE;
+
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
{
@@ -2642,7 +2688,7 @@ out:
}
/**
- * ufshcd_hba_enable - initialize the controller
+ * ufshcd_hba_execute_hce - initialize the controller
* @hba: per adapter instance
*
* The controller resets itself and controller firmware initialization
@@ -2651,7 +2697,7 @@ out:
*
* Returns 0 on success, non-zero value on failure
*/
-static int ufshcd_hba_enable(struct ufs_hba *hba)
+static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
{
int retry;
@@ -2717,6 +2763,32 @@ static int ufshcd_hba_enable(struct ufs_hba *hba)
return 0;
}
+static int ufshcd_hba_enable(struct ufs_hba *hba)
+{
+ int ret;
+
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
+ ufshcd_set_link_off(hba);
+ if (hba->vops && hba->vops->hce_enable_notify)
+ hba->vops->hce_enable_notify(hba, PRE_CHANGE);
+
+ /* enable UIC related interrupts */
+ ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
+ ret = ufshcd_dme_reset(hba);
+ if (!ret) {
+ ret = ufshcd_dme_enable(hba);
+ if (!ret && hba->vops && hba->vops->hce_enable_notify)
+ hba->vops->hce_enable_notify(hba, POST_CHANGE);
+ if (ret)
+ dev_err(hba->dev,
+ "Host controller enable failed with
non-hce\n");
+ }
+ } else {
+ ret = ufshcd_hba_execute_hce(hba);
+ }
+
+ return ret;
+}
static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
{
int tx_lanes, i, err = 0;
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 7986a54..f4ad3df 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -477,6 +477,11 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_BROKEN_RESET_INTR_AGGR UFS_BIT(8)
+ /*
+* This quirks needs to be enabled if host controller cannot be
+* enabled via HCE register.
+*/
+ #define UFSHCI_QUIRK_BROKEN_HCE UFS_BIT(9)
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH 00/10] exynos-ufs: add support for Exynos
This patch-set introduces UFS (Universal Flash Storage) host support for Samsung Exynos SoC. Mostly, it consists of UFS PHY and host specific driver. And it also contains some quirks handling for Exynos. Seungwon Jeon (10): phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC scsi: ufs: add quirk to contain unconformable utrd field scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr scsi: ufs: add quirk not to allow reset of interrupt aggregation scsi: ufs: add quirk to enable host controller without hce scsi: ufs: add specific callback for nexus type scsi: ufs: add add specific callback for hibern8 scsi: ufs: make ufshcd_config_pwr_mode of non-static func scsi: ufs: return value of pwr_change_notify scsi: ufs-exynos: add UFS host support for Exynos SoCs .../devicetree/bindings/phy/samsung-phy.txt| 22 + .../devicetree/bindings/ufs/ufs-exynos.txt | 92 ++ drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos-ufs.c | 277 + drivers/phy/phy-exynos-ufs.h | 73 ++ drivers/phy/phy-exynos7-ufs.h | 89 ++ drivers/scsi/ufs/Kconfig | 12 + drivers/scsi/ufs/Makefile |1 + drivers/scsi/ufs/ufs-exynos-hw.c | 147 +++ drivers/scsi/ufs/ufs-exynos-hw.h | 43 + drivers/scsi/ufs/ufs-exynos.c | 1175 drivers/scsi/ufs/ufs-exynos.h | 463 drivers/scsi/ufs/ufshcd.c | 196 +++- drivers/scsi/ufs/ufshcd.h | 34 + drivers/scsi/ufs/ufshci.h | 26 +- drivers/scsi/ufs/unipro.h | 47 + include/linux/phy/phy-exynos-ufs.h | 107 ++ 18 files changed, 2785 insertions(+), 27 deletions(-) create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt create mode 100644 drivers/phy/phy-exynos-ufs.c create mode 100644 drivers/phy/phy-exynos-ufs.h create mode 100644 drivers/phy/phy-exynos7-ufs.h create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h create mode 100644 drivers/scsi/ufs/ufs-exynos.c create mode 100644 drivers/scsi/ufs/ufs-exynos.h create mode 100644 include/linux/phy/phy-exynos-ufs.h -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 02/10] scsi: ufs: add quirk to contain unconformable utrd field
From: Seungwon Jeon
UTRD(UTP Transfer Request Descriptor)'s field such as offset/length,
especially response's has DWORD expression. This quirk can be specified
for host controller not to conform standard.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 28 +---
drivers/scsi/ufs/ufshcd.h |7 +++
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index b0ade73..f882bf0 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1009,7 +1009,7 @@ ufshcd_send_uic_cmd(struct ufs_hba *hba, struct
uic_command *uic_cmd)
*
* Returns 0 in case of success, non-zero value in case of failure
*/
-static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
+static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
{
struct ufshcd_sg_entry *prd_table;
struct scatterlist *sg;
@@ -1023,8 +1023,13 @@ static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
return sg_segments;
if (sg_segments) {
- lrbp->utr_descriptor_ptr->prd_table_length =
- cpu_to_le16((u16) (sg_segments));
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_UTRD)
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16)(sg_segments *
+ sizeof(struct ufshcd_sg_entry)));
+ else
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16) (sg_segments));
prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
@@ -1347,7 +1352,7 @@ static int ufshcd_queuecommand(struct Scsi_Host *host,
struct scsi_cmnd *cmd)
/* form UPIU before issuing the command */
ufshcd_compose_upiu(hba, lrbp);
- err = ufshcd_map_sg(lrbp);
+ err = ufshcd_map_sg(hba, lrbp);
if (err) {
lrbp->cmd = NULL;
clear_bit_unlock(tag, &hba->lrb_in_use);
@@ -2035,12 +2040,21 @@ static void ufshcd_host_memory_configure(struct ufs_hba
*hba)
cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
/* Response upiu and prdt offset should be in double words */
- utrdlp[i].response_upiu_offset =
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_UTRD) {
+ utrdlp[i].response_upiu_offset =
+ cpu_to_le16(response_offset);
+ utrdlp[i].prd_table_offset =
+ cpu_to_le16(prdt_offset);
+ utrdlp[i].response_upiu_length =
+ cpu_to_le16(ALIGNED_UPIU_SIZE);
+ } else {
+ utrdlp[i].response_upiu_offset =
cpu_to_le16((response_offset >> 2));
- utrdlp[i].prd_table_offset =
+ utrdlp[i].prd_table_offset =
cpu_to_le16((prdt_offset >> 2));
- utrdlp[i].response_upiu_length =
+ utrdlp[i].response_upiu_length =
cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
+ }
hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
hba->lrb[i].ucd_req_ptr =
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index c40a0e7..1fa5ac1 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -459,6 +459,13 @@ struct ufs_hba {
*/
#define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION UFS_BIT(5)
+ /*
+* This quirk needs to be enabled if host controller doesn't conform
+* with UTRD. Some fields such as offset/length might not be in double
word,
+* but in byte.
+*/
+ #define UFSHCI_QUIRK_BROKEN_UTRDUFS_BIT(6)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH 07/10] scsi: ufs: add add specific callback for hibern8
From: Seungwon Jeon
Some host controller needs specific handling before/after
(un)hibernation, This change adds specific callback function
to support vendor's implementation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 36
drivers/scsi/ufs/ufshcd.h |3 +++
2 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index bc27f5e..d425ea1 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -181,8 +181,7 @@ static int ufshcd_probe_hba(struct ufs_hba *hba);
static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
bool skip_ref_clk);
static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
@@ -215,6 +214,16 @@ static inline void ufshcd_disable_irq(struct ufs_hba *hba)
}
}
+static inline int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, true);
+}
+
+static inline int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, false);
+}
+
/*
* ufshcd_wait_for_register - wait for register value to change
* @hba - per-adapter interface
@@ -2395,7 +2404,7 @@ out:
return ret;
}
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
@@ -2404,7 +2413,7 @@ static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
return ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
}
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
int ret;
@@ -2419,6 +2428,25 @@ static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
return ret;
}
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en)
+{
+ int ret;
+
+ if (hba->vops && hba->vops->hibern8_notify)
+ hba->vops->hibern8_notify(hba, en, PRE_CHANGE);
+
+ ret = en ? __ufshcd_uic_hibern8_enter(hba) :
+ __ufshcd_uic_hibern8_exit(hba);
+ if (ret)
+ goto out;
+
+ if (hba->vops && hba->vops->hibern8_notify)
+ hba->vops->hibern8_notify(hba, en, POST_CHANGE);
+
+out:
+ return ret;
+}
+
/**
* ufshcd_init_pwr_info - setting the POR (power on reset)
* values in hba power info
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 0b7dde0..045968e 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -260,6 +260,8 @@ struct ufs_pwr_mode_info {
* @specify_nexus_t_xfer_req:
* @specify_nexus_t_tm_req: called before command is issued to allow vendor
* specific handling to be set for nexus type.
+ * @hibern8_notify: called before and after hibernate/unhibernate is carried
out
+ * to allow vendor spesific implementation.
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
*/
@@ -276,6 +278,7 @@ struct ufs_hba_variant_ops {
int (*pwr_change_notify)(struct ufs_hba *,
bool, struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+ int (*hibern8_notify)(struct ufs_hba *, bool, bool);
void(*specify_nexus_t_xfer_req)(struct ufs_hba *,
int, struct scsi_cmnd *);
void(*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
--
1.7.10.4
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[PATCH 08/10] scsi: ufs: make ufshcd_config_pwr_mode of non-static func
From: Seungwon Jeon
It can be used in the vendor's driver for the specific purpose.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |5 ++---
drivers/scsi/ufs/ufshcd.h |2 ++
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index d425ea1..8982da9 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -185,8 +185,6 @@ static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba,
bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
- struct ufs_pa_layer_attr *desired_pwr_mode);
static int ufshcd_change_power_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *pwr_mode);
@@ -2597,7 +2595,7 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
* @hba: per-adapter instance
* @desired_pwr_mode: desired power configuration
*/
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+int ufshcd_config_pwr_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *desired_pwr_mode)
{
struct ufs_pa_layer_attr final_params = { 0 };
@@ -2613,6 +2611,7 @@ static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
return ret;
}
+EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
/**
* ufshcd_complete_dev_init() - checks device readiness
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 045968e..13368e1 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -636,6 +636,8 @@ extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32
attr_sel,
u8 attr_set, u32 mib_val, u8 peer);
extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
u32 *mib_val, u8 peer);
+extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+ struct ufs_pa_layer_attr *desired_pwr_mode);
/* UIC command interfaces for DME primitives */
#define DME_LOCAL 0
--
1.7.10.4
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[PATCH 10/10] scsi: ufs-exynos: add UFS host support for Exynos SoCs
From: Seungwon Jeon
This patch introduces Exynos UFS host controller driver,
which mainly handles vendor-specific operations including
link startup, power mode change and hibernation/unhibernation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
.../devicetree/bindings/ufs/ufs-exynos.txt | 92 ++
drivers/scsi/ufs/Kconfig | 12 +
drivers/scsi/ufs/Makefile |1 +
drivers/scsi/ufs/ufs-exynos-hw.c | 147 +++
drivers/scsi/ufs/ufs-exynos-hw.h | 43 +
drivers/scsi/ufs/ufs-exynos.c | 1175
drivers/scsi/ufs/ufs-exynos.h | 463
drivers/scsi/ufs/ufshci.h | 26 +-
drivers/scsi/ufs/unipro.h | 47 +
9 files changed, 2005 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
create mode 100644 drivers/scsi/ufs/ufs-exynos.c
create mode 100644 drivers/scsi/ufs/ufs-exynos.h
diff --git a/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
new file mode 100644
index 000..1a6184d
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
@@ -0,0 +1,92 @@
+* Exynos Universal Flash Storage (UFS) Host Controller
+
+UFSHC nodes are defined to describe on-chip UFS host controllers.
+Each UFS controller instance should have its own node.
+
+Required properties:
+- compatible: compatible list, contains "samsung,exynos7-ufs"
+- interrupts:
+- reg :
+
+Optional properties:
+- vdd-hba-supply: phandle to UFS host controller supply regulator node
+- vcc-supply: phandle to VCC supply regulator node
+- vccq-supply : phandle to VCCQ supply regulator node
+- vccq2-supply : phandle to VCCQ2 supply regulator node
+- vcc-supply-1p8: For embedded UFS devices, valid VCC range is
1.7-1.95V
+ or 2.7-3.6V. This boolean property when set,
specifies
+ to use low voltage range of 1.7-1.95V. Note for
external
+ UFS cards this property is invalid and valid VCC
range is
+ always 2.7-3.6V.
+- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
+- vccq-max-microamp : specifies max. load that can be drawn from vccq
supply
+- vccq2-max-microamp: specifies max. load that can be drawn from vccq2
supply
+- -fixed-regulator : boolean property specifying that -supply is a
fixed regulator
+
+- clocks: List of phandle and clock specifier pairs
+- clock-names : List of clock input name strings sorted in the same
+ order as the clocks property.
+- freq-table-hz: Array of operating frequencies
stored in the same
+ order as the clocks property. If this property is not
+ defined or a value in the array is "0" then it is
assumed
+ that the frequency is set by the parent clock or a
+ fixed rate clock source.
+- pclk-freq-avail-range : specifies available frequency range(min/max) for APB
clock
+- ufs,pwr-attr-mode : specifies mode value for power mode change
+- ufs,pwr-attr-lane : specifies lane count value for power mode change
+- ufs,pwr-attr-gear : specifies gear count value for power mode change
+- ufs,pwr-attr-hs-series : specifies HS rate series for power mode change
+- ufs,pwr-local-l2-timer : specifies array of local UNIPRO L2 timer values
+
+- ufs,pwr-remote-l2-timer : specifies array of remote UNIPR L2 timer values
+
+- ufs-rx-adv-fine-gran-sup_en : specifies support of fine granularity of MPHY
+- ufs-rx-adv-fine-gran-step : specifies granularity steps of MPHY
+- ufs-rx-adv-min-activate-time-cap : specifies rx advanced minimum activate
time of MPHY
+- ufs-pa-granularity : specifies Granularity for PA_TActivate and
PA_Hibern8Time
+- ufs-pa-tacctivate : specifies time wake-up remote M-RX
+- ufs-pa-hibern8time : specifies minimum time to wait in HIBERN8 state
+
+Note: If above properties are not defined it can be assumed that the supply
+regulators or clocks are always on.
+
+Example:
+ ufshc@0x1557 {
+ compatible = "samsung,exynos7-ufs";
+ reg = <0xfc598000 0x800>;
+ reg = <0x1557 0x100>,
+ <0x15570100 0x100>,
+ <0x15571000 0x200>,
+ <0x15572000 0x300>;
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts
Re: [PATCH 02/10] scsi: ufs: add quirk to contain unconformable utrd field
Hi Amit,
Thanks for your review comments.
On 08/26/2015 11:43 AM, amit daniel kachhap wrote:
Few minor comments below,
On Fri, Aug 21, 2015 at 2:57 PM, Alim Akhtar wrote:
From: Seungwon Jeon
UTRD(UTP Transfer Request Descriptor)'s field such as offset/length,
especially response's has DWORD expression. This quirk can be specified
for host controller not to conform standard.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 28 +---
drivers/scsi/ufs/ufshcd.h |7 +++
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index b0ade73..f882bf0 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1009,7 +1009,7 @@ ufshcd_send_uic_cmd(struct ufs_hba *hba, struct
uic_command *uic_cmd)
*
* Returns 0 in case of success, non-zero value in case of failure
*/
-static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
+static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
{
struct ufshcd_sg_entry *prd_table;
struct scatterlist *sg;
@@ -1023,8 +1023,13 @@ static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
return sg_segments;
if (sg_segments) {
- lrbp->utr_descriptor_ptr->prd_table_length =
- cpu_to_le16((u16) (sg_segments));
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_UTRD)
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16)(sg_segments *
+ sizeof(struct ufshcd_sg_entry)));
+ else
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16) (sg_segments));
prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
@@ -1347,7 +1352,7 @@ static int ufshcd_queuecommand(struct Scsi_Host *host,
struct scsi_cmnd *cmd)
/* form UPIU before issuing the command */
ufshcd_compose_upiu(hba, lrbp);
- err = ufshcd_map_sg(lrbp);
+ err = ufshcd_map_sg(hba, lrbp);
if (err) {
lrbp->cmd = NULL;
clear_bit_unlock(tag, &hba->lrb_in_use);
@@ -2035,12 +2040,21 @@ static void ufshcd_host_memory_configure(struct ufs_hba
*hba)
cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
/* Response upiu and prdt offset should be in double words */
This comment can be moved below for the else case.
ok
- utrdlp[i].response_upiu_offset =
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_UTRD) {
+ utrdlp[i].response_upiu_offset =
+ cpu_to_le16(response_offset);
+ utrdlp[i].prd_table_offset =
+ cpu_to_le16(prdt_offset);
+ utrdlp[i].response_upiu_length =
+ cpu_to_le16(ALIGNED_UPIU_SIZE);
+ } else {
+ utrdlp[i].response_upiu_offset =
cpu_to_le16((response_offset >> 2));
- utrdlp[i].prd_table_offset =
+ utrdlp[i].prd_table_offset =
cpu_to_le16((prdt_offset >> 2));
- utrdlp[i].response_upiu_length =
+ utrdlp[i].response_upiu_length =
cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
+ }
hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
hba->lrb[i].ucd_req_ptr =
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index c40a0e7..1fa5ac1 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -459,6 +459,13 @@ struct ufs_hba {
*/
#define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION UFS_BIT(5)
+ /*
+* This quirk needs to be enabled if host controller doesn't conform
+* with UTRD. Some fields such as offset/length might not be in double
word,
+* but in byte.
+*/
+ #define UFSHCI_QUIRK_BROKEN_UTRDUFS_BIT(6)
This macro name may be given more meaningful name such as
UFSHCI_QUIRK_BYTE_ALIGN_UTRD or something similar.
ok, will change
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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Re: [PATCH 01/10] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
HI Alexey,
Thanks for review.
I will address your comments in v2 of this patch.
On 08/24/2015 04:15 AM, Alexey Klimov wrote:
Hi Alim,
On Fri, Aug 21, 2015 at 12:27 PM, Alim Akhtar wrote:
From: Seungwon Jeon
This patch introduces Exynos UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/samsung-phy.txt| 22 ++
drivers/phy/Kconfig|7 +
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos-ufs.c | 277
drivers/phy/phy-exynos-ufs.h | 73 ++
drivers/phy/phy-exynos7-ufs.h | 89 +++
include/linux/phy/phy-exynos-ufs.h | 107
7 files changed, 576 insertions(+)
create mode 100644 drivers/phy/phy-exynos-ufs.c
create mode 100644 drivers/phy/phy-exynos-ufs.h
create mode 100644 drivers/phy/phy-exynos7-ufs.h
create mode 100644 include/linux/phy/phy-exynos-ufs.h
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 60c6f2a..1abe2c4 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -174,3 +174,25 @@ Example:
usbdrdphy0 = &usb3_phy0;
usbdrdphy1 = &usb3_phy1;
};
+
+Samsung Exynos7 soc serise UFS PHY Controller
+-
+
+UFS PHY nodes are defined to describe on-chip UFS Physical layer controllers.
+Each UFS PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible list, contains "samsung,exynos7-ufs-phy"
+- reg : offset and length of the UFS PHY register set;
+- reg-names : reg name(s) must be 'phy-pma';
+- #phy-cells : must be zero
+- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
+
+Example:
+ ufs_phy: ufs-phy@0x15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 6b8dd16..7449376 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -358,4 +358,11 @@ config PHY_BRCMSTB_SATA
Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
Likely useful only with CONFIG_SATA_BRCMSTB enabled.
+config PHY_EXYNOS_UFS
+ tristate "EXYNOS SoC series UFS PHY driver"
+ depends on OF && ARCH_EXYNOS
+ select GENERIC_PHY
+ help
+ Support for UFS PHY on Samsung EXYNOS chipsets.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f344e1b..7a36818 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -45,3 +45,4 @@ obj-$(CONFIG_PHY_QCOM_UFS)+= phy-qcom-ufs-qmp-14nm.o
obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
obj-$(CONFIG_PHY_PISTACHIO_USB)+= phy-pistachio-usb.o
+obj-$(CONFIG_PHY_EXYNOS_UFS) += phy-exynos-ufs.o
diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
new file mode 100644
index 000..840375d
--- /dev/null
+++ b/drivers/phy/phy-exynos-ufs.c
@@ -0,0 +1,277 @@
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
What do you think about sorting this?
+#include "phy-exynos-ufs.h"
+
+#define for_each_phy_lane(phy, i) \
+ for (i = 0; i < (phy)->lane_cnt; i++)
+#define for_each_phy_cfg(cfg) \
+ for (; (cfg)->id; (cfg)++)
+
+#define phy_pma_writel(phy, val, reg) \
+ writel((val), (phy)->reg_pma + (reg))
+#define phy_pma_readl(phy, reg) \
+ readl((phy)->reg_pma + (reg))
+
+#define PHY_DEF_LANE_CNT 1
+
+static inline struct exynos_ufs_phy *get_exynos_ufs_phy(struct phy *phy)
+{
+ return (struct exynos_ufs_phy *)phy_get_drvdata(phy);
+}
Let compiler decide when to inline static function.
Please don't make static inline functions in *.c files.
Thanks.
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Re: [PATCH 10/10] scsi: ufs-exynos: add UFS host support for Exynos SoCs
HI Amit,
On 08/26/2015 12:12 PM, amit daniel kachhap wrote:
On Fri, Aug 21, 2015 at 2:58 PM, Alim Akhtar wrote:
From: Seungwon Jeon
This patch introduces Exynos UFS host controller driver,
which mainly handles vendor-specific operations including
link startup, power mode change and hibernation/unhibernation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
.../devicetree/bindings/ufs/ufs-exynos.txt | 92 ++
drivers/scsi/ufs/Kconfig | 12 +
drivers/scsi/ufs/Makefile |1 +
drivers/scsi/ufs/ufs-exynos-hw.c | 147 +++
drivers/scsi/ufs/ufs-exynos-hw.h | 43 +
drivers/scsi/ufs/ufs-exynos.c | 1175
drivers/scsi/ufs/ufs-exynos.h | 463
drivers/scsi/ufs/ufshci.h | 26 +-
drivers/scsi/ufs/unipro.h | 47 +
9 files changed, 2005 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
create mode 100644 drivers/scsi/ufs/ufs-exynos.c
create mode 100644 drivers/scsi/ufs/ufs-exynos.h
diff --git a/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
new file mode 100644
index 000..1a6184d
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
@@ -0,0 +1,92 @@
+* Exynos Universal Flash Storage (UFS) Host Controller
+
+UFSHC nodes are defined to describe on-chip UFS host controllers.
+Each UFS controller instance should have its own node.
+
+Required properties:
+- compatible: compatible list, contains "samsung,exynos7-ufs"
+- interrupts:
+- reg :
+
+Optional properties:
+- vdd-hba-supply: phandle to UFS host controller supply regulator node
+- vcc-supply: phandle to VCC supply regulator node
+- vccq-supply : phandle to VCCQ supply regulator node
+- vccq2-supply : phandle to VCCQ2 supply regulator node
+- vcc-supply-1p8: For embedded UFS devices, valid VCC range is
1.7-1.95V
+ or 2.7-3.6V. This boolean property when set,
specifies
+ to use low voltage range of 1.7-1.95V. Note for
external
+ UFS cards this property is invalid and valid VCC
range is
+ always 2.7-3.6V.
+- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
+- vccq-max-microamp : specifies max. load that can be drawn from vccq
supply
+- vccq2-max-microamp: specifies max. load that can be drawn from vccq2
supply
+- -fixed-regulator : boolean property specifying that -supply is a
fixed regulator
+
+- clocks: List of phandle and clock specifier pairs
+- clock-names : List of clock input name strings sorted in the same
+ order as the clocks property.
+- freq-table-hz: Array of operating frequencies
stored in the same
+ order as the clocks property. If this property is not
+ defined or a value in the array is "0" then it is
assumed
+ that the frequency is set by the parent clock or a
+ fixed rate clock source.
+- pclk-freq-avail-range : specifies available frequency range(min/max) for APB
clock
+- ufs,pwr-attr-mode : specifies mode value for power mode change
+- ufs,pwr-attr-lane : specifies lane count value for power mode change
+- ufs,pwr-attr-gear : specifies gear count value for power mode change
+- ufs,pwr-attr-hs-series : specifies HS rate series for power mode change
+- ufs,pwr-local-l2-timer : specifies array of local UNIPRO L2 timer values
+
+- ufs,pwr-remote-l2-timer : specifies array of remote UNIPR L2 timer values
s/UNIPR/UNIPRO
ok
+
+- ufs-rx-adv-fine-gran-sup_en : specifies support of fine granularity of MPHY
I suppose this field is bool type. This can be mentioned here.
+- ufs-rx-adv-fine-gran-step : specifies granularity steps of MPHY
+- ufs-rx-adv-min-activate-time-cap : specifies rx advanced minimum activate
time of MPHY
+- ufs-pa-granularity : specifies Granularity for PA_TActivate and
PA_Hibern8Time
+- ufs-pa-tacctivate : specifies time wake-up remote M-RX
+- ufs-pa-hibern8time : specifies minimum time to wait in HIBERN8 state
+
+Note: If above properties are not defined it can be assumed that the supply
+regulators or clocks are always on.
+
+Example:
+ ufshc@0x1557 {
+ compatible = "samsung,exynos7-ufs";
+ reg = <0xfc598000 0x800>;
+ reg = <0x1557 0x100>,
+ <0x15570100 0x
Re: [PATCH 04/10] scsi: ufs: add quirk not to allow reset of interrupt aggregation
Hi Amit
On 08/26/2015 11:46 AM, amit daniel kachhap wrote:
Few comments below,
On Fri, Aug 21, 2015 at 2:57 PM, Alim Akhtar wrote:
From: Seungwon Jeon
Some host controller supports interrupt aggregation, but doesn't
allow to reset counter and timer by s/w.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |3 ++-
drivers/scsi/ufs/ufshcd.h |6 ++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index b441a39..35380aa 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -3204,7 +3204,8 @@ static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
* false interrupt if device completes another request after resetting
* aggregation and before reading the DB.
*/
- if (ufshcd_is_intr_aggr_allowed(hba))
+ if (ufshcd_is_intr_aggr_allowed(hba) &&
+ !(hba->quirks & UFSHCI_QUIRK_BROKEN_RESET_INTR_AGGR))
How about to rename this quirk as UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR as
there are some drawbacks about the existing method also as per the
comments above. Or this can be also put as opts instead as quirk.
Ok will rename this. Thanks
ufshcd_reset_intr_aggr(hba);
tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 24245c9..7986a54 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -471,6 +471,12 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLRUFS_BIT(7)
+ /*
+* This quirk needs to be enabled if host controller doesn't allow
+* that the interrupt aggregation timer and counter are reset by s/w.
+*/
+ #define UFSHCI_QUIRK_BROKEN_RESET_INTR_AGGR UFS_BIT(8)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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Re: [PATCH 07/10] scsi: ufs: add add specific callback for hibern8
Hi Amit,
On 08/26/2015 11:51 AM, amit daniel kachhap wrote:
On Fri, Aug 21, 2015 at 2:57 PM, Alim Akhtar wrote:
From: Seungwon Jeon
Some host controller needs specific handling before/after
(un)hibernation, This change adds specific callback function
to support vendor's implementation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 36
drivers/scsi/ufs/ufshcd.h |3 +++
2 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index bc27f5e..d425ea1 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -181,8 +181,7 @@ static int ufshcd_probe_hba(struct ufs_hba *hba);
static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
bool skip_ref_clk);
static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
@@ -215,6 +214,16 @@ static inline void ufshcd_disable_irq(struct ufs_hba *hba)
}
}
+static inline int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, true);
+}
+
+static inline int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, false);
+}
+
/*
* ufshcd_wait_for_register - wait for register value to change
* @hba - per-adapter interface
@@ -2395,7 +2404,7 @@ out:
return ret;
}
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
@@ -2404,7 +2413,7 @@ static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
return ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
}
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
int ret;
@@ -2419,6 +2428,25 @@ static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
return ret;
}
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en)
+{
+ int ret;
+
+ if (hba->vops && hba->vops->hibern8_notify)
+ hba->vops->hibern8_notify(hba, en, PRE_CHANGE);
Return of hibern8_notify is not checked. Otherwise make the return type void.
ok will change.
+
+ ret = en ? __ufshcd_uic_hibern8_enter(hba) :
+ __ufshcd_uic_hibern8_exit(hba);
+ if (ret)
+ goto out;
+
+ if (hba->vops && hba->vops->hibern8_notify)
+ hba->vops->hibern8_notify(hba, en, POST_CHANGE);
+
+out:
+ return ret;
+}
+
/**
* ufshcd_init_pwr_info - setting the POR (power on reset)
* values in hba power info
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 0b7dde0..045968e 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -260,6 +260,8 @@ struct ufs_pwr_mode_info {
* @specify_nexus_t_xfer_req:
* @specify_nexus_t_tm_req: called before command is issued to allow vendor
* specific handling to be set for nexus type.
+ * @hibern8_notify: called before and after hibernate/unhibernate is carried
out
+ * to allow vendor spesific implementation.
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
*/
@@ -276,6 +278,7 @@ struct ufs_hba_variant_ops {
int (*pwr_change_notify)(struct ufs_hba *,
bool, struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+ int (*hibern8_notify)(struct ufs_hba *, bool, bool);
void(*specify_nexus_t_xfer_req)(struct ufs_hba *,
int, struct scsi_cmnd *);
void(*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
--
1.7.10.4
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Re: [PATCH 08/10] scsi: ufs: make ufshcd_config_pwr_mode of non-static func
Hi Amit,
On 08/26/2015 11:53 AM, amit daniel kachhap wrote:
On Fri, Aug 21, 2015 at 2:57 PM, Alim Akhtar wrote:
From: Seungwon Jeon
It can be used in the vendor's driver for the specific purpose.
more description of this log will be useful.
Will reword.
Thanks
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |5 ++---
drivers/scsi/ufs/ufshcd.h |2 ++
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index d425ea1..8982da9 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -185,8 +185,6 @@ static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba,
bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
- struct ufs_pa_layer_attr *desired_pwr_mode);
static int ufshcd_change_power_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *pwr_mode);
@@ -2597,7 +2595,7 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
* @hba: per-adapter instance
* @desired_pwr_mode: desired power configuration
*/
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+int ufshcd_config_pwr_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *desired_pwr_mode)
{
struct ufs_pa_layer_attr final_params = { 0 };
@@ -2613,6 +2611,7 @@ static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
return ret;
}
+EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
/**
* ufshcd_complete_dev_init() - checks device readiness
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 045968e..13368e1 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -636,6 +636,8 @@ extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32
attr_sel,
u8 attr_set, u32 mib_val, u8 peer);
extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
u32 *mib_val, u8 peer);
+extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+ struct ufs_pa_layer_attr *desired_pwr_mode);
/* UIC command interfaces for DME primitives */
#define DME_LOCAL 0
--
1.7.10.4
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Re: [PATCH 09/10] scsi: ufs: return value of pwr_change_notify
Hi Amit
On 08/26/2015 11:55 AM, amit daniel kachhap wrote:
On Fri, Aug 21, 2015 at 2:58 PM, Alim Akhtar wrote:
From: Seungwon Jeon
Behavior of the "powwer mode change" contains vendor specific
s/powwer/power
ok
operation known as pwr_change_notify. This change adds return
for pwr_change_notify to find success or failure.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 8982da9..142a927 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2579,14 +2579,18 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
dev_err(hba->dev,
"%s: power mode change failed %d\n", __func__, ret);
} else {
- if (hba->vops && hba->vops->pwr_change_notify)
- hba->vops->pwr_change_notify(hba,
- POST_CHANGE, NULL, pwr_mode);
+ if (hba->vops && hba->vops->pwr_change_notify) {
+ ret = hba->vops->pwr_change_notify(hba,
+ POST_CHANGE, NULL, pwr_mode);
+ if (ret)
+ goto out;
+ }
memcpy(&hba->pwr_info, pwr_mode,
sizeof(struct ufs_pa_layer_attr));
}
+out:
return ret;
}
@@ -2601,14 +2605,18 @@ int ufshcd_config_pwr_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr final_params = { 0 };
int ret;
- if (hba->vops && hba->vops->pwr_change_notify)
- hba->vops->pwr_change_notify(hba,
-PRE_CHANGE, desired_pwr_mode, &final_params);
- else
+ if (hba->vops && hba->vops->pwr_change_notify) {
+ ret = hba->vops->pwr_change_notify(hba,
+ PRE_CHANGE, desired_pwr_mode, &final_params);
+ if (ret)
+ goto out;
+ } else {
memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
+ }
ret = ufshcd_change_power_mode(hba, &final_params);
+out:
return ret;
}
EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
--
1.7.10.4
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[PATCH v2 05/11] scsi: ufs: add quirk to enable host controller without hce
From: Seungwon Jeon
Some host controller doesn't support host controller enable via HCE.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 76 +++--
drivers/scsi/ufs/ufshcd.h |5 +++
2 files changed, 79 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 7b87075..0fcfa71 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2106,6 +2106,52 @@ static int ufshcd_dme_link_startup(struct ufs_hba *hba)
"dme-link-startup: error code %d\n", ret);
return ret;
}
+/**
+ * ufshcd_dme_reset - UIC command for DME_RESET
+ * @hba: per adapter instance
+ *
+ * DME_RESET command is issued in order to reset UniPro stack.
+ * This function now deal with cold reset.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_reset(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_RESET;
+
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
+
+/**
+ * ufshcd_dme_enable - UIC command for DME_ENABLE
+ * @hba: per adapter instance
+ *
+ * DME_ENABLE command is issued in order to enable UniPro stack.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_enable(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_ENABLE;
+
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
{
@@ -2642,7 +2688,7 @@ out:
}
/**
- * ufshcd_hba_enable - initialize the controller
+ * ufshcd_hba_execute_hce - initialize the controller
* @hba: per adapter instance
*
* The controller resets itself and controller firmware initialization
@@ -2651,7 +2697,7 @@ out:
*
* Returns 0 on success, non-zero value on failure
*/
-static int ufshcd_hba_enable(struct ufs_hba *hba)
+static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
{
int retry;
@@ -2717,6 +2763,32 @@ static int ufshcd_hba_enable(struct ufs_hba *hba)
return 0;
}
+static int ufshcd_hba_enable(struct ufs_hba *hba)
+{
+ int ret;
+
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
+ ufshcd_set_link_off(hba);
+ if (hba->vops && hba->vops->hce_enable_notify)
+ hba->vops->hce_enable_notify(hba, PRE_CHANGE);
+
+ /* enable UIC related interrupts */
+ ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
+ ret = ufshcd_dme_reset(hba);
+ if (!ret) {
+ ret = ufshcd_dme_enable(hba);
+ if (!ret && hba->vops && hba->vops->hce_enable_notify)
+ hba->vops->hce_enable_notify(hba, POST_CHANGE);
+ if (ret)
+ dev_err(hba->dev,
+ "Host controller enable failed with
non-hce\n");
+ }
+ } else {
+ ret = ufshcd_hba_execute_hce(hba);
+ }
+
+ return ret;
+}
static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
{
int tx_lanes, i, err = 0;
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index c59f8ae..c6dc107 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -477,6 +477,11 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR UFS_BIT(8)
+ /*
+* This quirks needs to be enabled if host controller cannot be
+* enabled via HCE register.
+*/
+ #define UFSHCI_QUIRK_BROKEN_HCE UFS_BIT(9)
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v2 04/11] scsi: ufs: add quirk not to allow reset of interrupt aggregation
From: Seungwon Jeon
Some host controller supports interrupt aggregation, but doesn't
allow to reset counter and timer by s/w.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |3 ++-
drivers/scsi/ufs/ufshcd.h |6 ++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 257bffc..7b87075 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -3204,7 +3204,8 @@ static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
* false interrupt if device completes another request after resetting
* aggregation and before reading the DB.
*/
- if (ufshcd_is_intr_aggr_allowed(hba))
+ if (ufshcd_is_intr_aggr_allowed(hba) &&
+ !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
ufshcd_reset_intr_aggr(hba);
tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index ba38842..c59f8ae 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -471,6 +471,12 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLRUFS_BIT(7)
+ /*
+* This quirk needs to be enabled if host controller doesn't allow
+* that the interrupt aggregation timer and counter are reset by s/w.
+*/
+ #define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR UFS_BIT(8)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v2 08/11] scsi: ufs: make ufshcd_config_pwr_mode of non-static func
From: Seungwon Jeon
This makes ufshcd_config_pwr_mode non-static so that other vendors
like exynos can use the same.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |5 ++---
drivers/scsi/ufs/ufshcd.h |2 ++
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index ccf7c83..da52c45 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -185,8 +185,6 @@ static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba,
bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
- struct ufs_pa_layer_attr *desired_pwr_mode);
static int ufshcd_change_power_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *pwr_mode);
@@ -2597,7 +2595,7 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
* @hba: per-adapter instance
* @desired_pwr_mode: desired power configuration
*/
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+int ufshcd_config_pwr_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *desired_pwr_mode)
{
struct ufs_pa_layer_attr final_params = { 0 };
@@ -2613,6 +2611,7 @@ static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
return ret;
}
+EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
/**
* ufshcd_complete_dev_init() - checks device readiness
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 2fd0c3c..83fe605 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -636,6 +636,8 @@ extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32
attr_sel,
u8 attr_set, u32 mib_val, u8 peer);
extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
u32 *mib_val, u8 peer);
+extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+ struct ufs_pa_layer_attr *desired_pwr_mode);
/* UIC command interfaces for DME primitives */
#define DME_LOCAL 0
--
1.7.10.4
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[PATCH v2 11/11] scsi: ufs: Add exynos ufs platform data
This adds ufs_hba_exynos_ops{} to platform data, so that
exynos ufs driver can be probed.
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd-pltfrm.c |2 ++
drivers/scsi/ufs/ufshcd.h|1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/scsi/ufs/ufshcd-pltfrm.c b/drivers/scsi/ufs/ufshcd-pltfrm.c
index 7db9564..39dae76 100644
--- a/drivers/scsi/ufs/ufshcd-pltfrm.c
+++ b/drivers/scsi/ufs/ufshcd-pltfrm.c
@@ -373,6 +373,8 @@ static int ufshcd_pltfrm_remove(struct platform_device
*pdev)
static const struct of_device_id ufs_of_match[] = {
{ .compatible = "jedec,ufs-1.1"},
+ { .compatible = "samsung,exynos7-ufs",
+.data = &ufs_hba_exynos_ops},
{},
};
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 83fe605..15f2a7c 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -687,4 +687,5 @@ static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
int ufshcd_hold(struct ufs_hba *hba, bool async);
void ufshcd_release(struct ufs_hba *hba);
+extern const struct ufs_hba_variant_ops ufs_hba_exynos_ops;
#endif /* End of Header */
--
1.7.10.4
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[PATCH v2 09/11] scsi: ufs: return value of pwr_change_notify
From: Seungwon Jeon
Behavior of the "power mode change" contains vendor specific
operation known as pwr_change_notify. This change adds return
for pwr_change_notify to find success or failure.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index da52c45..0c9f319 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2579,14 +2579,18 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
dev_err(hba->dev,
"%s: power mode change failed %d\n", __func__, ret);
} else {
- if (hba->vops && hba->vops->pwr_change_notify)
- hba->vops->pwr_change_notify(hba,
- POST_CHANGE, NULL, pwr_mode);
+ if (hba->vops && hba->vops->pwr_change_notify) {
+ ret = hba->vops->pwr_change_notify(hba,
+ POST_CHANGE, NULL, pwr_mode);
+ if (ret)
+ goto out;
+ }
memcpy(&hba->pwr_info, pwr_mode,
sizeof(struct ufs_pa_layer_attr));
}
+out:
return ret;
}
@@ -2601,14 +2605,18 @@ int ufshcd_config_pwr_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr final_params = { 0 };
int ret;
- if (hba->vops && hba->vops->pwr_change_notify)
- hba->vops->pwr_change_notify(hba,
-PRE_CHANGE, desired_pwr_mode, &final_params);
- else
+ if (hba->vops && hba->vops->pwr_change_notify) {
+ ret = hba->vops->pwr_change_notify(hba,
+ PRE_CHANGE, desired_pwr_mode, &final_params);
+ if (ret)
+ goto out;
+ } else {
memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
+ }
ret = ufshcd_change_power_mode(hba, &final_params);
+out:
return ret;
}
EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
--
1.7.10.4
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[PATCH v2 10/11] scsi: ufs-exynos: add UFS host support for Exynos SoCs
From: Seungwon Jeon
This patch introduces Exynos UFS host controller driver,
which mainly handles vendor-specific operations including
link startup, power mode change and hibernation/unhibernation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
.../devicetree/bindings/ufs/ufs-exynos.txt | 93 ++
drivers/scsi/ufs/Kconfig | 12 +
drivers/scsi/ufs/Makefile |1 +
drivers/scsi/ufs/ufs-exynos-hw.c | 147 +++
drivers/scsi/ufs/ufs-exynos-hw.h | 43 +
drivers/scsi/ufs/ufs-exynos.c | 1173
drivers/scsi/ufs/ufs-exynos.h | 463
drivers/scsi/ufs/ufshci.h | 26 +-
drivers/scsi/ufs/unipro.h | 47 +
9 files changed, 2004 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
create mode 100644 drivers/scsi/ufs/ufs-exynos.c
create mode 100644 drivers/scsi/ufs/ufs-exynos.h
diff --git a/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
new file mode 100644
index 000..188a240
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
@@ -0,0 +1,93 @@
+* Exynos Universal Flash Storage (UFS) Host Controller
+
+UFSHC nodes are defined to describe on-chip UFS host controllers.
+Each UFS controller instance should have its own node.
+
+Required properties:
+- compatible: compatible list, contains "samsung,exynos7-ufs"
+- interrupts:
+- reg :
+
+Optional properties:
+- vdd-hba-supply: phandle to UFS host controller supply regulator node
+- vcc-supply: phandle to VCC supply regulator node
+- vccq-supply : phandle to VCCQ supply regulator node
+- vccq2-supply : phandle to VCCQ2 supply regulator node
+- vcc-supply-1p8: For embedded UFS devices, valid VCC range is
1.7-1.95V
+ or 2.7-3.6V. This boolean property when set,
specifies
+ to use low voltage range of 1.7-1.95V. Note for
external
+ UFS cards this property is invalid and valid VCC
range is
+ always 2.7-3.6V.
+- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
+- vccq-max-microamp : specifies max. load that can be drawn from vccq
supply
+- vccq2-max-microamp: specifies max. load that can be drawn from vccq2
supply
+- -fixed-regulator : boolean property specifying that -supply is a
fixed regulator
+
+- clocks: List of phandle and clock specifier pairs
+- clock-names : List of clock input name strings sorted in the same
+ order as the clocks property.
+- freq-table-hz: Array of operating frequencies
stored in the same
+ order as the clocks property. If this property is not
+ defined or a value in the array is "0" then it is
assumed
+ that the frequency is set by the parent clock or a
+ fixed rate clock source.
+- pclk-freq-avail-range : specifies available frequency range(min/max) for APB
clock
+- ufs,pwr-attr-mode : specifies mode value for power mode change
+- ufs,pwr-attr-lane : specifies lane count value for power mode change
+- ufs,pwr-attr-gear : specifies gear count value for power mode change
+- ufs,pwr-attr-hs-series : specifies HS rate series for power mode change
+- ufs,pwr-local-l2-timer : specifies array of local UNIPRO L2 timer values
+
+- ufs,pwr-remote-l2-timer : specifies array of remote UNIPRO L2 timer values
+
+- ufs-rx-adv-fine-gran-sup_en : specifies support of fine granularity of MPHY,
+ this is a boolean property.
+- ufs-rx-adv-fine-gran-step : specifies granularity steps of MPHY
+- ufs-rx-adv-min-activate-time-cap : specifies rx advanced minimum activate
time of MPHY
+- ufs-pa-granularity : specifies Granularity for PA_TActivate and
PA_Hibern8Time
+- ufs-pa-tacctivate : specifies time wake-up remote M-RX
+- ufs-pa-hibern8time : specifies minimum time to wait in HIBERN8 state
+
+Note: If above properties are not defined it can be assumed that the supply
+regulators or clocks are always on.
+
+Example:
+ ufshc@0x1557 {
+ compatible = "samsung,exynos7-ufs";
+ reg = <0xfc598000 0x800>;
+ reg = <0x1557 0x100>,
+ <0x15570100 0x100>,
+ <0x15571000 0x200>,
+ <0x15572000 0x300>;
+ reg-names = "hci", "vs_hci", "unip
[PATCH v2 03/11] scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
From: Seungwon Jeon
In the right behavior, setting the bit to '0' indicates clear and
'1' indicates no change. If host contoller handles this the other way,
UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR can be used.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 20 ++--
drivers/scsi/ufs/ufshcd.h |5 +
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 90f76e7..257bffc 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -358,7 +358,23 @@ static inline void ufshcd_put_tm_slot(struct ufs_hba *hba,
int slot)
*/
static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
{
- ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos),
REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+}
+
+/**
+ * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
+ * @hba: per adapter instance
+ * @pos: position of the bit to be cleared
+ */
+static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
+{
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
}
/**
@@ -3691,7 +3707,7 @@ static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int
tag)
goto out;
spin_lock_irqsave(hba->host->host_lock, flags);
- ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
+ ufshcd_utmrl_clear(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
/* poll for max. 1 sec to clear door bell register by h/w */
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 9ed4c9e..ba38842 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -466,6 +466,11 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_BYTE_ALIGN_UTRDUFS_BIT(6)
+ /*
+* Cleaer handling for transfer/task request list is just opposite.
+*/
+ #define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLRUFS_BIT(7)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v2 07/11] scsi: ufs: add add specific callback for hibern8
From: Seungwon Jeon
Some host controller needs specific handling before/after
(un)hibernation, This change adds specific callback function
to support vendor's implementation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 36
drivers/scsi/ufs/ufshcd.h |3 +++
2 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 2f0de4b..ccf7c83 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -181,8 +181,7 @@ static int ufshcd_probe_hba(struct ufs_hba *hba);
static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
bool skip_ref_clk);
static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
@@ -215,6 +214,16 @@ static inline void ufshcd_disable_irq(struct ufs_hba *hba)
}
}
+static inline int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, true);
+}
+
+static inline int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, false);
+}
+
/*
* ufshcd_wait_for_register - wait for register value to change
* @hba - per-adapter interface
@@ -2395,7 +2404,7 @@ out:
return ret;
}
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
@@ -2404,7 +2413,7 @@ static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
return ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
}
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
int ret;
@@ -2419,6 +2428,25 @@ static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
return ret;
}
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en)
+{
+ int ret;
+
+ if (hba->vops && hba->vops->hibern8_notify)
+ hba->vops->hibern8_notify(hba, en, PRE_CHANGE);
+
+ ret = en ? __ufshcd_uic_hibern8_enter(hba) :
+ __ufshcd_uic_hibern8_exit(hba);
+ if (ret)
+ goto out;
+
+ if (hba->vops && hba->vops->hibern8_notify)
+ hba->vops->hibern8_notify(hba, en, POST_CHANGE);
+
+out:
+ return ret;
+}
+
/**
* ufshcd_init_pwr_info - setting the POR (power on reset)
* values in hba power info
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 149d74e..2fd0c3c 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -260,6 +260,8 @@ struct ufs_pwr_mode_info {
* @specify_nexus_t_xfer_req:
* @specify_nexus_t_tm_req: called before command is issued to allow vendor
* specific handling to be set for nexus type.
+ * @hibern8_notify: called before and after hibernate/unhibernate is carried
out
+ * to allow vendor spesific implementation.
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
*/
@@ -276,6 +278,7 @@ struct ufs_hba_variant_ops {
int (*pwr_change_notify)(struct ufs_hba *,
bool, struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+ void(*hibern8_notify)(struct ufs_hba *, bool, bool);
void(*specify_nexus_t_xfer_req)(struct ufs_hba *,
int, struct scsi_cmnd *);
void(*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
--
1.7.10.4
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[PATCH v2 06/11] scsi: ufs: add specific callback for nexus type
From: Seungwon Jeon
Some host controller needs nexus type information for handling
command. This change adds specific callback function to support
vendor's implementation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |6 ++
drivers/scsi/ufs/ufshcd.h |6 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 0fcfa71..2f0de4b 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1377,6 +1377,8 @@ static int ufshcd_queuecommand(struct Scsi_Host *host,
struct scsi_cmnd *cmd)
/* issue command to the controller */
spin_lock_irqsave(hba->host->host_lock, flags);
+ if (hba->vops && hba->vops->specify_nexus_t_xfer_req)
+ hba->vops->specify_nexus_t_xfer_req(hba, tag, lrbp->cmd);
ufshcd_send_command(hba, tag);
out_unlock:
spin_unlock_irqrestore(hba->host->host_lock, flags);
@@ -1577,6 +1579,8 @@ static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
hba->dev_cmd.complete = &wait;
spin_lock_irqsave(hba->host->host_lock, flags);
+ if (hba->vops && hba->vops->specify_nexus_t_xfer_req)
+ hba->vops->specify_nexus_t_xfer_req(hba, tag, lrbp->cmd);
ufshcd_send_command(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
@@ -3848,6 +3852,8 @@ static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int
lun_id, int task_id,
task_req_upiup->input_param2 = cpu_to_be32(task_id);
/* send command to the controller */
+ if (hba->vops && hba->vops->specify_nexus_t_tm_req)
+ hba->vops->specify_nexus_t_tm_req(hba, free_slot, tm_function);
__set_bit(free_slot, &hba->outstanding_tasks);
ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index c6dc107..149d74e 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -257,6 +257,9 @@ struct ufs_pwr_mode_info {
* @pwr_change_notify: called before and after a power mode change
* is carried out to allow vendor spesific capabilities
* to be set.
+ * @specify_nexus_t_xfer_req:
+ * @specify_nexus_t_tm_req: called before command is issued to allow vendor
+ * specific handling to be set for nexus type.
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
*/
@@ -273,6 +276,9 @@ struct ufs_hba_variant_ops {
int (*pwr_change_notify)(struct ufs_hba *,
bool, struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+ void(*specify_nexus_t_xfer_req)(struct ufs_hba *,
+ int, struct scsi_cmnd *);
+ void(*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
int (*resume)(struct ufs_hba *, enum ufs_pm_op);
};
--
1.7.10.4
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[PATCH v2 00/11] exynos-ufs: add support for Exynos
This patch-set introduces UFS (Universal Flash Storage) host support for Samsung Exynos SoC. Mostly, it consists of UFS PHY and host specific driver. And it also contains some quirks handling for Exynos. -Changes since v1: * Addressed review comments from Alexey[1] and various review comments from Amit. * Updated email id of Seungwon as his samsung id is void now. * Added ufs platform data [1]-> https://lkml.org/lkml/2015/8/23/124 Alim Akhtar (1): scsi: ufs: Add exynos ufs platform data Seungwon Jeon (10): phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC scsi: ufs: add quirk to contain unconformable utrd field scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr scsi: ufs: add quirk not to allow reset of interrupt aggregation scsi: ufs: add quirk to enable host controller without hce scsi: ufs: add specific callback for nexus type scsi: ufs: add add specific callback for hibern8 scsi: ufs: make ufshcd_config_pwr_mode of non-static func scsi: ufs: return value of pwr_change_notify scsi: ufs-exynos: add UFS host support for Exynos SoCs .../devicetree/bindings/phy/samsung-phy.txt| 22 + .../devicetree/bindings/ufs/ufs-exynos.txt | 93 ++ drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos-ufs.c | 262 + drivers/phy/phy-exynos-ufs.h | 85 ++ drivers/phy/phy-exynos7-ufs.h | 89 ++ drivers/scsi/ufs/Kconfig | 12 + drivers/scsi/ufs/Makefile |1 + drivers/scsi/ufs/ufs-exynos-hw.c | 147 +++ drivers/scsi/ufs/ufs-exynos-hw.h | 43 + drivers/scsi/ufs/ufs-exynos.c | 1173 drivers/scsi/ufs/ufs-exynos.h | 463 drivers/scsi/ufs/ufshcd-pltfrm.c |2 + drivers/scsi/ufs/ufshcd.c | 196 +++- drivers/scsi/ufs/ufshcd.h | 35 + drivers/scsi/ufs/ufshci.h | 26 +- drivers/scsi/ufs/unipro.h | 47 + include/linux/phy/phy-exynos-ufs.h | 107 ++ 19 files changed, 2784 insertions(+), 27 deletions(-) create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt create mode 100644 drivers/phy/phy-exynos-ufs.c create mode 100644 drivers/phy/phy-exynos-ufs.h create mode 100644 drivers/phy/phy-exynos7-ufs.h create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h create mode 100644 drivers/scsi/ufs/ufs-exynos.c create mode 100644 drivers/scsi/ufs/ufs-exynos.h create mode 100644 include/linux/phy/phy-exynos-ufs.h -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 02/11] scsi: ufs: add quirk to contain unconformable utrd field
From: Seungwon Jeon
UTRD(UTP Transfer Request Descriptor)'s field such as offset/length,
especially response's has DWORD expression. This quirk can be specified
for host controller not to conform standard.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 28 +---
drivers/scsi/ufs/ufshcd.h |7 +++
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index b0ade73..90f76e7 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1009,7 +1009,7 @@ ufshcd_send_uic_cmd(struct ufs_hba *hba, struct
uic_command *uic_cmd)
*
* Returns 0 in case of success, non-zero value in case of failure
*/
-static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
+static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
{
struct ufshcd_sg_entry *prd_table;
struct scatterlist *sg;
@@ -1023,8 +1023,13 @@ static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
return sg_segments;
if (sg_segments) {
- lrbp->utr_descriptor_ptr->prd_table_length =
- cpu_to_le16((u16) (sg_segments));
+ if (hba->quirks & UFSHCI_QUIRK_BYTE_ALIGN_UTRD)
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16)(sg_segments *
+ sizeof(struct ufshcd_sg_entry)));
+ else
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16) (sg_segments));
prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
@@ -1347,7 +1352,7 @@ static int ufshcd_queuecommand(struct Scsi_Host *host,
struct scsi_cmnd *cmd)
/* form UPIU before issuing the command */
ufshcd_compose_upiu(hba, lrbp);
- err = ufshcd_map_sg(lrbp);
+ err = ufshcd_map_sg(hba, lrbp);
if (err) {
lrbp->cmd = NULL;
clear_bit_unlock(tag, &hba->lrb_in_use);
@@ -2034,13 +2039,22 @@ static void ufshcd_host_memory_configure(struct ufs_hba
*hba)
utrdlp[i].command_desc_base_addr_hi =
cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
+ if (hba->quirks & UFSHCI_QUIRK_BYTE_ALIGN_UTRD) {
+ utrdlp[i].response_upiu_offset =
+ cpu_to_le16(response_offset);
+ utrdlp[i].prd_table_offset =
+ cpu_to_le16(prdt_offset);
+ utrdlp[i].response_upiu_length =
+ cpu_to_le16(ALIGNED_UPIU_SIZE);
+ } else {
/* Response upiu and prdt offset should be in double words */
- utrdlp[i].response_upiu_offset =
+ utrdlp[i].response_upiu_offset =
cpu_to_le16((response_offset >> 2));
- utrdlp[i].prd_table_offset =
+ utrdlp[i].prd_table_offset =
cpu_to_le16((prdt_offset >> 2));
- utrdlp[i].response_upiu_length =
+ utrdlp[i].response_upiu_length =
cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
+ }
hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
hba->lrb[i].ucd_req_ptr =
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index c40a0e7..9ed4c9e 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -459,6 +459,13 @@ struct ufs_hba {
*/
#define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION UFS_BIT(5)
+ /*
+* This quirk needs to be enabled if host controller doesn't conform
+* with UTRD. Some fields such as offset/length might not be in double
word,
+* but in byte.
+*/
+ #define UFSHCI_QUIRK_BYTE_ALIGN_UTRDUFS_BIT(6)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v2 01/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
From: Seungwon Jeon
This patch introduces Exynos UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/samsung-phy.txt| 22 ++
drivers/phy/Kconfig|7 +
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos-ufs.c | 262
drivers/phy/phy-exynos-ufs.h | 85 +++
drivers/phy/phy-exynos7-ufs.h | 89 +++
include/linux/phy/phy-exynos-ufs.h | 107
7 files changed, 573 insertions(+)
create mode 100644 drivers/phy/phy-exynos-ufs.c
create mode 100644 drivers/phy/phy-exynos-ufs.h
create mode 100644 drivers/phy/phy-exynos7-ufs.h
create mode 100644 include/linux/phy/phy-exynos-ufs.h
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 60c6f2a..1abe2c4 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -174,3 +174,25 @@ Example:
usbdrdphy0 = &usb3_phy0;
usbdrdphy1 = &usb3_phy1;
};
+
+Samsung Exynos7 soc serise UFS PHY Controller
+-
+
+UFS PHY nodes are defined to describe on-chip UFS Physical layer controllers.
+Each UFS PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible list, contains "samsung,exynos7-ufs-phy"
+- reg : offset and length of the UFS PHY register set;
+- reg-names : reg name(s) must be 'phy-pma';
+- #phy-cells : must be zero
+- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
+
+Example:
+ ufs_phy: ufs-phy@0x15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 6b8dd16..7449376 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -358,4 +358,11 @@ config PHY_BRCMSTB_SATA
Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
Likely useful only with CONFIG_SATA_BRCMSTB enabled.
+config PHY_EXYNOS_UFS
+ tristate "EXYNOS SoC series UFS PHY driver"
+ depends on OF && ARCH_EXYNOS
+ select GENERIC_PHY
+ help
+ Support for UFS PHY on Samsung EXYNOS chipsets.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f344e1b..7a36818 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -45,3 +45,4 @@ obj-$(CONFIG_PHY_QCOM_UFS)+= phy-qcom-ufs-qmp-14nm.o
obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
obj-$(CONFIG_PHY_PISTACHIO_USB)+= phy-pistachio-usb.o
+obj-$(CONFIG_PHY_EXYNOS_UFS) += phy-exynos-ufs.o
diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
new file mode 100644
index 000..7d24610
--- /dev/null
+++ b/drivers/phy/phy-exynos-ufs.c
@@ -0,0 +1,262 @@
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "phy-exynos-ufs.h"
+
+#define for_each_phy_lane(phy, i) \
+ for (i = 0; i < (phy)->lane_cnt; i++)
+#define for_each_phy_cfg(cfg) \
+ for (; (cfg)->id; (cfg)++)
+
+#define phy_pma_writel(phy, val, reg) \
+ writel((val), (phy)->reg_pma + (reg))
+#define phy_pma_readl(phy, reg) \
+ readl((phy)->reg_pma + (reg))
+
+#define PHY_DEF_LANE_CNT 1
+
+static void exynos_ufs_phy_config(struct exynos_ufs_phy *phy,
+ const struct exynos_ufs_phy_cfg *cfg, u8 lane)
+{
+ enum {LANE_0, LANE_1}; /* lane index */
+
+ switch (lane) {
+ case LANE_0:
+ phy_pma_writel(phy, cfg->val, cfg->off_0);
+ break;
+ case LANE_1:
+ if (cfg->id == PHY_TRSV_BLK)
+ phy_pma_writel(phy, cfg->val, cfg->off_1);
+ break;
+ }
+}
+
+static bool match_cfg_to_pwr_mode(u8 desc, u8 required_pwr)
+{
Re: [PATCH 01/10] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
Hi Kishon,
On 09/18/2015 11:05 AM, Kishon Vijay Abraham I wrote:
Hi,
On Friday 21 August 2015 02:57 PM, Alim Akhtar wrote:
From: Seungwon Jeon
This patch introduces Exynos UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/samsung-phy.txt| 22 ++
drivers/phy/Kconfig|7 +
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos-ufs.c | 277
drivers/phy/phy-exynos-ufs.h | 73 ++
drivers/phy/phy-exynos7-ufs.h | 89 +++
include/linux/phy/phy-exynos-ufs.h | 107
7 files changed, 576 insertions(+)
create mode 100644 drivers/phy/phy-exynos-ufs.c
create mode 100644 drivers/phy/phy-exynos-ufs.h
create mode 100644 drivers/phy/phy-exynos7-ufs.h
create mode 100644 include/linux/phy/phy-exynos-ufs.h
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 60c6f2a..1abe2c4 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -174,3 +174,25 @@ Example:
usbdrdphy0 = &usb3_phy0;
usbdrdphy1 = &usb3_phy1;
};
+
+Samsung Exynos7 soc serise UFS PHY Controller
%s/serise/series
ok
+-
+
+UFS PHY nodes are defined to describe on-chip UFS Physical layer controllers.
+Each UFS PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible list, contains "samsung,exynos7-ufs-phy"
compatible list?
will change
+- reg : offset and length of the UFS PHY register set;
The sentences need not end with semi-colon.
+- reg-names : reg name(s) must be 'phy-pma';
+- #phy-cells : must be zero
+- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
+
+Example:
+ ufs_phy: ufs-phy@0x15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 6b8dd16..7449376 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -358,4 +358,11 @@ config PHY_BRCMSTB_SATA
Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
Likely useful only with CONFIG_SATA_BRCMSTB enabled.
+config PHY_EXYNOS_UFS
+ tristate "EXYNOS SoC series UFS PHY driver"
+ depends on OF && ARCH_EXYNOS
+ select GENERIC_PHY
+ help
+ Support for UFS PHY on Samsung EXYNOS chipsets.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f344e1b..7a36818 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -45,3 +45,4 @@ obj-$(CONFIG_PHY_QCOM_UFS)+= phy-qcom-ufs-qmp-14nm.o
obj-$(CONFIG_PHY_TUSB1210)+= phy-tusb1210.o
obj-$(CONFIG_PHY_BRCMSTB_SATA)+= phy-brcmstb-sata.o
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
+obj-$(CONFIG_PHY_EXYNOS_UFS) += phy-exynos-ufs.o
diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
new file mode 100644
index 000..840375d
--- /dev/null
+++ b/drivers/phy/phy-exynos-ufs.c
@@ -0,0 +1,277 @@
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "phy-exynos-ufs.h"
+
+#define for_each_phy_lane(phy, i) \
+ for (i = 0; i < (phy)->lane_cnt; i++)
+#define for_each_phy_cfg(cfg) \
+ for (; (cfg)->id; (cfg)++)
+
+#define phy_pma_writel(phy, val, reg) \
+ writel((val), (phy)->reg_pma + (reg))
+#define phy_pma_readl(phy, reg) \
+ readl((phy)->reg_pma + (reg))
would prefer having functions for readl and writel.
ok, will use writel instead as not many places it is being used.
+
+#define PHY_DEF_LANE_CNT 1
+
+static inline struct exynos_ufs_phy *get_exynos_ufs_phy(struct phy *phy)
+{
+ return (struct exynos_ufs_phy *)phy_get_drvdata(phy);
+}
+
+static void exynos_ufs_phy_config(struct exynos_ufs_phy
Re: [PATCH v2 01/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
HI Rob,
Thanks for your time.
On 09/21/2015 08:03 PM, Rob Herring wrote:
On 09/17/2015 04:45 AM, Alim Akhtar wrote:
From: Seungwon Jeon
This patch introduces Exynos UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/samsung-phy.txt| 22 ++
It is preferred to put the binding in a separate patch.
Ok, will make a separate patch to add bindings.
drivers/phy/Kconfig|7 +
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos-ufs.c | 262
drivers/phy/phy-exynos-ufs.h | 85 +++
drivers/phy/phy-exynos7-ufs.h | 89 +++
include/linux/phy/phy-exynos-ufs.h | 107
7 files changed, 573 insertions(+)
create mode 100644 drivers/phy/phy-exynos-ufs.c
create mode 100644 drivers/phy/phy-exynos-ufs.h
create mode 100644 drivers/phy/phy-exynos7-ufs.h
create mode 100644 include/linux/phy/phy-exynos-ufs.h
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 60c6f2a..1abe2c4 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -174,3 +174,25 @@ Example:
usbdrdphy0 = &usb3_phy0;
usbdrdphy1 = &usb3_phy1;
};
+
+Samsung Exynos7 soc serise UFS PHY Controller
s/serise/series/
ok
+-
+
+UFS PHY nodes are defined to describe on-chip UFS Physical layer controllers.
+Each UFS PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible list, contains "samsung,exynos7-ufs-phy"
+- reg : offset and length of the UFS PHY register set;
+- reg-names : reg name(s) must be 'phy-pma';
+- #phy-cells : must be zero
+- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
How about samsung,pmu-syscon as syscon can mean a variety of things?
agree, will change it.
+
+Example:
+ ufs_phy: ufs-phy@0x15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 6b8dd16..7449376 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -358,4 +358,11 @@ config PHY_BRCMSTB_SATA
Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
Likely useful only with CONFIG_SATA_BRCMSTB enabled.
+config PHY_EXYNOS_UFS
+ tristate "EXYNOS SoC series UFS PHY driver"
+ depends on OF && ARCH_EXYNOS
|| COMPILE_TEST
ok will add
+ select GENERIC_PHY
+ help
+ Support for UFS PHY on Samsung EXYNOS chipsets.
+
endmenu
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[PATCH v3 01/13] Documentation: samsung-phy: Add dt bindings for UFS
Adds exynos UFS PHY device tree bindings information.
Signed-off-by: Alim Akhtar
---
.../devicetree/bindings/phy/samsung-phy.txt| 22
1 file changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 60c6f2a..c92ce53 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -174,3 +174,25 @@ Example:
usbdrdphy0 = &usb3_phy0;
usbdrdphy1 = &usb3_phy1;
};
+
+Samsung Exynos7 soc series UFS PHY Controller
+-
+
+UFS PHY nodes are defined to describe on-chip UFS Physical layer controllers.
+Each UFS PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible should be set to "samsung,exynos7-ufs-phy"
+- reg : offset and length of the UFS PHY register set
+- reg-names : reg name(s) must be 'phy-pma'
+- #phy-cells : must be zero
+- samsung,pmu-syscon : a phandle to the PMU system controller, no arguments
+
+Example:
+ ufs_phy: ufs-phy@0x15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ };
--
1.7.10.4
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[PATCH v3 00/13] exynos-ufs: add support for Exynos
This patch-set introduces UFS (Universal Flash Storage) host support for Samsung Exynos SoC. Mostly, it consists of UFS PHY and host specific driver. And it also contains some quirks handling for Exynos. -Chanes since v2: * Addressed review comments from Kishon[1] and Rob Herring [2] * Splited ufs dt binding documetation from ufs driver patch -Changes since v1: * Addressed review comments from Alexey[3] and various review comments from Amit. * Updated email id of Seungwon as his samsung id is void now. * Added ufs platform data [1]-> https://lkml.org/lkml/2015/9/18/29 [2]-> https://lkml.org/lkml/2015/9/21/668 [3]-> https://lkml.org/lkml/2015/8/23/124 This patch set is tested on exynos7-espresso board. Alim Akhtar (2): Documentation: samsung-phy: Add dt bindings for UFS scsi: ufs: Add exynos ufs platform data Seungwon Jeon (11): phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC scsi: ufs: add quirk to contain unconformable utrd field scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr scsi: ufs: add quirk not to allow reset of interrupt aggregation scsi: ufs: add quirk to enable host controller without hce scsi: ufs: add specific callback for nexus type scsi: ufs: add add specific callback for hibern8 scsi: ufs: make ufshcd_config_pwr_mode of non-static func scsi: ufs: return value of pwr_change_notify Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller scsi: ufs-exynos: add UFS host support for Exynos SoCs .../devicetree/bindings/phy/samsung-phy.txt| 22 + .../devicetree/bindings/ufs/ufs-exynos.txt | 93 ++ drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos-ufs.c | 257 + drivers/phy/phy-exynos-ufs.h | 87 ++ drivers/phy/phy-exynos7-ufs.h | 89 ++ drivers/scsi/ufs/Kconfig | 12 + drivers/scsi/ufs/Makefile |1 + drivers/scsi/ufs/ufs-exynos-hw.c | 147 +++ drivers/scsi/ufs/ufs-exynos-hw.h | 43 + drivers/scsi/ufs/ufs-exynos.c | 1186 drivers/scsi/ufs/ufs-exynos.h | 463 drivers/scsi/ufs/ufshcd-pltfrm.c |2 + drivers/scsi/ufs/ufshcd.c | 196 +++- drivers/scsi/ufs/ufshcd.h | 35 + drivers/scsi/ufs/ufshci.h | 26 +- drivers/scsi/ufs/unipro.h | 47 + include/linux/phy/phy-exynos-ufs.h | 101 ++ 19 files changed, 2788 insertions(+), 27 deletions(-) create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt create mode 100644 drivers/phy/phy-exynos-ufs.c create mode 100644 drivers/phy/phy-exynos-ufs.h create mode 100644 drivers/phy/phy-exynos7-ufs.h create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h create mode 100644 drivers/scsi/ufs/ufs-exynos.c create mode 100644 drivers/scsi/ufs/ufs-exynos.h create mode 100644 include/linux/phy/phy-exynos-ufs.h -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 02/13] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
From: Seungwon Jeon
This patch introduces Exynos UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
---
drivers/phy/Kconfig|7 +
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos-ufs.c | 257
drivers/phy/phy-exynos-ufs.h | 88
drivers/phy/phy-exynos7-ufs.h | 89 +
include/linux/phy/phy-exynos-ufs.h | 101 ++
6 files changed, 543 insertions(+)
create mode 100644 drivers/phy/phy-exynos-ufs.c
create mode 100644 drivers/phy/phy-exynos-ufs.h
create mode 100644 drivers/phy/phy-exynos7-ufs.h
create mode 100644 include/linux/phy/phy-exynos-ufs.h
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 6b8dd16..199a865 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -358,4 +358,11 @@ config PHY_BRCMSTB_SATA
Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
Likely useful only with CONFIG_SATA_BRCMSTB enabled.
+config PHY_EXYNOS_UFS
+ tristate "EXYNOS SoC series UFS PHY driver"
+ depends on OF && ARCH_EXYNOS || COMPILE_TEST
+ select GENERIC_PHY
+ help
+ Support for UFS PHY on Samsung EXYNOS chipsets.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f344e1b..7a36818 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -45,3 +45,4 @@ obj-$(CONFIG_PHY_QCOM_UFS)+= phy-qcom-ufs-qmp-14nm.o
obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
obj-$(CONFIG_PHY_PISTACHIO_USB)+= phy-pistachio-usb.o
+obj-$(CONFIG_PHY_EXYNOS_UFS) += phy-exynos-ufs.o
diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
new file mode 100644
index 000..343fcaf
--- /dev/null
+++ b/drivers/phy/phy-exynos-ufs.c
@@ -0,0 +1,257 @@
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "phy-exynos-ufs.h"
+
+#define for_each_phy_lane(phy, i) \
+ for (i = 0; i < (phy)->lane_cnt; i++)
+#define for_each_phy_cfg(cfg) \
+ for (; (cfg)->id; (cfg)++)
+
+#define PHY_DEF_LANE_CNT 1
+
+static void exynos_ufs_phy_config(struct exynos_ufs_phy *phy,
+ const struct exynos_ufs_phy_cfg *cfg, u8 lane)
+{
+ enum {LANE_0, LANE_1}; /* lane index */
+
+ switch (lane) {
+ case LANE_0:
+ writel(cfg->val, (phy)->reg_pma + cfg->off_0);
+ break;
+ case LANE_1:
+ if (cfg->id == PHY_TRSV_BLK)
+ writel(cfg->val, (phy)->reg_pma + cfg->off_1);
+ break;
+ }
+}
+
+static bool match_cfg_to_pwr_mode(u8 desc, u8 required_pwr)
+{
+ if (IS_PWR_MODE_ANY(desc))
+ return true;
+
+ if (IS_PWR_MODE_HS(required_pwr) && IS_PWR_MODE_HS_ANY(desc))
+ return true;
+
+ if (COMP_PWR_MODE(required_pwr, desc))
+ return true;
+
+ if (COMP_PWR_MODE_MD(required_pwr, desc) &&
+ COMP_PWR_MODE_GEAR(required_pwr, desc) &&
+ COMP_PWR_MODE_SER(required_pwr, desc))
+ return true;
+
+ return false;
+}
+
+int exynos_ufs_phy_calibrate(struct phy *phy, enum phy_cfg_tag tag, u8 pwr)
+{
+ struct exynos_ufs_phy *ufs_phy = get_exynos_ufs_phy(phy);
+ struct exynos_ufs_phy_cfg **cfgs = ufs_phy->cfg;
+ const struct exynos_ufs_phy_cfg *cfg;
+ int i;
+
+ if (unlikely(tag < CFG_PRE_INIT || tag >= CFG_TAG_MAX)) {
+ dev_err(ufs_phy->dev, "invalid phy config index %d\n", tag);
+ return -EINVAL;
+ }
+
+ cfg = cfgs[tag];
+ if (!cfg)
+ goto out;
+
+ for_each_phy_cfg(cfg) {
+ for_each_phy_lane(ufs_phy, i) {
+ if (match_cfg_to_pwr_mode(cfg->desc, pwr))
+ exynos_ufs_phy_config(ufs_phy, cfg, i);
+ }
+ }
+
+out:
+ return 0;
+}
+
+void exynos_ufs_phy_set_lane_cnt(struct phy *phy, u8 lane_cnt)
+{
+ struct exynos_ufs_phy *ufs_phy = get_exynos_ufs_phy(phy);
+
+ ufs_phy->lane_cnt = lane_cnt;
+}
+
+int exynos_ufs_phy_wait_for_lock_acq(struct phy *phy)
+{
+ struct exynos_ufs
[PATCH v3 03/13] scsi: ufs: add quirk to contain unconformable utrd field
From: Seungwon Jeon
UTRD(UTP Transfer Request Descriptor)'s field such as offset/length,
especially response's has DWORD expression. This quirk can be specified
for host controller not to conform standard.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 28 +---
drivers/scsi/ufs/ufshcd.h |7 +++
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index b0ade73..90f76e7 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1009,7 +1009,7 @@ ufshcd_send_uic_cmd(struct ufs_hba *hba, struct
uic_command *uic_cmd)
*
* Returns 0 in case of success, non-zero value in case of failure
*/
-static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
+static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
{
struct ufshcd_sg_entry *prd_table;
struct scatterlist *sg;
@@ -1023,8 +1023,13 @@ static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
return sg_segments;
if (sg_segments) {
- lrbp->utr_descriptor_ptr->prd_table_length =
- cpu_to_le16((u16) (sg_segments));
+ if (hba->quirks & UFSHCI_QUIRK_BYTE_ALIGN_UTRD)
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16)(sg_segments *
+ sizeof(struct ufshcd_sg_entry)));
+ else
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16) (sg_segments));
prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
@@ -1347,7 +1352,7 @@ static int ufshcd_queuecommand(struct Scsi_Host *host,
struct scsi_cmnd *cmd)
/* form UPIU before issuing the command */
ufshcd_compose_upiu(hba, lrbp);
- err = ufshcd_map_sg(lrbp);
+ err = ufshcd_map_sg(hba, lrbp);
if (err) {
lrbp->cmd = NULL;
clear_bit_unlock(tag, &hba->lrb_in_use);
@@ -2034,13 +2039,22 @@ static void ufshcd_host_memory_configure(struct ufs_hba
*hba)
utrdlp[i].command_desc_base_addr_hi =
cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
+ if (hba->quirks & UFSHCI_QUIRK_BYTE_ALIGN_UTRD) {
+ utrdlp[i].response_upiu_offset =
+ cpu_to_le16(response_offset);
+ utrdlp[i].prd_table_offset =
+ cpu_to_le16(prdt_offset);
+ utrdlp[i].response_upiu_length =
+ cpu_to_le16(ALIGNED_UPIU_SIZE);
+ } else {
/* Response upiu and prdt offset should be in double words */
- utrdlp[i].response_upiu_offset =
+ utrdlp[i].response_upiu_offset =
cpu_to_le16((response_offset >> 2));
- utrdlp[i].prd_table_offset =
+ utrdlp[i].prd_table_offset =
cpu_to_le16((prdt_offset >> 2));
- utrdlp[i].response_upiu_length =
+ utrdlp[i].response_upiu_length =
cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
+ }
hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
hba->lrb[i].ucd_req_ptr =
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index c40a0e7..2f96abe 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -459,6 +459,13 @@ struct ufs_hba {
*/
#define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION UFS_BIT(5)
+ /*
+* This quirk needs to be enabled if host controller doesn't conform
+* with UTRD. Some fields such as offset/length might not be in double
+* word, but in byte.
+*/
+ #define UFSHCI_QUIRK_BYTE_ALIGN_UTRDUFS_BIT(6)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v3 04/13] scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
From: Seungwon Jeon
In the right behavior, setting the bit to '0' indicates clear and
'1' indicates no change. If host contoller handles this the other way,
UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR can be used.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 21 +++--
drivers/scsi/ufs/ufshcd.h |5 +
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 90f76e7..d41d57d 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -358,7 +358,24 @@ static inline void ufshcd_put_tm_slot(struct ufs_hba *hba,
int slot)
*/
static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
{
- ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos),
+ REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+}
+
+/**
+ * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
+ * @hba: per adapter instance
+ * @pos: position of the bit to be cleared
+ */
+static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
+{
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
}
/**
@@ -3691,7 +3708,7 @@ static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int
tag)
goto out;
spin_lock_irqsave(hba->host->host_lock, flags);
- ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
+ ufshcd_utmrl_clear(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
/* poll for max. 1 sec to clear door bell register by h/w */
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 2f96abe..3702b92 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -466,6 +466,11 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_BYTE_ALIGN_UTRDUFS_BIT(6)
+ /*
+* Cleaer handling for transfer/task request list is just opposite.
+*/
+ #define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLRUFS_BIT(7)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v3 05/13] scsi: ufs: add quirk not to allow reset of interrupt aggregation
From: Seungwon Jeon
Some host controller supports interrupt aggregation, but doesn't
allow to reset counter and timer by s/w.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |3 ++-
drivers/scsi/ufs/ufshcd.h |6 ++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index d41d57d..e388edc 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -3205,7 +3205,8 @@ static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
* false interrupt if device completes another request after resetting
* aggregation and before reading the DB.
*/
- if (ufshcd_is_intr_aggr_allowed(hba))
+ if (ufshcd_is_intr_aggr_allowed(hba) &&
+ !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
ufshcd_reset_intr_aggr(hba);
tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 3702b92..0b185e1 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -471,6 +471,12 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLRUFS_BIT(7)
+ /*
+* This quirk needs to be enabled if host controller doesn't allow
+* that the interrupt aggregation timer and counter are reset by s/w.
+*/
+ #define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR UFS_BIT(8)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v3 06/13] scsi: ufs: add quirk to enable host controller without hce
From: Seungwon Jeon
Some host controller doesn't support host controller enable via HCE.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 76 +++--
drivers/scsi/ufs/ufshcd.h |5 +++
2 files changed, 79 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index e388edc..07659be 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2107,6 +2107,52 @@ static int ufshcd_dme_link_startup(struct ufs_hba *hba)
"dme-link-startup: error code %d\n", ret);
return ret;
}
+/**
+ * ufshcd_dme_reset - UIC command for DME_RESET
+ * @hba: per adapter instance
+ *
+ * DME_RESET command is issued in order to reset UniPro stack.
+ * This function now deal with cold reset.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_reset(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_RESET;
+
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
+
+/**
+ * ufshcd_dme_enable - UIC command for DME_ENABLE
+ * @hba: per adapter instance
+ *
+ * DME_ENABLE command is issued in order to enable UniPro stack.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_enable(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_ENABLE;
+
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
{
@@ -2643,7 +2689,7 @@ out:
}
/**
- * ufshcd_hba_enable - initialize the controller
+ * ufshcd_hba_execute_hce - initialize the controller
* @hba: per adapter instance
*
* The controller resets itself and controller firmware initialization
@@ -2652,7 +2698,7 @@ out:
*
* Returns 0 on success, non-zero value on failure
*/
-static int ufshcd_hba_enable(struct ufs_hba *hba)
+static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
{
int retry;
@@ -2718,6 +2764,32 @@ static int ufshcd_hba_enable(struct ufs_hba *hba)
return 0;
}
+static int ufshcd_hba_enable(struct ufs_hba *hba)
+{
+ int ret;
+
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
+ ufshcd_set_link_off(hba);
+ if (hba->vops && hba->vops->hce_enable_notify)
+ hba->vops->hce_enable_notify(hba, PRE_CHANGE);
+
+ /* enable UIC related interrupts */
+ ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
+ ret = ufshcd_dme_reset(hba);
+ if (!ret) {
+ ret = ufshcd_dme_enable(hba);
+ if (!ret && hba->vops && hba->vops->hce_enable_notify)
+ hba->vops->hce_enable_notify(hba, POST_CHANGE);
+ if (ret)
+ dev_err(hba->dev,
+ "Host controller enable failed with
non-hce\n");
+ }
+ } else {
+ ret = ufshcd_hba_execute_hce(hba);
+ }
+
+ return ret;
+}
static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
{
int tx_lanes, i, err = 0;
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 0b185e1..a4543c8 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -477,6 +477,11 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR UFS_BIT(8)
+ /*
+* This quirks needs to be enabled if host controller cannot be
+* enabled via HCE register.
+*/
+ #define UFSHCI_QUIRK_BROKEN_HCE UFS_BIT(9)
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v3 07/13] scsi: ufs: add specific callback for nexus type
From: Seungwon Jeon
Some host controller needs nexus type information for handling
command. This change adds specific callback function to support
vendor's implementation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |6 ++
drivers/scsi/ufs/ufshcd.h |6 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 07659be..46f92fe 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1378,6 +1378,8 @@ static int ufshcd_queuecommand(struct Scsi_Host *host,
struct scsi_cmnd *cmd)
/* issue command to the controller */
spin_lock_irqsave(hba->host->host_lock, flags);
+ if (hba->vops && hba->vops->specify_nexus_t_xfer_req)
+ hba->vops->specify_nexus_t_xfer_req(hba, tag, lrbp->cmd);
ufshcd_send_command(hba, tag);
out_unlock:
spin_unlock_irqrestore(hba->host->host_lock, flags);
@@ -1578,6 +1580,8 @@ static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
hba->dev_cmd.complete = &wait;
spin_lock_irqsave(hba->host->host_lock, flags);
+ if (hba->vops && hba->vops->specify_nexus_t_xfer_req)
+ hba->vops->specify_nexus_t_xfer_req(hba, tag, lrbp->cmd);
ufshcd_send_command(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
@@ -3849,6 +3853,8 @@ static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int
lun_id, int task_id,
task_req_upiup->input_param2 = cpu_to_be32(task_id);
/* send command to the controller */
+ if (hba->vops && hba->vops->specify_nexus_t_tm_req)
+ hba->vops->specify_nexus_t_tm_req(hba, free_slot, tm_function);
__set_bit(free_slot, &hba->outstanding_tasks);
ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index a4543c8..75af314 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -257,6 +257,9 @@ struct ufs_pwr_mode_info {
* @pwr_change_notify: called before and after a power mode change
* is carried out to allow vendor spesific capabilities
* to be set.
+ * @specify_nexus_t_xfer_req:
+ * @specify_nexus_t_tm_req: called before command is issued to allow vendor
+ * specific handling to be set for nexus type.
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
*/
@@ -273,6 +276,9 @@ struct ufs_hba_variant_ops {
int (*pwr_change_notify)(struct ufs_hba *,
bool, struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+ void(*specify_nexus_t_xfer_req)(struct ufs_hba *,
+ int, struct scsi_cmnd *);
+ void(*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
int (*resume)(struct ufs_hba *, enum ufs_pm_op);
};
--
1.7.10.4
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[PATCH v3 08/13] scsi: ufs: add add specific callback for hibern8
From: Seungwon Jeon
Some host controller needs specific handling before/after
(un)hibernation, This change adds specific callback function
to support vendor's implementation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 36
drivers/scsi/ufs/ufshcd.h |3 +++
2 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 46f92fe..73a8d13 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -181,8 +181,7 @@ static int ufshcd_probe_hba(struct ufs_hba *hba);
static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
bool skip_ref_clk);
static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
@@ -215,6 +214,16 @@ static inline void ufshcd_disable_irq(struct ufs_hba *hba)
}
}
+static inline int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, true);
+}
+
+static inline int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, false);
+}
+
/*
* ufshcd_wait_for_register - wait for register value to change
* @hba - per-adapter interface
@@ -2396,7 +2405,7 @@ out:
return ret;
}
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
@@ -2405,7 +2414,7 @@ static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
return ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
}
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
int ret;
@@ -2420,6 +2429,25 @@ static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
return ret;
}
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en)
+{
+ int ret;
+
+ if (hba->vops && hba->vops->hibern8_notify)
+ hba->vops->hibern8_notify(hba, en, PRE_CHANGE);
+
+ ret = en ? __ufshcd_uic_hibern8_enter(hba) :
+ __ufshcd_uic_hibern8_exit(hba);
+ if (ret)
+ goto out;
+
+ if (hba->vops && hba->vops->hibern8_notify)
+ hba->vops->hibern8_notify(hba, en, POST_CHANGE);
+
+out:
+ return ret;
+}
+
/**
* ufshcd_init_pwr_info - setting the POR (power on reset)
* values in hba power info
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 75af314..845d1c2 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -260,6 +260,8 @@ struct ufs_pwr_mode_info {
* @specify_nexus_t_xfer_req:
* @specify_nexus_t_tm_req: called before command is issued to allow vendor
* specific handling to be set for nexus type.
+ * @hibern8_notify: called before and after hibernate/unhibernate is carried
out
+ * to allow vendor spesific implementation.
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
*/
@@ -276,6 +278,7 @@ struct ufs_hba_variant_ops {
int (*pwr_change_notify)(struct ufs_hba *,
bool, struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+ void(*hibern8_notify)(struct ufs_hba *, bool, bool);
void(*specify_nexus_t_xfer_req)(struct ufs_hba *,
int, struct scsi_cmnd *);
void(*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
--
1.7.10.4
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[PATCH v3 09/13] scsi: ufs: make ufshcd_config_pwr_mode of non-static func
From: Seungwon Jeon
This makes ufshcd_config_pwr_mode non-static so that other vendors
like exynos can use the same.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |5 ++---
drivers/scsi/ufs/ufshcd.h |2 ++
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 73a8d13..66f2fb8 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -185,8 +185,6 @@ static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba,
bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
- struct ufs_pa_layer_attr *desired_pwr_mode);
static int ufshcd_change_power_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *pwr_mode);
@@ -2598,7 +2596,7 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
* @hba: per-adapter instance
* @desired_pwr_mode: desired power configuration
*/
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+int ufshcd_config_pwr_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *desired_pwr_mode)
{
struct ufs_pa_layer_attr final_params = { 0 };
@@ -2614,6 +2612,7 @@ static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
return ret;
}
+EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
/**
* ufshcd_complete_dev_init() - checks device readiness
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 845d1c2..f771cb8 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -636,6 +636,8 @@ extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32
attr_sel,
u8 attr_set, u32 mib_val, u8 peer);
extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
u32 *mib_val, u8 peer);
+extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+ struct ufs_pa_layer_attr *desired_pwr_mode);
/* UIC command interfaces for DME primitives */
#define DME_LOCAL 0
--
1.7.10.4
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[PATCH v3 10/13] scsi: ufs: return value of pwr_change_notify
From: Seungwon Jeon
Behavior of the "power mode change" contains vendor specific
operation known as pwr_change_notify. This change adds return
for pwr_change_notify to find success or failure.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 66f2fb8..682abbe 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2580,14 +2580,18 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
dev_err(hba->dev,
"%s: power mode change failed %d\n", __func__, ret);
} else {
- if (hba->vops && hba->vops->pwr_change_notify)
- hba->vops->pwr_change_notify(hba,
- POST_CHANGE, NULL, pwr_mode);
+ if (hba->vops && hba->vops->pwr_change_notify) {
+ ret = hba->vops->pwr_change_notify(hba,
+ POST_CHANGE, NULL, pwr_mode);
+ if (ret)
+ goto out;
+ }
memcpy(&hba->pwr_info, pwr_mode,
sizeof(struct ufs_pa_layer_attr));
}
+out:
return ret;
}
@@ -2602,14 +2606,18 @@ int ufshcd_config_pwr_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr final_params = { 0 };
int ret;
- if (hba->vops && hba->vops->pwr_change_notify)
- hba->vops->pwr_change_notify(hba,
-PRE_CHANGE, desired_pwr_mode, &final_params);
- else
+ if (hba->vops && hba->vops->pwr_change_notify) {
+ ret = hba->vops->pwr_change_notify(hba,
+ PRE_CHANGE, desired_pwr_mode, &final_params);
+ if (ret)
+ goto out;
+ } else {
memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
+ }
ret = ufshcd_change_power_mode(hba, &final_params);
+out:
return ret;
}
EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
--
1.7.10.4
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[PATCH v3 12/13] scsi: ufs-exynos: add UFS host support for Exynos SoCs
From: Seungwon Jeon
This patch introduces Exynos UFS host controller driver,
which mainly handles vendor-specific operations including
link startup, power mode change and hibernation/unhibernation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/Kconfig | 12 +
drivers/scsi/ufs/Makefile|1 +
drivers/scsi/ufs/ufs-exynos-hw.c | 147 +
drivers/scsi/ufs/ufs-exynos-hw.h | 43 ++
drivers/scsi/ufs/ufs-exynos.c| 1186 ++
drivers/scsi/ufs/ufs-exynos.h| 463 +++
drivers/scsi/ufs/ufshci.h| 26 +-
drivers/scsi/ufs/unipro.h| 47 ++
8 files changed, 1924 insertions(+), 1 deletion(-)
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
create mode 100644 drivers/scsi/ufs/ufs-exynos.c
create mode 100644 drivers/scsi/ufs/ufs-exynos.h
diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig
index e945383..14544d6 100644
--- a/drivers/scsi/ufs/Kconfig
+++ b/drivers/scsi/ufs/Kconfig
@@ -83,3 +83,15 @@ config SCSI_UFS_QCOM
Select this if you have UFS controller on QCOM chipset.
If unsure, say N.
+
+config SCSI_UFS_EXYNOS
+ bool "EXYNOS specific hooks to UFS controller platform driver"
+ depends on SCSI_UFSHCD_PLATFORM && ARCH_EXYNOS
+ select PHY_EXYNOS_UFS
+ help
+ This selects the EXYNOS specific additions to UFSHCD platform driver.
+ UFS host on EXYNOS includes HCI and UNIPRO layer, and associates with
+ UFS-PHY driver.
+
+ Select this if you have UFS host controller on EXYNOS chipset.
+ If unsure, say N.
diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile
index 8303bcc..2accf1e 100644
--- a/drivers/scsi/ufs/Makefile
+++ b/drivers/scsi/ufs/Makefile
@@ -1,5 +1,6 @@
# UFSHCD makefile
obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o
+obj-$(CONFIG_SCSI_UFS_EXYNOS) += ufs-exynos.o ufs-exynos-hw.o
obj-$(CONFIG_SCSI_UFSHCD) += ufshcd.o
obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o
obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o
diff --git a/drivers/scsi/ufs/ufs-exynos-hw.c b/drivers/scsi/ufs/ufs-exynos-hw.c
new file mode 100644
index 000..3df6d07
--- /dev/null
+++ b/drivers/scsi/ufs/ufs-exynos-hw.c
@@ -0,0 +1,147 @@
+/*
+ * UFS Host Controller driver for Exynos specific extensions
+ *
+ * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "ufshcd.h"
+#include "unipro.h"
+#include "ufs-exynos.h"
+#include "ufs-exynos-hw.h"
+
+static int ufs_clk_set_parent(struct device *dev, const char *c, const char *p)
+{
+ struct clk *_c, *_p;
+
+ _c = devm_clk_get(dev, c);
+ if (IS_ERR(_c)) {
+ dev_err(dev, "failed to get clock %s\n", c);
+ return -EINVAL;
+ }
+
+ _p = devm_clk_get(dev, p);
+ if (IS_ERR(_p)) {
+ dev_err(dev, "failed to get clock %s\n", p);
+ return -EINVAL;
+ }
+
+ return clk_set_parent(_c, _p);
+}
+
+static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
+{
+ int ret;
+ const char *const clks[] = {
+ "mout_sclk_combo_phy_embedded",
+ "top_sclk_phy_fsys1_26m",
+ };
+
+ ret = ufs_clk_set_parent(dev, clks[0], clks[1]);
+ if (ret)
+ dev_err(dev, "failed to set parent %s of clock %s\n",
+ clks[1], clks[0]);
+
+ return ret;
+}
+
+static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
+{
+ struct ufs_hba *hba = ufs->hba;
+ u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite;
+ int i;
+
+ exynos_ufs_enable_ov_tm(hba);
+ for_each_ufs_tx_lane(ufs, i)
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17);
+ for_each_ufs_rx_lane(ufs, i) {
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00);
+ }
+ exynos_ufs_disable_ov_tm(hba);
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE_DYN), 0xf);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE_DYN), 0xf);
+ for_each_ufs_tx_lane(ufs, i)
+ ufshcd_dme_set(hba,
+ UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1);
+ udelay(1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12));
+ ufshcd_dme_set(hba, UIC_ARG_MIB(P
[PATCH v3 13/13] scsi: ufs: Add exynos ufs platform data
This adds ufs_hba_exynos_ops{} to platform data, so that
exynos ufs driver can be probed.
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd-pltfrm.c |2 ++
drivers/scsi/ufs/ufshcd.h|1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/scsi/ufs/ufshcd-pltfrm.c b/drivers/scsi/ufs/ufshcd-pltfrm.c
index 7db9564..39dae76 100644
--- a/drivers/scsi/ufs/ufshcd-pltfrm.c
+++ b/drivers/scsi/ufs/ufshcd-pltfrm.c
@@ -373,6 +373,8 @@ static int ufshcd_pltfrm_remove(struct platform_device
*pdev)
static const struct of_device_id ufs_of_match[] = {
{ .compatible = "jedec,ufs-1.1"},
+ { .compatible = "samsung,exynos7-ufs",
+.data = &ufs_hba_exynos_ops},
{},
};
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index f771cb8..776d6e0 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -687,4 +687,5 @@ static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
int ufshcd_hold(struct ufs_hba *hba, bool async);
void ufshcd_release(struct ufs_hba *hba);
+extern const struct ufs_hba_variant_ops ufs_hba_exynos_ops;
#endif /* End of Header */
--
1.7.10.4
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[PATCH v3 11/13] Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller
From: Seungwon Jeon
This adds Exynos Universal Flash Storage (UFS) Host Controller DT bindings.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
.../devicetree/bindings/ufs/ufs-exynos.txt | 93
1 file changed, 93 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
diff --git a/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
new file mode 100644
index 000..00df72e
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
@@ -0,0 +1,93 @@
+* Exynos Universal Flash Storage (UFS) Host Controller
+
+UFSHC nodes are defined to describe on-chip UFS host controllers.
+Each UFS controller instance should have its own node.
+
+Required properties:
+- compatible: compatible name, contains "samsung,exynos7-ufs"
+- interrupts:
+- reg :
+
+Optional properties:
+- vdd-hba-supply: phandle to UFS host controller supply regulator node
+- vcc-supply: phandle to VCC supply regulator node
+- vccq-supply : phandle to VCCQ supply regulator node
+- vccq2-supply : phandle to VCCQ2 supply regulator node
+- vcc-supply-1p8: For embedded UFS devices, valid VCC range is
1.7-1.95V
+ or 2.7-3.6V. This boolean property when set,
specifies
+ to use low voltage range of 1.7-1.95V. Note for
external
+ UFS cards this property is invalid and valid VCC
range is
+ always 2.7-3.6V.
+- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
+- vccq-max-microamp : specifies max. load that can be drawn from vccq
supply
+- vccq2-max-microamp: specifies max. load that can be drawn from vccq2
supply
+- -fixed-regulator : boolean property specifying that -supply is a
fixed regulator
+
+- clocks: List of phandle and clock specifier pairs
+- clock-names : List of clock input name strings sorted in the same
+ order as the clocks property.
+- freq-table-hz: Array of operating frequencies
stored in the same
+ order as the clocks property. If this property is not
+ defined or a value in the array is "0" then it is
assumed
+ that the frequency is set by the parent clock or a
+ fixed rate clock source.
+- pclk-freq-avail-range : specifies available frequency range(min/max) for APB
clock
+- ufs,pwr-attr-mode : specifies mode value for power mode change
+- ufs,pwr-attr-lane : specifies lane count value for power mode change
+- ufs,pwr-attr-gear : specifies gear count value for power mode change
+- ufs,pwr-attr-hs-series : specifies HS rate series for power mode change
+- ufs,pwr-local-l2-timer : specifies array of local UNIPRO L2 timer values
+
+- ufs,pwr-remote-l2-timer : specifies array of remote UNIPRO L2 timer values
+
+- ufs-rx-adv-fine-gran-sup_en : specifies support of fine granularity of MPHY,
+ this is a boolean property.
+- ufs-rx-adv-fine-gran-step : specifies granularity steps of MPHY
+- ufs-rx-adv-min-activate-time-cap : specifies rx advanced minimum activate
time of MPHY
+- ufs-pa-granularity : specifies Granularity for PA_TActivate and
PA_Hibern8Time
+- ufs-pa-tacctivate : specifies time wake-up remote M-RX
+- ufs-pa-hibern8time : specifies minimum time to wait in HIBERN8 state
+
+Note: If above properties are not defined it can be assumed that the supply
+regulators or clocks are always on.
+
+Example:
+ ufshc@0x1557 {
+ compatible = "samsung,exynos7-ufs";
+ reg = <0xfc598000 0x800>;
+ reg = <0x1557 0x100>,
+ <0x15570100 0x100>,
+ <0x15571000 0x200>,
+ <0x15572000 0x300>;
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = <0 200 0>;
+
+ vdd-hba-supply = <&xxx_reg0>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&xxx_reg1>;
+ vcc-supply-1p8;
+ vccq-supply = <&xxx_reg2>;
+ vccq2-supply = <&xxx_reg3>;
+ vcc-max-microamp = 50;
+ vccq-max-microamp = 20;
+ vccq2-max-microamp = 20;
+
+ clocks = <&core 0>, <&ref 0>, <&iface 0>;
+ clock-names = "core_clk", "ref_clk", "iface_clk";
+ freq-table-hz = <1 2>, <0 0>, <0 0>;
+
+ pclk-freq-avail-range = <7000 1330
Re: [PATCH v3 13/13] scsi: ufs: Add exynos ufs platform data
CCing Rob Herring, Hi Arnd, On 10/01/2015 04:59 PM, Arnd Bergmann wrote: On Thursday 01 October 2015 18:46:34 kbuild test robot wrote: [auto build test results on v4.3-rc3 -- if it's inappropriate base, please ignore] config: x86_64-allmodconfig (attached as .config) reproduce: git checkout 6e153e3bf7c68b019e987c5a0ffadebd9c7d4fbb # save the attached .config to linux build tree make ARCH=x86_64 All error/warnings (new ones prefixed by >>): ERROR: "ufs_hba_exynos_ops" [drivers/scsi/ufs/ufshcd-pltfrm.ko] undefined! Ah, this seems to be a case of layering violation. It would be best to restructure the code so that the exynos driver registers a platform_driver by itself for the respective DT compatible string, and then calls into the common code from its probe function, rather than having the generic driver know about the specific backends. That approach will also make the generic driver more scalable as we add further chip-specific variations, and matches what we do in other drivers. Looks like some discussions on ufs variant driver probe method happened here [1] few months back. [1]-> https://lkml.org/lkml/2015/6/3/180 And since ufshcd-pltfrm is already a platform_driver, so I just add a platform data for the variant driver. I should have add a IS_ENABLED for it to avoid the compilation error for other ARCH. Thanks!! Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 13/13] scsi: ufs: Add exynos ufs platform data
Hi Rob, On Mon, Oct 5, 2015 at 7:41 PM, Rob Herring wrote: > On Mon, Oct 5, 2015 at 4:06 AM, Arnd Bergmann wrote: >> On Monday 05 October 2015 13:44:29 Alim Akhtar wrote: >>> CCing Rob Herring, >>> >>> Hi Arnd, >>> >>> On 10/01/2015 04:59 PM, Arnd Bergmann wrote: >>> > On Thursday 01 October 2015 18:46:34 kbuild test robot wrote: >>> >> [auto build test results on v4.3-rc3 -- if it's inappropriate base, >>> >> please ignore] >>> >> >>> >> config: x86_64-allmodconfig (attached as .config) >>> >> reproduce: >>> >> git checkout 6e153e3bf7c68b019e987c5a0ffadebd9c7d4fbb >>> >> # save the attached .config to linux build tree >>> >> make ARCH=x86_64 >>> >> >>> >> All error/warnings (new ones prefixed by >>): >>> >> >>> >>>> ERROR: "ufs_hba_exynos_ops" [drivers/scsi/ufs/ufshcd-pltfrm.ko] >>> >>>> undefined! >>> >> >>> >> >>> > >>> > Ah, this seems to be a case of layering violation. It would be best to >>> > restructure the code so that the exynos driver registers a platform_driver >>> > by itself for the respective DT compatible string, and then calls >>> > into the common code from its probe function, rather than having the >>> > generic driver know about the specific backends. >>> > >>> > That approach will also make the generic driver more scalable as we >>> > add further chip-specific variations, and matches what we do in other >>> > drivers. >>> > >>> >>> Looks like some discussions on ufs variant driver probe method happened >>> here [1] few months back. >>> [1]-> https://lkml.org/lkml/2015/6/3/180 >> >> Hmm, too bad we didn't catch it then, it's much more work to fix now. > > What you suggested is what is being implemented[1]. It is not merged > yet. The core is a library and the platform specific parts create the > driver. > > Rob > > [1] https://lkml.org/lkml/2015/9/2/364 Thanks for the pointer...let me have a look. At least now we have another variant to test it out. > -- > To unsubscribe from this list: send the line "unsubscribe linux-scsi" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- Regards, Alim -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 12/13] scsi: ufs-exynos: add UFS host support for Exynos SoCs
Hi Arnd,
On 10/01/2015 05:42 PM, Arnd Bergmann wrote:
On Thursday 01 October 2015 13:39:29 Alim Akhtar wrote:
+static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
+{
+ int ret;
+ const char *const clks[] = {
+ "mout_sclk_combo_phy_embedded",
+ "top_sclk_phy_fsys1_26m",
+ };
+
These clocks are neither in the binding nor in the example.
ok, I am cleaning this a bit, this will come from DT.
+struct exynos_ufs_drv_data exynos_ufs_drvs[] = {
+{
+ .compatible = "samsung,exynos7-ufs",
+ .uic_attr = &exynos7_uic_attr,
+ .quirks = UFSHCI_QUIRK_BYTE_ALIGN_UTRD |
+ UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
+ UFSHCI_QUIRK_BROKEN_HCE |
+ UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
+ .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
+ EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
+ EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
+ .drv_init = exynos7_ufs_drv_init,
+ .pre_link = exynos7_ufs_pre_link,
+ .post_link = exynos7_ufs_post_link,
+ .pre_pwr_change = exynos7_ufs_pre_pwr_change,
+ .post_pwr_change= exynos7_ufs_post_pwr_change,
+}, {
+}, };
The indentation is a bit unusual here.
hmm..ok will change
diff --git a/drivers/scsi/ufs/ufs-exynos-hw.h b/drivers/scsi/ufs/ufs-exynos-hw.h
new file mode 100644
index 000..8464ec8
--- /dev/null
+++ b/drivers/scsi/ufs/ufs-exynos-hw.h
@@ -0,0 +1,43 @@
+/*
+ * UFS Host Controller driver for Exynos specific extensions
+ *
+ * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _UFS_EXYNOS_HW_H_
+#define _UFS_EXYNOS_HW_H_
+
+#include "ufs-exynos.h"
+#include "unipro.h"
+
+static struct exynos_ufs_uic_attr exynos7_uic_attr = {
You cannot put 'static' variables into a header file.
will remove
+
+/**
+ * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
+ * Control should be disabled in the below cases
+ * - Before host controller S/W reset
+ * - Access to UFS protector's register
+ */
+static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en)
+{
+ u32 misc = hci_readl(ufs, HCI_MISC);
+
+ if (en)
+ hci_writel(ufs, misc | HCI_CORECLK_CTRL_EN, HCI_MISC);
+ else
+ hci_writel(ufs, misc & ~HCI_CORECLK_CTRL_EN, HCI_MISC);
Does this need a spinlock to ensure the change is done atomically?
will check and if needed will add,
+}
+
+static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en)
+{
+ u32 ctrl = hci_readl(ufs, HCI_CLKSTOP_CTRL);
+ u32 misc = hci_readl(ufs, HCI_MISC);
+
+ if (en) {
+ hci_writel(ufs, misc | CLK_CTRL_EN_MASK, HCI_MISC);
+ hci_writel(ufs, ctrl | CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
+ } else {
+ hci_writel(ufs, ctrl & ~CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
+ hci_writel(ufs, misc & ~CLK_CTRL_EN_MASK, HCI_MISC);
+ }
same here.
+
+static int exynos_ufs_get_clk_info(struct exynos_ufs *ufs)
+{
+ struct ufs_hba *hba = ufs->hba;
+ struct list_head *head = &hba->clk_list_head;
+ struct ufs_clk_info *clki;
+ u32 pclk_rate;
+ u32 f_min, f_max;
+ u8 div = 0;
+ int ret = 0;
+
+ if (!head || list_empty(head))
+ goto out;
+
+ list_for_each_entry(clki, head, list) {
+ if (!IS_ERR_OR_NULL(clki->clk)) {
+ if (!strcmp(clki->name, "aclk_ufs"))
+ ufs->clk_hci_core = clki->clk;
+ else if (!strcmp(clki->name, "sclk_unipro_apb"))
+ ufs->clk_apb = clki->clk;
+ else if (!strcmp(clki->name, "sclk_unipro_main"))
+ ufs->clk_unipro_main = clki->clk;
+ }
+ }
Using IS_ERR_OR_NULL is normally a bug. Also the list/loop can likely be
replaced with another way to express this.
ok
+ do {
+ delta = h8_time - ktime_us_delta(ktime_get(),
+ ufs->entry_hibern8_t);
+ if (delta <= 0)
+ break;
+
+ us = min_t(s64, delta, USEC_PER_MSEC);
+ if (us >
Re: [PATCH v3 11/13] Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller
Hi Arnd, On 10/01/2015 05:07 PM, Arnd Bergmann wrote: On Thursday 01 October 2015 13:39:28 Alim Akhtar wrote: From: Seungwon Jeon This adds Exynos Universal Flash Storage (UFS) Host Controller DT bindings. Signed-off-by: Seungwon Jeon Signed-off-by: Alim Akhtar --- .../devicetree/bindings/ufs/ufs-exynos.txt | 93 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt diff --git a/Documentation/devicetree/bindings/ufs/ufs-exynos.txt b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt new file mode 100644 index 000..00df72e --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt @@ -0,0 +1,93 @@ +* Exynos Universal Flash Storage (UFS) Host Controller + +UFSHC nodes are defined to describe on-chip UFS host controllers. +Each UFS controller instance should have its own node. + +Required properties: +- compatible: compatible name, contains "samsung,exynos7-ufs" +- interrupts: +- reg : This needs a list of all the register ranges, which order they are in and what the respective strings must be. will add the details +- clocks: List of phandle and clock specifier pairs +- clock-names : List of clock input name strings sorted in the same + order as the clocks property. You need to list the names you require here. Also the 'clock specifier' includes the phandle, it's not a pair but just a list of specifiers. ok will add +- ufs,pwr-attr-mode : specifies mode value for power mode change +- ufs,pwr-attr-lane : specifies lane count value for power mode change +- ufs,pwr-attr-gear : specifies gear count value for power mode change +- ufs,pwr-attr-hs-series : specifies HS rate series for power mode change +- ufs,pwr-local-l2-timer : specifies array of local UNIPRO L2 timer values + +- ufs,pwr-remote-l2-timer : specifies array of remote UNIPRO L2 timer values + +- ufs-rx-adv-fine-gran-sup_en : specifies support of fine granularity of MPHY, + this is a boolean property. +- ufs-rx-adv-fine-gran-step : specifies granularity steps of MPHY +- ufs-rx-adv-min-activate-time-cap : specifies rx advanced minimum activate time of MPHY +- ufs-pa-granularity : specifies Granularity for PA_TActivate and PA_Hibern8Time +- ufs-pa-tacctivate : specifies time wake-up remote M-RX +- ufs-pa-hibern8time : specifies minimum time to wait in HIBERN8 state These all require a specification of what the allowed values are and/or the units for the numbers. will update the specifications above + + clocks = <&core 0>, <&ref 0>, <&iface 0>; + clock-names = "core_clk", "ref_clk", "iface_clk"; Better rename them to "core", "ref" and "iface", no point requiring to spell out "clk" here. + ufs,pwr-attr-mode = "FAST"; A string is rather unusual here, what are the allowed values? Could you use a boolean property instead? will update the binding, supported modes are FAST, SLOW, FAST_auto etc, so kept the string for more readability + ufs,pwr-attr-lane = /bits/ 8 <2>; + ufs,pwr-attr-gear = /bits/ 8 <2>; Why the "/bits/ 8" ? I am using of_property_read_u8() to read 8 bit value from property. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH] phy: exynos-ufs: exynos_ufs_phy_calibrate() can be static
HI
How I am support to handle this patch? Should I just fix these warnings
in my patch or I just add this as a separate patch on the top of the series?
On 10/01/2015 04:34 PM, kbuild test robot wrote:
Signed-off-by: Fengguang Wu
---
phy-exynos-ufs.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
index 343fcaf..835ee78 100644
--- a/drivers/phy/phy-exynos-ufs.c
+++ b/drivers/phy/phy-exynos-ufs.c
@@ -66,7 +66,7 @@ static bool match_cfg_to_pwr_mode(u8 desc, u8 required_pwr)
return false;
}
-int exynos_ufs_phy_calibrate(struct phy *phy, enum phy_cfg_tag tag, u8 pwr)
+static int exynos_ufs_phy_calibrate(struct phy *phy, enum phy_cfg_tag tag, u8
pwr)
{
struct exynos_ufs_phy *ufs_phy = get_exynos_ufs_phy(phy);
struct exynos_ufs_phy_cfg **cfgs = ufs_phy->cfg;
@@ -93,14 +93,14 @@ out:
return 0;
}
-void exynos_ufs_phy_set_lane_cnt(struct phy *phy, u8 lane_cnt)
+static void exynos_ufs_phy_set_lane_cnt(struct phy *phy, u8 lane_cnt)
{
struct exynos_ufs_phy *ufs_phy = get_exynos_ufs_phy(phy);
ufs_phy->lane_cnt = lane_cnt;
}
-int exynos_ufs_phy_wait_for_lock_acq(struct phy *phy)
+static int exynos_ufs_phy_wait_for_lock_acq(struct phy *phy)
{
struct exynos_ufs_phy *ufs_phy = get_exynos_ufs_phy(phy);
const unsigned int timeout_us = 10;
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Re: [PATCH v3 12/13] scsi: ufs-exynos: add UFS host support for Exynos SoCs
On 10/13/2015 05:08 PM, Arnd Bergmann wrote: On Tuesday 13 October 2015 16:49:39 Alim Akhtar wrote: diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h new file mode 100644 index 000..58aa714 --- /dev/null +++ b/drivers/scsi/ufs/ufs-exynos.h @@ -0,0 +1,463 @@ +/* + * UFS Host Controller driver for Exynos specific extensions + * + * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _UFS_EXYNOS_H_ +#define _UFS_EXYNOS_H_ You have a lot of things in this header that are only used in one of the .c files, so just move them there and make the header as small as possible. hmm..these are mostly the registers defines, will removes the one which are not being used as of now. Do you think I should sill move them to .c file? Yes. No need to remove the unused register definitions, just don't put them into a separate header if they are only used in one place. Ok will do that in v4. Thanks. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 00/11] exynos-ufs: add support for Exynos
This patch-set introduces UFS (Universal Flash Storage) host support for Samsung Exynos SoC. Mostly, it consists of UFS PHY and host specific driver. And it also contains some quirks handling for Exynos. NOTE: ** This series has a dependency on [4]. ** -Changes since v3: * Fixed compilation warrings as reported by "Kbuild Test Robot"[5]. * Restructure the driver to make it as a platform driver, rebased on top of [4]. * Addressed review comments from Arnd Bergmann[5]. * Other misc changes and improvements. -Changes since v2: * Addressed review comments from Kishon[1] and Rob Herring [2] * Splited ufs dt binding documetation from ufs driver patch -Changes since v1: * Addressed review comments from Alexey[3] and various review comments from Amit. * Updated email id of Seungwon as his samsung id is void now. * Added ufs platform data [1]-> https://lkml.org/lkml/2015/9/18/29 [2]-> https://lkml.org/lkml/2015/9/21/668 [3]-> https://lkml.org/lkml/2015/8/23/124 [4]-> https://lkml.org/lkml/2015/9/2/364 [5]-> https://lkml.org/lkml/2015/10/1/402 This patch set is tested on exynos7-espresso board. Alim Akhtar (1): Documentation: samsung-phy: Add dt bindings for UFS Seungwon Jeon (10): phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC scsi: ufs: add quirk to contain unconformable utrd field scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr scsi: ufs: add quirk not to allow reset of interrupt aggregation scsi: ufs: add quirk to enable host controller without hce scsi: ufs: add specific callback for nexus type scsi: ufs: add add specific callback for hibern8 scsi: ufs: make ufshcd_config_pwr_mode of non-static func Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller scsi: ufs-exynos: add UFS host support for Exynos SoCs .../devicetree/bindings/phy/samsung-phy.txt| 22 + .../devicetree/bindings/ufs/ufs-exynos.txt | 104 ++ drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos-ufs.c | 257 drivers/phy/phy-exynos-ufs.h | 88 ++ drivers/phy/phy-exynos7-ufs.h | 89 ++ drivers/scsi/ufs/Kconfig | 12 + drivers/scsi/ufs/Makefile |1 + drivers/scsi/ufs/ufs-exynos-hw.c | 131 ++ drivers/scsi/ufs/ufs-exynos-hw.h | 43 + drivers/scsi/ufs/ufs-exynos.c | 1317 drivers/scsi/ufs/ufs-exynos.h | 247 drivers/scsi/ufs/ufshcd.c | 168 ++- drivers/scsi/ufs/ufshcd.h | 54 + drivers/scsi/ufs/ufshci.h | 26 +- drivers/scsi/ufs/unipro.h | 47 + include/linux/phy/phy-exynos-ufs.h | 101 ++ 18 files changed, 2695 insertions(+), 20 deletions(-) create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt create mode 100644 drivers/phy/phy-exynos-ufs.c create mode 100644 drivers/phy/phy-exynos-ufs.h create mode 100644 drivers/phy/phy-exynos7-ufs.h create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h create mode 100644 drivers/scsi/ufs/ufs-exynos.c create mode 100644 drivers/scsi/ufs/ufs-exynos.h create mode 100644 include/linux/phy/phy-exynos-ufs.h -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 02/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
From: Seungwon Jeon
This patch introduces Exynos UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
---
drivers/phy/Kconfig|7 +
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos-ufs.c | 257
drivers/phy/phy-exynos-ufs.h | 88
drivers/phy/phy-exynos7-ufs.h | 89 +
include/linux/phy/phy-exynos-ufs.h | 101 ++
6 files changed, 543 insertions(+)
create mode 100644 drivers/phy/phy-exynos-ufs.c
create mode 100644 drivers/phy/phy-exynos-ufs.h
create mode 100644 drivers/phy/phy-exynos7-ufs.h
create mode 100644 include/linux/phy/phy-exynos-ufs.h
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 47da573d0bab..499eec4a967c 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -371,4 +371,11 @@ config PHY_BRCMSTB_SATA
Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
Likely useful only with CONFIG_SATA_BRCMSTB enabled.
+config PHY_EXYNOS_UFS
+ tristate "EXYNOS SoC series UFS PHY driver"
+ depends on OF && ARCH_EXYNOS || COMPILE_TEST
+ select GENERIC_PHY
+ help
+ Support for UFS PHY on Samsung EXYNOS chipsets.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a5b18c18fc12..2a312ca20795 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -46,3 +46,4 @@ obj-$(CONFIG_PHY_QCOM_UFS)+= phy-qcom-ufs-qmp-14nm.o
obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
obj-$(CONFIG_PHY_PISTACHIO_USB)+= phy-pistachio-usb.o
+obj-$(CONFIG_PHY_EXYNOS_UFS) += phy-exynos-ufs.o
diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
new file mode 100644
index ..77330b85e3f8
--- /dev/null
+++ b/drivers/phy/phy-exynos-ufs.c
@@ -0,0 +1,257 @@
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "phy-exynos-ufs.h"
+
+#define for_each_phy_lane(phy, i) \
+ for (i = 0; i < (phy)->lane_cnt; i++)
+#define for_each_phy_cfg(cfg) \
+ for (; (cfg)->id; (cfg)++)
+
+#define PHY_DEF_LANE_CNT 1
+
+static void exynos_ufs_phy_config(struct exynos_ufs_phy *phy,
+ const struct exynos_ufs_phy_cfg *cfg, u8 lane)
+{
+ enum {LANE_0, LANE_1}; /* lane index */
+
+ switch (lane) {
+ case LANE_0:
+ writel(cfg->val, (phy)->reg_pma + cfg->off_0);
+ break;
+ case LANE_1:
+ if (cfg->id == PHY_TRSV_BLK)
+ writel(cfg->val, (phy)->reg_pma + cfg->off_1);
+ break;
+ }
+}
+
+static bool match_cfg_to_pwr_mode(u8 desc, u8 required_pwr)
+{
+ if (IS_PWR_MODE_ANY(desc))
+ return true;
+
+ if (IS_PWR_MODE_HS(required_pwr) && IS_PWR_MODE_HS_ANY(desc))
+ return true;
+
+ if (COMP_PWR_MODE(required_pwr, desc))
+ return true;
+
+ if (COMP_PWR_MODE_MD(required_pwr, desc) &&
+ COMP_PWR_MODE_GEAR(required_pwr, desc) &&
+ COMP_PWR_MODE_SER(required_pwr, desc))
+ return true;
+
+ return false;
+}
+
+static int exynos_ufs_phy_calibrate(struct phy *phy,
+ enum phy_cfg_tag tag, u8 pwr)
+{
+ struct exynos_ufs_phy *ufs_phy = get_exynos_ufs_phy(phy);
+ struct exynos_ufs_phy_cfg **cfgs = ufs_phy->cfg;
+ const struct exynos_ufs_phy_cfg *cfg;
+ int i;
+
+ if (unlikely(tag < CFG_PRE_INIT || tag >= CFG_TAG_MAX)) {
+ dev_err(ufs_phy->dev, "invalid phy config index %d\n", tag);
+ return -EINVAL;
+ }
+
+ cfg = cfgs[tag];
+ if (!cfg)
+ goto out;
+
+ for_each_phy_cfg(cfg) {
+ for_each_phy_lane(ufs_phy, i) {
+ if (match_cfg_to_pwr_mode(cfg->desc, pwr))
+ exynos_ufs_phy_config(ufs_phy, cfg, i);
+ }
+ }
+
+out:
+ return 0;
+}
+
+static void exynos_ufs_phy_set_lane_cnt(struct phy *phy, u8 lane_cnt)
+{
+ struct exynos_ufs_phy *ufs_phy = get_exynos_ufs_phy(phy);
+
+ ufs_phy->lane_cnt = lan
[PATCH v4 01/11] Documentation: samsung-phy: Add dt bindings for UFS
Adds exynos UFS PHY device tree bindings information.
Signed-off-by: Alim Akhtar
---
.../devicetree/bindings/phy/samsung-phy.txt| 22
1 file changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 60c6f2a633e0..c92ce537ceec 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -174,3 +174,25 @@ Example:
usbdrdphy0 = &usb3_phy0;
usbdrdphy1 = &usb3_phy1;
};
+
+Samsung Exynos7 soc series UFS PHY Controller
+-
+
+UFS PHY nodes are defined to describe on-chip UFS Physical layer controllers.
+Each UFS PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible should be set to "samsung,exynos7-ufs-phy"
+- reg : offset and length of the UFS PHY register set
+- reg-names : reg name(s) must be 'phy-pma'
+- #phy-cells : must be zero
+- samsung,pmu-syscon : a phandle to the PMU system controller, no arguments
+
+Example:
+ ufs_phy: ufs-phy@0x15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ };
--
1.7.10.4
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[PATCH v4 04/11] scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
From: Seungwon Jeon
In the right behavior, setting the bit to '0' indicates clear and
'1' indicates no change. If host contoller handles this the other way,
UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR can be used.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 21 +++--
drivers/scsi/ufs/ufshcd.h |5 +
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 587a9c8fbfe9..2b16eb363203 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -356,7 +356,24 @@ static inline void ufshcd_put_tm_slot(struct ufs_hba *hba,
int slot)
*/
static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
{
- ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos),
+ REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+}
+
+/**
+ * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
+ * @hba: per adapter instance
+ * @pos: position of the bit to be cleared
+ */
+static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
+{
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
}
/**
@@ -3685,7 +3702,7 @@ static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int
tag)
goto out;
spin_lock_irqsave(hba->host->host_lock, flags);
- ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
+ ufshcd_utmrl_clear(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
/* poll for max. 1 sec to clear door bell register by h/w */
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 6cd542a803d5..d625d01110b0 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -474,6 +474,11 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_BYTE_ALIGN_UTRDUFS_BIT(6)
+ /*
+* Cleaer handling for transfer/task request list is just opposite.
+*/
+ #define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLRUFS_BIT(7)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v4 03/11] scsi: ufs: add quirk to contain unconformable utrd field
From: Seungwon Jeon
UTRD(UTP Transfer Request Descriptor)'s field such as offset/length,
especially response's has DWORD expression. This quirk can be specified
for host controller not to conform standard.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 28 +---
drivers/scsi/ufs/ufshcd.h |7 +++
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 131c72038bf8..587a9c8fbfe9 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1009,7 +1009,7 @@ ufshcd_send_uic_cmd(struct ufs_hba *hba, struct
uic_command *uic_cmd)
*
* Returns 0 in case of success, non-zero value in case of failure
*/
-static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
+static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
{
struct ufshcd_sg_entry *prd_table;
struct scatterlist *sg;
@@ -1023,8 +1023,13 @@ static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
return sg_segments;
if (sg_segments) {
- lrbp->utr_descriptor_ptr->prd_table_length =
- cpu_to_le16((u16) (sg_segments));
+ if (hba->quirks & UFSHCI_QUIRK_BYTE_ALIGN_UTRD)
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16)(sg_segments *
+ sizeof(struct ufshcd_sg_entry)));
+ else
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16) (sg_segments));
prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
@@ -1347,7 +1352,7 @@ static int ufshcd_queuecommand(struct Scsi_Host *host,
struct scsi_cmnd *cmd)
/* form UPIU before issuing the command */
ufshcd_compose_upiu(hba, lrbp);
- err = ufshcd_map_sg(lrbp);
+ err = ufshcd_map_sg(hba, lrbp);
if (err) {
lrbp->cmd = NULL;
clear_bit_unlock(tag, &hba->lrb_in_use);
@@ -2034,13 +2039,22 @@ static void ufshcd_host_memory_configure(struct ufs_hba
*hba)
utrdlp[i].command_desc_base_addr_hi =
cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
+ if (hba->quirks & UFSHCI_QUIRK_BYTE_ALIGN_UTRD) {
+ utrdlp[i].response_upiu_offset =
+ cpu_to_le16(response_offset);
+ utrdlp[i].prd_table_offset =
+ cpu_to_le16(prdt_offset);
+ utrdlp[i].response_upiu_length =
+ cpu_to_le16(ALIGNED_UPIU_SIZE);
+ } else {
/* Response upiu and prdt offset should be in double words */
- utrdlp[i].response_upiu_offset =
+ utrdlp[i].response_upiu_offset =
cpu_to_le16((response_offset >> 2));
- utrdlp[i].prd_table_offset =
+ utrdlp[i].prd_table_offset =
cpu_to_le16((prdt_offset >> 2));
- utrdlp[i].response_upiu_length =
+ utrdlp[i].response_upiu_length =
cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
+ }
hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
hba->lrb[i].ucd_req_ptr =
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 2570d9477b37..6cd542a803d5 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -467,6 +467,13 @@ struct ufs_hba {
*/
#define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION UFS_BIT(5)
+ /*
+* This quirk needs to be enabled if host controller doesn't conform
+* with UTRD. Some fields such as offset/length might not be in double
+* word, but in byte.
+*/
+ #define UFSHCI_QUIRK_BYTE_ALIGN_UTRDUFS_BIT(6)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v4 05/11] scsi: ufs: add quirk not to allow reset of interrupt aggregation
From: Seungwon Jeon
Some host controller supports interrupt aggregation, but doesn't
allow to reset counter and timer by s/w.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |3 ++-
drivers/scsi/ufs/ufshcd.h |6 ++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 2b16eb363203..ca7483cd899e 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -3199,7 +3199,8 @@ static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
* false interrupt if device completes another request after resetting
* aggregation and before reading the DB.
*/
- if (ufshcd_is_intr_aggr_allowed(hba))
+ if (ufshcd_is_intr_aggr_allowed(hba) &&
+ !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
ufshcd_reset_intr_aggr(hba);
tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index d625d01110b0..4ae32e9316de 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -479,6 +479,12 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLRUFS_BIT(7)
+ /*
+* This quirk needs to be enabled if host controller doesn't allow
+* that the interrupt aggregation timer and counter are reset by s/w.
+*/
+ #define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR UFS_BIT(8)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v4 07/11] scsi: ufs: add specific callback for nexus type
From: Seungwon Jeon
Some host controller needs nexus type information for handling
command. This change adds specific callback function to support
vendor's implementation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |3 +++
drivers/scsi/ufs/ufshcd.h | 19 +++
2 files changed, 22 insertions(+)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index e8b96ec65987..eeb7835c52ab 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1378,6 +1378,7 @@ static int ufshcd_queuecommand(struct Scsi_Host *host,
struct scsi_cmnd *cmd)
/* issue command to the controller */
spin_lock_irqsave(hba->host->host_lock, flags);
+ ufshcd_vops_specify_nexus_t_xfer_req(hba, tag, lrbp);
ufshcd_send_command(hba, tag);
out_unlock:
spin_unlock_irqrestore(hba->host->host_lock, flags);
@@ -1578,6 +1579,7 @@ static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
hba->dev_cmd.complete = &wait;
spin_lock_irqsave(hba->host->host_lock, flags);
+ ufshcd_vops_specify_nexus_t_xfer_req(hba, tag, lrbp);
ufshcd_send_command(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
@@ -3842,6 +3844,7 @@ static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int
lun_id, int task_id,
task_req_upiup->input_param2 = cpu_to_be32(task_id);
/* send command to the controller */
+ ufshcd_vops_specify_nexus_t_tm_req(hba, free_slot, tm_function);
__set_bit(free_slot, &hba->outstanding_tasks);
ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 500e137bf68a..b3dd08420100 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -259,6 +259,9 @@ struct ufs_pwr_mode_info {
* @pwr_change_notify: called before and after a power mode change
* is carried out to allow vendor spesific capabilities
* to be set.
+ * @specify_nexus_t_xfer_req:
+ * @specify_nexus_t_tm_req: called before command is issued to allow vendor
+ * specific handling to be set for nexus type.
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
* @dbg_register_dump: used to dump controller debug information
@@ -280,6 +283,9 @@ struct ufs_hba_variant_ops {
enum ufs_notify_change_status status,
struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+ void(*specify_nexus_t_xfer_req)(struct ufs_hba *,
+ int, struct scsi_cmnd *);
+ void(*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
int (*resume)(struct ufs_hba *, enum ufs_pm_op);
void(*dbg_register_dump)(struct ufs_hba *hba);
@@ -811,4 +817,17 @@ static inline void ufshcd_vops_dbg_register_dump(struct
ufs_hba *hba)
hba->vops->dbg_register_dump(hba);
}
+static inline void ufshcd_vops_specify_nexus_t_xfer_req(struct ufs_hba *hba,
+ int tag, struct ufshcd_lrb *lrbp)
+{
+ if (hba->vops && hba->vops->specify_nexus_t_xfer_req)
+ hba->vops->specify_nexus_t_xfer_req(hba, tag, lrbp->cmd);
+}
+
+static inline void ufshcd_vops_specify_nexus_t_tm_req(struct ufs_hba *hba,
+ int free_slot, u8 tm_function)
+{
+ if (hba->vops && hba->vops->specify_nexus_t_tm_req)
+ hba->vops->specify_nexus_t_tm_req(hba, free_slot, tm_function);
+}
#endif /* End of Header */
--
1.7.10.4
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[PATCH v4 06/11] scsi: ufs: add quirk to enable host controller without hce
From: Seungwon Jeon
Some host controller doesn't support host controller enable via HCE.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 75 +++--
drivers/scsi/ufs/ufshcd.h |5 +++
2 files changed, 78 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index ca7483cd899e..e8b96ec65987 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2107,6 +2107,52 @@ static int ufshcd_dme_link_startup(struct ufs_hba *hba)
"dme-link-startup: error code %d\n", ret);
return ret;
}
+/**
+ * ufshcd_dme_reset - UIC command for DME_RESET
+ * @hba: per adapter instance
+ *
+ * DME_RESET command is issued in order to reset UniPro stack.
+ * This function now deal with cold reset.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_reset(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_RESET;
+
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
+
+/**
+ * ufshcd_dme_enable - UIC command for DME_ENABLE
+ * @hba: per adapter instance
+ *
+ * DME_ENABLE command is issued in order to enable UniPro stack.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_enable(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_ENABLE;
+
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
{
@@ -2642,7 +2688,7 @@ out:
}
/**
- * ufshcd_hba_enable - initialize the controller
+ * ufshcd_hba_execute_hce - initialize the controller
* @hba: per adapter instance
*
* The controller resets itself and controller firmware initialization
@@ -2651,7 +2697,7 @@ out:
*
* Returns 0 on success, non-zero value on failure
*/
-static int ufshcd_hba_enable(struct ufs_hba *hba)
+static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
{
int retry;
@@ -2715,6 +2761,31 @@ static int ufshcd_hba_enable(struct ufs_hba *hba)
return 0;
}
+static int ufshcd_hba_enable(struct ufs_hba *hba)
+{
+ int ret;
+
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
+ ufshcd_set_link_off(hba);
+ ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
+
+ /* enable UIC related interrupts */
+ ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
+ ret = ufshcd_dme_reset(hba);
+ if (!ret) {
+ ret = ufshcd_dme_enable(hba);
+ if (!ret)
+ ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
+ if (ret)
+ dev_err(hba->dev,
+ "Host controller enable failed with
non-hce\n");
+ }
+ } else {
+ ret = ufshcd_hba_execute_hce(hba);
+ }
+
+ return ret;
+}
static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
{
int tx_lanes, i, err = 0;
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 4ae32e9316de..500e137bf68a 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -485,6 +485,11 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR UFS_BIT(8)
+ /*
+* This quirks needs to be enabled if host controller cannot be
+* enabled via HCE register.
+*/
+ #define UFSHCI_QUIRK_BROKEN_HCE UFS_BIT(9)
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v4 08/11] scsi: ufs: add add specific callback for hibern8
From: Seungwon Jeon
Some host controller needs specific handling before/after
(un)hibernation, This change adds specific callback function
to support vendor's implementation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 33 +
drivers/scsi/ufs/ufshcd.h | 10 ++
2 files changed, 39 insertions(+), 4 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index eeb7835c52ab..075b7bf13080 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -181,8 +181,7 @@ static int ufshcd_probe_hba(struct ufs_hba *hba);
static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
bool skip_ref_clk);
static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
@@ -215,6 +214,16 @@ static inline void ufshcd_disable_irq(struct ufs_hba *hba)
}
}
+static inline int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, true);
+}
+
+static inline int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, false);
+}
+
/*
* ufshcd_wait_for_register - wait for register value to change
* @hba - per-adapter interface
@@ -2394,7 +2403,7 @@ out:
return ret;
}
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
@@ -2403,7 +2412,7 @@ static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
return ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
}
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
int ret;
@@ -2418,6 +2427,22 @@ static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
return ret;
}
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en)
+{
+ int ret;
+
+ ufshcd_vops_hibern8_notify(hba, en, PRE_CHANGE);
+ ret = en ? __ufshcd_uic_hibern8_enter(hba) :
+ __ufshcd_uic_hibern8_exit(hba);
+ if (ret)
+ goto out;
+
+ ufshcd_vops_hibern8_notify(hba, en, POST_CHANGE);
+
+out:
+ return ret;
+}
+
/**
* ufshcd_init_pwr_info - setting the POR (power on reset)
* values in hba power info
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index b3dd08420100..9c69dd2f3672 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -262,6 +262,8 @@ struct ufs_pwr_mode_info {
* @specify_nexus_t_xfer_req:
* @specify_nexus_t_tm_req: called before command is issued to allow vendor
* specific handling to be set for nexus type.
+ * @hibern8_notify: called before and after hibernate/unhibernate is carried
out
+ * to allow vendor spesific implementation.
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
* @dbg_register_dump: used to dump controller debug information
@@ -283,6 +285,7 @@ struct ufs_hba_variant_ops {
enum ufs_notify_change_status status,
struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+ void(*hibern8_notify)(struct ufs_hba *, bool, bool);
void(*specify_nexus_t_xfer_req)(struct ufs_hba *,
int, struct scsi_cmnd *);
void(*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
@@ -830,4 +833,11 @@ static inline void
ufshcd_vops_specify_nexus_t_tm_req(struct ufs_hba *hba,
if (hba->vops && hba->vops->specify_nexus_t_tm_req)
hba->vops->specify_nexus_t_tm_req(hba, free_slot, tm_function);
}
+
+static inline void ufshcd_vops_hibern8_notify(struct ufs_hba *hba,
+ bool en, enum ufs_notify_change_status status)
+{
+ if (hba->vops && hba->vops->hibern8_notify)
+ hba->vops->hibern8_notify(hba, en, status);
+}
#endif /* End of Header */
--
1.7.10.4
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[PATCH v4 09/11] scsi: ufs: make ufshcd_config_pwr_mode of non-static func
From: Seungwon Jeon
This makes ufshcd_config_pwr_mode non-static so that other vendors
like exynos can use the same.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |5 ++---
drivers/scsi/ufs/ufshcd.h |2 ++
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 075b7bf13080..358d9114a1a5 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -185,8 +185,6 @@ static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba,
bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
- struct ufs_pa_layer_attr *desired_pwr_mode);
static int ufshcd_change_power_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *pwr_mode);
@@ -2592,7 +2590,7 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
* @hba: per-adapter instance
* @desired_pwr_mode: desired power configuration
*/
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+int ufshcd_config_pwr_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *desired_pwr_mode)
{
struct ufs_pa_layer_attr final_params = { 0 };
@@ -2608,6 +2606,7 @@ static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
return ret;
}
+EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
/**
* ufshcd_complete_dev_init() - checks device readiness
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 9c69dd2f3672..8cad52c072d4 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -666,6 +666,8 @@ extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32
attr_sel,
u8 attr_set, u32 mib_val, u8 peer);
extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
u32 *mib_val, u8 peer);
+extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+ struct ufs_pa_layer_attr *desired_pwr_mode);
/* UIC command interfaces for DME primitives */
#define DME_LOCAL 0
--
1.7.10.4
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[PATCH v4 10/11] Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller
From: Seungwon Jeon
This adds Exynos Universal Flash Storage (UFS) Host Controller DT bindings.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
.../devicetree/bindings/ufs/ufs-exynos.txt | 104
1 file changed, 104 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
diff --git a/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
new file mode 100644
index ..042dedf4e323
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
@@ -0,0 +1,104 @@
+* Exynos Universal Flash Storage (UFS) Host Controller
+
+UFSHC nodes are defined to describe on-chip UFS host controllers.
+Each UFS controller instance should have its own node.
+
+Required properties:
+- compatible: compatible name, contains "samsung,exynos7-ufs"
+- interrupts:
+- reg : Should contain HCI, vendor specific, UNIPRO and
+ UFS protector address space
+- reg-names: "hci", "vs_hci", "unipro", "ufsp";
+
+Optional properties:
+- vdd-hba-supply: phandle to UFS host controller supply regulator node
+- vcc-supply: phandle to VCC supply regulator node
+- vccq-supply : phandle to VCCQ supply regulator node
+- vccq2-supply : phandle to VCCQ2 supply regulator node
+- vcc-supply-1p8: For embedded UFS devices, valid VCC range is
1.7-1.95V
+ or 2.7-3.6V. This boolean property when set,
specifies
+ to use low voltage range of 1.7-1.95V. Note for
external
+ UFS cards this property is invalid and valid VCC
range is
+ always 2.7-3.6V.
+- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
+- vccq-max-microamp : specifies max. load that can be drawn from vccq
supply
+- vccq2-max-microamp: specifies max. load that can be drawn from vccq2
supply
+- -fixed-regulator : boolean property specifying that -supply is a
fixed regulator
+
+- clocks: List of phandle and clock specifier pairs
+- clock-names : List of clock input name strings sorted in the same
+ order as the clocks property.
+ "core", "sclk_unipro_main", "ref" and ref_parent
+
+- freq-table-hz: Array of operating frequencies
stored in the same
+ order as the clocks property. If this property is not
+ defined or a value in the array is "0" then it is
assumed
+ that the frequency is set by the parent clock or a
+ fixed rate clock source.
+- pclk-freq-avail-range : specifies available frequency range(min/max) for APB
clock
+- ufs,pwr-attr-mode : specifies mode value for power mode change, possible
values are
+ "FAST", "SLOW", "FAST_auto" and "SLOW_auto"
+- ufs,pwr-attr-lane : specifies lane count value for power mode change
+ allowed values are 1 or 2
+- ufs,pwr-attr-gear : specifies gear count value for power mode change
+ allowed values are 1 or 2
+- ufs,pwr-attr-hs-series : specifies HS rate series for power mode change
+ can be one of "HS_rate_b" or "HS_rate_a"
+- ufs,pwr-local-l2-timer : specifies array of local UNIPRO L2 timer values
+ 3 timers supported
+
+- ufs,pwr-remote-l2-timer : specifies array of remote UNIPRO L2 timer values
+ 3 timers supported
+
+- ufs-rx-adv-fine-gran-sup_en : specifies support of fine granularity of MPHY,
+ this is a boolean property.
+- ufs-rx-adv-fine-gran-step : specifies granularity steps of MPHY,
+ allowed step size is 0 to 3
+- ufs-rx-adv-min-activate-time-cap : specifies rx advanced minimum activate
time of MPHY
+range is 1 to 9
+- ufs-pa-granularity : specifies Granularity for PA_TActivate and
PA_Hibern8Time
+- ufs-pa-tacctivate : specifies time to wake-up remote M-RX
+- ufs-pa-hibern8time : specifies minimum time to wait in HIBERN8 state
+
+Note: If above properties are not defined it can be assumed that the supply
+regulators or clocks are always on.
+
+Example:
+ ufshc@0x1557 {
+ compatible = "samsung,exynos7-ufs";
+ reg = <0x1557 0x100>,
+ <0x15570100 0x100>,
+ <0x15571000 0x200>,
+ <0x15572000 0x300>;
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+
[PATCH v4 11/11] scsi: ufs-exynos: add UFS host support for Exynos SoCs
From: Seungwon Jeon
This patch introduces Exynos UFS host controller driver,
which mainly handles vendor-specific operations including
link startup, power mode change and hibernation/unhibernation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/Kconfig | 12 +
drivers/scsi/ufs/Makefile|1 +
drivers/scsi/ufs/ufs-exynos-hw.c | 131
drivers/scsi/ufs/ufs-exynos-hw.h | 43 ++
drivers/scsi/ufs/ufs-exynos.c| 1317 ++
drivers/scsi/ufs/ufs-exynos.h| 247 +++
drivers/scsi/ufs/ufshci.h| 26 +-
drivers/scsi/ufs/unipro.h| 47 ++
8 files changed, 1823 insertions(+), 1 deletion(-)
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
create mode 100644 drivers/scsi/ufs/ufs-exynos.c
create mode 100644 drivers/scsi/ufs/ufs-exynos.h
diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig
index 5f4530744e0a..bc602be94458 100644
--- a/drivers/scsi/ufs/Kconfig
+++ b/drivers/scsi/ufs/Kconfig
@@ -83,3 +83,15 @@ config SCSI_UFS_QCOM
Select this if you have UFS controller on QCOM chipset.
If unsure, say N.
+
+config SCSI_UFS_EXYNOS
+ bool "EXYNOS specific hooks to UFS controller platform driver"
+ depends on SCSI_UFSHCD_PLATFORM && ARCH_EXYNOS || COMPILE_TEST
+ select PHY_EXYNOS_UFS
+ help
+ This selects the EXYNOS specific additions to UFSHCD platform driver.
+ UFS host on EXYNOS includes HCI and UNIPRO layer, and associates with
+ UFS-PHY driver.
+
+ Select this if you have UFS host controller on EXYNOS chipset.
+ If unsure, say N.
diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile
index 8303bcce7a23..2accf1e628b3 100644
--- a/drivers/scsi/ufs/Makefile
+++ b/drivers/scsi/ufs/Makefile
@@ -1,5 +1,6 @@
# UFSHCD makefile
obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o
+obj-$(CONFIG_SCSI_UFS_EXYNOS) += ufs-exynos.o ufs-exynos-hw.o
obj-$(CONFIG_SCSI_UFSHCD) += ufshcd.o
obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o
obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o
diff --git a/drivers/scsi/ufs/ufs-exynos-hw.c b/drivers/scsi/ufs/ufs-exynos-hw.c
new file mode 100644
index ..be6c61541a8f
--- /dev/null
+++ b/drivers/scsi/ufs/ufs-exynos-hw.c
@@ -0,0 +1,131 @@
+/*
+ * UFS Host Controller driver for Exynos specific extensions
+ *
+ * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "ufshcd.h"
+#include "unipro.h"
+
+#include "ufs-exynos.h"
+#include "ufs-exynos-hw.h"
+
+static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
+{
+ struct clk *child, *parent;
+
+ child = devm_clk_get(dev, "ref_clk");
+ if (IS_ERR(child)) {
+ dev_err(dev, "failed to get ref_clk clock\n");
+ return -EINVAL;
+ }
+
+ parent = devm_clk_get(dev, "ref_clk_parent");
+ if (IS_ERR(parent)) {
+ dev_err(dev, "failed to get ref_clk_parent clock\n");
+ return -EINVAL;
+ }
+ return clk_set_parent(child, parent);
+}
+
+static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
+{
+ struct ufs_hba *hba = ufs->hba;
+ u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite;
+ int i;
+
+ exynos_ufs_enable_ov_tm(hba);
+ for_each_ufs_tx_lane(ufs, i)
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17);
+ for_each_ufs_rx_lane(ufs, i) {
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00);
+ }
+ exynos_ufs_disable_ov_tm(hba);
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE_DYN), 0xf);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE_DYN), 0xf);
+ for_each_ufs_tx_lane(ufs, i)
+ ufshcd_dme_set(hba,
+ UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1);
+ udelay(1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12));
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1);
+ udelay(1600);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val);
+
+ return 0;
+}
+
+static int exynos7_ufs_post_link(struct exynos_ufs *ufs)
+{
+ struct
Re: [PATCH v4 02/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
Hi,
On Wed, Oct 14, 2015 at 9:31 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Wednesday 14 October 2015 06:25 PM, Alim Akhtar wrote:
>> From: Seungwon Jeon
>>
>> This patch introduces Exynos UFS PHY driver. This driver
>> supports to deal with phy calibration and power control
>> according to UFS host driver's behavior.
>>
>> Signed-off-by: Seungwon Jeon
>> Signed-off-by: Alim Akhtar
>> Cc: Kishon Vijay Abraham I
>> ---
>> drivers/phy/Kconfig|7 +
>> drivers/phy/Makefile |1 +
>> drivers/phy/phy-exynos-ufs.c | 257
>>
>> drivers/phy/phy-exynos-ufs.h | 88
>> drivers/phy/phy-exynos7-ufs.h | 89 +
>> include/linux/phy/phy-exynos-ufs.h | 101 ++
>> 6 files changed, 543 insertions(+)
>> create mode 100644 drivers/phy/phy-exynos-ufs.c
>> create mode 100644 drivers/phy/phy-exynos-ufs.h
>> create mode 100644 drivers/phy/phy-exynos7-ufs.h
>> create mode 100644 include/linux/phy/phy-exynos-ufs.h
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 47da573d0bab..499eec4a967c 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -371,4 +371,11 @@ config PHY_BRCMSTB_SATA
>> Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
>> Likely useful only with CONFIG_SATA_BRCMSTB enabled.
>>
>> +config PHY_EXYNOS_UFS
>> + tristate "EXYNOS SoC series UFS PHY driver"
>> + depends on OF && ARCH_EXYNOS || COMPILE_TEST
>> + select GENERIC_PHY
>> + help
>> + Support for UFS PHY on Samsung EXYNOS chipsets.
>> +
>> endmenu
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index a5b18c18fc12..2a312ca20795 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -46,3 +46,4 @@ obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o
>> obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
>> obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
>> obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
>> +obj-$(CONFIG_PHY_EXYNOS_UFS) += phy-exynos-ufs.o
>> diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
>> new file mode 100644
>> index ..77330b85e3f8
>> --- /dev/null
>> +++ b/drivers/phy/phy-exynos-ufs.c
>> @@ -0,0 +1,257 @@
>> +/*
>> + * UFS PHY driver for Samsung EXYNOS SoC
>> + *
>> + * Copyright (C) 2015 Samsung Electronics Co., Ltd.
>> + * Author: Seungwon Jeon
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + */
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include "phy-exynos-ufs.h"
>> +
>> +#define for_each_phy_lane(phy, i) \
>> + for (i = 0; i < (phy)->lane_cnt; i++)
>> +#define for_each_phy_cfg(cfg) \
>> + for (; (cfg)->id; (cfg)++)
>> +
>> +#define PHY_DEF_LANE_CNT 1
>> +
>> +static void exynos_ufs_phy_config(struct exynos_ufs_phy *phy,
>> + const struct exynos_ufs_phy_cfg *cfg, u8 lane)
>> +{
>> + enum {LANE_0, LANE_1}; /* lane index */
>> +
>> + switch (lane) {
>> + case LANE_0:
>> + writel(cfg->val, (phy)->reg_pma + cfg->off_0);
>> + break;
>> + case LANE_1:
>> + if (cfg->id == PHY_TRSV_BLK)
>> + writel(cfg->val, (phy)->reg_pma + cfg->off_1);
>> + break;
>> + }
>> +}
>> +
>> +static bool match_cfg_to_pwr_mode(u8 desc, u8 required_pwr)
>> +{
>> + if (IS_PWR_MODE_ANY(desc))
>> + return true;
>> +
>> + if (IS_PWR_MODE_HS(required_pwr) && IS_PWR_MODE_HS_ANY(desc))
>> + return true;
>> +
>> + if (COMP_PWR_MODE(required_pwr, desc))
>> + return true;
>> +
>> + if (COMP_PWR_MODE_MD(required_pwr, desc) &&
>> + COMP_PWR_MODE_GEAR(required_pwr, desc) &&
>> + COMP_PWR_MODE
Re: [PATCH v4 11/11] scsi: ufs-exynos: add UFS host support for Exynos SoCs
+CCing kishon Vijay,
On 10/14/2015 06:25 PM, Alim Akhtar wrote:
From: Seungwon Jeon
This patch introduces Exynos UFS host controller driver,
which mainly handles vendor-specific operations including
link startup, power mode change and hibernation/unhibernation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/Kconfig | 12 +
drivers/scsi/ufs/Makefile|1 +
drivers/scsi/ufs/ufs-exynos-hw.c | 131
drivers/scsi/ufs/ufs-exynos-hw.h | 43 ++
drivers/scsi/ufs/ufs-exynos.c| 1317 ++
drivers/scsi/ufs/ufs-exynos.h| 247 +++
drivers/scsi/ufs/ufshci.h| 26 +-
drivers/scsi/ufs/unipro.h| 47 ++
8 files changed, 1823 insertions(+), 1 deletion(-)
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
create mode 100644 drivers/scsi/ufs/ufs-exynos.c
create mode 100644 drivers/scsi/ufs/ufs-exynos.h
diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig
index 5f4530744e0a..bc602be94458 100644
--- a/drivers/scsi/ufs/Kconfig
+++ b/drivers/scsi/ufs/Kconfig
@@ -83,3 +83,15 @@ config SCSI_UFS_QCOM
Select this if you have UFS controller on QCOM chipset.
If unsure, say N.
+
+config SCSI_UFS_EXYNOS
+ bool "EXYNOS specific hooks to UFS controller platform driver"
+ depends on SCSI_UFSHCD_PLATFORM && ARCH_EXYNOS || COMPILE_TEST
+ select PHY_EXYNOS_UFS
+ help
+ This selects the EXYNOS specific additions to UFSHCD platform driver.
+ UFS host on EXYNOS includes HCI and UNIPRO layer, and associates with
+ UFS-PHY driver.
+
+ Select this if you have UFS host controller on EXYNOS chipset.
+ If unsure, say N.
diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile
index 8303bcce7a23..2accf1e628b3 100644
--- a/drivers/scsi/ufs/Makefile
+++ b/drivers/scsi/ufs/Makefile
@@ -1,5 +1,6 @@
# UFSHCD makefile
obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o
+obj-$(CONFIG_SCSI_UFS_EXYNOS) += ufs-exynos.o ufs-exynos-hw.o
obj-$(CONFIG_SCSI_UFSHCD) += ufshcd.o
obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o
obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o
diff --git a/drivers/scsi/ufs/ufs-exynos-hw.c b/drivers/scsi/ufs/ufs-exynos-hw.c
new file mode 100644
index ..be6c61541a8f
--- /dev/null
+++ b/drivers/scsi/ufs/ufs-exynos-hw.c
@@ -0,0 +1,131 @@
+/*
+ * UFS Host Controller driver for Exynos specific extensions
+ *
+ * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "ufshcd.h"
+#include "unipro.h"
+
+#include "ufs-exynos.h"
+#include "ufs-exynos-hw.h"
+
+static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
+{
+ struct clk *child, *parent;
+
+ child = devm_clk_get(dev, "ref_clk");
+ if (IS_ERR(child)) {
+ dev_err(dev, "failed to get ref_clk clock\n");
+ return -EINVAL;
+ }
+
+ parent = devm_clk_get(dev, "ref_clk_parent");
+ if (IS_ERR(parent)) {
+ dev_err(dev, "failed to get ref_clk_parent clock\n");
+ return -EINVAL;
+ }
+ return clk_set_parent(child, parent);
+}
+
+static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
+{
+ struct ufs_hba *hba = ufs->hba;
+ u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite;
+ int i;
+
+ exynos_ufs_enable_ov_tm(hba);
+ for_each_ufs_tx_lane(ufs, i)
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17);
+ for_each_ufs_rx_lane(ufs, i) {
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00);
+ }
+ exynos_ufs_disable_ov_tm(hba);
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE_DYN), 0xf);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE_DYN), 0xf);
+ for_each_ufs_tx_lane(ufs, i)
+ ufshcd_dme_set(hba,
+ UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1);
+ udelay(1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12));
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1);
+ udelay(1600);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val);
+
+ return 0;
+}
Re: [PATCH v4 00/11] exynos-ufs: add support for Exynos
A Gentle Reminder !! On 10/14/2015 06:25 PM, Alim Akhtar wrote: This patch-set introduces UFS (Universal Flash Storage) host support for Samsung Exynos SoC. Mostly, it consists of UFS PHY and host specific driver. And it also contains some quirks handling for Exynos. NOTE: ** This series has a dependency on [4]. ** -Changes since v3: * Fixed compilation warrings as reported by "Kbuild Test Robot"[5]. * Restructure the driver to make it as a platform driver, rebased on top of [4]. * Addressed review comments from Arnd Bergmann[5]. * Other misc changes and improvements. -Changes since v2: * Addressed review comments from Kishon[1] and Rob Herring [2] * Splited ufs dt binding documetation from ufs driver patch -Changes since v1: * Addressed review comments from Alexey[3] and various review comments from Amit. * Updated email id of Seungwon as his samsung id is void now. * Added ufs platform data [1]-> https://lkml.org/lkml/2015/9/18/29 [2]-> https://lkml.org/lkml/2015/9/21/668 [3]-> https://lkml.org/lkml/2015/8/23/124 [4]-> https://lkml.org/lkml/2015/9/2/364 [5]-> https://lkml.org/lkml/2015/10/1/402 This patch set is tested on exynos7-espresso board. Alim Akhtar (1): Documentation: samsung-phy: Add dt bindings for UFS Seungwon Jeon (10): phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC scsi: ufs: add quirk to contain unconformable utrd field scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr scsi: ufs: add quirk not to allow reset of interrupt aggregation scsi: ufs: add quirk to enable host controller without hce scsi: ufs: add specific callback for nexus type scsi: ufs: add add specific callback for hibern8 scsi: ufs: make ufshcd_config_pwr_mode of non-static func Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller scsi: ufs-exynos: add UFS host support for Exynos SoCs .../devicetree/bindings/phy/samsung-phy.txt| 22 + .../devicetree/bindings/ufs/ufs-exynos.txt | 104 ++ drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos-ufs.c | 257 drivers/phy/phy-exynos-ufs.h | 88 ++ drivers/phy/phy-exynos7-ufs.h | 89 ++ drivers/scsi/ufs/Kconfig | 12 + drivers/scsi/ufs/Makefile |1 + drivers/scsi/ufs/ufs-exynos-hw.c | 131 ++ drivers/scsi/ufs/ufs-exynos-hw.h | 43 + drivers/scsi/ufs/ufs-exynos.c | 1317 drivers/scsi/ufs/ufs-exynos.h | 247 drivers/scsi/ufs/ufshcd.c | 168 ++- drivers/scsi/ufs/ufshcd.h | 54 + drivers/scsi/ufs/ufshci.h | 26 +- drivers/scsi/ufs/unipro.h | 47 + include/linux/phy/phy-exynos-ufs.h | 101 ++ 18 files changed, 2695 insertions(+), 20 deletions(-) create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt create mode 100644 drivers/phy/phy-exynos-ufs.c create mode 100644 drivers/phy/phy-exynos-ufs.h create mode 100644 drivers/phy/phy-exynos7-ufs.h create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h create mode 100644 drivers/scsi/ufs/ufs-exynos.c create mode 100644 drivers/scsi/ufs/ufs-exynos.h create mode 100644 include/linux/phy/phy-exynos-ufs.h -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 11/11] scsi: ufs-exynos: add UFS host support for Exynos SoCs
Hi Kishon
Thanks again for you review.
On Fri, Oct 23, 2015 at 8:48 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 15 October 2015 08:38 AM, Alim Akhtar wrote:
>> +CCing kishon Vijay,
>>
>> On 10/14/2015 06:25 PM, Alim Akhtar wrote:
>>> From: Seungwon Jeon
>>>
>>> This patch introduces Exynos UFS host controller driver,
>>> which mainly handles vendor-specific operations including
>>> link startup, power mode change and hibernation/unhibernation.
>>>
>>> Signed-off-by: Seungwon Jeon
>>> Signed-off-by: Alim Akhtar
>>> ---
>>> drivers/scsi/ufs/Kconfig | 12 +
>>> drivers/scsi/ufs/Makefile|1 +
>>> drivers/scsi/ufs/ufs-exynos-hw.c | 131
>>> drivers/scsi/ufs/ufs-exynos-hw.h | 43 ++
>>> drivers/scsi/ufs/ufs-exynos.c| 1317
>>> ++
>>> drivers/scsi/ufs/ufs-exynos.h| 247 +++
>>> drivers/scsi/ufs/ufshci.h| 26 +-
>>> drivers/scsi/ufs/unipro.h| 47 ++
>>> 8 files changed, 1823 insertions(+), 1 deletion(-)
>>> create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
>>> create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
>>> create mode 100644 drivers/scsi/ufs/ufs-exynos.c
>>> create mode 100644 drivers/scsi/ufs/ufs-exynos.h
>>>
> .
> .
>
> .
> .
>>> diff --git a/drivers/scsi/ufs/ufs-exynos-hw.c
>>> b/drivers/scsi/ufs/ufs-exynos-hw.c
>>> new file mode 100644
>>> index ..be6c61541a8f
>>> --- /dev/null
>>> +++ b/drivers/scsi/ufs/ufs-exynos-hw.c
>>> @@ -0,0 +1,131 @@
> .
> .
>
> .
> .
>>> +
>>> +#define PWR_MODE_STR_LEN64
>>> +static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba,
>>> +struct ufs_pa_layer_attr *pwr_max,
>>> +struct ufs_pa_layer_attr *pwr_req)
>>> +{
>>> +struct exynos_ufs *ufs = to_exynos_ufs(hba);
>>> +struct exynos_ufs_phy_info *phy_info = phy_get_drvdata(ufs->phy);
>
> This is abusing the interface. phy_get_drvdata is meant to be used only
> by the PHY driver.
>>> +struct exynos_ufs_phy_specific_ops *phy_ops =
>>> +phy_info->phy_specific_ops;
>
> I'm really not happy about having platform specific ops for PHY. We have
> to see if existing PHY ops can be used for this or in worst case add new
> PHY ops.
Well you said you like the controller driver to use only PHY ops[1], I
am sorry If I misunderstood that point, can you please help me to
understand that?
[1]-> https://lkml.org/lkml/2015/9/18/29
>>> +struct uic_pwr_mode *pwr = &ufs->pwr_act;
>>> +char pwr_str[PWR_MODE_STR_LEN] = "";
>>> +int ret = 0;
>>> +
>>> +if (ufs->drv_data->post_pwr_change)
>>> +ufs->drv_data->post_pwr_change(ufs, pwr);
>>> +
>>> +if (IS_UFS_PWR_MODE_HS(pwr->mode)) {
>>> +switch (pwr->hs_series) {
>>> +case PA_HS_MODE_A:
>>> +case PA_HS_MODE_B:
>>> +phy_ops->calibrate_phy(ufs->phy, CFG_POST_PWR_HS,
>>> +PWR_MODE_HS(pwr->gear, pwr->hs_series));
>>> +break;
>>> +}
>>> +
>>> +ret = phy_ops->wait_for_lock_acq(ufs->phy);
>>> +snprintf(pwr_str, sizeof(pwr_str), "Fast%s series_%s G_%d L_%d",
>>> +pwr->mode == FASTAUTO_MODE ? "_Auto" : "",
>>> +pwr->hs_series == PA_HS_MODE_A ? "A" : "B",
>>> +pwr->gear, pwr->lane);
>>> +} else if (IS_UFS_PWR_MODE_PWM(pwr->mode)) {
>>> +snprintf(pwr_str, sizeof(pwr_str), "Slow%s G_%d L_%d",
>>> +pwr->mode == SLOWAUTO_MODE ? "_Auto" : "",
>>> +pwr->gear, pwr->lane);
>>> +}
>>> +
>>> +dev_info(hba->dev, "Power mode change %d : %s\n", ret, pwr_str);
>>> +return ret;
>>> +}
>>> +
>>> +static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba,
>>> +int tag, struct scsi_cmnd *cmd)
>>> +{
>>> +struct exynos_ufs *ufs = to_exynos_ufs(hba);
>>> +u32 type;
>>> +
>>> +type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE);
>>> +
>>> +if (cmd)
>>> +hci_writel(ufs, type | (1 <
Re: [PATCH v9 0/8] Fix error message and present UFS variant
Hi Yaniv, On Wed, Oct 28, 2015 at 4:45 PM, Yaniv Gardi wrote: > V9: update commit message with Reviewed-by > and update commit message of patch 4/8 > > V8: add phy attributes to UFS devicetree documentation file > > V7: removed additional dead code > > V6: removed dead code from ufs-qcom.c and added > calling to ufshcd_dealloc_host() in ufshcd-pltfrm.c in case > of an error after a successfull ufshcd_alloc_host() > > V5: removed a redundant null check > > V4: add file > Documentation/devicetree/bindings/ufs/ufs-qcom.txt > and modify the compatible strings in > Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt > > V3: fixes a few minor issues. > > V2: fixes a few issues of unnecessary EXPORT_SYMBOL, > types of parameters in routine definition, > build errors in case CONFIG_PM is not defined and some > other minor fixes. > > Yaniv Gardi (8): > phy: qcom-ufs: fix build error when the component is built as a module > scsi: ufs-qcom: fix compilation warning if compiled as a module > scsi: ufs-qcom: update configuration option of SCSI_UFS_QCOM component > scsi: ufs: add ufshcd_get_variant ufshcd_set_variant > scsi: ufs: creates wrapper functions for vops > scsi: ufs: make the UFS variant a platform device for patch 4 ~ 6, ufshcd bits, have tested on a exynos variant, so feel free to add Tested-by: Alim Akhtar > scsi: ufs-qcom: add debug prints for test bus > scsi: ufs-qcom: add QUniPro hardware support and power optimizations > > Documentation/devicetree/bindings/ufs/ufs-qcom.txt | 58 ++ > .../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 11 +- > drivers/phy/phy-qcom-ufs.c | 11 + > drivers/scsi/ufs/Kconfig | 2 +- > drivers/scsi/ufs/ufs-qcom.c| 905 > - > drivers/scsi/ufs/ufs-qcom.h| 68 +- > drivers/scsi/ufs/ufshcd-pltfrm.c | 98 +-- > drivers/scsi/ufs/ufshcd-pltfrm.h | 41 + > drivers/scsi/ufs/ufshcd.c | 122 ++- > drivers/scsi/ufs/ufshcd.h | 149 +++- > 10 files changed, 1127 insertions(+), 338 deletions(-) > create mode 100644 Documentation/devicetree/bindings/ufs/ufs-qcom.txt > create mode 100644 drivers/scsi/ufs/ufshcd-pltfrm.h > > -- > 1.8.5.2 > > -- > QUALCOMM ISRAEL, on behalf of Qualcomm Innovation Center, Inc. is a member of > Code Aurora Forum, hosted by The Linux Foundation > -- > To unsubscribe from this list: send the line "unsubscribe linux-scsi" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- Regards, Alim -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 11/11] scsi: ufs-exynos: add UFS host support for Exynos SoCs
Hi Kishon,
Thanks for your time.
On 10/28/2015 06:23 PM, Kishon Vijay Abraham I wrote:
Hi,
On Sunday 25 October 2015 05:34 PM, Alim Akhtar wrote:
Hi Kishon
Thanks again for you review.
On Fri, Oct 23, 2015 at 8:48 PM, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 15 October 2015 08:38 AM, Alim Akhtar wrote:
+CCing kishon Vijay,
On 10/14/2015 06:25 PM, Alim Akhtar wrote:
From: Seungwon Jeon
This patch introduces Exynos UFS host controller driver,
which mainly handles vendor-specific operations including
link startup, power mode change and hibernation/unhibernation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/Kconfig | 12 +
drivers/scsi/ufs/Makefile|1 +
drivers/scsi/ufs/ufs-exynos-hw.c | 131
drivers/scsi/ufs/ufs-exynos-hw.h | 43 ++
drivers/scsi/ufs/ufs-exynos.c| 1317
++
drivers/scsi/ufs/ufs-exynos.h| 247 +++
drivers/scsi/ufs/ufshci.h| 26 +-
drivers/scsi/ufs/unipro.h| 47 ++
8 files changed, 1823 insertions(+), 1 deletion(-)
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
create mode 100644 drivers/scsi/ufs/ufs-exynos.c
create mode 100644 drivers/scsi/ufs/ufs-exynos.h
.
.
.
.
diff --git a/drivers/scsi/ufs/ufs-exynos-hw.c
b/drivers/scsi/ufs/ufs-exynos-hw.c
new file mode 100644
index ..be6c61541a8f
--- /dev/null
+++ b/drivers/scsi/ufs/ufs-exynos-hw.c
@@ -0,0 +1,131 @@
.
.
.
.
+
+#define PWR_MODE_STR_LEN64
+static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba,
+struct ufs_pa_layer_attr *pwr_max,
+struct ufs_pa_layer_attr *pwr_req)
+{
+struct exynos_ufs *ufs = to_exynos_ufs(hba);
+struct exynos_ufs_phy_info *phy_info = phy_get_drvdata(ufs->phy);
This is abusing the interface. phy_get_drvdata is meant to be used only
by the PHY driver.
+struct exynos_ufs_phy_specific_ops *phy_ops =
+phy_info->phy_specific_ops;
I'm really not happy about having platform specific ops for PHY. We have
to see if existing PHY ops can be used for this or in worst case add new
PHY ops.
Well you said you like the controller driver to use only PHY ops[1], I
am sorry If I misunderstood that point, can you please help me to
understand that?
I meant PHY generic ops and not PHY ops.
Ok, got it, will use only generic phy here in controller driver.
- Will remove the platform specific PHY ops from phy driver introduce in
this series (patch 02/11)
[1]-> https://lkml.org/lkml/2015/9/18/29
+struct uic_pwr_mode *pwr = &ufs->pwr_act;
+char pwr_str[PWR_MODE_STR_LEN] = "";
+int ret = 0;
+
+if (ufs->drv_data->post_pwr_change)
+ufs->drv_data->post_pwr_change(ufs, pwr);
+
+if (IS_UFS_PWR_MODE_HS(pwr->mode)) {
+switch (pwr->hs_series) {
+case PA_HS_MODE_A:
+case PA_HS_MODE_B:
+phy_ops->calibrate_phy(ufs->phy, CFG_POST_PWR_HS,
+PWR_MODE_HS(pwr->gear, pwr->hs_series));
+break;
+}
+
+ret = phy_ops->wait_for_lock_acq(ufs->phy);
+snprintf(pwr_str, sizeof(pwr_str), "Fast%s series_%s G_%d L_%d",
+pwr->mode == FASTAUTO_MODE ? "_Auto" : "",
+pwr->hs_series == PA_HS_MODE_A ? "A" : "B",
+pwr->gear, pwr->lane);
+} else if (IS_UFS_PWR_MODE_PWM(pwr->mode)) {
+snprintf(pwr_str, sizeof(pwr_str), "Slow%s G_%d L_%d",
+pwr->mode == SLOWAUTO_MODE ? "_Auto" : "",
+pwr->gear, pwr->lane);
+}
+
+dev_info(hba->dev, "Power mode change %d : %s\n", ret, pwr_str);
+return ret;
+}
+
+static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba,
+int tag, struct scsi_cmnd *cmd)
+{
+struct exynos_ufs *ufs = to_exynos_ufs(hba);
+u32 type;
+
+type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE);
+
+if (cmd)
+hci_writel(ufs, type | (1 << tag), HCI_UTRL_NEXUS_TYPE);
+else
+hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE);
+}
+
+static void exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba *hba,
+int tag, u8 func)
+{
+struct exynos_ufs *ufs = to_exynos_ufs(hba);
+u32 type;
+
+type = hci_readl(ufs, HCI_UTMRL_NEXUS_TYPE);
+
+switch (func) {
+case UFS_ABORT_TASK:
+case UFS_QUERY_TASK:
+hci_writel(ufs, type | (1 << tag), HCI_UTMRL_NEXUS_TYPE);
+break;
+case UFS_ABORT_TASK_SET:
+case UFS_CLEAR_TASK_SET:
+case UFS_LOGICAL_RESET:
+case UFS_QUERY_TASK_SET:
+hci_writel(ufs, type & ~(1 << tag), HCI_UTMRL_NEXUS_TYPE);
+break;
+}
+}
+
+static void exynos_ufs_phy_init(struct exynos_ufs
[PATCH v5 01/11] Documentation: samsung-phy: Add dt bindings for UFS
Adds exynos UFS PHY device tree bindings information.
Signed-off-by: Alim Akhtar
---
.../devicetree/bindings/phy/samsung-phy.txt| 22
1 file changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 0289d3b07853..565200d72e91 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -177,3 +177,25 @@ Example:
usbdrdphy0 = &usb3_phy0;
usbdrdphy1 = &usb3_phy1;
};
+
+Samsung Exynos7 soc series UFS PHY Controller
+-
+
+UFS PHY nodes are defined to describe on-chip UFS Physical layer controllers.
+Each UFS PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible should be set to "samsung,exynos7-ufs-phy"
+- reg : offset and length of the UFS PHY register set
+- reg-names : reg name(s) must be 'phy-pma'
+- #phy-cells : must be zero
+- samsung,pmu-syscon : a phandle to the PMU system controller, no arguments
+
+Example:
+ ufs_phy: ufs-phy@0x15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ };
--
1.7.10.4
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[PATCH v5 00/11] exynos-ufs: add support for Exynos
This patch-set introduces UFS (Universal Flash Storage) host support
for Samsung Exynos SoC. Mostly, it consists of UFS PHY and host specific driver.
And it also contains some quirks handling for Exynos.
NOTE: ** This series has a dependency on [4]. **
-Changes since v4:
* Removed platform specific PHY ops as suggested by Kishon
* Rebased on the top of Yaniv Gardi's work [4]
* make use of newly introduce ufshcd_{get,set}_variant
* other small changes and improvements.
* rebased on the top of linux next-20151109
-Changes since v3:
* Fixed compilation warrings as reported by "Kbuild Test Robot"[5].
* Restructure the driver to make it as a platform driver, rebased on top of [4].
* Addressed review comments from Arnd Bergmann[5].
* Other misc changes and improvements.
-Changes since v2:
* Addressed review comments from Kishon[1] and Rob Herring [2]
* Splited ufs dt binding documetation from ufs driver patch
-Changes since v1:
* Addressed review comments from Alexey[3] and various review comments from
Amit.
* Updated email id of Seungwon as his samsung id is void now.
* Added ufs platform data
[1]-> https://lkml.org/lkml/2015/9/18/29
[2]-> https://lkml.org/lkml/2015/9/21/668
[3]-> https://lkml.org/lkml/2015/8/23/124
[4]-> https://lkml.org/lkml/2015/10/28/271
[5]-> https://lkml.org/lkml/2015/10/1/402
This patch set is tested on exynos7-espresso board.
Alim Akhtar (1):
Documentation: samsung-phy: Add dt bindings for UFS
Seungwon Jeon (10):
phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
scsi: ufs: add quirk to contain unconformable utrd field
scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
scsi: ufs: add quirk not to allow reset of interrupt aggregation
scsi: ufs: add quirk to enable host controller without hce
scsi: ufs: add specific callback for nexus type
scsi: ufs: add add specific callback for hibern8
scsi: ufs: make ufshcd_config_pwr_mode of non-static func
Documentation: devicetree: ufs: Add DT bindings for exynos UFS host
controller
scsi: ufs-exynos: add UFS host support for Exynos SoCs
.../devicetree/bindings/phy/samsung-phy.txt| 22 +
.../devicetree/bindings/ufs/ufs-exynos.txt | 104 ++
drivers/phy/Kconfig|7 +
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos-ufs.c | 241
drivers/phy/phy-exynos-ufs.h | 85 ++
drivers/phy/phy-exynos7-ufs.h | 89 ++
drivers/scsi/ufs/Kconfig | 12 +
drivers/scsi/ufs/Makefile |1 +
drivers/scsi/ufs/ufs-exynos-hw.c | 131 ++
drivers/scsi/ufs/ufs-exynos-hw.h | 43 +
drivers/scsi/ufs/ufs-exynos.c | 1304
drivers/scsi/ufs/ufs-exynos.h | 247
drivers/scsi/ufs/ufshcd.c | 168 ++-
drivers/scsi/ufs/ufshcd.h | 54 +
drivers/scsi/ufs/ufshci.h | 26 +-
drivers/scsi/ufs/unipro.h | 47 +
include/linux/phy/phy-exynos-ufs.h | 85 ++
18 files changed, 2647 insertions(+), 20 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
create mode 100644 drivers/phy/phy-exynos-ufs.c
create mode 100644 drivers/phy/phy-exynos-ufs.h
create mode 100644 drivers/phy/phy-exynos7-ufs.h
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
create mode 100644 drivers/scsi/ufs/ufs-exynos.c
create mode 100644 drivers/scsi/ufs/ufs-exynos.h
create mode 100644 include/linux/phy/phy-exynos-ufs.h
--
1.7.10.4
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[PATCH v5 02/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
From: Seungwon Jeon
This patch introduces Exynos UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
---
drivers/phy/Kconfig|7 ++
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos-ufs.c | 241
drivers/phy/phy-exynos-ufs.h | 85 +
drivers/phy/phy-exynos7-ufs.h | 89 +
include/linux/phy/phy-exynos-ufs.h | 85 +
6 files changed, 508 insertions(+)
create mode 100644 drivers/phy/phy-exynos-ufs.c
create mode 100644 drivers/phy/phy-exynos-ufs.h
create mode 100644 drivers/phy/phy-exynos7-ufs.h
create mode 100644 include/linux/phy/phy-exynos-ufs.h
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 7eb5859dd035..7d38a92e0297 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -389,4 +389,11 @@ config PHY_CYGNUS_PCIE
Enable this to support the Broadcom Cygnus PCIe PHY.
If unsure, say N.
+config PHY_EXYNOS_UFS
+ tristate "EXYNOS SoC series UFS PHY driver"
+ depends on OF && ARCH_EXYNOS || COMPILE_TEST
+ select GENERIC_PHY
+ help
+ Support for UFS PHY on Samsung EXYNOS chipsets.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 075db1a81aa5..9bec4d1a89e1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY)+=
phy-armada375-usb2.o
obj-$(CONFIG_BCM_KONA_USB2_PHY)+= phy-bcm-kona-usb2.o
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
+obj-$(CONFIG_PHY_EXYNOS_UFS) += phy-exynos-ufs.o
obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
obj-$(CONFIG_PHY_PXA_28NM_USB2)+= phy-pxa-28nm-usb2.o
obj-$(CONFIG_PHY_PXA_28NM_HSIC)+= phy-pxa-28nm-hsic.o
diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
new file mode 100644
index ..cb1aeaa3d4eb
--- /dev/null
+++ b/drivers/phy/phy-exynos-ufs.c
@@ -0,0 +1,241 @@
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "phy-exynos-ufs.h"
+
+#define for_each_phy_lane(phy, i) \
+ for (i = 0; i < (phy)->lane_cnt; i++)
+#define for_each_phy_cfg(cfg) \
+ for (; (cfg)->id; (cfg)++)
+
+#define PHY_DEF_LANE_CNT 1
+
+static void exynos_ufs_phy_config(struct exynos_ufs_phy *phy,
+ const struct exynos_ufs_phy_cfg *cfg, u8 lane)
+{
+ enum {LANE_0, LANE_1}; /* lane index */
+
+ switch (lane) {
+ case LANE_0:
+ writel(cfg->val, (phy)->reg_pma + cfg->off_0);
+ break;
+ case LANE_1:
+ if (cfg->id == PHY_TRSV_BLK)
+ writel(cfg->val, (phy)->reg_pma + cfg->off_1);
+ break;
+ }
+}
+
+static bool match_cfg_to_pwr_mode(u8 desc, u8 required_pwr)
+{
+ if (IS_PWR_MODE_ANY(desc))
+ return true;
+
+ if (IS_PWR_MODE_HS(required_pwr) && IS_PWR_MODE_HS_ANY(desc))
+ return true;
+
+ if (COMP_PWR_MODE(required_pwr, desc))
+ return true;
+
+ if (COMP_PWR_MODE_MD(required_pwr, desc) &&
+ COMP_PWR_MODE_GEAR(required_pwr, desc) &&
+ COMP_PWR_MODE_SER(required_pwr, desc))
+ return true;
+
+ return false;
+}
+
+int exynos_ufs_phy_calibrate(struct phy *phy,
+ enum phy_cfg_tag tag, u8 pwr)
+{
+ struct exynos_ufs_phy *ufs_phy = get_exynos_ufs_phy(phy);
+ struct exynos_ufs_phy_cfg **cfgs = ufs_phy->cfg;
+ const struct exynos_ufs_phy_cfg *cfg;
+ int i;
+
+ if (unlikely(tag < CFG_PRE_INIT || tag >= CFG_TAG_MAX)) {
+ dev_err(ufs_phy->dev, "invalid phy config index %d\n", tag);
+ return -EINVAL;
+ }
+
+ cfg = cfgs[tag];
+ if (!cfg)
+ goto out;
+
+ for_each_phy_cfg(cfg) {
+ for_each_phy_lane(ufs_phy, i) {
+ if (match_cfg_to_pwr_mode(cfg->desc, pwr))
+ exynos_ufs_phy_config(ufs_phy, cfg, i);
+ }
+ }
+
+out:
+ return 0;
+}
+
+void exynos_u
[PATCH v5 03/11] scsi: ufs: add quirk to contain unconformable utrd field
From: Seungwon Jeon
UTRD(UTP Transfer Request Descriptor)'s field such as offset/length,
especially response's has DWORD expression. This quirk can be specified
for host controller not to conform standard.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 28 +---
drivers/scsi/ufs/ufshcd.h |7 +++
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 131c72038bf8..587a9c8fbfe9 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1009,7 +1009,7 @@ ufshcd_send_uic_cmd(struct ufs_hba *hba, struct
uic_command *uic_cmd)
*
* Returns 0 in case of success, non-zero value in case of failure
*/
-static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
+static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
{
struct ufshcd_sg_entry *prd_table;
struct scatterlist *sg;
@@ -1023,8 +1023,13 @@ static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
return sg_segments;
if (sg_segments) {
- lrbp->utr_descriptor_ptr->prd_table_length =
- cpu_to_le16((u16) (sg_segments));
+ if (hba->quirks & UFSHCI_QUIRK_BYTE_ALIGN_UTRD)
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16)(sg_segments *
+ sizeof(struct ufshcd_sg_entry)));
+ else
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16) (sg_segments));
prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
@@ -1347,7 +1352,7 @@ static int ufshcd_queuecommand(struct Scsi_Host *host,
struct scsi_cmnd *cmd)
/* form UPIU before issuing the command */
ufshcd_compose_upiu(hba, lrbp);
- err = ufshcd_map_sg(lrbp);
+ err = ufshcd_map_sg(hba, lrbp);
if (err) {
lrbp->cmd = NULL;
clear_bit_unlock(tag, &hba->lrb_in_use);
@@ -2034,13 +2039,22 @@ static void ufshcd_host_memory_configure(struct ufs_hba
*hba)
utrdlp[i].command_desc_base_addr_hi =
cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
+ if (hba->quirks & UFSHCI_QUIRK_BYTE_ALIGN_UTRD) {
+ utrdlp[i].response_upiu_offset =
+ cpu_to_le16(response_offset);
+ utrdlp[i].prd_table_offset =
+ cpu_to_le16(prdt_offset);
+ utrdlp[i].response_upiu_length =
+ cpu_to_le16(ALIGNED_UPIU_SIZE);
+ } else {
/* Response upiu and prdt offset should be in double words */
- utrdlp[i].response_upiu_offset =
+ utrdlp[i].response_upiu_offset =
cpu_to_le16((response_offset >> 2));
- utrdlp[i].prd_table_offset =
+ utrdlp[i].prd_table_offset =
cpu_to_le16((prdt_offset >> 2));
- utrdlp[i].response_upiu_length =
+ utrdlp[i].response_upiu_length =
cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
+ }
hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
hba->lrb[i].ucd_req_ptr =
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 2570d9477b37..6cd542a803d5 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -467,6 +467,13 @@ struct ufs_hba {
*/
#define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION UFS_BIT(5)
+ /*
+* This quirk needs to be enabled if host controller doesn't conform
+* with UTRD. Some fields such as offset/length might not be in double
+* word, but in byte.
+*/
+ #define UFSHCI_QUIRK_BYTE_ALIGN_UTRDUFS_BIT(6)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v5 04/11] scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
From: Seungwon Jeon
In the right behavior, setting the bit to '0' indicates clear and
'1' indicates no change. If host contoller handles this the other way,
UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR can be used.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 21 +++--
drivers/scsi/ufs/ufshcd.h |5 +
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 587a9c8fbfe9..2b16eb363203 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -356,7 +356,24 @@ static inline void ufshcd_put_tm_slot(struct ufs_hba *hba,
int slot)
*/
static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
{
- ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos),
+ REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+}
+
+/**
+ * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
+ * @hba: per adapter instance
+ * @pos: position of the bit to be cleared
+ */
+static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
+{
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
}
/**
@@ -3685,7 +3702,7 @@ static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int
tag)
goto out;
spin_lock_irqsave(hba->host->host_lock, flags);
- ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
+ ufshcd_utmrl_clear(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
/* poll for max. 1 sec to clear door bell register by h/w */
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 6cd542a803d5..d625d01110b0 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -474,6 +474,11 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_BYTE_ALIGN_UTRDUFS_BIT(6)
+ /*
+* Cleaer handling for transfer/task request list is just opposite.
+*/
+ #define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLRUFS_BIT(7)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v5 05/11] scsi: ufs: add quirk not to allow reset of interrupt aggregation
From: Seungwon Jeon
Some host controller supports interrupt aggregation, but doesn't
allow to reset counter and timer by s/w.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |3 ++-
drivers/scsi/ufs/ufshcd.h |6 ++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 2b16eb363203..ca7483cd899e 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -3199,7 +3199,8 @@ static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
* false interrupt if device completes another request after resetting
* aggregation and before reading the DB.
*/
- if (ufshcd_is_intr_aggr_allowed(hba))
+ if (ufshcd_is_intr_aggr_allowed(hba) &&
+ !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
ufshcd_reset_intr_aggr(hba);
tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index d625d01110b0..4ae32e9316de 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -479,6 +479,12 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLRUFS_BIT(7)
+ /*
+* This quirk needs to be enabled if host controller doesn't allow
+* that the interrupt aggregation timer and counter are reset by s/w.
+*/
+ #define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR UFS_BIT(8)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v5 07/11] scsi: ufs: add specific callback for nexus type
From: Seungwon Jeon
Some host controller needs nexus type information for handling
command. This change adds specific callback function to support
vendor's implementation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |3 +++
drivers/scsi/ufs/ufshcd.h | 19 +++
2 files changed, 22 insertions(+)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index e8b96ec65987..eeb7835c52ab 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1378,6 +1378,7 @@ static int ufshcd_queuecommand(struct Scsi_Host *host,
struct scsi_cmnd *cmd)
/* issue command to the controller */
spin_lock_irqsave(hba->host->host_lock, flags);
+ ufshcd_vops_specify_nexus_t_xfer_req(hba, tag, lrbp);
ufshcd_send_command(hba, tag);
out_unlock:
spin_unlock_irqrestore(hba->host->host_lock, flags);
@@ -1578,6 +1579,7 @@ static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
hba->dev_cmd.complete = &wait;
spin_lock_irqsave(hba->host->host_lock, flags);
+ ufshcd_vops_specify_nexus_t_xfer_req(hba, tag, lrbp);
ufshcd_send_command(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
@@ -3842,6 +3844,7 @@ static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int
lun_id, int task_id,
task_req_upiup->input_param2 = cpu_to_be32(task_id);
/* send command to the controller */
+ ufshcd_vops_specify_nexus_t_tm_req(hba, free_slot, tm_function);
__set_bit(free_slot, &hba->outstanding_tasks);
ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 500e137bf68a..b3dd08420100 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -259,6 +259,9 @@ struct ufs_pwr_mode_info {
* @pwr_change_notify: called before and after a power mode change
* is carried out to allow vendor spesific capabilities
* to be set.
+ * @specify_nexus_t_xfer_req:
+ * @specify_nexus_t_tm_req: called before command is issued to allow vendor
+ * specific handling to be set for nexus type.
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
* @dbg_register_dump: used to dump controller debug information
@@ -280,6 +283,9 @@ struct ufs_hba_variant_ops {
enum ufs_notify_change_status status,
struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+ void(*specify_nexus_t_xfer_req)(struct ufs_hba *,
+ int, struct scsi_cmnd *);
+ void(*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
int (*resume)(struct ufs_hba *, enum ufs_pm_op);
void(*dbg_register_dump)(struct ufs_hba *hba);
@@ -811,4 +817,17 @@ static inline void ufshcd_vops_dbg_register_dump(struct
ufs_hba *hba)
hba->vops->dbg_register_dump(hba);
}
+static inline void ufshcd_vops_specify_nexus_t_xfer_req(struct ufs_hba *hba,
+ int tag, struct ufshcd_lrb *lrbp)
+{
+ if (hba->vops && hba->vops->specify_nexus_t_xfer_req)
+ hba->vops->specify_nexus_t_xfer_req(hba, tag, lrbp->cmd);
+}
+
+static inline void ufshcd_vops_specify_nexus_t_tm_req(struct ufs_hba *hba,
+ int free_slot, u8 tm_function)
+{
+ if (hba->vops && hba->vops->specify_nexus_t_tm_req)
+ hba->vops->specify_nexus_t_tm_req(hba, free_slot, tm_function);
+}
#endif /* End of Header */
--
1.7.10.4
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[PATCH v5 06/11] scsi: ufs: add quirk to enable host controller without hce
From: Seungwon Jeon
Some host controller doesn't support host controller enable via HCE.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 75 +++--
drivers/scsi/ufs/ufshcd.h |5 +++
2 files changed, 78 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index ca7483cd899e..e8b96ec65987 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2107,6 +2107,52 @@ static int ufshcd_dme_link_startup(struct ufs_hba *hba)
"dme-link-startup: error code %d\n", ret);
return ret;
}
+/**
+ * ufshcd_dme_reset - UIC command for DME_RESET
+ * @hba: per adapter instance
+ *
+ * DME_RESET command is issued in order to reset UniPro stack.
+ * This function now deal with cold reset.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_reset(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_RESET;
+
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
+
+/**
+ * ufshcd_dme_enable - UIC command for DME_ENABLE
+ * @hba: per adapter instance
+ *
+ * DME_ENABLE command is issued in order to enable UniPro stack.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_enable(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_ENABLE;
+
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
{
@@ -2642,7 +2688,7 @@ out:
}
/**
- * ufshcd_hba_enable - initialize the controller
+ * ufshcd_hba_execute_hce - initialize the controller
* @hba: per adapter instance
*
* The controller resets itself and controller firmware initialization
@@ -2651,7 +2697,7 @@ out:
*
* Returns 0 on success, non-zero value on failure
*/
-static int ufshcd_hba_enable(struct ufs_hba *hba)
+static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
{
int retry;
@@ -2715,6 +2761,31 @@ static int ufshcd_hba_enable(struct ufs_hba *hba)
return 0;
}
+static int ufshcd_hba_enable(struct ufs_hba *hba)
+{
+ int ret;
+
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
+ ufshcd_set_link_off(hba);
+ ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
+
+ /* enable UIC related interrupts */
+ ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
+ ret = ufshcd_dme_reset(hba);
+ if (!ret) {
+ ret = ufshcd_dme_enable(hba);
+ if (!ret)
+ ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
+ if (ret)
+ dev_err(hba->dev,
+ "Host controller enable failed with
non-hce\n");
+ }
+ } else {
+ ret = ufshcd_hba_execute_hce(hba);
+ }
+
+ return ret;
+}
static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
{
int tx_lanes, i, err = 0;
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 4ae32e9316de..500e137bf68a 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -485,6 +485,11 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR UFS_BIT(8)
+ /*
+* This quirks needs to be enabled if host controller cannot be
+* enabled via HCE register.
+*/
+ #define UFSHCI_QUIRK_BROKEN_HCE UFS_BIT(9)
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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[PATCH v5 09/11] scsi: ufs: make ufshcd_config_pwr_mode of non-static func
From: Seungwon Jeon
This makes ufshcd_config_pwr_mode non-static so that other vendors
like exynos can use the same.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c |5 ++---
drivers/scsi/ufs/ufshcd.h |2 ++
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 075b7bf13080..358d9114a1a5 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -185,8 +185,6 @@ static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba,
bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
- struct ufs_pa_layer_attr *desired_pwr_mode);
static int ufshcd_change_power_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *pwr_mode);
@@ -2592,7 +2590,7 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
* @hba: per-adapter instance
* @desired_pwr_mode: desired power configuration
*/
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+int ufshcd_config_pwr_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *desired_pwr_mode)
{
struct ufs_pa_layer_attr final_params = { 0 };
@@ -2608,6 +2606,7 @@ static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
return ret;
}
+EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
/**
* ufshcd_complete_dev_init() - checks device readiness
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 9c69dd2f3672..8cad52c072d4 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -666,6 +666,8 @@ extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32
attr_sel,
u8 attr_set, u32 mib_val, u8 peer);
extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
u32 *mib_val, u8 peer);
+extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+ struct ufs_pa_layer_attr *desired_pwr_mode);
/* UIC command interfaces for DME primitives */
#define DME_LOCAL 0
--
1.7.10.4
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[PATCH v5 11/11] scsi: ufs-exynos: add UFS host support for Exynos SoCs
From: Seungwon Jeon
This patch introduces Exynos UFS host controller driver,
which mainly handles vendor-specific operations including
link startup, power mode change and hibernation/unhibernation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/Kconfig | 12 +
drivers/scsi/ufs/Makefile|1 +
drivers/scsi/ufs/ufs-exynos-hw.c | 131
drivers/scsi/ufs/ufs-exynos-hw.h | 43 ++
drivers/scsi/ufs/ufs-exynos.c| 1304 ++
drivers/scsi/ufs/ufs-exynos.h| 247
drivers/scsi/ufs/ufshci.h| 26 +-
drivers/scsi/ufs/unipro.h| 47 ++
8 files changed, 1810 insertions(+), 1 deletion(-)
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
create mode 100644 drivers/scsi/ufs/ufs-exynos.c
create mode 100644 drivers/scsi/ufs/ufs-exynos.h
diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig
index 5f4530744e0a..bc602be94458 100644
--- a/drivers/scsi/ufs/Kconfig
+++ b/drivers/scsi/ufs/Kconfig
@@ -83,3 +83,15 @@ config SCSI_UFS_QCOM
Select this if you have UFS controller on QCOM chipset.
If unsure, say N.
+
+config SCSI_UFS_EXYNOS
+ bool "EXYNOS specific hooks to UFS controller platform driver"
+ depends on SCSI_UFSHCD_PLATFORM && ARCH_EXYNOS || COMPILE_TEST
+ select PHY_EXYNOS_UFS
+ help
+ This selects the EXYNOS specific additions to UFSHCD platform driver.
+ UFS host on EXYNOS includes HCI and UNIPRO layer, and associates with
+ UFS-PHY driver.
+
+ Select this if you have UFS host controller on EXYNOS chipset.
+ If unsure, say N.
diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile
index 8303bcce7a23..2accf1e628b3 100644
--- a/drivers/scsi/ufs/Makefile
+++ b/drivers/scsi/ufs/Makefile
@@ -1,5 +1,6 @@
# UFSHCD makefile
obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o
+obj-$(CONFIG_SCSI_UFS_EXYNOS) += ufs-exynos.o ufs-exynos-hw.o
obj-$(CONFIG_SCSI_UFSHCD) += ufshcd.o
obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o
obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o
diff --git a/drivers/scsi/ufs/ufs-exynos-hw.c b/drivers/scsi/ufs/ufs-exynos-hw.c
new file mode 100644
index ..be6c61541a8f
--- /dev/null
+++ b/drivers/scsi/ufs/ufs-exynos-hw.c
@@ -0,0 +1,131 @@
+/*
+ * UFS Host Controller driver for Exynos specific extensions
+ *
+ * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "ufshcd.h"
+#include "unipro.h"
+
+#include "ufs-exynos.h"
+#include "ufs-exynos-hw.h"
+
+static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
+{
+ struct clk *child, *parent;
+
+ child = devm_clk_get(dev, "ref_clk");
+ if (IS_ERR(child)) {
+ dev_err(dev, "failed to get ref_clk clock\n");
+ return -EINVAL;
+ }
+
+ parent = devm_clk_get(dev, "ref_clk_parent");
+ if (IS_ERR(parent)) {
+ dev_err(dev, "failed to get ref_clk_parent clock\n");
+ return -EINVAL;
+ }
+ return clk_set_parent(child, parent);
+}
+
+static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
+{
+ struct ufs_hba *hba = ufs->hba;
+ u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite;
+ int i;
+
+ exynos_ufs_enable_ov_tm(hba);
+ for_each_ufs_tx_lane(ufs, i)
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17);
+ for_each_ufs_rx_lane(ufs, i) {
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00);
+ }
+ exynos_ufs_disable_ov_tm(hba);
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE_DYN), 0xf);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE_DYN), 0xf);
+ for_each_ufs_tx_lane(ufs, i)
+ ufshcd_dme_set(hba,
+ UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1);
+ udelay(1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12));
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1);
+ udelay(1600);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val);
+
+ return 0;
+}
+
+static int exynos7_ufs_post_link(struct exynos_ufs *ufs)
+{
+ struct
[PATCH v5 08/11] scsi: ufs: add add specific callback for hibern8
From: Seungwon Jeon
Some host controller needs specific handling before/after
(un)hibernation, This change adds specific callback function
to support vendor's implementation.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 33 +
drivers/scsi/ufs/ufshcd.h | 10 ++
2 files changed, 39 insertions(+), 4 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index eeb7835c52ab..075b7bf13080 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -181,8 +181,7 @@ static int ufshcd_probe_hba(struct ufs_hba *hba);
static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
bool skip_ref_clk);
static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
@@ -215,6 +214,16 @@ static inline void ufshcd_disable_irq(struct ufs_hba *hba)
}
}
+static inline int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, true);
+}
+
+static inline int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, false);
+}
+
/*
* ufshcd_wait_for_register - wait for register value to change
* @hba - per-adapter interface
@@ -2394,7 +2403,7 @@ out:
return ret;
}
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
@@ -2403,7 +2412,7 @@ static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
return ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
}
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
int ret;
@@ -2418,6 +2427,22 @@ static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
return ret;
}
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en)
+{
+ int ret;
+
+ ufshcd_vops_hibern8_notify(hba, en, PRE_CHANGE);
+ ret = en ? __ufshcd_uic_hibern8_enter(hba) :
+ __ufshcd_uic_hibern8_exit(hba);
+ if (ret)
+ goto out;
+
+ ufshcd_vops_hibern8_notify(hba, en, POST_CHANGE);
+
+out:
+ return ret;
+}
+
/**
* ufshcd_init_pwr_info - setting the POR (power on reset)
* values in hba power info
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index b3dd08420100..9c69dd2f3672 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -262,6 +262,8 @@ struct ufs_pwr_mode_info {
* @specify_nexus_t_xfer_req:
* @specify_nexus_t_tm_req: called before command is issued to allow vendor
* specific handling to be set for nexus type.
+ * @hibern8_notify: called before and after hibernate/unhibernate is carried
out
+ * to allow vendor spesific implementation.
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
* @dbg_register_dump: used to dump controller debug information
@@ -283,6 +285,7 @@ struct ufs_hba_variant_ops {
enum ufs_notify_change_status status,
struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+ void(*hibern8_notify)(struct ufs_hba *, bool, bool);
void(*specify_nexus_t_xfer_req)(struct ufs_hba *,
int, struct scsi_cmnd *);
void(*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
@@ -830,4 +833,11 @@ static inline void
ufshcd_vops_specify_nexus_t_tm_req(struct ufs_hba *hba,
if (hba->vops && hba->vops->specify_nexus_t_tm_req)
hba->vops->specify_nexus_t_tm_req(hba, free_slot, tm_function);
}
+
+static inline void ufshcd_vops_hibern8_notify(struct ufs_hba *hba,
+ bool en, enum ufs_notify_change_status status)
+{
+ if (hba->vops && hba->vops->hibern8_notify)
+ hba->vops->hibern8_notify(hba, en, status);
+}
#endif /* End of Header */
--
1.7.10.4
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[PATCH v5 10/11] Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller
From: Seungwon Jeon
This adds Exynos Universal Flash Storage (UFS) Host Controller DT bindings.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
.../devicetree/bindings/ufs/ufs-exynos.txt | 104
1 file changed, 104 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
diff --git a/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
new file mode 100644
index ..08e2d1497b1b
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
@@ -0,0 +1,104 @@
+* Exynos Universal Flash Storage (UFS) Host Controller
+
+UFSHC nodes are defined to describe on-chip UFS host controllers.
+Each UFS controller instance should have its own node.
+
+Required properties:
+- compatible: compatible name, contains "samsung,exynos7-ufs"
+- interrupts:
+- reg : Should contain HCI, vendor specific, UNIPRO and
+ UFS protector address space
+- reg-names: "hci", "vs_hci", "unipro", "ufsp";
+
+Optional properties:
+- vdd-hba-supply: phandle to UFS host controller supply regulator node
+- vcc-supply: phandle to VCC supply regulator node
+- vccq-supply : phandle to VCCQ supply regulator node
+- vccq2-supply : phandle to VCCQ2 supply regulator node
+- vcc-supply-1p8: For embedded UFS devices, valid VCC range is
1.7-1.95V
+ or 2.7-3.6V. This boolean property when set,
specifies
+ to use low voltage range of 1.7-1.95V. Note for
external
+ UFS cards this property is invalid and valid VCC
range is
+ always 2.7-3.6V.
+- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
+- vccq-max-microamp : specifies max. load that can be drawn from vccq
supply
+- vccq2-max-microamp: specifies max. load that can be drawn from vccq2
supply
+- -fixed-regulator : boolean property specifying that -supply is a
fixed regulator
+
+- clocks: List of phandle and clock specifier pairs
+- clock-names : List of clock input name strings sorted in the same
+ order as the clocks property.
+ "core", "sclk_unipro_main", "ref" and ref_parent
+
+- freq-table-hz: Array of operating frequencies
stored in the same
+ order as the clocks property. If this property is not
+ defined or a value in the array is "0" then it is
assumed
+ that the frequency is set by the parent clock or a
+ fixed rate clock source.
+- pclk-freq-avail-range : specifies available frequency range(min/max) for APB
clock
+- ufs,pwr-attr-mode : specifies mode value for power mode change, possible
values are
+ "FAST", "SLOW", "FAST_auto" and "SLOW_auto"
+- ufs,pwr-attr-lane : specifies lane count value for power mode change
+ allowed values are 1 or 2
+- ufs,pwr-attr-gear : specifies gear count value for power mode change
+ allowed values are 1 or 2
+- ufs,pwr-attr-hs-series : specifies HS rate series for power mode change
+ can be one of "HS_rate_b" or "HS_rate_a"
+- ufs,pwr-local-l2-timer : specifies array of local UNIPRO L2 timer values
+ 3 timers supported
+
+- ufs,pwr-remote-l2-timer : specifies array of remote UNIPRO L2 timer values
+ 3 timers supported
+
+- ufs-rx-adv-fine-gran-sup_en : specifies support of fine granularity of MPHY,
+ this is a boolean property.
+- ufs-rx-adv-fine-gran-step : specifies granularity steps of MPHY,
+ allowed step size is 0 to 3
+- ufs-rx-adv-min-activate-time-cap : specifies rx advanced minimum activate
time of MPHY
+range is 1 to 9
+- ufs-pa-granularity : specifies Granularity for PA_TActivate and
PA_Hibern8Time
+- ufs-pa-tacctivate : specifies time to wake-up remote M-RX
+- ufs-pa-hibern8time : specifies minimum time to wait in HIBERN8 state
+
+Note: If above properties are not defined it can be assumed that the supply
+regulators or clocks are always on.
+
+Example:
+ ufshc@0x1557 {
+ compatible = "samsung,exynos7-ufs";
+ reg = <0x1557 0x100>,
+ <0x15570100 0x100>,
+ <0x15571000 0x200>,
+ <0x15572000 0x300>;
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+
Re: [PATCH v5 10/11] Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller
Hi Rob, On 11/09/2015 09:53 PM, Rob Herring wrote: On Mon, Nov 09, 2015 at 10:56:26AM +0530, Alim Akhtar wrote: From: Seungwon Jeon This adds Exynos Universal Flash Storage (UFS) Host Controller DT bindings. Signed-off-by: Seungwon Jeon Signed-off-by: Alim Akhtar --- .../devicetree/bindings/ufs/ufs-exynos.txt | 104 1 file changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt diff --git a/Documentation/devicetree/bindings/ufs/ufs-exynos.txt b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt new file mode 100644 index ..08e2d1497b1b --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt @@ -0,0 +1,104 @@ +* Exynos Universal Flash Storage (UFS) Host Controller + +UFSHC nodes are defined to describe on-chip UFS host controllers. +Each UFS controller instance should have its own node. + +Required properties: +- compatible: compatible name, contains "samsung,exynos7-ufs" +- interrupts: +- reg : Should contain HCI, vendor specific, UNIPRO and + UFS protector address space +- reg-names: "hci", "vs_hci", "unipro", "ufsp"; No phy for MPHY? ufs-phy is documented, see 01/11 of this series. + +Optional properties: +- vdd-hba-supply: phandle to UFS host controller supply regulator node +- vcc-supply: phandle to VCC supply regulator node +- vccq-supply : phandle to VCCQ supply regulator node +- vccq2-supply : phandle to VCCQ2 supply regulator node +- vcc-supply-1p8: For embedded UFS devices, valid VCC range is 1.7-1.95V + or 2.7-3.6V. This boolean property when set, specifies + to use low voltage range of 1.7-1.95V. Note for external + UFS cards this property is invalid and valid VCC range is + always 2.7-3.6V. +- vcc-max-microamp : specifies max. load that can be drawn from vcc supply +- vccq-max-microamp : specifies max. load that can be drawn from vccq supply +- vccq2-max-microamp: specifies max. load that can be drawn from vccq2 supply Some of these are supplies to the flash chip, so you should make these common properties (in a common doc). Ah, yes these are duplicated, already documented in common ufshcd file Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt What is the recommended way, do I need to include it here as well? or just mentioning that "same as documented in ufshcd-pltfrm.txt"? +- -fixed-regulator : boolean property specifying that -supply is a fixed regulator This should be determined from the regulator. Same as above already documented as part of ufshcd-pltfrm binding. + +- clocks: List of phandle and clock specifier pairs +- clock-names : List of clock input name strings sorted in the same + order as the clocks property. + "core", "sclk_unipro_main", "ref" and ref_parent + +- freq-table-hz: Array of operating frequencies stored in the same + order as the clocks property. If this property is not + defined or a value in the array is "0" then it is assumed + that the frequency is set by the parent clock or a + fixed rate clock source. +- pclk-freq-avail-range : specifies available frequency range(min/max) for APB clock +- ufs,pwr-attr-mode : specifies mode value for power mode change, possible values are + "FAST", "SLOW", "FAST_auto" and "SLOW_auto" ufs is not a vendor. Use a '-' rather than ','. Ok will change. +- ufs,pwr-attr-lane : specifies lane count value for power mode change + allowed values are 1 or 2 +- ufs,pwr-attr-gear : specifies gear count value for power mode change + allowed values are 1 or 2 +- ufs,pwr-attr-hs-series : specifies HS rate series for power mode change + can be one of "HS_rate_b" or "HS_rate_a" +- ufs,pwr-local-l2-timer : specifies array of local UNIPRO L2 timer values + 3 timers supported + +- ufs,pwr-remote-l2-timer : specifies array of remote UNIPRO L2 timer values + 3 timers supported + +- ufs-rx-adv-fine-gran-sup_en : specifies support of fine granularity of MPHY, + this is a boolean property. +- ufs-rx-adv-fine-gran-step : specifies granularity steps of MPHY, + allowed step size is 0 to 3 +- ufs-rx-adv-min-activate-time-cap : specifies rx advanced minimum activate time of MPHY +
Re: [PATCH v5 00/11] exynos-ufs: add support for Exynos
Hi Kishon,
Any more concern on the PHY part of this series?
Thanks!
On Mon, Nov 9, 2015 at 10:56 AM, Alim Akhtar wrote:
> This patch-set introduces UFS (Universal Flash Storage) host support
> for Samsung Exynos SoC. Mostly, it consists of UFS PHY and host specific
> driver.
> And it also contains some quirks handling for Exynos.
>
> NOTE: ** This series has a dependency on [4]. **
>
> -Changes since v4:
> * Removed platform specific PHY ops as suggested by Kishon
> * Rebased on the top of Yaniv Gardi's work [4]
> * make use of newly introduce ufshcd_{get,set}_variant
> * other small changes and improvements.
> * rebased on the top of linux next-20151109
>
> -Changes since v3:
> * Fixed compilation warrings as reported by "Kbuild Test Robot"[5].
> * Restructure the driver to make it as a platform driver, rebased on top of
> [4].
> * Addressed review comments from Arnd Bergmann[5].
> * Other misc changes and improvements.
>
> -Changes since v2:
> * Addressed review comments from Kishon[1] and Rob Herring [2]
> * Splited ufs dt binding documetation from ufs driver patch
>
> -Changes since v1:
> * Addressed review comments from Alexey[3] and various review comments from
> Amit.
> * Updated email id of Seungwon as his samsung id is void now.
> * Added ufs platform data
>
> [1]-> https://lkml.org/lkml/2015/9/18/29
> [2]-> https://lkml.org/lkml/2015/9/21/668
> [3]-> https://lkml.org/lkml/2015/8/23/124
> [4]-> https://lkml.org/lkml/2015/10/28/271
> [5]-> https://lkml.org/lkml/2015/10/1/402
>
> This patch set is tested on exynos7-espresso board.
>
>
> Alim Akhtar (1):
> Documentation: samsung-phy: Add dt bindings for UFS
>
> Seungwon Jeon (10):
> phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
> scsi: ufs: add quirk to contain unconformable utrd field
> scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
> scsi: ufs: add quirk not to allow reset of interrupt aggregation
> scsi: ufs: add quirk to enable host controller without hce
> scsi: ufs: add specific callback for nexus type
> scsi: ufs: add add specific callback for hibern8
> scsi: ufs: make ufshcd_config_pwr_mode of non-static func
> Documentation: devicetree: ufs: Add DT bindings for exynos UFS host
> controller
> scsi: ufs-exynos: add UFS host support for Exynos SoCs
>
> .../devicetree/bindings/phy/samsung-phy.txt| 22 +
> .../devicetree/bindings/ufs/ufs-exynos.txt | 104 ++
> drivers/phy/Kconfig|7 +
> drivers/phy/Makefile |1 +
> drivers/phy/phy-exynos-ufs.c | 241
> drivers/phy/phy-exynos-ufs.h | 85 ++
> drivers/phy/phy-exynos7-ufs.h | 89 ++
> drivers/scsi/ufs/Kconfig | 12 +
> drivers/scsi/ufs/Makefile |1 +
> drivers/scsi/ufs/ufs-exynos-hw.c | 131 ++
> drivers/scsi/ufs/ufs-exynos-hw.h | 43 +
> drivers/scsi/ufs/ufs-exynos.c | 1304
>
> drivers/scsi/ufs/ufs-exynos.h | 247
> drivers/scsi/ufs/ufshcd.c | 168 ++-
> drivers/scsi/ufs/ufshcd.h | 54 +
> drivers/scsi/ufs/ufshci.h | 26 +-
> drivers/scsi/ufs/unipro.h | 47 +
> include/linux/phy/phy-exynos-ufs.h | 85 ++
> 18 files changed, 2647 insertions(+), 20 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
> create mode 100644 drivers/phy/phy-exynos-ufs.c
> create mode 100644 drivers/phy/phy-exynos-ufs.h
> create mode 100644 drivers/phy/phy-exynos7-ufs.h
> create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
> create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
> create mode 100644 drivers/scsi/ufs/ufs-exynos.c
> create mode 100644 drivers/scsi/ufs/ufs-exynos.h
> create mode 100644 include/linux/phy/phy-exynos-ufs.h
>
> --
> 1.7.10.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-scsi" in
> the body of a message to majord...@vger.kernel.org
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--
Regards,
Alim
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Re: [PATCH v5 02/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
Hi
Thanks again for looking into this.
On 11/17/2015 11:46 AM, Kishon Vijay Abraham I wrote:
Hi,
On Monday 09 November 2015 10:56 AM, Alim Akhtar wrote:
From: Seungwon Jeon
This patch introduces Exynos UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
---
drivers/phy/Kconfig|7 ++
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos-ufs.c | 241
drivers/phy/phy-exynos-ufs.h | 85 +
drivers/phy/phy-exynos7-ufs.h | 89 +
include/linux/phy/phy-exynos-ufs.h | 85 +
6 files changed, 508 insertions(+)
create mode 100644 drivers/phy/phy-exynos-ufs.c
create mode 100644 drivers/phy/phy-exynos-ufs.h
create mode 100644 drivers/phy/phy-exynos7-ufs.h
create mode 100644 include/linux/phy/phy-exynos-ufs.h
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 7eb5859dd035..7d38a92e0297 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -389,4 +389,11 @@ config PHY_CYGNUS_PCIE
Enable this to support the Broadcom Cygnus PCIe PHY.
If unsure, say N.
+config PHY_EXYNOS_UFS
+ tristate "EXYNOS SoC series UFS PHY driver"
+ depends on OF && ARCH_EXYNOS || COMPILE_TEST
+ select GENERIC_PHY
+ help
+ Support for UFS PHY on Samsung EXYNOS chipsets.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 075db1a81aa5..9bec4d1a89e1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY)+=
phy-armada375-usb2.o
obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
+obj-$(CONFIG_PHY_EXYNOS_UFS) += phy-exynos-ufs.o
obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
obj-$(CONFIG_PHY_PXA_28NM_USB2) += phy-pxa-28nm-usb2.o
obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o
diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
new file mode 100644
index ..cb1aeaa3d4eb
--- /dev/null
+++ b/drivers/phy/phy-exynos-ufs.c
@@ -0,0 +1,241 @@
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "phy-exynos-ufs.h"
+
+#define for_each_phy_lane(phy, i) \
+ for (i = 0; i < (phy)->lane_cnt; i++)
+#define for_each_phy_cfg(cfg) \
+ for (; (cfg)->id; (cfg)++)
+
+#define PHY_DEF_LANE_CNT 1
+
+static void exynos_ufs_phy_config(struct exynos_ufs_phy *phy,
+ const struct exynos_ufs_phy_cfg *cfg, u8 lane)
+{
+ enum {LANE_0, LANE_1}; /* lane index */
+
+ switch (lane) {
+ case LANE_0:
+ writel(cfg->val, (phy)->reg_pma + cfg->off_0);
+ break;
+ case LANE_1:
+ if (cfg->id == PHY_TRSV_BLK)
+ writel(cfg->val, (phy)->reg_pma + cfg->off_1);
+ break;
+ }
+}
+
+static bool match_cfg_to_pwr_mode(u8 desc, u8 required_pwr)
+{
+ if (IS_PWR_MODE_ANY(desc))
+ return true;
+
+ if (IS_PWR_MODE_HS(required_pwr) && IS_PWR_MODE_HS_ANY(desc))
+ return true;
+
+ if (COMP_PWR_MODE(required_pwr, desc))
+ return true;
+
+ if (COMP_PWR_MODE_MD(required_pwr, desc) &&
+ COMP_PWR_MODE_GEAR(required_pwr, desc) &&
+ COMP_PWR_MODE_SER(required_pwr, desc))
+ return true;
+
+ return false;
+}
+
+int exynos_ufs_phy_calibrate(struct phy *phy,
+ enum phy_cfg_tag tag, u8 pwr)
This is similar to the first version of your patch without EXPORT_SYMBOL.
I think you have to create a new generic PHY_OPS for calibrate PHY while making
sure that it is as generic as possible (which means calibrate_phy shouldn't
have tag and pwr arguments or a strong justification as to why those arguments
are required in a generic API).
I don't see the advantage to making this a generic phy_ops, this is
exynos specific ufs-phy, please have a look at other implementations
drivers/phy/phy-qcom-ufs.c (which I belive mereged recently)
may be other vendors might come with th
Re: [PATCH v5 02/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
Hi Kishon,
On 11/19/2015 07:09 PM, Kishon Vijay Abraham I wrote:
Hi,
On Tuesday 17 November 2015 01:41 PM, Alim Akhtar wrote:
Hi
Thanks again for looking into this.
On 11/17/2015 11:46 AM, Kishon Vijay Abraham I wrote:
Hi,
On Monday 09 November 2015 10:56 AM, Alim Akhtar wrote:
From: Seungwon Jeon
This patch introduces Exynos UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
---
drivers/phy/Kconfig|7 ++
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos-ufs.c | 241
drivers/phy/phy-exynos-ufs.h | 85 +
drivers/phy/phy-exynos7-ufs.h | 89 +
include/linux/phy/phy-exynos-ufs.h | 85 +
6 files changed, 508 insertions(+)
create mode 100644 drivers/phy/phy-exynos-ufs.c
create mode 100644 drivers/phy/phy-exynos-ufs.h
create mode 100644 drivers/phy/phy-exynos7-ufs.h
create mode 100644 include/linux/phy/phy-exynos-ufs.h
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 7eb5859dd035..7d38a92e0297 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -389,4 +389,11 @@ config PHY_CYGNUS_PCIE
Enable this to support the Broadcom Cygnus PCIe PHY.
If unsure, say N.
+config PHY_EXYNOS_UFS
+tristate "EXYNOS SoC series UFS PHY driver"
+depends on OF && ARCH_EXYNOS || COMPILE_TEST
+select GENERIC_PHY
+help
+ Support for UFS PHY on Samsung EXYNOS chipsets.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 075db1a81aa5..9bec4d1a89e1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY)+=
phy-armada375-usb2.o
obj-$(CONFIG_BCM_KONA_USB2_PHY)+= phy-bcm-kona-usb2.o
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO)+= phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
+obj-$(CONFIG_PHY_EXYNOS_UFS)+= phy-exynos-ufs.o
obj-$(CONFIG_PHY_LPC18XX_USB_OTG)+= phy-lpc18xx-usb-otg.o
obj-$(CONFIG_PHY_PXA_28NM_USB2)+= phy-pxa-28nm-usb2.o
obj-$(CONFIG_PHY_PXA_28NM_HSIC)+= phy-pxa-28nm-hsic.o
diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
new file mode 100644
index ..cb1aeaa3d4eb
--- /dev/null
+++ b/drivers/phy/phy-exynos-ufs.c
@@ -0,0 +1,241 @@
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "phy-exynos-ufs.h"
+
+#define for_each_phy_lane(phy, i) \
+for (i = 0; i < (phy)->lane_cnt; i++)
+#define for_each_phy_cfg(cfg) \
+for (; (cfg)->id; (cfg)++)
+
+#define PHY_DEF_LANE_CNT1
+
+static void exynos_ufs_phy_config(struct exynos_ufs_phy *phy,
+const struct exynos_ufs_phy_cfg *cfg, u8 lane)
+{
+enum {LANE_0, LANE_1}; /* lane index */
+
+switch (lane) {
+case LANE_0:
+writel(cfg->val, (phy)->reg_pma + cfg->off_0);
+break;
+case LANE_1:
+if (cfg->id == PHY_TRSV_BLK)
+writel(cfg->val, (phy)->reg_pma + cfg->off_1);
+break;
+}
+}
+
+static bool match_cfg_to_pwr_mode(u8 desc, u8 required_pwr)
+{
+if (IS_PWR_MODE_ANY(desc))
+return true;
+
+if (IS_PWR_MODE_HS(required_pwr) && IS_PWR_MODE_HS_ANY(desc))
+return true;
+
+if (COMP_PWR_MODE(required_pwr, desc))
+return true;
+
+if (COMP_PWR_MODE_MD(required_pwr, desc) &&
+COMP_PWR_MODE_GEAR(required_pwr, desc) &&
+COMP_PWR_MODE_SER(required_pwr, desc))
+return true;
+
+return false;
+}
+
+int exynos_ufs_phy_calibrate(struct phy *phy,
+enum phy_cfg_tag tag, u8 pwr)
This is similar to the first version of your patch without EXPORT_SYMBOL.
I think you have to create a new generic PHY_OPS for calibrate PHY while making
sure that it is as generic as possible (which means calibrate_phy shouldn't
have tag and pwr arguments or a strong justification as to why those arguments
are required in a generic API).
I don't see the advantage to making this a generic phy_ops, this is exynos
specific ufs-phy, please have a look at other implementations
only the implementation is specific to exynos. I've seen lot of other vendors
want to do something like calibrate phy.
So if we add something like (*
Re: [PATCH v5 02/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
On Fri, Feb 3, 2017 at 2:49 PM, Alim Akhtar wrote: > Hi Kishon, > > > On 11/19/2015 07:09 PM, Kishon Vijay Abraham I wrote: >> >> Hi, >> >> On Tuesday 17 November 2015 01:41 PM, Alim Akhtar wrote: >>> >>> Hi >>> Thanks again for looking into this. >>> >>> On 11/17/2015 11:46 AM, Kishon Vijay Abraham I wrote: >>>> >>>> Hi, >>>> >>>> On Monday 09 November 2015 10:56 AM, Alim Akhtar wrote: >>>>> >>>>> From: Seungwon Jeon >>>>> >>>>> This patch introduces Exynos UFS PHY driver. This driver >>>>> supports to deal with phy calibration and power control >>>>> according to UFS host driver's behavior. >>>>> >>>>> Signed-off-by: Seungwon Jeon >>>>> Signed-off-by: Alim Akhtar >>>>> Cc: Kishon Vijay Abraham I >>>>> --- >>>>> drivers/phy/Kconfig|7 ++ >>>>> drivers/phy/Makefile |1 + >>>>> drivers/phy/phy-exynos-ufs.c | 241 >>>>> >>>>> drivers/phy/phy-exynos-ufs.h | 85 + >>>>> drivers/phy/phy-exynos7-ufs.h | 89 + >>>>> include/linux/phy/phy-exynos-ufs.h | 85 + >>>>> 6 files changed, 508 insertions(+) >>>>> create mode 100644 drivers/phy/phy-exynos-ufs.c >>>>> create mode 100644 drivers/phy/phy-exynos-ufs.h >>>>> create mode 100644 drivers/phy/phy-exynos7-ufs.h >>>>> create mode 100644 include/linux/phy/phy-exynos-ufs.h >>>>> >>>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig >>>>> index 7eb5859dd035..7d38a92e0297 100644 >>>>> --- a/drivers/phy/Kconfig >>>>> +++ b/drivers/phy/Kconfig >>>>> @@ -389,4 +389,11 @@ config PHY_CYGNUS_PCIE >>>>> Enable this to support the Broadcom Cygnus PCIe PHY. >>>>> If unsure, say N. >>>>> >>>>> +config PHY_EXYNOS_UFS >>>>> +tristate "EXYNOS SoC series UFS PHY driver" >>>>> +depends on OF && ARCH_EXYNOS || COMPILE_TEST >>>>> +select GENERIC_PHY >>>>> +help >>>>> + Support for UFS PHY on Samsung EXYNOS chipsets. >>>>> + >>>>> endmenu >>>>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile >>>>> index 075db1a81aa5..9bec4d1a89e1 100644 >>>>> --- a/drivers/phy/Makefile >>>>> +++ b/drivers/phy/Makefile >>>>> @@ -10,6 +10,7 @@ obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY)+= >>>>> phy-armada375-usb2.o >>>>> obj-$(CONFIG_BCM_KONA_USB2_PHY)+= phy-bcm-kona-usb2.o >>>>> obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO)+= phy-exynos-dp-video.o >>>>> obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o >>>>> +obj-$(CONFIG_PHY_EXYNOS_UFS)+= phy-exynos-ufs.o >>>>> obj-$(CONFIG_PHY_LPC18XX_USB_OTG)+= phy-lpc18xx-usb-otg.o >>>>> obj-$(CONFIG_PHY_PXA_28NM_USB2)+= phy-pxa-28nm-usb2.o >>>>> obj-$(CONFIG_PHY_PXA_28NM_HSIC)+= phy-pxa-28nm-hsic.o >>>>> diff --git a/drivers/phy/phy-exynos-ufs.c >>>>> b/drivers/phy/phy-exynos-ufs.c >>>>> new file mode 100644 >>>>> index ..cb1aeaa3d4eb >>>>> --- /dev/null >>>>> +++ b/drivers/phy/phy-exynos-ufs.c >>>>> @@ -0,0 +1,241 @@ >>>>> +/* >>>>> + * UFS PHY driver for Samsung EXYNOS SoC >>>>> + * >>>>> + * Copyright (C) 2015 Samsung Electronics Co., Ltd. >>>>> + * Author: Seungwon Jeon >>>>> + * >>>>> + * This program is free software; you can redistribute it and/or >>>>> modify >>>>> + * it under the terms of the GNU General Public License as published >>>>> by >>>>> + * the Free Software Foundation; either version 2 of the License, or >>>>> + * (at your option) any later version. >>>>> + */ >>>>> +#include >>>>> +#include >>>>> +#include >>>>> +#include >>>>> +#include >>>>> +#include >>>>> +#include >>>>> +#include >>>>> +#include >
Re: [PATCH v5 02/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
Hi Kishon, On 02/27/2017 10:56 AM, Kishon Vijay Abraham I wrote: > Hi, > > On Thursday 23 February 2017 12:20 AM, Alim Akhtar wrote: >> On Fri, Feb 3, 2017 at 2:49 PM, Alim Akhtar wrote: >>> Hi Kishon, >>> >>> >>> On 11/19/2015 07:09 PM, Kishon Vijay Abraham I wrote: >>>> >>>> Hi, >>>> >>>> On Tuesday 17 November 2015 01:41 PM, Alim Akhtar wrote: >>>>> >>>>> Hi >>>>> Thanks again for looking into this. >>>>> >>>>> On 11/17/2015 11:46 AM, Kishon Vijay Abraham I wrote: >>>>>> >>>>>> Hi, >>>>>> >>>>>> On Monday 09 November 2015 10:56 AM, Alim Akhtar wrote: >>>>>>> >>>>>>> From: Seungwon Jeon >>>>>>> >>>>>>> This patch introduces Exynos UFS PHY driver. This driver >>>>>>> supports to deal with phy calibration and power control >>>>>>> according to UFS host driver's behavior. >>>>>>> >>>>>>> Signed-off-by: Seungwon Jeon >>>>>>> Signed-off-by: Alim Akhtar >>>>>>> Cc: Kishon Vijay Abraham I >>>>>>> --- >>>>>>> drivers/phy/Kconfig|7 ++ >>>>>>> drivers/phy/Makefile |1 + >>>>>>> drivers/phy/phy-exynos-ufs.c | 241 >>>>>>> >>>>>>> drivers/phy/phy-exynos-ufs.h | 85 + >>>>>>> drivers/phy/phy-exynos7-ufs.h | 89 + >>>>>>> include/linux/phy/phy-exynos-ufs.h | 85 + >>>>>>> 6 files changed, 508 insertions(+) >>>>>>> create mode 100644 drivers/phy/phy-exynos-ufs.c >>>>>>> create mode 100644 drivers/phy/phy-exynos-ufs.h >>>>>>> create mode 100644 drivers/phy/phy-exynos7-ufs.h >>>>>>> create mode 100644 include/linux/phy/phy-exynos-ufs.h >>>>>>> >>>>>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig >>>>>>> index 7eb5859dd035..7d38a92e0297 100644 >>>>>>> --- a/drivers/phy/Kconfig >>>>>>> +++ b/drivers/phy/Kconfig >>>>>>> @@ -389,4 +389,11 @@ config PHY_CYGNUS_PCIE >>>>>>> Enable this to support the Broadcom Cygnus PCIe PHY. >>>>>>> If unsure, say N. >>>>>>> >>>>>>> +config PHY_EXYNOS_UFS >>>>>>> +tristate "EXYNOS SoC series UFS PHY driver" >>>>>>> +depends on OF && ARCH_EXYNOS || COMPILE_TEST >>>>>>> +select GENERIC_PHY >>>>>>> +help >>>>>>> + Support for UFS PHY on Samsung EXYNOS chipsets. >>>>>>> + >>>>>>> endmenu >>>>>>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile >>>>>>> index 075db1a81aa5..9bec4d1a89e1 100644 >>>>>>> --- a/drivers/phy/Makefile >>>>>>> +++ b/drivers/phy/Makefile >>>>>>> @@ -10,6 +10,7 @@ obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY)+= >>>>>>> phy-armada375-usb2.o >>>>>>> obj-$(CONFIG_BCM_KONA_USB2_PHY)+= phy-bcm-kona-usb2.o >>>>>>> obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO)+= phy-exynos-dp-video.o >>>>>>> obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o >>>>>>> +obj-$(CONFIG_PHY_EXYNOS_UFS)+= phy-exynos-ufs.o >>>>>>> obj-$(CONFIG_PHY_LPC18XX_USB_OTG)+= phy-lpc18xx-usb-otg.o >>>>>>> obj-$(CONFIG_PHY_PXA_28NM_USB2)+= phy-pxa-28nm-usb2.o >>>>>>> obj-$(CONFIG_PHY_PXA_28NM_HSIC)+= phy-pxa-28nm-hsic.o >>>>>>> diff --git a/drivers/phy/phy-exynos-ufs.c >>>>>>> b/drivers/phy/phy-exynos-ufs.c >>>>>>> new file mode 100644 >>>>>>> index ..cb1aeaa3d4eb >>>>>>> --- /dev/null >>>>>>> +++ b/drivers/phy/phy-exynos-ufs.c >>>>>>> @@ -0,0 +1,241 @@ >>>>>>> +/* >>>>>>> + * UFS PHY driver for Samsung EXYNOS SoC >>>>>>> + * >>>>>>> + * Copyright (C) 2015 Samsun
Re: [PATCH v5 02/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
Hi Kishon, On 02/28/2017 09:04 AM, Kishon Vijay Abraham I wrote: > Hi, > > On Monday 27 February 2017 07:40 PM, Alim Akhtar wrote: >> Hi Kishon, >> >> On 02/27/2017 10:56 AM, Kishon Vijay Abraham I wrote: >>> Hi, >>> >>> On Thursday 23 February 2017 12:20 AM, Alim Akhtar wrote: >>>> On Fri, Feb 3, 2017 at 2:49 PM, Alim Akhtar >>>> wrote: >>>>> Hi Kishon, >>>>> >>>>> >>>>> On 11/19/2015 07:09 PM, Kishon Vijay Abraham I wrote: >>>>>> >>>>>> Hi, >>>>>> >>>>>> On Tuesday 17 November 2015 01:41 PM, Alim Akhtar wrote: >>>>>>> >>>>>>> Hi >>>>>>> Thanks again for looking into this. >>>>>>> >>>>>>> On 11/17/2015 11:46 AM, Kishon Vijay Abraham I wrote: >>>>>>>> >>>>>>>> Hi, >>>>>>>> >>>>>>>> On Monday 09 November 2015 10:56 AM, Alim Akhtar wrote: >>>>>>>>> >>>>>>>>> From: Seungwon Jeon >>>>>>>>> >>>>>>>>> This patch introduces Exynos UFS PHY driver. This driver >>>>>>>>> supports to deal with phy calibration and power control >>>>>>>>> according to UFS host driver's behavior. >>>>>>>>> >>>>>>>>> Signed-off-by: Seungwon Jeon >>>>>>>>> Signed-off-by: Alim Akhtar >>>>>>>>> Cc: Kishon Vijay Abraham I >>>>>>>>> --- >>>>>>>>> drivers/phy/Kconfig|7 ++ >>>>>>>>> drivers/phy/Makefile |1 + >>>>>>>>> drivers/phy/phy-exynos-ufs.c | 241 >>>>>>>>> >>>>>>>>> drivers/phy/phy-exynos-ufs.h | 85 + >>>>>>>>> drivers/phy/phy-exynos7-ufs.h | 89 + >>>>>>>>> include/linux/phy/phy-exynos-ufs.h | 85 + >>>>>>>>> 6 files changed, 508 insertions(+) >>>>>>>>> create mode 100644 drivers/phy/phy-exynos-ufs.c >>>>>>>>> create mode 100644 drivers/phy/phy-exynos-ufs.h >>>>>>>>> create mode 100644 drivers/phy/phy-exynos7-ufs.h >>>>>>>>> create mode 100644 include/linux/phy/phy-exynos-ufs.h >>>>>>>>> >>>>>>>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig >>>>>>>>> index 7eb5859dd035..7d38a92e0297 100644 >>>>>>>>> --- a/drivers/phy/Kconfig >>>>>>>>> +++ b/drivers/phy/Kconfig >>>>>>>>> @@ -389,4 +389,11 @@ config PHY_CYGNUS_PCIE >>>>>>>>> Enable this to support the Broadcom Cygnus PCIe PHY. >>>>>>>>> If unsure, say N. >>>>>>>>> >>>>>>>>> +config PHY_EXYNOS_UFS >>>>>>>>> +tristate "EXYNOS SoC series UFS PHY driver" >>>>>>>>> +depends on OF && ARCH_EXYNOS || COMPILE_TEST >>>>>>>>> +select GENERIC_PHY >>>>>>>>> +help >>>>>>>>> + Support for UFS PHY on Samsung EXYNOS chipsets. >>>>>>>>> + >>>>>>>>> endmenu >>>>>>>>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile >>>>>>>>> index 075db1a81aa5..9bec4d1a89e1 100644 >>>>>>>>> --- a/drivers/phy/Makefile >>>>>>>>> +++ b/drivers/phy/Makefile >>>>>>>>> @@ -10,6 +10,7 @@ obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY)+= >>>>>>>>> phy-armada375-usb2.o >>>>>>>>> obj-$(CONFIG_BCM_KONA_USB2_PHY)+= phy-bcm-kona-usb2.o >>>>>>>>> obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO)+= phy-exynos-dp-video.o >>>>>>>>> obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o >>>>>>>>> +obj-$(CONFIG_PHY_EXYNOS_UFS)+= phy-exynos-ufs.o >>>>>>>>> obj-$(CONFIG_PHY_LPC18XX_USB_OTG)+= phy-lpc18xx-usb-otg.o >>>&
Re: [PATCH v2] MAINTAINERS: Mark UFS as Orphan
On 28/01/19 4:05 PM, Marc Gonzalez wrote: > On 22/01/2019 18:39, Joao Pinto wrote: > >> On 1/22/2019 5:15 PM, Marc Gonzalez wrote: >> >>> Looking through git log and the linux-scsi archives, it seems that >>> Vinayak vanished after 2013. Removing him as a maintainer will make >>> get_maintainer.pl generate the list of relevant contributors. >>> >>> Signed-off-by: Marc Gonzalez >>> --- >>> Martin, sorry for v1, it was a mistake. >>> --- >>> MAINTAINERS | 3 +-- >>> 1 file changed, 1 insertion(+), 2 deletions(-) >>> >>> diff --git a/MAINTAINERS b/MAINTAINERS >>> index 32d76a90..76104c9c4824 100644 >>> --- a/MAINTAINERS >>> +++ b/MAINTAINERS >>> @@ -15666,9 +15666,8 @@ F: drivers/visorbus/ >>> F:drivers/staging/unisys/ >>> >>> UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER >>> -M: Vinayak Holikatti >>> L:linux-scsi@vger.kernel.org >>> -S: Supported >>> +S: Orphan >>> F:Documentation/scsi/ufs.txt >>> F:drivers/scsi/ufs/ >>> >> >> I started contributing to the UFS, but currently I am managing one of the >> driver >> development teams in Synopsys, so my bandwitdh is now low. >> >> Currently I have a person in my team that is very involved in SW development >> for >> UFS Host and we have plans to improve Synopsys driver and submit the >> improvements. >> >> I was planning to send this week a patch to add my team member as Maintainer >> of >> the Synopsys UFS driver and if you agree I could suggest him to pick the >> total >> UFS maintenance. >> >> Please let me know your thoughts about this. > > As far as I'm concerned, "Supported" or "Maintained" is better than "Orphan" > ;-) > > @Vinayak, do you want to remain as maintainer? > Should your email address be updated? > > @Joao, is your team member still interested? > I can send a patch adding him as maintainer, what's his name and address? > > Is anyone else interested in being maintainer for drivers/scsi/ufs/ ? > Lately I was adding support for Samsung ufs HCI then got busy with some other stuffs, now I am coming back to those patch (patches will be posted soon), I am interested in Reviewing UFS related patches upstream. > Regards. > >
Re: [PATCH v3] MAINTAINERS: Add reviewers for UFS patches
Thanks Marc. On 04/02/19 5:41 PM, Marc Gonzalez wrote: > According to git log and the linux-scsi archives, Vinayak has been > inactive for several years. Removing him as maintainer will make the > get_maintainer.pl script generate an extensive list of recipients. > Add three reviewers as well to vet future UFS patches. > > Signed-off-by: Marc Gonzalez > --- Acked-by: Alim Akhtar > Alim, Avri, Pedro, can we get your Acked-by for this patch? > Did I leave anyone out who wants to be an official Reviewer? > Martin: I'm hoping you can land this patch in time for 5.1-rc1 so that future > patches get routed to the right people. > --- > MAINTAINERS | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 8c68de3cfd80..7386f5d0f9d1 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -15676,7 +15676,9 @@ F:drivers/visorbus/ > F: drivers/staging/unisys/ > > UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER > -M: Vinayak Holikatti > +R: Alim Akhtar > +R: Avri Altman > +R: Pedro Sousa > L: linux-scsi@vger.kernel.org > S: Supported > F: Documentation/scsi/ufs.txt >
Re: [PATCH v3 5/5] Revert "scsi: ufs: disable vccq if it's not needed by UFS device"
Hi Marc,
On 04/02/19 11:12 PM, Marc Gonzalez wrote:
> This reverts commit 60f0187031c05e04cbadffb62f557d0ff3564490.
>
> Calling ufshcd_set_vccq_rail_unused hangs my system.
> It seems vccq is not *not* needed.
>
> Signed-off-by: Marc Gonzalez
> ---
AFAIK Samsung and Toshiba UFS devices does not use VCCQ (this pin is
either floating or connected to Ground, at least on the devices that I
have worked on).
You said your system hanged, I believe you have set UFS_DEVICE_NO_VCCQ
quirks, in that case VCCQ regulator should having been disabled.
So you mean your system hanged because vccq regulator got disabled?
> drivers/scsi/ufs/ufs.h| 1 -
> drivers/scsi/ufs/ufshcd.c | 59 +++
> 2 files changed, 4 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/scsi/ufs/ufs.h b/drivers/scsi/ufs/ufs.h
> index dd65fea07687..7da7318eb6a6 100644
> --- a/drivers/scsi/ufs/ufs.h
> +++ b/drivers/scsi/ufs/ufs.h
> @@ -514,7 +514,6 @@ struct ufs_vreg {
> struct regulator *reg;
> const char *name;
> bool enabled;
> - bool unused;
> int min_uV;
> int max_uV;
> int min_uA;
> diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
> index 9ba7671b84f8..8b9a01073d62 100644
> --- a/drivers/scsi/ufs/ufshcd.c
> +++ b/drivers/scsi/ufs/ufshcd.c
> @@ -245,7 +245,6 @@ static int ufshcd_probe_hba(struct ufs_hba *hba);
> static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
>bool skip_ref_clk);
> static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
> -static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
> static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
> static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
> static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
> @@ -6819,11 +6818,6 @@ static int ufshcd_probe_hba(struct ufs_hba *hba)
> ufs_fixup_device_setup(hba, &card);
> ufshcd_tune_unipro_params(hba);
>
> - ret = ufshcd_set_vccq_rail_unused(hba,
> - (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
> - if (ret)
> - goto out;
> -
> /* UFS device is also active now */
> ufshcd_set_ufs_dev_active(hba);
> ufshcd_force_reset_auto_bkops(hba);
> @@ -7007,24 +7001,13 @@ static int ufshcd_config_vreg_load(struct device
> *dev, struct ufs_vreg *vreg,
> static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
>struct ufs_vreg *vreg)
> {
> - if (!vreg)
> - return 0;
> - else if (vreg->unused)
> - return 0;
> - else
> - return ufshcd_config_vreg_load(hba->dev, vreg,
> -UFS_VREG_LPM_LOAD_UA);
> + return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
> }
>
> static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
>struct ufs_vreg *vreg)
> {
> - if (!vreg)
> - return 0;
> - else if (vreg->unused)
> - return 0;
> - else
> - return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
> + return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
> }
>
> static int ufshcd_config_vreg(struct device *dev,
> @@ -7062,9 +7045,7 @@ static int ufshcd_enable_vreg(struct device *dev,
> struct ufs_vreg *vreg)
> {
> int ret = 0;
>
> - if (!vreg)
> - goto out;
> - else if (vreg->enabled || vreg->unused)
> + if (!vreg || vreg->enabled)
> goto out;
>
> ret = ufshcd_config_vreg(dev, vreg, true);
> @@ -7084,9 +7065,7 @@ static int ufshcd_disable_vreg(struct device *dev,
> struct ufs_vreg *vreg)
> {
> int ret = 0;
>
> - if (!vreg)
> - goto out;
> - else if (!vreg->enabled || vreg->unused)
> + if (!vreg || !vreg->enabled)
> goto out;
>
> ret = regulator_disable(vreg->reg);
> @@ -7192,36 +7171,6 @@ static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
> return 0;
> }
>
> -static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
> -{
> - int ret = 0;
> - struct ufs_vreg_info *info = &hba->vreg_info;
> -
> - if (!info)
> - goto out;
> - else if (!info->vccq)
> - goto out;
> -
> - if (unused) {
> - /* shut off the rail here */
> - ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
> - /*
> - * Mark this rail as no longer used, so it doesn't get enabled
> - * later by mistake
> - */
> - if (!ret)
> - info->vccq->unused = true;
> - } else {
> - /*
> - * rail should have been already enabled hence just make sure
> - * that unused flag is cleared.
> - */
> - info->vc
Re: [PATCH v3 5/5] Revert "scsi: ufs: disable vccq if it's not needed by UFS device"
Hi Bjorn,
On 05/02/19 11:57 AM, Bjorn Andersson wrote:
> On Mon 04 Feb 20:58 PST 2019, Alim Akhtar wrote:
>
>> Hi Marc,
>>
>> On 04/02/19 11:12 PM, Marc Gonzalez wrote:
>>> This reverts commit 60f0187031c05e04cbadffb62f557d0ff3564490.
>>>
>>> Calling ufshcd_set_vccq_rail_unused hangs my system.
>>> It seems vccq is not *not* needed.
>>>
>>> Signed-off-by: Marc Gonzalez
>>> ---
>>
>> AFAIK Samsung and Toshiba UFS devices does not use VCCQ (this pin is
>> either floating or connected to Ground, at least on the devices that I
>> have worked on).
>
> But why does such system define a vccq-supply? If the system doesn't
> have a regulator connected to VCCQ, then the UFS driver shouldn't be
> told that there is one. And if VCCQ is optional the UFS driver should
> support the fact that this regulator might not be supplied (i.e. call
> regulator_get_optional() and handle the error indicating that the supply
> isn't specified).
>
As per JESD220C, chapter 6.1, it does says "VCCQ - Supply voltage used
typically for the memory controller and optionally for the PHY
interface, the memory IO, and any other internal very low voltage block"
And we have VCCQ2 - which serve the pretty much same purpose. The
voltage range for VCCQ and VCCQ2 are different, VCCQ has a lower voltage
suitable to some low voltage block inside UFS device. I think this is
design consideration which allow some vendor to use one less physical
pin may be. And also depends on the voltage requirements of some of the
internal circuit.
> Regards,
> Bjorn
>
>> You said your system hanged, I believe you have set UFS_DEVICE_NO_VCCQ
>> quirks, in that case VCCQ regulator should having been disabled.
>> So you mean your system hanged because vccq regulator got disabled?
>>
>>>drivers/scsi/ufs/ufs.h| 1 -
>>>drivers/scsi/ufs/ufshcd.c | 59 +++
>>>2 files changed, 4 insertions(+), 56 deletions(-)
>>>
>>> diff --git a/drivers/scsi/ufs/ufs.h b/drivers/scsi/ufs/ufs.h
>>> index dd65fea07687..7da7318eb6a6 100644
>>> --- a/drivers/scsi/ufs/ufs.h
>>> +++ b/drivers/scsi/ufs/ufs.h
>>> @@ -514,7 +514,6 @@ struct ufs_vreg {
>>> struct regulator *reg;
>>> const char *name;
>>> bool enabled;
>>> - bool unused;
>>> int min_uV;
>>> int max_uV;
>>> int min_uA;
>>> diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
>>> index 9ba7671b84f8..8b9a01073d62 100644
>>> --- a/drivers/scsi/ufs/ufshcd.c
>>> +++ b/drivers/scsi/ufs/ufshcd.c
>>> @@ -245,7 +245,6 @@ static int ufshcd_probe_hba(struct ufs_hba *hba);
>>>static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
>>> bool skip_ref_clk);
>>>static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
>>> -static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
>>>static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
>>>static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
>>>static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
>>> @@ -6819,11 +6818,6 @@ static int ufshcd_probe_hba(struct ufs_hba *hba)
>>> ufs_fixup_device_setup(hba, &card);
>>> ufshcd_tune_unipro_params(hba);
>>>
>>> - ret = ufshcd_set_vccq_rail_unused(hba,
>>> - (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
>>> - if (ret)
>>> - goto out;
>>> -
>>> /* UFS device is also active now */
>>> ufshcd_set_ufs_dev_active(hba);
>>> ufshcd_force_reset_auto_bkops(hba);
>>> @@ -7007,24 +7001,13 @@ static int ufshcd_config_vreg_load(struct device
>>> *dev, struct ufs_vreg *vreg,
>>>static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
>>> struct ufs_vreg *vreg)
>>>{
>>> - if (!vreg)
>>> - return 0;
>>> - else if (vreg->unused)
>>> - return 0;
>>> - else
>>> - return ufshcd_config_vreg_load(hba->dev, vreg,
>>> - UFS_VREG_LPM_LOAD_UA);
>>> + return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
>>>}
>>>
>>>static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
>>> struct ufs_vreg *vreg)
>>>
Re: [PATCH v3 5/5] Revert "scsi: ufs: disable vccq if it's not needed by UFS device"
On 06/02/19 1:16 AM, Bjorn Andersson wrote:
> On Tue 05 Feb 02:52 PST 2019, Alim Akhtar wrote:
>
>> Hi Bjorn,
>>
>> On 05/02/19 11:57 AM, Bjorn Andersson wrote:
>>> On Mon 04 Feb 20:58 PST 2019, Alim Akhtar wrote:
>>>
>>>> Hi Marc,
>>>>
>>>> On 04/02/19 11:12 PM, Marc Gonzalez wrote:
>>>>> This reverts commit 60f0187031c05e04cbadffb62f557d0ff3564490.
>>>>>
>>>>> Calling ufshcd_set_vccq_rail_unused hangs my system.
>>>>> It seems vccq is not *not* needed.
>>>>>
>>>>> Signed-off-by: Marc Gonzalez
>>>>> ---
>>>>
>>>> AFAIK Samsung and Toshiba UFS devices does not use VCCQ (this pin is
>>>> either floating or connected to Ground, at least on the devices that I
>>>> have worked on).
>>>
>>> But why does such system define a vccq-supply? If the system doesn't
>>> have a regulator connected to VCCQ, then the UFS driver shouldn't be
>>> told that there is one. And if VCCQ is optional the UFS driver should
>>> support the fact that this regulator might not be supplied (i.e. call
>>> regulator_get_optional() and handle the error indicating that the supply
>>> isn't specified).
>>>
>> As per JESD220C, chapter 6.1, it does says "VCCQ - Supply voltage used
>> typically for the memory controller and optionally for the PHY
>> interface, the memory IO, and any other internal very low voltage block"
>> And we have VCCQ2 - which serve the pretty much same purpose. The
>> voltage range for VCCQ and VCCQ2 are different, VCCQ has a lower voltage
>> suitable to some low voltage block inside UFS device. I think this is
>> design consideration which allow some vendor to use one less physical
>> pin may be. And also depends on the voltage requirements of some of the
>> internal circuit.
>>
>
> This looks to me that you are required to have a VCCQ. But you said that
> you do not have a regulator supplying VCCQ on your board, and if that
> really is the case then you should not specify vccq-supply.
>
> The patch Marc is reverting states that for devices that does not have
> VCCQ connected, some unrelated regulator should be assigned to the UFS
> driver so that it can turn it off.
>
>
> If you have a regulator connected to VCCQ then it should go in
> vccq-supply, if you have a regulator connected to VCCQ2 the is should go
> in vccq2-supply. If you don't have these pins connected then there
> shouldn't be any regulators specified here!
>
Yes, that's correct, it should be like what you are suggesting, DT
entries should match the board schematic.
> Regards,
> Bjorn
>
>>
>>> Regards,
>>> Bjorn
>>>
>>>> You said your system hanged, I believe you have set UFS_DEVICE_NO_VCCQ
>>>> quirks, in that case VCCQ regulator should having been disabled.
>>>> So you mean your system hanged because vccq regulator got disabled?
>>>>
>>>>> drivers/scsi/ufs/ufs.h| 1 -
>>>>> drivers/scsi/ufs/ufshcd.c | 59 +++
>>>>> 2 files changed, 4 insertions(+), 56 deletions(-)
>>>>>
>>>>> diff --git a/drivers/scsi/ufs/ufs.h b/drivers/scsi/ufs/ufs.h
>>>>> index dd65fea07687..7da7318eb6a6 100644
>>>>> --- a/drivers/scsi/ufs/ufs.h
>>>>> +++ b/drivers/scsi/ufs/ufs.h
>>>>> @@ -514,7 +514,6 @@ struct ufs_vreg {
>>>>> struct regulator *reg;
>>>>> const char *name;
>>>>> bool enabled;
>>>>> - bool unused;
>>>>> int min_uV;
>>>>> int max_uV;
>>>>> int min_uA;
>>>>> diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
>>>>> index 9ba7671b84f8..8b9a01073d62 100644
>>>>> --- a/drivers/scsi/ufs/ufshcd.c
>>>>> +++ b/drivers/scsi/ufs/ufshcd.c
>>>>> @@ -245,7 +245,6 @@ static int ufshcd_probe_hba(struct ufs_hba *hba);
>>>>> static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
>>>>>bool skip_ref_clk);
>>>>> static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
>>>>> -static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
>>>>> static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
>>>>> static int ufshcd_uic_hibern8_enter(struct ufs_
Re: [PATCH v3 5/5] Revert "scsi: ufs: disable vccq if it's not needed by UFS device"
Hi Marc, On 06/02/19 8:29 PM, Marc Gonzalez wrote: > [ Google, stop making email so hard. No, this is not spam, you twat of a > Bayesian filter ] > > On 05/02/2019 18:51, Marc Gonzalez wrote: > >> On 05/02/2019 18:24, Marc Gonzalez wrote: >> >> Silly me. The system crashes in ufshcd_dump_regs() which is a bug >> I fixed myself. Once I cherry-pick the appropriate fix, the board >> no longer reboots, but UFS init does fail. >> >> Full boot log here: >> https://pastebin.ubuntu.com/p/KwpRnWMFw5/ > > Here's a better failure log, with timestamps: > > [0.00] Booting Linux on physical CPU 0x00 [0x51af8014] > [0.00] Linux version 5.0.0-rc5-next-20190206 (mgonzalez@venus) (gcc > version 7.3.1 20180425 [linaro-7.3-2018.05 revision > d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05)) #19 SMP > PREEMPT Wed Feb 6 15:42:45 CET 2019 > [0.00] Machine model: Qualcomm Technologies, Inc. MSM8998 v1 MTP > [0.00] printk: debug: ignoring loglevel setting. > [0.00] On node 0 totalpages: 1028544 > [0.00] DMA32 zone: 8192 pages used for memmap > [0.00] DMA32 zone: 0 pages reserved > [0.00] DMA32 zone: 511488 pages, LIFO batch:63 > [0.00] Normal zone: 8079 pages used for memmap > [0.00] Normal zone: 517056 pages, LIFO batch:63 > [0.00] psci: probing for conduit method from DT. > [0.00] psci: PSCIv1.0 detected in firmware. > [0.00] psci: Using standard PSCI v0.2 function IDs > [0.00] psci: MIGRATE_INFO_TYPE not supported. > [0.00] psci: SMC Calling Convention v1.0 > [0.00] random: get_random_bytes called from start_kernel+0xa8/0x470 > with crng_init=0 > [0.00] percpu: Embedded 22 pages/cpu @(ptrval) s50184 r8192 > d31736 u90112 > [0.00] pcpu-alloc: s50184 r8192 d31736 u90112 alloc=22*4096 > [0.00] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 [0] 6 [0] 7 > [0.00] Detected VIPT I-cache on CPU0 > [0.00] CPU features: detected: Kernel page table isolation (KPTI) > [0.00] Built 1 zonelists, mobility grouping on. Total pages: 1012273 > [0.00] Kernel command line: ignore_loglevel > androidboot.bootdevice=1da4000.ufshc androidboot.serialno=53733c35 > androidboot.baseband=apq mdss_mdp.panel=1:hdmi:16 > [0.00] Dentry cache hash table entries: 524288 (order: 10, 4194304 > bytes) > [0.00] Inode-cache hash table entries: 262144 (order: 9, 2097152 > bytes) > [0.00] software IO TLB: mapped [mem 0xfbfff000-0xf000] (64MB) > [0.00] Memory: 3955464K/4114176K available (3262K kernel code, 410K > rwdata, 944K rodata, 6016K init, 1161K bss, 158712K reserved, 0K cma-reserved) > [0.00] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1 > [0.00] ftrace: allocating 12605 entries in 50 pages > [0.00] rcu: Preemptible hierarchical RCU implementation. > [0.00] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8. > [0.00] Tasks RCU enabled. > [0.00] rcu: RCU calculated value of scheduler-enlistment delay is 25 > jiffies. > [0.00] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8 > [0.00] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 > [0.00] REMAP: PA=17a0 VA=ff801004 SIZE=1 > [0.00] REMAP: PA=17b0 VA=ff8010d0 SIZE=10 > [0.00] GICv3: Distributor has no Range Selector support > [0.00] GICv3: no VLPI support, no direct LPI support > [0.00] GICv3: CPU0: found redistributor 0 region 0:0x17b0 > [0.00] ITS: No ITS available, not enabling LPIs > [0.00] REMAP: PA=1792 VA=ff8010005000 SIZE=1000 > [0.00] REMAP: PA=17921000 VA=ff801000d000 SIZE=1000 > [0.00] REMAP: PA=17921000 VA=ff8010015000 SIZE=1000 > [0.00] arch_timer: cp15 and mmio timer(s) running at 19.20MHz > (virt/virt). > [0.00] clocksource: arch_sys_counter: mask: 0xff > max_cycles: 0x46d987e47, max_idle_ns: 440795202767 ns > [0.03] sched_clock: 56 bits at 19MHz, resolution 52ns, wraps every > 4398046511078ns > [0.61] Console: colour dummy device 80x25 > [0.000405] printk: console [tty0] enabled > [0.000428] Calibrating delay loop (skipped), value calculated using timer > frequency.. 38.40 BogoMIPS (lpj=76800) > [0.000444] pid_max: default: 32768 minimum: 301 > [0.000542] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes) > [0.000563] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 > bytes) > [0.000864] *** VALIDATE proc *** > [0.023878] ASID allocator initialised with 32768 entries > [0.031878] rcu: Hierarchical SRCU implementation. > [0.051914] smp: Bringing up secondary CPUs ... > [0.086062] Detected VIPT I-cache on CPU1 > [0.086092] GICv3: CPU1: found redistributor 1 region 0:0x17b2
Re: [PATCH v3 5/5] Revert "scsi: ufs: disable vccq if it's not needed by UFS device"
Hi Marc, On 06/02/19 9:22 PM, Marc Gonzalez wrote: > On 06/02/2019 16:27, Alim Akhtar wrote: > >> On 06/02/19 8:29 PM, Marc Gonzalez wrote: >> >>> [2.405734] regulator_disable: ENTER vdd_l26 >>> [2.405958] regulator_disable: EXIT vdd_l26 >>> [2.406032] regulator_set_load: vdd_l26 = 0 uA >>> [3.930447] ufshcd-qcom 1da4000.ufshc: ufshcd_query_attr: opcode 0x04 >>> for idn 13 failed, index 0, err = -11 >>> [5.434358] ufshcd-qcom 1da4000.ufshc: ufshcd_query_attr: opcode 0x04 >>> for idn 13 failed, index 0, err = -11 >>> [6.938318] ufshcd-qcom 1da4000.ufshc: ufshcd_query_attr: opcode 0x04 >>> for idn 13 failed, index 0, err = -11 >>> [6.938414] ufshcd-qcom 1da4000.ufshc: ufshcd_query_attr_retry: query >>> attribute, idn 13, failed with error -11 after 3 retires >>> [6.946959] ufshcd-qcom 1da4000.ufshc: ufshcd_disable_auto_bkops: failed >>> to enable exception event -11 >>> [6.958523] ufshcd-qcom 1da4000.ufshc: dme-peer-get: attr-id 0x1587 >>> failed 3 retries >>> [6.967730] ufshcd-qcom 1da4000.ufshc: dme-peer-get: attr-id 0x1586 >>> failed 3 retries >>> [6.975576] ufshcd-qcom 1da4000.ufshc: ufshcd_get_max_pwr_mode: invalid >>> max pwm tx gear read = 0 >>> [6.983306] ufshcd-qcom 1da4000.ufshc: ufshcd_probe_hba: Failed getting >>> max supported power mode >>> [8.506314] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag >>> query for idn 3 failed, err = -11 >>> [ 10.010352] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag >>> query for idn 3 failed, err = -11 >>> [ 11.514313] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag >>> query for idn 3 failed, err = -11 >>> [ 11.514412] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: query >>> attribute, opcode 5, idn 3, failed with error -11 after 3 retires >>> [ 13.050354] ufshcd-qcom 1da4000.ufshc: __ufshcd_query_descriptor: opcode >>> 0x01 for idn 8 failed, index 0, err = -11 >>> [ 14.554313] ufshcd-qcom 1da4000.ufshc: __ufshcd_query_descriptor: opcode >>> 0x01 for idn 8 failed, index 0, err = -11 >>> [ 16.058313] ufshcd-qcom 1da4000.ufshc: __ufshcd_query_descriptor: opcode >>> 0x01 for idn 8 failed, index 0, err = -11 >>> [ 16.058421] ufshcd-qcom 1da4000.ufshc: ufshcd_read_desc_param: Failed >>> reading descriptor. desc_id 8, desc_index 0, param_offset 0, ret -11 >>> [ 16.067654] ufshcd-qcom 1da4000.ufshc: ufshcd_init_icc_levels: Failed >>> reading power descriptor.len = 98 ret = -11 >>> [ 37.074334] ufshcd-qcom 1da4000.ufshc: link startup failed 1 >> >> Can you check if your UFS device RESET_N is asserted correctly. It might >> be connected to some regulator and may be you can try keeping that >> regulator as "regulator-always-on" from your DT node. > > How do I check RESET_N? In software or hardware? > RST_N is the reset logic for UFS device core logic and it is input to the device from UFS host controller.So, in your platform please check if this line somehow connected to (pulled up) a PMIC supply. If that is the case, please keep that regulator ON and see if this issue is resolved. > Do you think it is not a good idea to revert > 60f0187031c05e04cbadffb62f557d0ff3564490 ? > Please hold on till we understand the real cause of this issue. Or we have a consensuses for reverting the said commit. Thanks! > Regards. > >
Re: [PATCH v3 5/5] Revert "scsi: ufs: disable vccq if it's not needed by UFS device"
Hi Jeffrey, On 07/02/19 8:22 PM, Jeffrey Hugo wrote: > On 2/7/2019 1:50 AM, Alim Akhtar wrote: >> Hi Marc, >> >> On 06/02/19 9:22 PM, Marc Gonzalez wrote: >>> On 06/02/2019 16:27, Alim Akhtar wrote: >>> >>>> On 06/02/19 8:29 PM, Marc Gonzalez wrote: >>>> >>>>> [ 2.405734] regulator_disable: ENTER vdd_l26 >>>>> [ 2.405958] regulator_disable: EXIT vdd_l26 >>>>> [ 2.406032] regulator_set_load: vdd_l26 = 0 uA >>>>> [ 3.930447] ufshcd-qcom 1da4000.ufshc: ufshcd_query_attr: opcode >>>>> 0x04 for idn 13 failed, index 0, err = -11 >>>>> [ 5.434358] ufshcd-qcom 1da4000.ufshc: ufshcd_query_attr: opcode >>>>> 0x04 for idn 13 failed, index 0, err = -11 >>>>> [ 6.938318] ufshcd-qcom 1da4000.ufshc: ufshcd_query_attr: opcode >>>>> 0x04 for idn 13 failed, index 0, err = -11 >>>>> [ 6.938414] ufshcd-qcom 1da4000.ufshc: ufshcd_query_attr_retry: >>>>> query attribute, idn 13, failed with error -11 after 3 retires >>>>> [ 6.946959] ufshcd-qcom 1da4000.ufshc: >>>>> ufshcd_disable_auto_bkops: failed to enable exception event -11 >>>>> [ 6.958523] ufshcd-qcom 1da4000.ufshc: dme-peer-get: attr-id >>>>> 0x1587 failed 3 retries >>>>> [ 6.967730] ufshcd-qcom 1da4000.ufshc: dme-peer-get: attr-id >>>>> 0x1586 failed 3 retries >>>>> [ 6.975576] ufshcd-qcom 1da4000.ufshc: ufshcd_get_max_pwr_mode: >>>>> invalid max pwm tx gear read = 0 >>>>> [ 6.983306] ufshcd-qcom 1da4000.ufshc: ufshcd_probe_hba: Failed >>>>> getting max supported power mode >>>>> [ 8.506314] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: >>>>> Sending flag query for idn 3 failed, err = -11 >>>>> [ 10.010352] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: >>>>> Sending flag query for idn 3 failed, err = -11 >>>>> [ 11.514313] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: >>>>> Sending flag query for idn 3 failed, err = -11 >>>>> [ 11.514412] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: >>>>> query attribute, opcode 5, idn 3, failed with error -11 after 3 >>>>> retires >>>>> [ 13.050354] ufshcd-qcom 1da4000.ufshc: >>>>> __ufshcd_query_descriptor: opcode 0x01 for idn 8 failed, index 0, >>>>> err = -11 >>>>> [ 14.554313] ufshcd-qcom 1da4000.ufshc: >>>>> __ufshcd_query_descriptor: opcode 0x01 for idn 8 failed, index 0, >>>>> err = -11 >>>>> [ 16.058313] ufshcd-qcom 1da4000.ufshc: >>>>> __ufshcd_query_descriptor: opcode 0x01 for idn 8 failed, index 0, >>>>> err = -11 >>>>> [ 16.058421] ufshcd-qcom 1da4000.ufshc: ufshcd_read_desc_param: >>>>> Failed reading descriptor. desc_id 8, desc_index 0, param_offset 0, >>>>> ret -11 >>>>> [ 16.067654] ufshcd-qcom 1da4000.ufshc: ufshcd_init_icc_levels: >>>>> Failed reading power descriptor.len = 98 ret = -11 >>>>> [ 37.074334] ufshcd-qcom 1da4000.ufshc: link startup failed 1 >>>> >>>> Can you check if your UFS device RESET_N is asserted correctly. It >>>> might >>>> be connected to some regulator and may be you can try keeping that >>>> regulator as "regulator-always-on" from your DT node. >>> >>> How do I check RESET_N? In software or hardware? >>> >> RST_N is the reset logic for UFS device core logic and it is input to >> the device from UFS host controller.So, in your platform please check if >> this line somehow connected to (pulled up) a PMIC supply. If that is the >> case, please keep that regulator ON and see if this issue is resolved. > > The reset line is routed though the global clock controller (GCC), and > must be explicitly asserted within the GCC to trigger a reset. As far > as I am aware, Linux is not touching this. > > Additionally, I fail to see how if this was a reset issue, reverting > 60f0187031c0 would have any impact (which doing so addresses our issue) > OK, that's again implementation dependent and your platform used that way. My point was to make sure that reset part is ok, if reset/power is not proper to the UFS device core logic this kind of issues comes. >>> Do you think it is not a good idea to revert >>> 60f0187031c05e04cbadffb62f557d0ff3564490 ? >>> >> Please hold on till we understand the real caus
Re: [PATCH v3 5/5] Revert "scsi: ufs: disable vccq if it's not needed by UFS device"
On 08/02/19 8:29 PM, Jeffrey Hugo wrote: > On 2/8/2019 2:09 AM, Alim Akhtar wrote: >> Hi Jeffrey, >> >> On 07/02/19 8:22 PM, Jeffrey Hugo wrote: >>> On 2/7/2019 1:50 AM, Alim Akhtar wrote: >>>> Hi Marc, >>>> >>>> On 06/02/19 9:22 PM, Marc Gonzalez wrote: >>>>> On 06/02/2019 16:27, Alim Akhtar wrote: >>>>> >>>>>> On 06/02/19 8:29 PM, Marc Gonzalez wrote: >>>>>> >>>>>>> [ 2.405734] regulator_disable: ENTER vdd_l26 >>>>>>> [ 2.405958] regulator_disable: EXIT vdd_l26 >>>>>>> [ 2.406032] regulator_set_load: vdd_l26 = 0 uA >>>>>>> [ 3.930447] ufshcd-qcom 1da4000.ufshc: ufshcd_query_attr: opcode >>>>>>> 0x04 for idn 13 failed, index 0, err = -11 >>>>>>> [ 5.434358] ufshcd-qcom 1da4000.ufshc: ufshcd_query_attr: opcode >>>>>>> 0x04 for idn 13 failed, index 0, err = -11 >>>>>>> [ 6.938318] ufshcd-qcom 1da4000.ufshc: ufshcd_query_attr: opcode >>>>>>> 0x04 for idn 13 failed, index 0, err = -11 >>>>>>> [ 6.938414] ufshcd-qcom 1da4000.ufshc: ufshcd_query_attr_retry: >>>>>>> query attribute, idn 13, failed with error -11 after 3 retires >>>>>>> [ 6.946959] ufshcd-qcom 1da4000.ufshc: >>>>>>> ufshcd_disable_auto_bkops: failed to enable exception event -11 >>>>>>> [ 6.958523] ufshcd-qcom 1da4000.ufshc: dme-peer-get: attr-id >>>>>>> 0x1587 failed 3 retries >>>>>>> [ 6.967730] ufshcd-qcom 1da4000.ufshc: dme-peer-get: attr-id >>>>>>> 0x1586 failed 3 retries >>>>>>> [ 6.975576] ufshcd-qcom 1da4000.ufshc: ufshcd_get_max_pwr_mode: >>>>>>> invalid max pwm tx gear read = 0 >>>>>>> [ 6.983306] ufshcd-qcom 1da4000.ufshc: ufshcd_probe_hba: Failed >>>>>>> getting max supported power mode >>>>>>> [ 8.506314] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: >>>>>>> Sending flag query for idn 3 failed, err = -11 >>>>>>> [ 10.010352] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: >>>>>>> Sending flag query for idn 3 failed, err = -11 >>>>>>> [ 11.514313] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: >>>>>>> Sending flag query for idn 3 failed, err = -11 >>>>>>> [ 11.514412] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: >>>>>>> query attribute, opcode 5, idn 3, failed with error -11 after 3 >>>>>>> retires >>>>>>> [ 13.050354] ufshcd-qcom 1da4000.ufshc: >>>>>>> __ufshcd_query_descriptor: opcode 0x01 for idn 8 failed, index 0, >>>>>>> err = -11 >>>>>>> [ 14.554313] ufshcd-qcom 1da4000.ufshc: >>>>>>> __ufshcd_query_descriptor: opcode 0x01 for idn 8 failed, index 0, >>>>>>> err = -11 >>>>>>> [ 16.058313] ufshcd-qcom 1da4000.ufshc: >>>>>>> __ufshcd_query_descriptor: opcode 0x01 for idn 8 failed, index 0, >>>>>>> err = -11 >>>>>>> [ 16.058421] ufshcd-qcom 1da4000.ufshc: ufshcd_read_desc_param: >>>>>>> Failed reading descriptor. desc_id 8, desc_index 0, param_offset 0, >>>>>>> ret -11 >>>>>>> [ 16.067654] ufshcd-qcom 1da4000.ufshc: ufshcd_init_icc_levels: >>>>>>> Failed reading power descriptor.len = 98 ret = -11 >>>>>>> [ 37.074334] ufshcd-qcom 1da4000.ufshc: link startup failed 1 >>>>>> >>>>>> Can you check if your UFS device RESET_N is asserted correctly. It >>>>>> might >>>>>> be connected to some regulator and may be you can try keeping that >>>>>> regulator as "regulator-always-on" from your DT node. >>>>> >>>>> How do I check RESET_N? In software or hardware? >>>>> >>>> RST_N is the reset logic for UFS device core logic and it is input to >>>> the device from UFS host controller.So, in your platform please >>>> check if >>>> this line somehow connected to (pulled up) a PMIC supply. If that is >>>> the >>>> case, please keep that regulator ON and see if this issue is resolved. >>> >>> The reset line is routed though the global clock controller (GCC), and >>> must be explicitl
Re: Request for opinion: ufsutils
On 12/02/19 2:29 AM, Avri Altman wrote: > Hello Pedro, > >> >> Hello everyone, >> >> We are planning to build an open source tool for UFS, (let's name it >> "ufsutils"). The idea is to interact with the ufs driver for debug and test >> purposes. For us it would be useful for scenarios like bring up of new >> hardware, >> debug while adding new features, force specific conditions for testing, check >> specific registers from any of the layers (UFS/UniPro/MPhy) at any time... >> >> We would like to check with you what would be the advisable method to >> interact >> with the driver from user-space (sysfs, debugFS, ioctls, etc.). I am aware of >> the ioctl through sg but we may have use cases without a device. >> >> Do you think this would be useful for you? Any suggestions? > Great minds think alike :) > Actually, we already did all that: we introduced a new bsg companion to the > ufs driver, > To support the very exactly ufs-utils. It was merged in 4.20. > You can look it up using "scsi: Add ufs bsg endpoint". > We also have a supplementary short series, see > https://www.spinics.net/lists/linux-scsi/msg127370.html. > We are about to publish ufs-utils in the coming days. > Good Work, will be really good to have this for UFS community. > Thanks, > Avri >
Re: [PATCH v5 0/2] Clean up UFSHC driver
Hi Marc, On 11/02/19 7:01 PM, Marc Gonzalez wrote: > Casting a wide net to get as many eyeballs on the subject as possible. > > I'm splitting this mini series off from the main "UFS on APQ8098/MSM8998" > as it's 1) ufs/scsi specific 2) controversial (to my surprise) > > Please send all your Reviewed-by: tags if you agree with the patch, > and/or voice your concerns ASAP. > > This series removes the "disable-VCCQ-power-rail-for-some-Flash-chips" quirk, > and cleans up after the dust settles. > > Marc Gonzalez (2): >scsi: ufs: Do not disable vccq in UFSHC driver >scsi: ufs: Remove unused device quirks > > drivers/scsi/ufs/ufs.h| 1 - > drivers/scsi/ufs/ufs_quirks.h | 29 > drivers/scsi/ufs/ufshcd.c | 63 +++ > 3 files changed, 4 insertions(+), 89 deletions(-) > For this series Reviewed-by: Alim Akhtar As no other platform has claimed issues with this we can land this. Others let us know if your opinion differs here. Acked-by: Alim Akhtar Thanks!
