Re: [PATCH 20/22] scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error

2017-06-13 Thread John Garry 

On 17/05/2017 13:38, John Garry wrote:

On 17/05/2017 13:27, Arnd Bergmann wrote:

On Wed, May 17, 2017 at 12:49 PM, John Garry 
wrote:

> From: Xiang Chen 
>
> For ECC 1bit error, logic can recover it, so we only print a warning.
> For ECC multi-bit and AXI bus fatal error, we panic.
>
> Signed-off-by: John Garry 
> Signed-off-by: Xiang Chen 

This one is tricky as there are conflicting requirements:

- For debugging purposes, you want to continue running the system
  to figure out what exactly went wrong. Often enough, having the
  kernel panic means you don't get to see the panic message because
  console access is unavailable and you cannot log in any more

- For data consistency purposes you want to stop the system as
  soon as there is any uncorrectable data error

I see that most scsi drivers don't ever call panic or BUG(), though
you already do so for v1 and v2 hw.

Maybe the SCSI maintainers can provide some more guidance here.

  Arnd

.



Hi Arnd,

Actually latest code for v2 has been updated to do a controller reset,
and not panic, for unrecoverable error:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c?h=v4.12-rc1#n2926


We never got around to implementing controller reset for v1 as this
platform (hip05) is not used much anymore.

As for v3, we will change to to do same once controller reset is
implemented. I should have added this to the commit log.

Thanks,
John


It has come to light that hip08 RAS architecture requires handling 
certain errors with firmware first model. I am not sure on the flow of 
controller reset for fatal errors - I'm currently checking the details.


But it is not worth adding this non-critical patch and reverting it 
later, so I'll omit this patch when sending the v6 patchset which 
includes the fix for sloppy spinlock usage.


Thanks,
John

Re: [PATCH 20/22] scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error

2017-05-17 Thread John Garry 

On 17/05/2017 13:27, Arnd Bergmann wrote:

On Wed, May 17, 2017 at 12:49 PM, John Garry  wrote:

> From: Xiang Chen 
>
> For ECC 1bit error, logic can recover it, so we only print a warning.
> For ECC multi-bit and AXI bus fatal error, we panic.
>
> Signed-off-by: John Garry 
> Signed-off-by: Xiang Chen 

This one is tricky as there are conflicting requirements:

- For debugging purposes, you want to continue running the system
  to figure out what exactly went wrong. Often enough, having the
  kernel panic means you don't get to see the panic message because
  console access is unavailable and you cannot log in any more

- For data consistency purposes you want to stop the system as
  soon as there is any uncorrectable data error

I see that most scsi drivers don't ever call panic or BUG(), though
you already do so for v1 and v2 hw.

Maybe the SCSI maintainers can provide some more guidance here.

  Arnd

.



Hi Arnd,

Actually latest code for v2 has been updated to do a controller reset, 
and not panic, for unrecoverable error:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c?h=v4.12-rc1#n2926

We never got around to implementing controller reset for v1 as this 
platform (hip05) is not used much anymore.


As for v3, we will change to to do same once controller reset is 
implemented. I should have added this to the commit log.


Thanks,
John

Re: [PATCH 20/22] scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error

2017-05-17 Thread Arnd Bergmann 
On Wed, May 17, 2017 at 12:49 PM, John Garry  wrote:
> From: Xiang Chen 
>
> For ECC 1bit error, logic can recover it, so we only print a warning.
> For ECC multi-bit and AXI bus fatal error, we panic.
>
> Signed-off-by: John Garry 
> Signed-off-by: Xiang Chen 

This one is tricky as there are conflicting requirements:

- For debugging purposes, you want to continue running the system
  to figure out what exactly went wrong. Often enough, having the
  kernel panic means you don't get to see the panic message because
  console access is unavailable and you cannot log in any more

- For data consistency purposes you want to stop the system as
  soon as there is any uncorrectable data error

I see that most scsi drivers don't ever call panic or BUG(), though
you already do so for v1 and v2 hw.

Maybe the SCSI maintainers can provide some more guidance here.

  Arnd

[PATCH 20/22] scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error

2017-05-17 Thread John Garry 
From: Xiang Chen 

For ECC 1bit error, logic can recover it, so we only print a warning.
For ECC multi-bit and AXI bus fatal error, we panic.

Signed-off-by: John Garry 
Signed-off-by: Xiang Chen 
---
 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 401 -
 1 file changed, 399 insertions(+), 2 deletions(-)

diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 
b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index fa686e5..195276b 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -51,7 +51,39 @@
 #define CFG_SET_ABORTED_IPTT_OFF   0
 #define CFG_SET_ABORTED_IPTT_MSK   (0xfff << CFG_SET_ABORTED_IPTT_OFF)
 #define CFG_1US_TIMER_TRSH 0xcc
+#define HGC_LM_DFX_STATUS2 0x128
+#define HGC_LM_DFX_STATUS2_IOSTLIST_OFF0
+#define HGC_LM_DFX_STATUS2_IOSTLIST_MSK(0xfff <<\
+   HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
+#define HGC_LM_DFX_STATUS2_ITCTLIST_OFF12
+#define HGC_LM_DFX_STATUS2_ITCTLIST_MSK(0x7ff <<\
+   HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
+#define HGC_CQE_ECC_ADDR   0x13c
+#define HGC_CQE_ECC_1B_ADDR_OFF0
+#define HGC_CQE_ECC_1B_ADDR_MSK(0x3f << 
HGC_CQE_ECC_1B_ADDR_OFF)
+#define HGC_CQE_ECC_MB_ADDR_OFF8
+#define HGC_CQE_ECC_MB_ADDR_MSK(0x3f << 
HGC_CQE_ECC_MB_ADDR_OFF)
+#define HGC_IOST_ECC_ADDR  0x140
+#define HGC_IOST_ECC_1B_ADDR_OFF   0
+#define HGC_IOST_ECC_1B_ADDR_MSK   (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
+#define HGC_IOST_ECC_MB_ADDR_OFF   16
+#define HGC_IOST_ECC_MB_ADDR_MSK   (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
+#define HGC_DQE_ECC_ADDR   0x144
+#define HGC_DQE_ECC_1B_ADDR_OFF0
+#define HGC_DQE_ECC_1B_ADDR_MSK(0xfff << 
HGC_DQE_ECC_1B_ADDR_OFF)
+#define HGC_DQE_ECC_MB_ADDR_OFF16
+#define HGC_DQE_ECC_MB_ADDR_MSK(0xfff << 
HGC_DQE_ECC_MB_ADDR_OFF)
 #define CHNL_INT_STATUS0x148
+#define HGC_ITCT_ECC_ADDR  0x150
+#define HGC_ITCT_ECC_1B_ADDR_OFF   0
+#define HGC_ITCT_ECC_1B_ADDR_MSK   (0x3ff << HGC_ITCT_ECC_1B_ADDR_OFF)
+#define HGC_ITCT_ECC_MB_ADDR_OFF   16
+#define HGC_ITCT_ECC_MB_ADDR_MSK   (0x3ff << HGC_ITCT_ECC_MB_ADDR_OFF)
+#define HGC_AXI_FIFO_ERR_INFO  0x154
+#define AXI_ERR_INFO_OFF   0
+#define AXI_ERR_INFO_MSK   (0xff << AXI_ERR_INFO_OFF)
+#define FIFO_ERR_INFO_OFF  8
+#define FIFO_ERR_INFO_MSK  (0xff << FIFO_ERR_INFO_OFF)
 #define INT_COAL_EN0x19c
 #define OQ_INT_COAL_TIME   0x1a0
 #define OQ_INT_COAL_CNT0x1a4
@@ -85,6 +117,26 @@
 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
 #define SAS_ECC_INTR   0x1e8
 #define SAS_ECC_INTR_MSK   0x1ec
+#define SAS_ECC_INTR_DQE_ECC_1B_OFF0
+#define SAS_ECC_INTR_DQE_ECC_MB_OFF1
+#define SAS_ECC_INTR_IOST_ECC_1B_OFF   2
+#define SAS_ECC_INTR_IOST_ECC_MB_OFF   3
+#define SAS_ECC_INTR_ITCT_ECC_MB_OFF   4
+#define SAS_ECC_INTR_ITCT_ECC_1B_OFF   5
+#define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF   6
+#define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF   7
+#define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF   8
+#define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF   9
+#define SAS_ECC_INTR_CQE_ECC_1B_OFF10
+#define SAS_ECC_INTR_CQE_ECC_MB_OFF11
+#define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF   12
+#define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF   13
+#define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF   14
+#define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF   15
+#define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF   16
+#define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF   17
+#define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF   18
+#define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF   19
 #define HGC_ERR_STAT_EN0x238
 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
@@ -98,6 +150,20 @@
 #define COMPL_Q_0_DEPTH0x4e8
 #define COMPL_Q_0_WR_PTR   0x4ec
 #define COMPL_Q_0_RD_PTR   0x4f0
+#define HGC_RXM_DFX_STATUS14   0xae8
+#define HGC_RXM_DFX_STATUS14_MEM0_OFF  0
+#define HGC_RXM_DFX_STATUS14_MEM0_MSK  (0x1ff <<\
+   HGC_RXM_DFX_STATUS14_MEM0_OFF)
+#define HGC_RXM_DFX_STATUS14_MEM1_OFF  9
+#define HGC_RXM_DFX_STATUS14_MEM1_MSK  (0x1ff <<\
+   HGC_RXM_DFX_STATUS14_MEM1_OFF)
+#define HGC_RXM_DFX_STATUS14_MEM2_OFF  18
+#define HGC_RXM_DFX_STATUS14_MEM2_MSK  (0x1ff <<\
+   HGC_RXM_DFX_STATUS14_MEM2_OFF)
+#define HGC_RXM_DFX_STATUS15