[PATCH v17 1/4] arm64: Add APM X-Gene SoC 15Gbps Multi-purpose PHY DTS entries

[Loc Ho]

This patch adds the DTS entries for the APM X-Gene SoC 15Gbps Multi-purpose
PHY driver. The PHY for SATA controller 2 and 3 are enabled by default.

Signed-off-by: Loc Ho 
Signed-off-by: Tuan Phan 
Signed-off-by: Suman Tripathi 
---
 arch/arm64/boot/dts/apm-storm.dtsi |   75 
 1 files changed, 75 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/boot/dts/apm-storm.dtsi 
b/arch/arm64/boot/dts/apm-storm.dtsi
index d37d736..c78ddcf 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -176,6 +176,51 @@
reg-names = "csr-reg";
clock-output-names = "eth8clk";
};
+
+   sataphy1clk: sataphy1clk@1f21c000 {
+   compatible = "apm,xgene-device-clock";
+   #clock-cells = <1>;
+   clocks = <&socplldiv2 0>;
+   clock-names = "socplldiv2";
+   reg = <0x0 0x1f21c000 0x0 0x1000>;
+   reg-names = "csr-reg";
+   clock-output-names = "sataphy1clk";
+   status = "disabled";
+   csr-offset = <0x4>;
+   csr-mask = <0x00>;
+   enable-offset = <0x0>;
+   enable-mask = <0x06>;
+   };
+
+   sataphy2clk: sataphy1clk@1f22c000 {
+   compatible = "apm,xgene-device-clock";
+   #clock-cells = <1>;
+   clocks = <&socplldiv2 0>;
+   clock-names = "socplldiv2";
+   reg = <0x0 0x1f22c000 0x0 0x1000>;
+   reg-names = "csr-reg";
+   clock-output-names = "sataphy2clk";
+   status = "ok";
+   csr-offset = <0x4>;
+   csr-mask = <0x3a>;
+   enable-offset = <0x0>;
+   enable-mask = <0x06>;
+   };
+
+   sataphy3clk: sataphy1clk@1f23c000 {
+   compatible = "apm,xgene-device-clock";
+   #clock-cells = <1>;
+   clocks = <&socplldiv2 0>;
+   clock-names = "socplldiv2";
+   reg = <0x0 0x1f23c000 0x0 0x1000>;
+   reg-names = "csr-reg";
+   clock-output-names = "sataphy3clk";
+   status = "ok";
+   csr-offset = <0x4>;
+   csr-mask = <0x3a>;
+   enable-offset = <0x0>;
+   enable-mask = <0x06>;
+   };
};
 
serial0: serial@1c02 {
@@ -187,5 +232,35 @@
interrupt-parent = <&gic>;
interrupts = <0x0 0x4c 0x4>;
};
+
+   phy1: phy@1f21a000 {
+   compatible = "apm,xgene-phy";
+   reg = <0x0 0x1f21a000 0x0 0x100>;
+   #phy-cells = <1>;
+   clocks = <&sataphy1clk 0>;
+   status = "disabled";
+   apm,tx-boost-gain = <30 30 30 30 30 30>;
+   apm,tx-eye-tuning = <2 10 10 2 10 10>;
+   };
+
+   phy2: phy@1f22a000 {
+   compatible = "apm,xgene-phy";
+   reg = <0x0 0x1f22a000 0x0 0x100>;
+   #phy-cells = <1>;
+   clocks = <&sataphy2clk 0>;
+   status = "ok";
+   apm,tx-boost-gain = <30 30 30 30 30 30>;
+   apm,tx-eye-tuning = <1 10 10 2 10 10>;
+   };
+
+   phy3: phy@1f23a000 {
+   compatible = "apm,xgene-phy";
+   reg = <0x0 0x1f23a000 0x0 0x100>;
+   #phy-cells = <1>;
+   clocks = <&sataphy3clk 0>;
+   status = "ok";
+   apm,tx-boost-gain = <31 31 31 31 31 31>;
+   apm,tx-eye-tuning = <2 10 10 2 10 10>;
+   };
};
 };
-- 
1.5.5

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Re: [PATCH v17 1/4] arm64: Add APM X-Gene SoC 15Gbps Multi-purpose PHY DTS entries

[Arnd Bergmann]

On Wednesday 12 March 2014, Loc Ho wrote:
> +   sataphy1clk: sataphy1clk@1f21c000 {
> +   compatible = "apm,xgene-device-clock";
> +   #clock-cells = <1>;
> +   clocks = <&socplldiv2 0>;
> +   clock-names = "socplldiv2";

I think we still need to resolve the question regarding the
"clock-names" properties in your clock provider nodes. I've commented
on this in the past, since it shows up in all the x-gene drivers,
but it's very inconsistent.

The binding says

+- clock-names : shall be the name of the device clock. If missing, use the
+device name.

which to me makes no sense. What will "use the device name", and
which device? Your clock driver doesn't actually use these strings,
so could you please fix the binding to remove this, and stop adding
the strings to any clock nodes?

Since nothing ever used these and they are marked "optional"
in the binding, I don't think there is a chance of breaking
anything by changing it now.

Arnd
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