Adding new ARC platforms (was Re: Handling stub code for new platforms)
Hi Alexandru,
On 08/11/2017 12:58 AM, Alexandru Gagniuc wrote:
Hi,
Looking under arch/arc, I see the current way is to add a plat-[socname] for each
new SoC. However, it seems that plat-sim, and plat-tb10x are just place-holders
for the compatible bindings.
I was going to do the same for plat-anarion, which required an early boot
workaround. However, with Alexey's INTC patch, this workaround is no longer
required, so plat-anarion would become just another stub.
I don't like the idea of adding dead code whenever a new platform arrives. My
thought is to merge these into a plat-generic, and add the following two
compatible bindings:
* "snps,arccompact-generic"
* "snps,arcv2-generic"
Keep the existing bindings for compatibility reasons, but require all new
platforms that don't need boot stubs to use one of the generic .compatible
bindings. Do you agree with the plan?
Your proposal is reasonable but I'd still prefer the explicit platform/soC binding
for calling out the various arc based platforms if nothing else !
However the boilerplate code can be pretty minimal ! If the platform is simple
enough, no need for any new Kconfig entries. I've already eliminated
CONFIG_ARC_PLAT_SIM (look at my #for-curr in kernel.org repo / linux-next)
So you just need to
1. create plat-xxx/{Makefile, platform.c} and a simple board description in
latter.
2. And add this platform unconditionally to arch/arc/Makefile
Does that work for you ?
-Vineet
___
linux-snps-arc mailing list
linux-snps-arc@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Handling stub code for new platforms
Hi, Looking under arch/arc, I see the current way is to add a plat-[socname] for each new SoC. However, it seems that plat-sim, and plat-tb10x are just place-holders for the compatible bindings. I was going to do the same for plat-anarion, which required an early boot workaround. However, with Alexey's INTC patch, this workaround is no longer required, so plat-anarion would become just another stub. I don't like the idea of adding dead code whenever a new platform arrives. My thought is to merge these into a plat-generic, and add the following two compatible bindings: * "snps,arccompact-generic" * "snps,arcv2-generic" Keep the existing bindings for compatibility reasons, but require all new platforms that don't need boot stubs to use one of the generic .compatible bindings. Do you agree with the plan? Alex ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH] arc: Mask individual IRQ lines during core INTC init
On 08/10/2017 08:07 AM, Alexey Brodkin wrote:
ARC cores on reset have all interrupt lines of built-in INTC enabled.
Which means once we globally enable interrupts (very early on boot)
faulty hardware blocks may trigger an interrupt that Linux kernel
cannot handle yet as corresponding handler is not yet installed.
In that case system falls in "interrupt storm" and basically never
does anything useful except entering and exiting generic IRQ handling
code.
One real example of that kind of problematic hardware is DW GMAC which
also has interrupts enabled on reset and if Ethernet PHY informs GMAC
about link state, GMAC immediately reports that upstream to ARC core
and here we are.
Now with that change we mask all individual IRQ lines making entire
system more fool-proof.
Signed-off-by: Alexey Brodkin
Cc: Eugeniy Paltsev
Cc: Alexandru Gagniuc
Tested-by: Alexandru Gagniuc
---
arch/arc/kernel/intc-arcv2.c | 3 +++
arch/arc/kernel/intc-compact.c | 14 +-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
index f928795fd07a..cf90714a676d 100644
--- a/arch/arc/kernel/intc-arcv2.c
+++ b/arch/arc/kernel/intc-arcv2.c
@@ -75,10 +75,13 @@ void arc_init_IRQ(void)
* Set a default priority for all available interrupts to prevent
* switching of register banks if Fast IRQ and multiple register banks
* are supported by CPU.
+* Also disable all IRQ lines so faulty external hardware won't
+* trigger interrupt that kernel is not ready to handle.
*/
for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
write_aux_reg(AUX_IRQ_SELECT, i);
write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
+ write_aux_reg(AUX_IRQ_ENABLE, 0);
}
/* setup status32, don't enable intr yet as kernel doesn't want */
diff --git a/arch/arc/kernel/intc-compact.c b/arch/arc/kernel/intc-compact.c
index 7e608c6b0a01..cef388025adf 100644
--- a/arch/arc/kernel/intc-compact.c
+++ b/arch/arc/kernel/intc-compact.c
@@ -27,7 +27,7 @@
*/
void arc_init_IRQ(void)
{
- int level_mask = 0;
+ int level_mask = 0, i;
/* Is timer high priority Interrupt (Level2 in ARCompact jargon) */
level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ;
@@ -40,6 +40,18 @@ void arc_init_IRQ(void)
if (level_mask)
pr_info("Level-2 interrupts bitset %x\n", level_mask);
+
+ /*
+* Disable all IRQ lines so faulty external hardware won't
+* trigger interrupt that kernel is not ready to handle.
+*/
+ for (i = TIMER0_IRQ; i < NR_CPU_IRQS; i++) {
+ unsigned int ienb;
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb &= ~(1 << i);
+ write_aux_reg(AUX_IENABLE, ienb);
+ }
}
/*
___
linux-snps-arc mailing list
linux-snps-arc@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH] ARC: reset: introduce AXS10x reset driver
ARC AXS10x boards support custom IP-block which allows to control
reset signals of selected peripherals. For example DW GMAC, etc...
This block is controlled via memory-mapped register (AKA CREG) which
represents up-to 32 reset lines.
As of today only the following lines are used:
- DW GMAC - line 5
Signed-off-by: Eugeniy Paltsev
---
.../bindings/reset/snps,axs10x-reset.txt | 34 +++
MAINTAINERS| 6 ++
drivers/reset/Kconfig | 6 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-axs10x.c | 109 +
5 files changed, 156 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt
create mode 100644 drivers/reset/reset-axs10x.c
diff --git a/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt
b/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt
new file mode 100644
index 000..32eed7a
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt
@@ -0,0 +1,34 @@
+Binding for the AXS10x reset controller
+
+This binding describes the ARC AXS10x boards custom IP-block which allows
+to control reset signals of selected peripherals. For example DW GMAC, etc...
+This block is controlled via memory-mapped register (AKA CREG) which
+represents up-to 32 reset lines.
+
+As of today only the following lines are used:
+ - DW GMAC - line 5
+
+This binding uses the common reset binding[1].
+
+[1] Documentation/devicetree/bindings/reset/reset.txt
+
+Required properties:
+- compatible: should be "snps,axs10x-reset".
+- reg: should always contain pair address - length: for creg reset
+ bits register.
+- #reset-cells: from common reset binding; Should always be set to 1.
+
+Example:
+ reset: reset@11220 {
+ compatible = "snps,axs10x-reset";
+ #reset-cells = <1>;
+ reg = <0x11220 0x4>;
+ };
+
+Specifying reset lines connected to IP modules:
+ ethernet@ {
+
+ resets = <&reset 5>;
+
+ };
+
diff --git a/MAINTAINERS b/MAINTAINERS
index 93dfb9d..f14e804 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12711,6 +12711,12 @@ F: arch/arc/plat-axs10x
F: arch/arc/boot/dts/ax*
F: Documentation/devicetree/bindings/arc/axs10*
+SYNOPSYS AXS10x RESET CONTROLLER DRIVER
+M: Eugeniy Paltsev
+S: Supported
+F: drivers/reset/reset-axs10x.c
+F: Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt
+
SYNOPSYS DESIGNWARE DMAC DRIVER
M: Viresh Kumar
M: Andy Shevchenko
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 52d5251..65d13f4 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -28,6 +28,12 @@ config RESET_ATH79
This enables the ATH79 reset controller driver that supports the
AR71xx SoC reset controller.
+config RESET_AXS10X
+ bool "AXS10x Reset Driver" if COMPILE_TEST
+ default ARC_PLAT_AXS10X
+ help
+ This enables the reset controller driver for AXS10x.
+
config RESET_BERLIN
bool "Berlin Reset Driver" if COMPILE_TEST
default ARCH_BERLIN
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index b62783f..45000a5 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_STI) += sti/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
+obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
obj-$(CONFIG_RESET_HSDK_V1) += reset-hsdk-v1.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
diff --git a/drivers/reset/reset-axs10x.c b/drivers/reset/reset-axs10x.c
new file mode 100644
index 000..17a4cb4
--- /dev/null
+++ b/drivers/reset/reset-axs10x.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2017 Synopsys.
+ *
+ * Synopsys AXS10x reset driver.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define to_axs10x_rst(p) container_of((p), struct axs10x_rst, rcdev)
+
+#define AXS10X_MAX_RESETS 32
+
+struct axs10x_rst {
+ void __iomem*regs_rst;
+ spinlock_t lock;
+ struct reset_controller_dev rcdev;
+};
+
+static int axs10x_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct axs10x_rst *rst = to_axs10x_rst(rcdev);
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(&rst->lock, flags);
+ reg = readl(rst->regs_rst);
+ reg |= BIT(id);
+ writel(reg, rst->regs_rst);
+ spin_unlock_i
[PATCH] arc: Mask individual IRQ lines during core INTC init
ARC cores on reset have all interrupt lines of built-in INTC enabled.
Which means once we globally enable interrupts (very early on boot)
faulty hardware blocks may trigger an interrupt that Linux kernel
cannot handle yet as corresponding handler is not yet installed.
In that case system falls in "interrupt storm" and basically never
does anything useful except entering and exiting generic IRQ handling
code.
One real example of that kind of problematic hardware is DW GMAC which
also has interrupts enabled on reset and if Ethernet PHY informs GMAC
about link state, GMAC immediately reports that upstream to ARC core
and here we are.
Now with that change we mask all individual IRQ lines making entire
system more fool-proof.
Signed-off-by: Alexey Brodkin
Cc: Eugeniy Paltsev
Cc: Alexandru Gagniuc
---
arch/arc/kernel/intc-arcv2.c | 3 +++
arch/arc/kernel/intc-compact.c | 14 +-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
index f928795fd07a..cf90714a676d 100644
--- a/arch/arc/kernel/intc-arcv2.c
+++ b/arch/arc/kernel/intc-arcv2.c
@@ -75,10 +75,13 @@ void arc_init_IRQ(void)
* Set a default priority for all available interrupts to prevent
* switching of register banks if Fast IRQ and multiple register banks
* are supported by CPU.
+* Also disable all IRQ lines so faulty external hardware won't
+* trigger interrupt that kernel is not ready to handle.
*/
for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
write_aux_reg(AUX_IRQ_SELECT, i);
write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
+ write_aux_reg(AUX_IRQ_ENABLE, 0);
}
/* setup status32, don't enable intr yet as kernel doesn't want */
diff --git a/arch/arc/kernel/intc-compact.c b/arch/arc/kernel/intc-compact.c
index 7e608c6b0a01..cef388025adf 100644
--- a/arch/arc/kernel/intc-compact.c
+++ b/arch/arc/kernel/intc-compact.c
@@ -27,7 +27,7 @@
*/
void arc_init_IRQ(void)
{
- int level_mask = 0;
+ int level_mask = 0, i;
/* Is timer high priority Interrupt (Level2 in ARCompact jargon) */
level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ;
@@ -40,6 +40,18 @@ void arc_init_IRQ(void)
if (level_mask)
pr_info("Level-2 interrupts bitset %x\n", level_mask);
+
+ /*
+* Disable all IRQ lines so faulty external hardware won't
+* trigger interrupt that kernel is not ready to handle.
+*/
+ for (i = TIMER0_IRQ; i < NR_CPU_IRQS; i++) {
+ unsigned int ienb;
+
+ ienb = read_aux_reg(AUX_IENABLE);
+ ienb &= ~(1 << i);
+ write_aux_reg(AUX_IENABLE, ienb);
+ }
}
/*
--
2.7.5
___
linux-snps-arc mailing list
linux-snps-arc@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-snps-arc
