Re: [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency

[Eugeniy Paltsev]

On Tue, 2017-09-12 at 11:38 -0700, Vineet Gupta wrote:
> On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote:
> > DW sdio controller has external ciu clock divider controlled
> > via register in SDIO IP. It divides sdio_ref_clk
> > (which comes from CGU) by 16 for default. So default mmcclk
> > clock (which comes to sdk_in) is 2500 Hz.
> > 
> > So fix wrong current value (5000 Hz) to actual 2500 Hz.
> 
> Is this a preventive fix or there are known issues with what we have today.

Yes, it's kinda a preventive fix.
We check axs10x ciu frequency when we found what hsdk ciu frequency was wrong
and found that it is wring too.

I tried to run SD stress test with wrong ciu frequency (5000 Hz) and it 
passed
successfully, but we must take into account the fact that it depends on SD
card itself. For example: this SD card mostly works fine on HSDK with ciu 
frequency 8x times higher than expected!

Alexey says that he faced with unstable SD card work on axs103 earlier but
he didn't save any artifacts about it.

> Is this triggered after addition of AXS clk driver ?
No.

> > 
> > Signed-off-by: Eugeniy Paltsev 
> > ---
> >   arch/arc/boot/dts/axs10x_mb.dtsi | 9 -
> >   1 file changed, 8 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi 
> > b/arch/arc/boot/dts/axs10x_mb.dtsi
> > index 0ff7e07..7bdf581 100644
> > --- a/arch/arc/boot/dts/axs10x_mb.dtsi
> > +++ b/arch/arc/boot/dts/axs10x_mb.dtsi
> > @@ -44,7 +44,14 @@
> >   
> >     mmcclk: mmcclk {
> >     compatible = "fixed-clock";
> > -   clock-frequency = <5000>;
> > +   /*
> > +    * DW sdio controller has external ciu clock 
> > divider
> > +    * controlled via register in SDIO IP. It 
> > divides
> > +    * sdio_ref_clk (which comes from CGU) by 16 for
> > +    * default. So default mmcclk clock (which comes
> > +    * to sdk_in) is 2500 Hz.
> > +    */
> > +   clock-frequency = <2500>;
> >     #clock-cells = <0>;
> >     };
> >   
> 
> 
-- 
 Eugeniy Paltsev
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Re: [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency

[Vineet Gupta]

On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote:

DW sdio controller has external ciu clock divider controlled
via register in SDIO IP. It divides sdio_ref_clk
(which comes from CGU) by 16 for default. So default mmcclk
clock (which comes to sdk_in) is 2500 Hz.

So fix wrong current value (5000 Hz) to actual 2500 Hz.


Is this a preventive fix or there are known issues with what we have today.
Is this triggered after addition of AXS clk driver ?



Signed-off-by: Eugeniy Paltsev 
---
  arch/arc/boot/dts/axs10x_mb.dtsi | 9 -
  1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index 0ff7e07..7bdf581 100644
--- a/arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/axs10x_mb.dtsi
@@ -44,7 +44,14 @@
  
  			mmcclk: mmcclk {

compatible = "fixed-clock";
-   clock-frequency = <5000>;
+   /*
+* DW sdio controller has external ciu clock 
divider
+* controlled via register in SDIO IP. It 
divides
+* sdio_ref_clk (which comes from CGU) by 16 for
+* default. So default mmcclk clock (which comes
+* to sdk_in) is 2500 Hz.
+*/
+   clock-frequency = <2500>;
#clock-cells = <0>;
};
  



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[PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency

[Eugeniy Paltsev]

DW sdio controller has external ciu clock divider controlled
via register in SDIO IP. It divides sdio_ref_clk
(which comes from CGU) by 16 for default. So default mmcclk
clock (which comes to sdk_in) is 2500 Hz.

So fix wrong current value (5000 Hz) to actual 2500 Hz.

Signed-off-by: Eugeniy Paltsev 
---
 arch/arc/boot/dts/axs10x_mb.dtsi | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index 0ff7e07..7bdf581 100644
--- a/arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/axs10x_mb.dtsi
@@ -44,7 +44,14 @@
 
mmcclk: mmcclk {
compatible = "fixed-clock";
-   clock-frequency = <5000>;
+   /*
+* DW sdio controller has external ciu clock 
divider
+* controlled via register in SDIO IP. It 
divides
+* sdio_ref_clk (which comes from CGU) by 16 for
+* default. So default mmcclk clock (which comes
+* to sdk_in) is 2500 Hz.
+*/
+   clock-frequency = <2500>;
#clock-cells = <0>;
};
 
-- 
2.9.3


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