Re: [PATCH 2/2] ARC: mm: fix new code about cache aliasing
On 3/28/24 06:57, Mathieu Desnoyers wrote:
> On 2024-03-28 01:39, Vineet Gupta wrote:
>> Manual/partial revert of 8690bbcf3b70 ("Introduce cpu_dcache_is_aliasing()
>> across all architectures")
>>
>> Current generation of ARCv2/ARCv3 based HSxx cores are only PIPT (to software
>> at least).
>>
>> Legacy ARC700 cpus could be VIPT aliasing (based on cache geometry and
>> PAGE_SIZE) however recently that support was ripped out so VIPT aliasing
>> cache is not relevant to ARC anymore.
>>
>> P.S. : This has been discussed a few times on lists [1]
>> P.S.2: Please CC the arch maintainers and/or mailing list before adding
>> such interfaces.
> Because 8690bbcf3b70 was introducing a tree-wide change affecting all
> architectures, I CC'd linux-a...@vger.kernel.org. I expected all
> architecture maintainers to follow that list, which is relatively
> low volume.
Ideally yeah arch maintainers should be lurking there.
> I'm sorry that you learn about this after the fact as a result.
Please don't be, no harm done, the fix was easy ;-)
> My intent was to use the list rather than CC about 50 additional
> people/mailing lists.
That is true but I don't think maintainers mind that in general. I still
posit that any new interfaces to arch code should be explicitly run by them.
> Of course, if VIPT aliasing is removed from ARC, removing the
> config ARCH_HAS_CPU_CACHE_ALIASING and using the generic
> cpu_dcache_is_aliasing() is the way to go. Feel free to add
> my:
>
> Acked-by: Mathieu Desnoyers
Thx,
-Vineet
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Re: [PATCH 2/2] ARC: mm: fix new code about cache aliasing
On 2024-03-28 01:39, Vineet Gupta wrote:
Manual/partial revert of 8690bbcf3b70 ("Introduce cpu_dcache_is_aliasing() across
all architectures")
Current generation of ARCv2/ARCv3 based HSxx cores are only PIPT (to software
at least).
Legacy ARC700 cpus could be VIPT aliasing (based on cache geometry and
PAGE_SIZE) however recently that support was ripped out so VIPT aliasing
cache is not relevant to ARC anymore.
P.S. : This has been discussed a few times on lists [1]
P.S.2: Please CC the arch maintainers and/or mailing list before adding
such interfaces.
Because 8690bbcf3b70 was introducing a tree-wide change affecting all
architectures, I CC'd linux-a...@vger.kernel.org. I expected all
architecture maintainers to follow that list, which is relatively
low volume.
I'm sorry that you learn about this after the fact as a result.
My intent was to use the list rather than CC about 50 additional
people/mailing lists.
Of course, if VIPT aliasing is removed from ARC, removing the
config ARCH_HAS_CPU_CACHE_ALIASING and using the generic
cpu_dcache_is_aliasing() is the way to go. Feel free to add
my:
Acked-by: Mathieu Desnoyers
Thanks,
Mathieu
[1]
http://lists.infradead.org/pipermail/linux-snps-arc/2023-February/006899.html
Cc: Mathieu Desnoyers
Signed-off-by: Vineet Gupta
---
arch/arc/Kconfig | 1 -
arch/arc/include/asm/cachetype.h | 9 -
2 files changed, 10 deletions(-)
delete mode 100644 arch/arc/include/asm/cachetype.h
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 99d2845f3feb..4092bec198be 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -6,7 +6,6 @@
config ARC
def_bool y
select ARC_TIMERS
- select ARCH_HAS_CPU_CACHE_ALIASING
select ARCH_HAS_CACHE_LINE_SIZE
select ARCH_HAS_DEBUG_VM_PGTABLE
select ARCH_HAS_DMA_PREP_COHERENT
diff --git a/arch/arc/include/asm/cachetype.h b/arch/arc/include/asm/cachetype.h
deleted file mode 100644
index 05fc7ed59712..
--- a/arch/arc/include/asm/cachetype.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_ARC_CACHETYPE_H
-#define __ASM_ARC_CACHETYPE_H
-
-#include
-
-#define cpu_dcache_is_aliasing() true
-
-#endif
--
Mathieu Desnoyers
EfficiOS Inc.
https://www.efficios.com
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[PATCH 2/2] ARC: mm: fix new code about cache aliasing
Manual/partial revert of 8690bbcf3b70 ("Introduce cpu_dcache_is_aliasing()
across all architectures")
Current generation of ARCv2/ARCv3 based HSxx cores are only PIPT (to software
at least).
Legacy ARC700 cpus could be VIPT aliasing (based on cache geometry and
PAGE_SIZE) however recently that support was ripped out so VIPT aliasing
cache is not relevant to ARC anymore.
P.S. : This has been discussed a few times on lists [1]
P.S.2: Please CC the arch maintainers and/or mailing list before adding
such interfaces.
[1]
http://lists.infradead.org/pipermail/linux-snps-arc/2023-February/006899.html
Cc: Mathieu Desnoyers
Signed-off-by: Vineet Gupta
---
arch/arc/Kconfig | 1 -
arch/arc/include/asm/cachetype.h | 9 -
2 files changed, 10 deletions(-)
delete mode 100644 arch/arc/include/asm/cachetype.h
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 99d2845f3feb..4092bec198be 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -6,7 +6,6 @@
config ARC
def_bool y
select ARC_TIMERS
- select ARCH_HAS_CPU_CACHE_ALIASING
select ARCH_HAS_CACHE_LINE_SIZE
select ARCH_HAS_DEBUG_VM_PGTABLE
select ARCH_HAS_DMA_PREP_COHERENT
diff --git a/arch/arc/include/asm/cachetype.h b/arch/arc/include/asm/cachetype.h
deleted file mode 100644
index 05fc7ed59712..
--- a/arch/arc/include/asm/cachetype.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_ARC_CACHETYPE_H
-#define __ASM_ARC_CACHETYPE_H
-
-#include
-
-#define cpu_dcache_is_aliasing() true
-
-#endif
--
2.34.1
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