[linux-sunxi] [PATCH] clk: sunxi: add correct divider table for sun4i-apb0 clock
The sun4i-apb0 clock, as found on all platforms using it, is a
power-of-two-based divider clock, with a special divider of 2
for value 0.
This was causing the clock framework to incorrectly calculate
the clock rate for apb1 and related modules on sun6i and sun8i.
On sun[4/5/7]i, u-boot SPL configures the divider with value 1
for /2 divider, so no suprises there.
This patch adds a proper divider table for it, so the correct
clock rate can be calculated.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sunxi.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index b654b7b..2cf6581 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -762,10 +762,19 @@ static const struct div_data sun4i_ahb_data __initconst =
{
.width = 2,
};
+static const struct clk_div_table sun4i_apb0_table[] __initconst = {
+ { .val = 0, .div = 2 },
+ { .val = 1, .div = 2 },
+ { .val = 2, .div = 4 },
+ { .val = 3, .div = 8 },
+ { } /* sentinel */
+};
+
static const struct div_data sun4i_apb0_data __initconst = {
.shift = 8,
.pow= 1,
.width = 2,
+ .table = sun4i_apb0_table,
};
static const struct div_data sun6i_a31_apb2_div_data __initconst = {
--
2.1.0
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Re: [linux-sunxi] [PATCH 0/8] meminfo: add generic dumping for A23/A31
On Thu, Sep 04, 2014 at 08:43:56AM +0200, Luc Verhaegen wrote: Crap, forgot to type --compose, so here goes. These patches add more generic register dumping for A31 and A23. Generic means: the three memory ranges get printed, so that we can, in future, when we finally have gotten solid information on the memory controllers on the newer SoCs, write small tools to extract the information we need for u-boot to set up a specific device. Currently, A31 tries to print whole register ranges for com, ctl and phy, and tries to also name them as much as possible. A23 just prints the non-null registers in those register ranges. A33 and A80 still are TODO. I expect that A33 will be the same as A23. A80 will need to also print the second channel CTL and PHY registers. Preliminary findings tell me that A31 and A23 share very little with respect to their memory controllers. Also, it seems that we have a divide too much or a shift too litte with our DRAM PLL, as we end up at exactly half of what the .fex tells us. For those who want a quick run: http://dl.linux-sunxi.org/users/libv/meminfo/meminfo For those with A33 and A80 hw, please hack this code to run it on those platforms. Thanks, Luc Verhaegen. Pushed. 2 patches will be created now which add theoretical A33 and A80 support. Luc Verhaegen. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 0/7] clk: sun6i: Unify AHB1 clock and fix rate calculation
Hi everyone, This series unifies the mux and divider parts of the AHB1 clock found on sun6i and sun8i, while also adding support for the pre-divider on the PLL6 input. The rate calculation logic must factor in which parent it is using to calculate the rate, to decide whether to use the pre-divider or not. This is beyond the original factors clk design in sunxi. To avoid feature bloat, this is implemented as a seperate composite clk. The new clock driver is registered with a separate OF_CLK_DECLARE. This is done so that assigned-clocks* properties on the clk provider node can actually work. The clock framework arranges the clock setup order by checking whether all clock parents are available, by checking the node matching OF_CLK_DECLARE. However, the sunxi clk driver is based on the root node compatible, has no defined dependencies (parents), and is setup before the fixed-rate clocks. Thus when the ahb1 clock is added, all parents have rate = 0. There is no way to calculate the required clock factors to set a default clock rate under these circumstances. This happens when we set the defaults in the clock node (provider), rather than a clock consumer. I can think of 2 ways to solve the dependency issue, but neither is pretty. One would be to move the root fixed-rate clocks into the sunxi clk driver. The other would be separating all the clocks into individual OF_CLK_DECLARE statements, which adds a lot of boilerplate code. The contents of this series are as follows: Patch 1 adds support for a fixed divider on the output of factor clocks, which is used by the next patch. Patch 2 fixes PLL6 rate calculation error, due to one of the factor values starting from 1, instead of 0. It also adds the /2 divider on the output. Patch 3 adds the unified AHB1 clock driver. Patch 4 and 5 unify the AHB1 clock nodes on sun6i and sun8i respectively. Patch 6 sets the default parent and clock rate for AHB1, as required by the DMA controller. Curiously I did not require this when I tried dmatest on my A31 Hummingbird. Patch 7 removes the clk_set_parent calls from the sun6i-dma driver, as it no longer works, and is replaced by the previous patch. Suggestions are more than welcome. Cheers ChenYu Chen-Yu Tsai (7): clk: sunxi: Add post clk divider for factor clocks clk: sunxi: Fix PLL6 calculation on sun6i clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider ARM: dts: sun8i: Unify ahb1 clock nodes ARM: dts: sun6i: Unify ahb1 clock nodes ARM: dts: sun6i: Add required ahb1 clock parent and rates for dma controller dmaengine: sun6i: Remove obsolete clk muxing code Documentation/devicetree/bindings/clock/sunxi.txt | 2 +- arch/arm/boot/dts/sun6i-a31.dtsi | 17 +- arch/arm/boot/dts/sun8i-a23.dtsi | 12 +- drivers/clk/sunxi/clk-factors.c | 3 + drivers/clk/sunxi/clk-factors.h | 1 + drivers/clk/sunxi/clk-sunxi.c | 215 +- drivers/dma/sun6i-dma.c | 23 --- 7 files changed, 227 insertions(+), 46 deletions(-) -- 2.1.0 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 2/7] clk: sunxi: Fix PLL6 calculation on sun6i
The N factor for PLL6 counts from 1 to 32, as specified in the A23
manual, and shown in Allwinner's original A31 code.
Also the PLL6 factors alone calculate the clock rate for PLL6x2, not
the normal halved output for PLL6. This is what the factors clk
.recalc_rate callback expects.
This patch fixes the N factor in the clock driver, and adds a post
PLL divider of 2 to calculate the rate for PLL6.
A further patch (to the DT) should add a fixed-factor x2 clock as
the PLL6x2 output.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sunxi.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index b654b7b..be9ac07 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -246,7 +246,7 @@ static void sun4i_get_pll5_factors(u32 *freq, u32
parent_rate,
/**
* sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
* PLL6 rate is calculated as follows
- * rate = parent_rate * n * (k + 1) / 2
+ * rate = parent_rate * (n + 1) * (k + 1) / 2
* parent_rate is always 24Mhz
*/
@@ -273,7 +273,7 @@ static void sun6i_a31_get_pll6_factors(u32 *freq, u32
parent_rate,
if (*k 3)
*k = 3;
- *n = DIV_ROUND_UP(div, (*k+1));
+ *n = DIV_ROUND_UP(div, (*k+1)) - 1;
}
/**
@@ -494,6 +494,8 @@ static struct clk_factors_config sun6i_a31_pll6_config = {
.nwidth = 5,
.kshift = 4,
.kwidth = 2,
+ .n_start = 1,
+ .post_div = 2,
};
static struct clk_factors_config sun4i_apb1_config = {
--
2.1.0
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[linux-sunxi] [PATCH 4/7] ARM: dts: sun8i: Unify ahb1 clock nodes
The clock driver has unified support for the ahb1 clock.
Unify the clock nodes so it works.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23.dtsi | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 2ec86d36..cc8c650 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -104,19 +104,11 @@
clock-output-names = axi;
};
- ahb1_mux: ahb1_mux_clk@01c20054 {
- #clock-cells = 0;
- compatible = allwinner,sun6i-a31-ahb1-mux-clk;
- reg = 0x01c20054 0x4;
- clocks = osc32k, osc24M, axi, pll6;
- clock-output-names = ahb1_mux;
- };
-
ahb1: ahb1_clk@01c20054 {
#clock-cells = 0;
- compatible = allwinner,sun4i-a10-ahb-clk;
+ compatible = allwinner,sun6i-a31-ahb1-clk;
reg = 0x01c20054 0x4;
- clocks = ahb1_mux;
+ clocks = osc32k, osc24M, axi, pll6;
clock-output-names = ahb1;
};
--
2.1.0
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[linux-sunxi] [PATCH 5/7] ARM: dts: sun6i: Unify ahb1 clock nodes
The clock driver has unified support for the ahb1 clock.
Unify the clock nodes so it works.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index c1295bf..8eb2c6d 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -126,19 +126,11 @@
clock-output-names = axi;
};
- ahb1_mux: ahb1_mux@01c20054 {
- #clock-cells = 0;
- compatible = allwinner,sun6i-a31-ahb1-mux-clk;
- reg = 0x01c20054 0x4;
- clocks = osc32k, osc24M, axi, pll6;
- clock-output-names = ahb1_mux;
- };
-
ahb1: ahb1@01c20054 {
#clock-cells = 0;
- compatible = allwinner,sun4i-a10-ahb-clk;
+ compatible = allwinner,sun6i-a31-ahb1-clk;
reg = 0x01c20054 0x4;
- clocks = ahb1_mux;
+ clocks = osc32k, osc24M, axi, pll6;
clock-output-names = ahb1;
};
--
2.1.0
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[linux-sunxi] [PATCH 1/7] clk: sunxi: Add post clk divider for factor clocks
Some factor clocks, mostly PLLs, have an extra fixed divider just before
the clock output. Add an option to the factor clk driver config data to
specify this divider.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-factors.c | 3 +++
drivers/clk/sunxi/clk-factors.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index 2057c8a..435111d 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -64,6 +64,9 @@ static unsigned long clk_factors_recalc_rate(struct clk_hw
*hw,
/* Calculate the rate */
rate = (parent_rate * (n + config-n_start) * (k + 1) p) / (m + 1);
+ if (config-post_div)
+ rate /= config-post_div;
+
return rate;
}
diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
index d2d0efa..ce70c65 100644
--- a/drivers/clk/sunxi/clk-factors.h
+++ b/drivers/clk/sunxi/clk-factors.h
@@ -16,6 +16,7 @@ struct clk_factors_config {
u8 pshift;
u8 pwidth;
u8 n_start;
+ u8 post_div;
};
struct clk_factors {
--
2.1.0
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[linux-sunxi] [PATCH 7/7] dmaengine: sun6i: Remove obsolete clk muxing code
The sun6i DMA controller requires the AHB1 bus clock to be
clocked from PLL6. This was originally done by the dmaengine
driver during probe time. The AHB1 clock driver has since been
unified, so the original code does not work.
Remove the clk muxing code, and replace it with DT clk default
properties.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/dma/sun6i-dma.c | 23 ---
1 file changed, 23 deletions(-)
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index 1f92a56..3aa10b3 100644
--- a/drivers/dma/sun6i-dma.c
+++ b/drivers/dma/sun6i-dma.c
@@ -862,7 +862,6 @@ static int sun6i_dma_probe(struct platform_device *pdev)
{
struct sun6i_dma_dev *sdc;
struct resource *res;
- struct clk *mux, *pll6;
int ret, i;
sdc = devm_kzalloc(pdev-dev, sizeof(*sdc), GFP_KERNEL);
@@ -886,28 +885,6 @@ static int sun6i_dma_probe(struct platform_device *pdev)
return PTR_ERR(sdc-clk);
}
- mux = clk_get(NULL, ahb1_mux);
- if (IS_ERR(mux)) {
- dev_err(pdev-dev, Couldn't get AHB1 Mux\n);
- return PTR_ERR(mux);
- }
-
- pll6 = clk_get(NULL, pll6);
- if (IS_ERR(pll6)) {
- dev_err(pdev-dev, Couldn't get PLL6\n);
- clk_put(mux);
- return PTR_ERR(pll6);
- }
-
- ret = clk_set_parent(mux, pll6);
- clk_put(pll6);
- clk_put(mux);
-
- if (ret) {
- dev_err(pdev-dev, Couldn't reparent AHB1 on PLL6\n);
- return ret;
- }
-
sdc-rstc = devm_reset_control_get(pdev-dev, NULL);
if (IS_ERR(sdc-rstc)) {
dev_err(pdev-dev, No reset controller specified\n);
--
2.1.0
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[linux-sunxi] [PATCH 3/7] clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider
This patch unifies the sun6i AHB1 clock, originally supported
with separate mux and divider clks. It also adds support for
the pre-divider on the PLL6 input, thus allowing the clock to
be muxed to PLL6 with proper clock rate calculation.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 2 +-
drivers/clk/sunxi/clk-sunxi.c | 209 ++
2 files changed, 210 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b/Documentation/devicetree/bindings/clock/sunxi.txt
index d3a5c3c..3d531d6 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -23,7 +23,7 @@ Required properties:
allwinner,sun5i-a10s-ahb-gates-clk - for the AHB gates on A10s
allwinner,sun7i-a20-ahb-gates-clk - for the AHB gates on A20
allwinner,sun6i-a31-ar100-clk - for the AR100 on A31
- allwinner,sun6i-a31-ahb1-mux-clk - for the AHB1 multiplexer on A31
+ allwinner,sun6i-a31-ahb1-clk - for the AHB1 clock on A31
allwinner,sun6i-a31-ahb1-gates-clk - for the AHB1 gates on A31
allwinner,sun8i-a23-ahb1-gates-clk - for the AHB1 gates on A23
allwinner,sun4i-a10-apb0-clk - for the APB0 clock
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index be9ac07..87b7740 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -19,6 +19,7 @@
#include linux/of.h
#include linux/of_address.h
#include linux/reset-controller.h
+#include linux/log2.h
#include clk-factors.h
@@ -1339,3 +1340,211 @@ static void __init sun6i_init_clocks(struct device_node
*node)
}
CLK_OF_DECLARE(sun6i_a31_clk_init, allwinner,sun6i-a31, sun6i_init_clocks);
CLK_OF_DECLARE(sun8i_a23_clk_init, allwinner,sun8i-a23, sun6i_init_clocks);
+
+
+/**
+ * sun6i_a31_ahb1_clk_setup() - Setup function for a31 ahb1 composite clk
+ */
+
+#define SUN6I_AHB1_MAX_PARENTS 4
+#define SUN6I_AHB1_MUX_PARENT_PLL6 3
+#define SUN6I_AHB1_MUX_SHIFT 12
+#define SUN6I_AHB1_MUX_MASK0x3
+#define SUN6I_AHB1_MUX_GET_PARENT(reg) ((reg SUN6I_AHB1_MUX_SHIFT) \
+SUN6I_AHB1_MUX_MASK)
+#define SUN6I_AHB1_DIV_SHIFT 4
+#define SUN6I_AHB1_DIV_MASK0x3
+#define SUN6I_AHB1_DIV_GET(reg)((reg SUN6I_AHB1_DIV_SHIFT)
\
+SUN6I_AHB1_DIV_MASK)
+#define SUN6I_AHB1_DIV_SET(reg, div) ((reg ~(SUN6I_AHB1_DIV_MASK \
+ SUN6I_AHB1_DIV_SHIFT)) | \
+(div SUN6I_AHB1_DIV_SHIFT))
+#define SUN6I_AHB1_PLL6_DIV_SHIFT 6
+#define SUN6I_AHB1_PLL6_DIV_MASK 0x3
+#define SUN6I_AHB1_PLL6_DIV_GET(reg) ((reg SUN6I_AHB1_PLL6_DIV_SHIFT) \
+SUN6I_AHB1_PLL6_DIV_MASK)
+#define SUN6I_AHB1_PLL6_DIV_SET(reg, div) ((reg \
+ ~(SUN6I_AHB1_PLL6_DIV_MASK \
+ SUN6I_AHB1_PLL6_DIV_SHIFT)) | \
+ (div SUN6I_AHB1_PLL6_DIV_SHIFT))
+
+struct sun6i_ahb1_clk {
+ struct clk_hw hw;
+ void __iomem *reg;
+};
+
+#define to_sun6i_ahb1_clk(_hw) container_of(_hw, struct sun6i_ahb1_clk, hw)
+
+static unsigned long sun6i_ahb1_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
+ unsigned long rate;
+ u32 reg;
+
+ /* Fetch the register value */
+ reg = readl(ahb1-reg);
+
+ /* apply pre-divider first if parent is pll6 */
+ if (SUN6I_AHB1_MUX_GET_PARENT(reg) == SUN6I_AHB1_MUX_PARENT_PLL6)
+ parent_rate /= SUN6I_AHB1_PLL6_DIV_GET(reg) + 1;
+
+ /* clk divider */
+ rate = parent_rate SUN6I_AHB1_DIV_GET(reg);
+
+ return rate;
+}
+
+static long sun6i_ahb1_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp,
+u8 parent, unsigned long parent_rate)
+{
+ u8 div, calcp, calcm = 1;
+
+ /* clock can only divide, so we will never be able to achieve
+* frequencies higher than the parent frequency */
+ if (parent_rate rate parent_rate)
+ rate = parent_rate;
+
+ div = DIV_ROUND_UP(parent_rate, rate);
+
+ /* calculate pre-divider if parent is pll6 */
+ if (parent == SUN6I_AHB1_MUX_PARENT_PLL6) {
+ if (div 4)
+ calcp = 0;
+ else if (div / 2 4)
+ calcp = 1;
+ else if (div / 4 4)
+ calcp = 2;
+ else
+ calcp = 3;
+
+ calcm = DIV_ROUND_UP(div, 1 calcp);
+ } else {
+ calcp = __roundup_pow_of_two(div);
+
[linux-sunxi] [PATCH 6/7] ARM: dts: sun6i: Add required ahb1 clock parent and rates for dma controller
The DMA controller requires AHB1 bus clock to be clocked from PLL6.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 8eb2c6d..1117989 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -317,6 +317,11 @@
clocks = ahb1_gates 6;
resets = ahb1_rst 6;
#dma-cells = 1;
+
+ /* DMA controller requires AHB1 clocked from PLL6 */
+ assigned-clocks = ahb1;
+ assigned-clock-parents = pll6;
+ assigned-clock-rates = 2;
};
mmc0: mmc@01c0f000 {
--
2.1.0
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Re: [linux-sunxi] Who is reviewing the sunxi-boards repo?
On Fri, Aug 29, 2014 at 09:31:20AM +0200, Luc Verhaegen wrote: On Fri, Aug 29, 2014 at 09:19:13AM +0200, Luc Verhaegen wrote: We have enough zombies in both our u-boot and sunxi-boards repos. We don't need any more. But ok, i will spend my next 10-15 minutes fixing up that page and getting the fex in our repo. Thank you for your contribution. Luc Verhaegen. http://linux-sunxi.org/New_Device_howto#Step_6:_Add_support_to_sunxi-boards In case you missed that, that's on the page linked in the Big Fat Warning on top of the Olimex A20 SOM page. If you really want to know why no fex was there, then read this: http://linux-sunxi.org/index.php?title=Olimex_A20-SOMaction=history Seems like Bruce didn't read the NDH either. Luc Verhaegen. Thanks. Luc Verhaegen. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] A31 development board
On Thu, Aug 28, 2014 at 01:49:42AM -0700, TsvetanUsunov wrote: Do I understand it right that these spare boards are specifically allocated for the developers willing to work on merging the sun6i code into the sunxi-3.4 kernel? I just write that we have few spare boards, if one want to develop but have no hardware we can provide Not everyone thinks that it is the best use of their time at this particular moment. But good luck with that and you are the boss :-) I guess it's too much work to merge in Linux-Sunxi tree all A31 differences, but this is not problem as there is alrernative SDK http://www.cnx-software.com/2014/08/20/allwinner-a31-android-linux-sdks-and-documentation-leaked/ which we successfully used to boot Linux on A31 Yeah, we have ignored A31 and A23 for too long. With the advent of A80 and A33 we have to start giving people a workable solution, even if that means having people work with u-boot and kernel from an SDK. Chen-Yu has been writing http://linux-sunxi.org/SDK_build_howto which i hope will turn into 4 separate Manual_build_howto pages soon. One for each of the 4 chips which do not have sunxi uboot/kernel support. I have been playing with meminfo, so we can collect all dram controller registers, and in future turn that into u-boot dram controller parameters for when Allwinner provides us with dram information. So yes, porting A31 to sunxi-3.4 does not make sense today. But we are slowly working on providing a temporary solution for everyone. Luc Verhaegen. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH] usb: gadget: midi: Fix ignored index and id module parameters
The MIDI USB gadget driver has index and id parameters which should determine the alsa sound card index and id to use when registering the card. Those parameters had no effect, as the relevant information is only set on the midi structure after f_midi_register_card is called. This patch moves the two initialisation statements before the function call. Signed-off-by: Marcus Weseloh mar...@weseloh.cc --- drivers/usb/gadget/f_midi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/gadget/f_midi.c b/drivers/usb/gadget/f_midi.c index 1bf9596..1c16bcb 100644 --- a/drivers/usb/gadget/f_midi.c +++ b/drivers/usb/gadget/f_midi.c @@ -959,6 +959,8 @@ int __init f_midi_bind_config(struct usb_configuration *c, /* set up ALSA midi devices */ midi-in_ports = in_ports; midi-out_ports = out_ports; + midi-id = kstrdup(id, GFP_KERNEL); + midi-index = index; status = f_midi_register_card(midi); if (status 0) goto setup_fail; @@ -970,8 +972,6 @@ int __init f_midi_bind_config(struct usb_configuration *c, midi-func.set_alt = f_midi_set_alt; midi-func.disable = f_midi_disable; - midi-id = kstrdup(id, GFP_KERNEL); - midi-index = index; midi-buflen = buflen; midi-qlen = qlen; -- 1.9.1 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] patched spi-sun7i.c and support for rfm12b radio module
Hello there, a rainy summer has some (though little) advantages. I was working on my home automation issues controlled by a cubietruck. For this, I wanted the board to control various rfm12b modules that I have around the house, as well as a plug following the home-easy protocol with RF on-off keying. The rfm12b module by hope electronics is controlled via the api bus. Unfortunately, only one SPI-Bus with only one chip select is broken out on the cubietruck. The trouble I went through to make this stuff work, I begin to understand why ;) I used the http://dl.cubieboard.org/parteners/waveshare/Source_Code/a20-cubieboard-dvk/driver%20source/spi-sun7i.c as a base for the spi-driver. The module has some obvious bugs, such as not addressing the right dma channels for the spi2 bus, or not releasing an interrupt when unloading the module, so that a second attempt to load the module crashes the kernel, to name the most significant ones. For the RFM12b control, I used https://github.com/gkaindl/rfm12b-linux It was written for the RPi, originally. The results are at https://github.com/matzrh/rfm12b-linux/ Would be happy if someone else found it useful and/or contributes to it. The on-off keying realization was achieved through some hacking in the spi-sun7i code (beyond the bug fixing) and seriously abusing the interbyte-usec parameter in the spi_transfer struct, but it achieved what I needed. Someone may want to extract these pieces (they are pretty obvious) and push spi-sun7i without the bugs to the kernel, if not done (I am using patwoods kernel as a base). Some more remarks in the README.md in my github. Best Matthias -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Report on recently added audio support
Hi,
I'm new to this group. I want to use analogue audio with a mainline kernel
on my Olinuxino A20, so I've been trying out the recent work of Emilio
López, Jon Smirl and others to add mainline audio support, and I'd like to
report my findings.
After applying the relevant changes from the sunxi-codec-v0 branch of
Emilio's repository https://bitbucket.org/emiliolopez/linux.git, I've
found that sound files play very well, except 16-bit mono. Although the
problem is not very noticeable at high sample rates like 44100Hz, at lower
rates like 8000Hz there is a very distinctive distortion in the sound. I
found I could closely simulate on a normal system the sound of this
distortion by zeroing out every alternate sample in a stream, so it seems
there is a processing error somewhere which is causing alternate samples to
be lost; perhaps some sort of 16/32-bit mismatch.
I looked for differences between Emilio's sound/soc/sunxi/sunxi-codec.c and
the equivalent in the sunxi-3.4 branch, which doesn't exhibit this
distortion, and I noticed that Emilio always sets TX_FIFO_MODE (i.e. bit 24
of register AC_DAC_FIFOC) to 0, whereas sunxi-3.4 appears to have it always
set to 1. According to Allwinner's A20 user manual (p.176 of
https://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf),
this bit controls what alignment the DAC expects the data in its TXDATA
register to have. I tried changing it to 1 and found this resolved the
problem for 16-bit streams. We wouldn't want to change it for 24-bit
streams though, since a setting of 1 in that case is Reserved and I've
found that 24-bit streams just play as white noise with that setting.
It would be good to understand why the 0 setting produces the effect it
does. I think Chen-Yu Tsai was onto something when he noticed in
https://www.mail-archive.com/linux-sunxi%40googlegroups.com/msg06152.html:
However, there is something puzzling about the FIFO modes. The manual
says that with TX FIFO modes 00/10, 16 bit audio should take the most
significant 2 bytes of the FIFO as the audio sample to convert. However
the DMA engine looks like it's writing the least significant 2 bytes.
I know the code as it is now works, but still I think we should get
this straightened out.
I'm new to most of this, so my mental model of the hardware and kernel may
well be wrong, but I think the audio stream is fed into the DAC through its
32-bit TXDATA register, from where it proceeds to the 24-bit FIFO within
the DAC, according to the data alignment rule specified in TX_FIFO_MODE.
And presumably the DMA engine is copying each 16-bit sample to the first
two memory-mapped bytes of the TXDATA register in the memory map, namely
locations 0x01c22c0c and 0x01c22c0d, which due to little-endianness are the
two least significant bytes of the register, i.e. bits [15:0], so
TX_FIFO_MODE needs to be 1. It's puzzling why TX_FIFO_MODE=0 produces any
sound at all for 16-bit streams, since it would take bits [31:16] from
TXDATA into the FIFO, and surely those bits would always be empty. Perhaps
the DMA engine always copies 4 bytes at a time? I'm just guessing.
Anyway, below is a patch that allows me to play undistorted 16-bit mono
without messing up 24-bit audio. It may not be the right solution but it
seems to work.
Thank you all for your work on linux-sunxi; I appreciate it very much.
Best wishes,
B.R. Oake.
P.S. My exact setup is as follows:
Hardware: Olimex Olinuxino-A20-Micro Revision F
OS: Debian Jessie
Kernel: Linux 3.16-1~exp1 armmp from Debian experimental repository, with
the following patches from Emilio's git repository:
9ee1da1 Audio codec support
ed103a8 Audio codec device tree
325ed71 PLL2 support
a08d5d8 PLL2 device tree
2808f1f Codec-clk support
f536e9a Codec-clk device tree
5a78102 DMA support
0a80f86 DMA device tree
628cd59 Hack to avoid duplicate widgets
Also the following patch, but for sun7i-a20-olinuxino-micro.dts rather than
sun7i-a20-cubietruck.dts:
e8d3803 Enable codec for Cubietruck
-
Patch to remove distortion on 16-bit mono
diff -Nur a/sound/soc/sunxi/sunxi-codec.c b/sound/soc/sunxi/sunxi-codec.c
--- a/sound/soc/sunxi/sunxi-codec.c 2014-09-04 23:16:06.921872000 +0100
+++ b/sound/soc/sunxi/sunxi-codec.c 2014-09-04 23:18:17.129872062 +0100
@@ -215,9 +215,6 @@
regmap_update_bits(priv-regmap, SUNXI_DAC_FIFOC, 0x1
SUNXI_DAC_FIFOC_FIR_VERSION, 0x1 SUNXI_DAC_FIFOC_FIR_VERSION);
}
- /* set TX FIFO MODE - 0 works for both 16 and 24 bits */
- regmap_update_bits(priv-regmap, SUNXI_DAC_FIFOC, 0x1
SUNXI_DAC_FIFOC_TX_FIFO_MODE, 0x0 SUNXI_DAC_FIFOC_TX_FIFO_MODE);
-
/* send last sample when DAC FIFO under run */
regmap_update_bits(priv-regmap, SUNXI_DAC_FIFOC, 0x1
SUNXI_DAC_FIFOC_SEND_LASAT, 0x0 SUNXI_DAC_FIFOC_SEND_LASAT);
} else {
@@ -329,6 +326,7 @@
[linux-sunxi] Re: [PATCH] clk: sunxi: fix mux clk takes register bit mask instead of width
Self NACK this one.
I misread the definition, and extrapolated from the init data.
The original code is correct. Sorry about the noise.
On Sat, Sep 6, 2014 at 12:06 PM, Chen-Yu Tsai w...@csie.org wrote:
clk_register_mux takes both register bit shift and mask as parameters
to which bits it should use to control the clock mux.
sunxi_mux_clk_setup incorrectly passed the width of effective bits,
instead of the bit mask. This would result in incorrect values being
read or set.
Fixes: e874a6697710 (clk: arm: sunxi: Add a new clock driver for sunxi SOCs)
Signed-off-by: Chen-Yu Tsai w...@csie.org
Cc: sta...@vger.kernel.org
---
We never ran into this because the mux clks do not have auto-reparenting
enabled, and the only time we did reparent was in the sun6i dma driver.
Luckily the new value is the same as the mask there.
---
drivers/clk/sunxi/clk-sunxi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index b654b7b..df61199 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -674,7 +674,7 @@ static struct clk * __init sunxi_factors_clk_setup(struct
device_node *node,
* sunxi_mux_clk_setup() - Setup function for muxes
*/
-#define SUNXI_MUX_GATE_WIDTH 2
+#define SUNXI_MUX_GATE_MASK0x3
struct mux_data {
u8 shift;
@@ -711,7 +711,7 @@ static void __init sunxi_mux_clk_setup(struct device_node
*node,
clk = clk_register_mux(NULL, clk_name, parents, i,
CLK_SET_RATE_NO_REPARENT, reg,
- data-shift, SUNXI_MUX_GATE_WIDTH,
+ data-shift, SUNXI_MUX_GATE_MASK,
0, clk_lock);
if (clk) {
--
2.1.0
--
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Re: [linux-sunxi] Report on recently added audio support
Hi!
El 06/09/14 a las 11:58, B.R. Oake escibió:
Hi,
I'm new to this group. I want to use analogue audio with a mainline kernel
on my Olinuxino A20, so I've been trying out the recent work of Emilio
López, Jon Smirl and others to add mainline audio support, and I'd like to
report my findings.
After applying the relevant changes from the sunxi-codec-v0 branch of
Emilio's repository https://bitbucket.org/emiliolopez/linux.git, I've
found that sound files play very well, except 16-bit mono. Although the
problem is not very noticeable at high sample rates like 44100Hz, at lower
rates like 8000Hz there is a very distinctive distortion in the sound. I
found I could closely simulate on a normal system the sound of this
distortion by zeroing out every alternate sample in a stream, so it seems
there is a processing error somewhere which is causing alternate samples to
be lost; perhaps some sort of 16/32-bit mismatch.
I looked for differences between Emilio's sound/soc/sunxi/sunxi-codec.c and
the equivalent in the sunxi-3.4 branch, which doesn't exhibit this
distortion, and I noticed that Emilio always sets TX_FIFO_MODE (i.e. bit 24
of register AC_DAC_FIFOC) to 0, whereas sunxi-3.4 appears to have it always
set to 1. According to Allwinner's A20 user manual (p.176 of
https://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf),
this bit controls what alignment the DAC expects the data in its TXDATA
register to have. I tried changing it to 1 and found this resolved the
problem for 16-bit streams. We wouldn't want to change it for 24-bit
streams though, since a setting of 1 in that case is Reserved and I've
found that 24-bit streams just play as white noise with that setting.
It would be good to understand why the 0 setting produces the effect it
does. I think Chen-Yu Tsai was onto something when he noticed in
https://www.mail-archive.com/linux-sunxi%40googlegroups.com/msg06152.html:
However, there is something puzzling about the FIFO modes. The manual
says that with TX FIFO modes 00/10, 16 bit audio should take the most
significant 2 bytes of the FIFO as the audio sample to convert. However
the DMA engine looks like it's writing the least significant 2 bytes.
I know the code as it is now works, but still I think we should get
this straightened out.
I'm new to most of this, so my mental model of the hardware and kernel may
well be wrong, but I think the audio stream is fed into the DAC through its
32-bit TXDATA register, from where it proceeds to the 24-bit FIFO within
the DAC, according to the data alignment rule specified in TX_FIFO_MODE.
And presumably the DMA engine is copying each 16-bit sample to the first
two memory-mapped bytes of the TXDATA register in the memory map, namely
locations 0x01c22c0c and 0x01c22c0d, which due to little-endianness are the
two least significant bytes of the register, i.e. bits [15:0], so
TX_FIFO_MODE needs to be 1. It's puzzling why TX_FIFO_MODE=0 produces any
sound at all for 16-bit streams, since it would take bits [31:16] from
TXDATA into the FIFO, and surely those bits would always be empty. Perhaps
the DMA engine always copies 4 bytes at a time? I'm just guessing.
Anyway, below is a patch that allows me to play undistorted 16-bit mono
without messing up 24-bit audio. It may not be the right solution but it
seems to work.
Thank you all for your work on linux-sunxi; I appreciate it very much.
Best wishes,
B.R. Oake.
P.S. My exact setup is as follows:
Hardware: Olimex Olinuxino-A20-Micro Revision F
OS: Debian Jessie
Kernel: Linux 3.16-1~exp1 armmp from Debian experimental repository, with
the following patches from Emilio's git repository:
9ee1da1 Audio codec support
ed103a8 Audio codec device tree
325ed71 PLL2 support
a08d5d8 PLL2 device tree
2808f1f Codec-clk support
f536e9a Codec-clk device tree
5a78102 DMA support
0a80f86 DMA device tree
628cd59 Hack to avoid duplicate widgets
Also the following patch, but for sun7i-a20-olinuxino-micro.dts rather than
sun7i-a20-cubietruck.dts:
e8d3803 Enable codec for Cubietruck
-
Patch to remove distortion on 16-bit mono
diff -Nur a/sound/soc/sunxi/sunxi-codec.c b/sound/soc/sunxi/sunxi-codec.c
--- a/sound/soc/sunxi/sunxi-codec.c 2014-09-04 23:16:06.921872000 +0100
+++ b/sound/soc/sunxi/sunxi-codec.c 2014-09-04 23:18:17.129872062 +0100
@@ -215,9 +215,6 @@
regmap_update_bits(priv-regmap, SUNXI_DAC_FIFOC, 0x1
SUNXI_DAC_FIFOC_FIR_VERSION, 0x1 SUNXI_DAC_FIFOC_FIR_VERSION);
}
- /* set TX FIFO MODE - 0 works for both 16 and 24 bits */
- regmap_update_bits(priv-regmap, SUNXI_DAC_FIFOC, 0x1
SUNXI_DAC_FIFOC_TX_FIFO_MODE, 0x0 SUNXI_DAC_FIFOC_TX_FIFO_MODE);
-
/* send last sample when DAC FIFO under run */
regmap_update_bits(priv-regmap, SUNXI_DAC_FIFOC, 0x1
SUNXI_DAC_FIFOC_SEND_LASAT, 0x0 SUNXI_DAC_FIFOC_SEND_LASAT);
} else {
@@
Re: [linux-sunxi] Re: A20 + OV5640 (parallel) issues
I thought I'd try and resurrect this thread. I've got a new Baseboard with a CSI1 header on it connected to a OV5642 camera module. For initial testing I am running a Cubian distro with a Cubieboard A20 board. I have the following environment: cubie@Cubian:~$ zcat /proc/config.gz | grep -i ov564 CONFIG_SOC_CAMERA_OV5642=m CONFIG_CSI_OV5640=m cubie@Cubian:~$ zcat /proc/config.gz | grep -i v4l CONFIG_VIDEO_V4L2_COMMON=y CONFIG_VIDEO_V4L2=y CONFIG_V4L_USB_DRIVERS=y CONFIG_V4L_PLATFORM_DRIVERS=y # CONFIG_V4L_MEM2MEM_DRIVERS is not set cubie@Cubian:~$ uname -a Linux Cubian 3.4.103-00029-g0c7986b #4 PREEMPT Mon Sep 1 09:30:06 PDT 2014 armv7l GNU/Linux Before I get too involved with trial and error testing I thought I would check here for advice and see if we can get this fully working for everyone. Thanks, George On Tuesday, July 29, 2014 5:28:18 AM UTC-7, Adilson Oliveira wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA256 Em 29-07-2014 09:09, Danny Song escreveu: I have enabled the ov5640 now. it works well. Thanks That's awesome. Is it the code already on the main kernel? -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.14 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBCAAGBQJT15NKAAoJENqn0z1Ab/Bx2TAIAKpd5BrgXpbzl4acPpGOyUSe Zf0iPiGVOJfpqUeLsCJ2ESHplQOkbTzNyRlGXCBI0wA6uU04yQi4dFhHVWz3+qRz G/u+feC7fC3J6XEb6+5uGEpwBjE+jaC/803JG0trHfUqSTXGyrfrnL6aKEs8YIpY ngr34HzFIZmqsCMzOfd2h1h72Pp/gwEiYYA6dLIDFKmZ8qwRDNbmoNF6LrnDdGGC Uv43tzzBz9bBhzddZHKWDTN/01+loa2uL8IPHU24VXLCn/zU6HlCxWF5Xxm+VPbu oCxkv98+CrxUyapw5JJSeha4552kEqw8CKge9Wg7u56r6hAEec+bzuy/aAld72w= =KIfl -END PGP SIGNATURE- -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: A20 + OV5640 (parallel) issues
The CSI source in the sunxi kernel is a couple of years old. First thing I would do is update to the latest source in the Allwinner SDK. On Sat, Sep 6, 2014 at 7:12 PM, George Ioakimedes georgei...@gmail.com wrote: I thought I'd try and resurrect this thread. I've got a new Baseboard with a CSI1 header on it connected to a OV5642 camera module. For initial testing I am running a Cubian distro with a Cubieboard A20 board. I have the following environment: cubie@Cubian:~$ zcat /proc/config.gz | grep -i ov564 CONFIG_SOC_CAMERA_OV5642=m CONFIG_CSI_OV5640=m cubie@Cubian:~$ zcat /proc/config.gz | grep -i v4l CONFIG_VIDEO_V4L2_COMMON=y CONFIG_VIDEO_V4L2=y CONFIG_V4L_USB_DRIVERS=y CONFIG_V4L_PLATFORM_DRIVERS=y # CONFIG_V4L_MEM2MEM_DRIVERS is not set cubie@Cubian:~$ uname -a Linux Cubian 3.4.103-00029-g0c7986b #4 PREEMPT Mon Sep 1 09:30:06 PDT 2014 armv7l GNU/Linux Before I get too involved with trial and error testing I thought I would check here for advice and see if we can get this fully working for everyone. Thanks, George On Tuesday, July 29, 2014 5:28:18 AM UTC-7, Adilson Oliveira wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA256 Em 29-07-2014 09:09, Danny Song escreveu: I have enabled the ov5640 now. it works well. Thanks That's awesome. Is it the code already on the main kernel? -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.14 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBCAAGBQJT15NKAAoJENqn0z1Ab/Bx2TAIAKpd5BrgXpbzl4acPpGOyUSe Zf0iPiGVOJfpqUeLsCJ2ESHplQOkbTzNyRlGXCBI0wA6uU04yQi4dFhHVWz3+qRz G/u+feC7fC3J6XEb6+5uGEpwBjE+jaC/803JG0trHfUqSTXGyrfrnL6aKEs8YIpY ngr34HzFIZmqsCMzOfd2h1h72Pp/gwEiYYA6dLIDFKmZ8qwRDNbmoNF6LrnDdGGC Uv43tzzBz9bBhzddZHKWDTN/01+loa2uL8IPHU24VXLCn/zU6HlCxWF5Xxm+VPbu oCxkv98+CrxUyapw5JJSeha4552kEqw8CKge9Wg7u56r6hAEec+bzuy/aAld72w= =KIfl -END PGP SIGNATURE- -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. -- Jon Smirl jonsm...@gmail.com -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
