Re: [linux-sunxi] Allwinner documentation (hardware datasheet, user manual) for A10, A10s, A13, A20, A31, A31s
Hi Kevin, I need some infos about the deinterlacer in sunxi display engine. Bob deinterlacing is working basically. Is there a possibility to get some info's about these two parameters and how to use/ get them: flag_addr: https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/include/video/sunxi_disp_ioctl.h#L390 flag_stride: https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/include/video/sunxi_disp_ioctl.h#L391 There is no (helpful) information in Allwinner Docs or sample code. Thanks Andreas Am 08.10.2014 02:39, schrieb ke...@allwinnertech.com: Hi, Raanan, About the A80's manual, there is no a clear time now. We are trying to make it available as soon as possible. Best Regards, kevin.z.m *From:* RFat mailto:raan...@gmail.com *Date:* 2014-10-06 20:55 *To:* linux-sunxi@googlegroups.com mailto:linux-sunxi@googlegroups.com *CC:* hen...@henriknordstrom.net mailto:hen...@henriknordstrom.net; sh...@allwinnertech.com mailto:sh...@allwinnertech.com; ke...@allwinnertech.com mailto:ke...@allwinnertech.com *Subject:* Re: Re: [linux-sunxi] Allwinner documentation (hardware datasheet, user manual) for A10, A10s, A13, A20, A31, A31s Hi Kevin, Publishing the user manuals will certainly increase Allwinner's chips popularity. I was wondering if there is a rough estimate as to when the A80's manual will be made available? Thanks! Raanan On Monday, September 29, 2014 12:46:53 PM UTC+3, ke...@allwinnertech.com wrote: Hi All, I have put the documents on github, and the url is https://github.com/allwinner-zh/documents.git https://github.com/allwinner-zh/documents.git Thanks Simos, Henrik and Luc's suggestion. And other documents will be upated to here when released. Best Regards, kevin.z.m *From:* HenrikNordström javascript: *Date:* 2014-09-29 08:46 *To:* linux...@googlegroups.com javascript: *CC:* sh...@allwinnertech.com javascript:; Meng Zhang javascript: *Subject:* Re: [linux-sunxi] Allwinner documentation (hardware datasheet, user manual) for A10, A10s, A13, A20, A31, A31s sön 2014-09-28 klockan 02:18 +0200 skrev Luc Verhaegen: Why didn't someone from Allwinner send these documents in him/herself? The current person discussion the matter with Allwiner was Simos, who is part of the linux-sunxi community. Allwinner sent current versions of the documents to Simos for distribution in the community. What is wrong? Mailing the full set of documents as attachments directly to the mailinglist is not appropriate. And for some strange and unknown reason Allwinner do not appear to have a public document archive for this kind of documents themselves, and seems to only distribute them via email to their customers when requested. The real question is why AW do not make the documents available in public themselves, and likewise why they do not have a public git repository for SDK sources etc (github or elsewhere). Regards Henrik NOTICE: This e-mail and any included attachments are intended only for the sole use of named and intended recipient (s) only. If you are the named and intended recipient, please note that the information contained in this email and its embedded files are confidential and privileged. If you are neither the intended nor named recipient, you are hereby notified that any unauthorized review, use, disclosure, dissemination, distribution, or copying of this communication, or any of its contents, is strictly prohibited. Please reply to the sender and destroy the original message and all your records of this message (whether electronic or otherwise). Furthermore, you should not disclose to any other person, use, copy or disseminate the contents of this e-mail and/or the documents accompanying it. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com mailto:linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an
[linux-sunxi] Re: mainline NAND
Hi Michal Le mardi 16 décembre 2014 19:01:58 UTC+1, Michal Suchanek a écrit : Hello, I tried to rebase the v7 patchset on top of 3.18 and add the DT bindings on cubieboard: https://github.com/hramrach/linux-sunxi/commit/a946d593ddcf443b0f035f6d39fe0c558189dacc The nand driver fails equally on both cubieboard versions: cubieboard: [0.643554] calling nand_base_init+0x0/0x20 @ 1 [0.643565] initcall nand_base_init+0x0/0x20 returned 0 after 3 usecs [0.643578] calling sunxi_nfc_driver_init+0x0/0x10 @ 1 [0.665751] nand: Could not find valid JEDEC parameter page; aborting [0.670907] nand: device found, Manufacturer ID: 0xec, Chip ID: 0xd7 [0.675949] nand: Samsung NAND 4GiB 3,3V 8-bit [0.679098] nand: 4096MiB, MLC, page size: 8192, OOB size: 640 [0.683748] sunxi_nand 1c03000.nand: ECC init failed: -22 [0.687839] sunxi_nand 1c03000.nand: failed to init nand chips [0.692440] sunxi_nand: probe of 1c03000.nand failed with error -22 [0.697500] initcall sunxi_nfc_driver_init+0x0/0x10 returned 0 after 52642 usecs cubieboard2: [0.666766] calling nand_base_init+0x0/0x20 @ 1 [0.666777] initcall nand_base_init+0x0/0x20 returned 0 after 3 usecs [0.666790] calling sunxi_nfc_driver_init+0x0/0x10 @ 1 [0.683003] nand: Could not find valid JEDEC parameter page; aborting [0.688159] nand: device found, Manufacturer ID: 0xec, Chip ID: 0xd7 [0.693201] nand: Samsung NAND 4GiB 3,3V 8-bit [0.696349] nand: 4096MiB, MLC, page size: 8192, OOB size: 640 [0.700956] sunxi_nand 1c03000.nand: ECC init failed: -22 [0.705060] sunxi_nand 1c03000.nand: failed to init nand chips [0.709658] sunxi_nand: probe of 1c03000.nand failed with error -22 [0.714768] initcall sunxi_nfc_driver_init+0x0/0x10 returned 0 after 46833 usecs Is this expected or does somebody have the driver working on some device? As Henrik already answered, it seems that your NAND chip is not properly defined in the nand_ids table [1]. Read your NAND datasheet and add a new entry (take a look at this one [2] as an example). You should also fill the correct timing mode, though mode 0 should work correctly on all recent NANDs. Best Regards, Boris [1]http://lxr.free-electrons.com/source/drivers/mtd/nand/nand_ids.c#L28 [2]http://lxr.free-electrons.com/source/drivers/mtd/nand/nand_ids.c#L49 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH resend v2] input: Add new sun4i-lradc-keys driver
Allwinnner sunxi SoCs have a low resolution adc (called lradc) which is
specifically designed to have various (tablet) keys (ie home, back, search,
etc). attached to it using a resistor network. This adds a driver for this.
There are 2 channels, currently this driver only supports chan0 since there
are no boards known to use chan1.
This has been tested on an olimex a10s-olinuxino-micro, a13-olinuxino, and
a20-olinuxino-micro.
Signed-off-by: Hans de Goede hdego...@redhat.com
--
Changes in v2:
-Change devicetree bindings to use a per key subnode, like gpio-keys does
---
.../devicetree/bindings/input/sun4i-lradc-keys.txt | 62 +
MAINTAINERS| 7 +
drivers/input/keyboard/Kconfig | 10 +
drivers/input/keyboard/Makefile| 1 +
drivers/input/keyboard/sun4i-lradc-keys.c | 258 +
5 files changed, 338 insertions(+)
create mode 100644 Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt
create mode 100644 drivers/input/keyboard/sun4i-lradc-keys.c
diff --git a/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt
b/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt
new file mode 100644
index 000..b9c32f6
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt
@@ -0,0 +1,62 @@
+Allwinner sun4i low res adc attached tablet keys
+
+
+Required properties:
+ - compatible: allwinner,sun4i-a10-lradc-keys
+ - reg: mmio address range of the chip
+ - interrupts: interrupt to which the chip is connected
+ - vref-supply: powersupply for the lradc reference voltage
+
+Each key is represented as a sub-node of allwinner,sun4i-a10-lradc-keys:
+
+Required subnode-properties:
+ - label: Descriptive name of the key.
+ - linux,code: Keycode to emit.
+ - channel: Channel this key is attached to, mut be 0 or 1.
+ - voltage: Voltage in µV at lradc input when this key is pressed.
+
+Example:
+
+#include dt-bindings/input/input.h
+
+ lradc: lradc@01c22800 {
+ compatible = allwinner,sun4i-a10-lradc-keys;
+ reg = 0x01c22800 0x100;
+ interrupts = 31;
+ vref-supply = reg_vcc3v0;
+
+ button@191 {
+ label = Volume Up;
+ linux,code = KEY_VOLUMEUP;
+ channel = 0;
+ voltage = 191274;
+ };
+
+ button@392 {
+ label = Volume Down;
+ linux,code = KEY_VOLUMEDOWN;
+ channel = 0;
+ voltage = 392644;
+ };
+
+ button@601 {
+ label = Menu;
+ linux,code = KEY_MENU;
+ channel = 0;
+ voltage = 601151;
+ };
+
+ button@795 {
+ label = Enter;
+ linux,code = KEY_ENTER;
+ channel = 0;
+ voltage = 795090;
+ };
+
+ button@987 {
+ label = Home;
+ linux,code = KEY_HOMEPAGE;
+ channel = 0;
+ voltage = 987387;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index fdffe96..fb3d33e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9193,6 +9193,13 @@ F: arch/m68k/sun3*/
F: arch/m68k/include/asm/sun3*
F: drivers/net/ethernet/i825xx/sun3*
+SUN4I LOW RES ADC ATTACHED TABLET KEYS DRIVER
+M: Hans de Goede hdego...@redhat.com
+L: linux-in...@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt
+F: drivers/input/keyboard/sun4i-lradc-keys.c
+
SUNDANCE NETWORK DRIVER
M: Denis Kirjanov k...@linux-powerpc.org
L: net...@vger.kernel.org
diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index a3958c6..2d11b44 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -567,6 +567,16 @@ config KEYBOARD_STMPE
To compile this driver as a module, choose M here: the module will be
called stmpe-keypad.
+config KEYBOARD_SUN4I_LRADC
+ tristate Allwinner sun4i low res adc attached tablet keys support
+ depends on ARCH_SUNXI
+ help
+ This selects support for the Allwinner low res adc attached tablet
+ keys found on Allwinner sunxi SoCs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called sun4i-lradc-keys.
+
config KEYBOARD_DAVINCI
tristate TI DaVinci Key Scan
depends on ARCH_DAVINCI_DM365
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index 0a33456..a35269a 100644
--- a/drivers/input/keyboard/Makefile
+++
[linux-sunxi] [PATCH v2 00/13] sun6i: Add A31s and ir support
Hi All, Here is v2 of my patch series to add sun6i A31s and ir support. Changes in v2: -pinctrl: sun6i: Add some missing functions, fix i2c3 muxing: -Drop the changes to the muxing of i2c3 this was based on A31s Datasheet v1.40.pdf, but all other A31 related info puts them at the pins where we already have them, so leave this as is -pinctrl: sun6i: Add A31s pinctrl support -Sync i2c3 muxing with v2 of pinctrl: sun6i: Add some missing functions -Add myself to the copyright header -clk: sunxi: Make the mod0 clk driver also a platform driver -New patch in v2 of the set -mfd: sun6i-prcm: Add support for the ir-clk -New patch in v2 of the set -ARM: dts: sun6i: Add sun6i-a31s.dtsi -include sun6i-a31.dtsi and override the pinctrl compatible, rather then copying everything -ARM: dts: sun6i: Add ir_clk node -Use allwinner,sun4i-a10-mod0-clk as compatible, rather then a prcm specific compatible Please queue this up for 3.20 . Thanks, Hans -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v2 01/13] pinctrl: sun6i: Add some missing functions
While working on pinctrl for the A31s, I noticed that function 4 of
PA15 - PA18 was missing, add these.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
Changes in v2:
-Drop the changes to the muxing of i2c3 this was based on
A31s Datasheet v1.40.pdf, but all other A31 related info puts them at the
pins where we already have them, so leave this as is
---
drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
index f42858e..18038f0 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
@@ -134,24 +134,28 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
SUNXI_FUNCTION(0x1, gpio_out),
SUNXI_FUNCTION(0x2, gmac), /* RXD4 */
SUNXI_FUNCTION(0x3, lcd1), /* D15 */
+ SUNXI_FUNCTION(0x4, clk_out_a),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
SUNXI_FUNCTION(0x0, gpio_in),
SUNXI_FUNCTION(0x1, gpio_out),
SUNXI_FUNCTION(0x2, gmac), /* RXD5 */
SUNXI_FUNCTION(0x3, lcd1), /* D16 */
+ SUNXI_FUNCTION(0x4, dmic), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
SUNXI_FUNCTION(0x0, gpio_in),
SUNXI_FUNCTION(0x1, gpio_out),
SUNXI_FUNCTION(0x2, gmac), /* RXD6 */
SUNXI_FUNCTION(0x3, lcd1), /* D17 */
+ SUNXI_FUNCTION(0x4, dmic), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
SUNXI_FUNCTION(0x0, gpio_in),
SUNXI_FUNCTION(0x1, gpio_out),
SUNXI_FUNCTION(0x2, gmac), /* RXD7 */
SUNXI_FUNCTION(0x3, lcd1), /* D18 */
+ SUNXI_FUNCTION(0x4, clk_out_b),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
SUNXI_FUNCTION(0x0, gpio_in),
@@ -207,6 +211,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
SUNXI_FUNCTION(0x1, gpio_out),
SUNXI_FUNCTION(0x2, gmac), /* MDC */
SUNXI_FUNCTION(0x3, lcd1), /* HSYNC */
+ SUNXI_FUNCTION(0x4, clk_out_c),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
SUNXI_FUNCTION(0x0, gpio_in),
--
2.1.0
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[linux-sunxi] [PATCH v2 05/13] rc: sunxi-cir: Add support for the larger fifo found on sun5i and sun6i
Add support for the larger fifo found on sun5i and sun6i, having a separate
compatible for the ir found on sun5i sun6i also is useful if we ever want
to add ir transmit support, because the sun5i sun6i version do not have
transmit support.
Note this commits also adds checking for the end-of-packet interrupt flag
(which was already enabled), as the fifo-data-available interrupt flag only
gets set when the trigger-level is exceeded. So far we've been getting away
with not doing this because of the low trigger-level, but this is something
which we should have done since day one.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Mauro Carvalho Chehab mche...@osg.samsung.com
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../devicetree/bindings/media/sunxi-ir.txt | 2 +-
drivers/media/rc/sunxi-cir.c| 21 -
2 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt
b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 6b70b9b..1811a06 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -1,7 +1,7 @@
Device-Tree bindings for SUNXI IR controller found in sunXi SoC family
Required properties:
-- compatible : should be allwinner,sun4i-a10-ir;
+- compatible : allwinner,sun4i-a10-ir or allwinner,sun5i-a13-ir
- clocks : list of clock specifiers, corresponding to
entries in clock-names property;
- clock-names : should contain apb and ir entries;
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 06170e0..7830aef 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -56,12 +56,12 @@
#define REG_RXINT_RAI_EN BIT(4)
/* Rx FIFO available byte level */
-#define REG_RXINT_RAL(val)(((val) 8) (GENMASK(11, 8)))
+#define REG_RXINT_RAL(val)((val) 8)
/* Rx Interrupt Status */
#define SUNXI_IR_RXSTA_REG0x30
/* RX FIFO Get Available Counter */
-#define REG_RXSTA_GET_AC(val) (((val) 8) (GENMASK(5, 0)))
+#define REG_RXSTA_GET_AC(val) (((val) 8) (ir-fifo_size * 2 - 1))
/* Clear all interrupt status value */
#define REG_RXSTA_CLEARALL0xff
@@ -72,10 +72,6 @@
/* CIR_REG register idle threshold */
#define REG_CIR_ITHR(val)(((val) 8) (GENMASK(15, 8)))
-/* Hardware supported fifo size */
-#define SUNXI_IR_FIFO_SIZE16
-/* How many messages in FIFO trigger IRQ */
-#define TRIGGER_LEVEL 8
/* Required frequency for IR0 or IR1 clock in CIR mode */
#define SUNXI_IR_BASE_CLK 800
/* Frequency after IR internal divider */
@@ -94,6 +90,7 @@ struct sunxi_ir {
struct rc_dev *rc;
void __iomem*base;
int irq;
+ int fifo_size;
struct clk *clk;
struct clk *apb_clk;
struct reset_control *rst;
@@ -115,11 +112,11 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
/* clean all pending statuses */
writel(status | REG_RXSTA_CLEARALL, ir-base + SUNXI_IR_RXSTA_REG);
- if (status REG_RXINT_RAI_EN) {
+ if (status (REG_RXINT_RAI_EN | REG_RXINT_RPEI_EN)) {
/* How many messages in fifo */
rc = REG_RXSTA_GET_AC(status);
/* Sanity check */
- rc = rc SUNXI_IR_FIFO_SIZE ? SUNXI_IR_FIFO_SIZE : rc;
+ rc = rc ir-fifo_size ? ir-fifo_size : rc;
/* If we have data */
for (cnt = 0; cnt rc; cnt++) {
/* for each bit in fifo */
@@ -156,6 +153,11 @@ static int sunxi_ir_probe(struct platform_device *pdev)
if (!ir)
return -ENOMEM;
+ if (of_device_is_compatible(dn, allwinner,sun5i-a13-ir))
+ ir-fifo_size = 64;
+ else
+ ir-fifo_size = 16;
+
/* Clock */
ir-apb_clk = devm_clk_get(dev, apb);
if (IS_ERR(ir-apb_clk)) {
@@ -271,7 +273,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
* level
*/
writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN |
- REG_RXINT_RAI_EN | REG_RXINT_RAL(TRIGGER_LEVEL - 1),
+ REG_RXINT_RAI_EN | REG_RXINT_RAL(ir-fifo_size / 2 - 1),
ir-base + SUNXI_IR_RXINT_REG);
/* Enable IR Module */
@@ -319,6 +321,7 @@ static int sunxi_ir_remove(struct platform_device *pdev)
static const struct of_device_id sunxi_ir_match[] = {
{ .compatible = allwinner,sun4i-a10-ir, },
+ { .compatible = allwinner,sun5i-a13-ir, },
{},
};
--
2.1.0
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[linux-sunxi] [PATCH v2 06/13] clk: sunxi: Make the mod0 clk driver also a platform driver
With the prcm in sun6i (and some later SoCs) some mod0 clocks are instantiated
through the mfd framework, and as such do not work with of_clk_declare, since
they do not have registers assigned to them yet at of_clk_declare init time.
Silence the error on not finding registers in the of_clk_declare mod0 clk
setup method, and also register mod0-clk support as a platform driver to work
properly with mfd instantiated mod0 clocks.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/clk/sunxi/clk-mod0.c | 41 -
1 file changed, 36 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c
index 658d74f..7ddab6f 100644
--- a/drivers/clk/sunxi/clk-mod0.c
+++ b/drivers/clk/sunxi/clk-mod0.c
@@ -17,6 +17,7 @@
#include linux/clk-provider.h
#include linux/clkdev.h
#include linux/of_address.h
+#include linux/platform_device.h
#include clk-factors.h
@@ -67,7 +68,7 @@ static struct clk_factors_config sun4i_a10_mod0_config = {
.pwidth = 2,
};
-static const struct factors_data sun4i_a10_mod0_data __initconst = {
+static const struct factors_data sun4i_a10_mod0_data = {
.enable = 31,
.mux = 24,
.muxmask = BIT(1) | BIT(0),
@@ -82,17 +83,47 @@ static void __init sun4i_a10_mod0_setup(struct device_node
*node)
void __iomem *reg;
reg = of_iomap(node, 0);
- if (!reg) {
- pr_err(Could not get registers for mod0-clk: %s\n,
- node-name);
+ if (!reg)
return;
- }
sunxi_factors_register(node, sun4i_a10_mod0_data,
sun4i_a10_mod0_lock, reg);
}
CLK_OF_DECLARE(sun4i_a10_mod0, allwinner,sun4i-a10-mod0-clk,
sun4i_a10_mod0_setup);
+static int sun4i_a10_mod0_clk_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev-dev.of_node;
+ struct resource *r;
+ void __iomem *reg;
+
+ if (!np)
+ return -ENODEV;
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ reg = devm_ioremap_resource(pdev-dev, r);
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
+
+ sunxi_factors_register(np, sun4i_a10_mod0_data,
+ sun4i_a10_mod0_lock, reg);
+ return 0;
+}
+
+static const struct of_device_id sun4i_a10_mod0_clk_dt_ids[] = {
+ { .compatible = allwinner,sun4i-a10-mod0-clk },
+ { /* sentinel */ }
+};
+
+static struct platform_driver sun4i_a10_mod0_clk_driver = {
+ .driver = {
+ .name = sun4i-a10-mod0-clk,
+ .of_match_table = sun4i_a10_mod0_clk_dt_ids,
+ },
+ .probe = sun4i_a10_mod0_clk_probe,
+};
+module_platform_driver(sun4i_a10_mod0_clk_driver);
+
static DEFINE_SPINLOCK(sun5i_a13_mbus_lock);
static void __init sun5i_a13_mbus_setup(struct device_node *node)
--
2.1.0
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[linux-sunxi] [PATCH v2 02/13] pinctrl: sun6i: Add A31s pinctrl support
The A31s is a stripped down version of the A31, as such it is missing some
pins and some functions on some pins.
The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c
with the missing pins and functions removed.
Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the
prcm pins are identical between the A31 and the A31s.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
Changes in v2:
-Sync i2c3 muxing with v2 of pinctrl: sun6i: Add some missing functions
-Add myself to the copyright header
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c | 815 +
4 files changed, 821 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
diff --git
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 93ce12e..fdd8046 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -11,6 +11,7 @@ Required properties:
allwinner,sun5i-a10s-pinctrl
allwinner,sun5i-a13-pinctrl
allwinner,sun6i-a31-pinctrl
+ allwinner,sun6i-a31s-pinctrl
allwinner,sun6i-a31-r-pinctrl
allwinner,sun7i-a20-pinctrl
allwinner,sun8i-a23-pinctrl
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 230a952..2eb893e 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -21,6 +21,10 @@ config PINCTRL_SUN6I_A31
def_bool MACH_SUN6I
select PINCTRL_SUNXI_COMMON
+config PINCTRL_SUN6I_A31S
+ def_bool MACH_SUN6I
+ select PINCTRL_SUNXI_COMMON
+
config PINCTRL_SUN6I_A31_R
def_bool MACH_SUN6I
depends on RESET_CONTROLLER
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index c7d92e4..b796d57 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o
obj-$(CONFIG_PINCTRL_SUN5I_A13)+= pinctrl-sun5i-a13.o
obj-$(CONFIG_PINCTRL_SUN6I_A31)+= pinctrl-sun6i-a31.o
+obj-$(CONFIG_PINCTRL_SUN6I_A31S) += pinctrl-sun6i-a31s.o
obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
obj-$(CONFIG_PINCTRL_SUN7I_A20)+= pinctrl-sun7i-a20.o
obj-$(CONFIG_PINCTRL_SUN8I_A23)+= pinctrl-sun8i-a23.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
new file mode 100644
index 000..9b5a91f
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
@@ -0,0 +1,815 @@
+/*
+ * Allwinner A31s SoCs pinctrl driver.
+ *
+ * Copyright (C) 2014 Hans de Goede hdego...@redhat.com
+ *
+ * Based on pinctrl-sun6i-a31.c, which is:
+ * Copyright (C) 2014 Maxime Ripard maxime.rip...@free-electrons.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/of.h
+#include linux/of_device.h
+#include linux/pinctrl/pinctrl.h
+
+#include pinctrl-sunxi.h
+
+static const struct sunxi_desc_pin sun6i_a31s_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, gmac), /* TXD0 */
+ SUNXI_FUNCTION(0x4, uart1), /* DTR */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, gmac), /* TXD1 */
+ SUNXI_FUNCTION(0x4, uart1), /* DSR */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, gmac), /* TXD2 */
+ SUNXI_FUNCTION(0x4, uart1), /* DCD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, gmac), /* TXD3 */
+ SUNXI_FUNCTION(0x4, uart1), /* RING */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
[linux-sunxi] [PATCH v2 03/13] ARM: sunxi: Add allwinner,sun6i-a31s to mach-sunxi
So far the A31s is 100% compatible with the A31, still lets do the same
as what we've done for the A13 / A10s and give it its own compatible string,
in case we need to differentiate later.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
Documentation/arm/sunxi/README | 1 -
arch/arm/mach-sunxi/platsmp.c | 3 ++-
arch/arm/mach-sunxi/sunxi.c| 1 +
drivers/clk/sunxi/clk-sunxi.c | 1 +
4 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index e68d163..1fe2d7f 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -50,7 +50,6 @@ SunXi family
http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20user%20manual%20V1.1%2020130630.pdf
- Allwinner A31s (sun6i)
-+ Not Supported
+ Datasheet
http://dl.linux-sunxi.org/A31/A3x_release_document/A31s/IC/A31s%20datasheet%20V1.3%2020131106.pdf
+ User Manual
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index e44d028..b1b5b7c 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -120,4 +120,5 @@ static struct smp_operations sun6i_smp_ops __initdata = {
.smp_prepare_cpus = sun6i_smp_prepare_cpus,
.smp_boot_secondary = sun6i_smp_boot_secondary,
};
-CPU_METHOD_OF_DECLARE(sun6i_smp, allwinner,sun6i-a31, sun6i_smp_ops);
+CPU_METHOD_OF_DECLARE(sun6i_a31_smp, allwinner,sun6i-a31, sun6i_smp_ops);
+CPU_METHOD_OF_DECLARE(sun6i_a31s_smp, allwinner,sun6i-a31s, sun6i_smp_ops);
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 1f98675..d4bb239 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -29,6 +29,7 @@ MACHINE_END
static const char * const sun6i_board_dt_compat[] = {
allwinner,sun6i-a31,
+ allwinner,sun6i-a31s,
NULL,
};
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index a9d10b9..ee9d7f2 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1235,6 +1235,7 @@ static void __init sun6i_init_clocks(struct device_node
*node)
ARRAY_SIZE(sun6i_critical_clocks));
}
CLK_OF_DECLARE(sun6i_a31_clk_init, allwinner,sun6i-a31, sun6i_init_clocks);
+CLK_OF_DECLARE(sun6i_a31s_clk_init, allwinner,sun6i-a31s, sun6i_init_clocks);
CLK_OF_DECLARE(sun8i_a23_clk_init, allwinner,sun8i-a23, sun6i_init_clocks);
static void __init sun9i_init_clocks(struct device_node *node)
--
2.1.0
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[linux-sunxi] [PATCH v2 09/13] ARM: dts: sun6i: Add ir node
Add a node for the ir receiver found on the A31.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 1c1d255..85c6365 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -896,6 +896,16 @@
reg = 0x01f01c00 0x300;
};
+ ir@01f02000 {
+ compatible = allwinner,sun5i-a13-ir;
+ clocks = apb0_gates 1, ir_clk;
+ clock-names = apb, ir;
+ resets = apb0_rst 1;
+ interrupts = 0 37 4;
+ reg = 0x01f02000 0x40;
+ status = disabled;
+ };
+
r_pio: pinctrl@01f02c00 {
compatible = allwinner,sun6i-a31-r-pinctrl;
reg = 0x01f02c00 0x400;
--
2.1.0
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[linux-sunxi] [PATCH v2 08/13] ARM: dts: sun6i: Add ir_clk node
Add an ir_clk sub-node to the prcm node.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
Changes in v2:
-Use allwinner,sun4i-a10-mod0-clk as compatible, rather then a prcm specific
compatible
---
arch/arm/boot/dts/sun6i-a31.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index f47156b..1c1d255 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -878,6 +878,13 @@
apb0_i2c;
};
+ ir_clk: ir_clk {
+ #clock-cells = 0;
+ compatible = allwinner,sun4i-a10-mod0-clk;
+ clocks = osc32k, osc24M;
+ clock-output-names = ir;
+ };
+
apb0_rst: apb0_rst {
compatible = allwinner,sun6i-a31-clock-reset;
#reset-cells = 1;
--
2.1.0
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[linux-sunxi] [PATCH v2 04/13] rc: sunxi-cir: Add support for an optional reset controller
On sun6i the cir block is attached to the reset controller, add support
for de-asserting the reset if a reset controller is specified in dt.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Mauro Carvalho Chehab mche...@osg.samsung.com
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../devicetree/bindings/media/sunxi-ir.txt | 2 ++
drivers/media/rc/sunxi-cir.c | 25 --
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt
b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 23dd5ad..6b70b9b 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -10,6 +10,7 @@ Required properties:
Optional properties:
- linux,rc-map-name : Remote control map name.
+- resets : phandle + reset specifier pair
Example:
@@ -17,6 +18,7 @@ ir0: ir@01c21800 {
compatible = allwinner,sun4i-a10-ir;
clocks = apb0_gates 6, ir0_clk;
clock-names = apb, ir;
+ resets = apb0_rst 1;
interrupts = 0 5 1;
reg = 0x01C21800 0x40;
linux,rc-map-name = rc-rc6-mce;
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 340f7f5..06170e0 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -23,6 +23,7 @@
#include linux/interrupt.h
#include linux/module.h
#include linux/of_platform.h
+#include linux/reset.h
#include media/rc-core.h
#define SUNXI_IR_DEV sunxi-ir
@@ -95,6 +96,7 @@ struct sunxi_ir {
int irq;
struct clk *clk;
struct clk *apb_clk;
+ struct reset_control *rst;
const char *map_name;
};
@@ -166,15 +168,29 @@ static int sunxi_ir_probe(struct platform_device *pdev)
return PTR_ERR(ir-clk);
}
+ /* Reset (optional) */
+ ir-rst = devm_reset_control_get_optional(dev, NULL);
+ if (IS_ERR(ir-rst)) {
+ ret = PTR_ERR(ir-rst);
+ if (ret == -EPROBE_DEFER)
+ return ret;
+ ir-rst = NULL;
+ } else {
+ ret = reset_control_deassert(ir-rst);
+ if (ret)
+ return ret;
+ }
+
ret = clk_set_rate(ir-clk, SUNXI_IR_BASE_CLK);
if (ret) {
dev_err(dev, set ir base clock failed!\n);
- return ret;
+ goto exit_reset_assert;
}
if (clk_prepare_enable(ir-apb_clk)) {
dev_err(dev, try to enable apb_ir_clk failed\n);
- return -EINVAL;
+ ret = -EINVAL;
+ goto exit_reset_assert;
}
if (clk_prepare_enable(ir-clk)) {
@@ -271,6 +287,9 @@ exit_clkdisable_clk:
clk_disable_unprepare(ir-clk);
exit_clkdisable_apb_clk:
clk_disable_unprepare(ir-apb_clk);
+exit_reset_assert:
+ if (ir-rst)
+ reset_control_assert(ir-rst);
return ret;
}
@@ -282,6 +301,8 @@ static int sunxi_ir_remove(struct platform_device *pdev)
clk_disable_unprepare(ir-clk);
clk_disable_unprepare(ir-apb_clk);
+ if (ir-rst)
+ reset_control_assert(ir-rst);
spin_lock_irqsave(ir-ir_lock, flags);
/* disable IR IRQ */
--
2.1.0
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[linux-sunxi] [PATCH v2 11/13] ARM: dts: sun6i: Enable ir receiver on the Mele M9
The Mele M9 has an ir receiver, enable it.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31-m9.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts
b/arch/arm/boot/dts/sun6i-a31-m9.dts
index 3ab544f..fccf709 100644
--- a/arch/arm/boot/dts/sun6i-a31-m9.dts
+++ b/arch/arm/boot/dts/sun6i-a31-m9.dts
@@ -121,6 +121,12 @@
reg = 1;
};
};
+
+ ir@01f02000 {
+ pinctrl-names = default;
+ pinctrl-0 = ir_pins_a;
+ status = okay;
+ };
};
leds {
--
2.1.0
--
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[linux-sunxi] [PATCH v2 13/13] ARM: dts: sun6i: Add dts file for CSQ CS908 board
The CSQ CS908 is an A31s based top-set box, with 1G RAM, 8G NAND,
rtl8188etv usb wifi, 2 USB A receptacles (1 connected through the OTG
controller), ethernet, 3.5 mm jack with a/v out and hdmi out.
Note it has no sdcard slot and therefore can only be fel booted.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/sun6i-a31s-cs908.dts | 109 +
2 files changed, 111 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/sun6i-a31s-cs908.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index bc58ac3..28506ab 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -459,7 +459,8 @@ dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-app4-evb1.dtb \
sun6i-a31-colombus.dtb \
sun6i-a31-hummingbird.dtb \
- sun6i-a31-m9.dtb
+ sun6i-a31-m9.dtb \
+ sun6i-a31s-cs908.dtb
dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-bananapi.dtb \
sun7i-a20-cubieboard2.dtb \
diff --git a/arch/arm/boot/dts/sun6i-a31s-cs908.dts
b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
new file mode 100644
index 000..48d3a70
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2014 Hans de Goede hdego...@redhat.com
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+/include/ sun6i-a31s.dtsi
+
+/ {
+ model = CSQ CS908 top set box;
+ compatible = csq,cs908, allwinner,sun6i-a31s;
+
+ chosen {
+ bootargs = earlyprintk console=ttyS0,115200;
+ };
+
+ soc@01c0 {
+ usbphy: phy@01c19400 {
+ status = okay;
+ };
+
+ ehci0: usb@01c1a000 {
+ status = okay;
+ };
+
+ ehci1: usb@01c1b000 {
+ status = okay;
+ };
+
+ ohci1: usb@01c1b400 {
+ status = okay;
+ };
+
+ pio: pinctrl@01c20800 {
+ usb1_vbus_pin_csq908: usb1_vbus_pin@0 {
+ allwinner,pins = PC27;
+ allwinner,function = gpio_out;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
+ };
+
+ uart0: serial@01c28000 {
+ pinctrl-names = default;
+ pinctrl-0 = uart0_pins_a;
+ status = okay;
+ };
+
+ gmac: ethernet@01c3 {
+ pinctrl-names = default;
+ pinctrl-0 = gmac_pins_mii_a;
+ phy = phy1;
+ phy-mode = mii;
+
[linux-sunxi] [PATCH v2 10/13] ARM: dts: sun6i: Add pinmux settings for the ir pins
Add pinmux settings for the ir receive pin of the A31.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 85c6365..9e9504c 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -918,6 +918,13 @@
#interrupt-cells = 2;
#size-cells = 0;
#gpio-cells = 3;
+
+ ir_pins_a: ir@0 {
+ allwinner,pins = PL4;
+ allwinner,function = s_ir;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
};
};
};
--
2.1.0
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[linux-sunxi] [PATCH v2 12/13] ARM: dts: sun6i: Add sun6i-a31s.dtsi
Add a dtsi file for A31s based boards.
Since the A31s is the same die as the A31 in a different package, this dtsi
simply includes sun6i-a31.dtsi and then overrides the pinctrl compatible to
reflect the different package, everything else is identical.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
Changes in v2:
-include sun6i-a31.dtsi and override the pinctrl compatible, rather then
copying everything
---
arch/arm/boot/dts/sun6i-a31s.dtsi | 62 +++
1 file changed, 62 insertions(+)
create mode 100644 arch/arm/boot/dts/sun6i-a31s.dtsi
diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi
b/arch/arm/boot/dts/sun6i-a31s.dtsi
new file mode 100644
index 000..d0bd2b9
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2014 Hans de Goede hdego...@redhat.com
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * The A31s is the same die as the A31 in a different package, this is
+ * reflected by it having different pinctrl compatible everything else is
+ * identical.
+ */
+
+/include/ sun6i-a31.dtsi
+
+/ {
+ soc@01c0 {
+ pio: pinctrl@01c20800 {
+ compatible = allwinner,sun6i-a31s-pinctrl;
+ };
+ };
+};
--
2.1.0
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[linux-sunxi] Re: [PATCH resend v2] input: Add new sun4i-lradc-keys driver
On Wednesday, December 17, 2014 03:43:31 PM Hans de Goede wrote:
+ /*
+* lradc supports only one keypress at a time, release does not give
+* any info as to which key was released, so we cache the keycode.
+*/
+ if ((ints CHAN0_KEYDOWN_IRQ) lradc-chan0_keycode == 0) {
+ val = readl(lradc-base + LRADC_DATA0) 0x3f;
+ voltage = val * lradc-vref / 63;
+
+ for (i = 0; i lradc-chan0_map_count; i++) {
+ diff = abs(lradc-chan0_map[i].voltage - voltage);
+ if (diff closest) {
+ closest = diff;
+ keycode = lradc-chan0_map[i].keycode;
+ }
+ }
+
+ lradc-chan0_keycode = keycode;
+ input_report_key(lradc-input, lradc-chan0_keycode, 1);
+ }
+
+ if (ints CHAN0_KEYUP_IRQ) {
+ input_report_key(lradc-input, lradc-chan0_keycode, 0);
+ lradc-chan0_keycode = 0;
+ }
Can release and press be reported simultaneously? Should we process release
first?
Thanks.
--
Dmitry
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Re: [linux-sunxi] Re: mainline NAND
Hello, On 17 December 2014 at 11:40, Boris BREZILLON b.brezillon@gmail.com wrote: Hi Michal Le mardi 16 décembre 2014 19:01:58 UTC+1, Michal Suchanek a écrit : Hello, I tried to rebase the v7 patchset on top of 3.18 and add the DT bindings on cubieboard: https://github.com/hramrach/linux-sunxi/commit/a946d593ddcf443b0f035f6d39fe0c558189dacc The nand driver fails equally on both cubieboard versions: cubieboard: [0.643554] calling nand_base_init+0x0/0x20 @ 1 [0.643565] initcall nand_base_init+0x0/0x20 returned 0 after 3 usecs [0.643578] calling sunxi_nfc_driver_init+0x0/0x10 @ 1 [0.665751] nand: Could not find valid JEDEC parameter page; aborting [0.670907] nand: device found, Manufacturer ID: 0xec, Chip ID: 0xd7 [0.675949] nand: Samsung NAND 4GiB 3,3V 8-bit [0.679098] nand: 4096MiB, MLC, page size: 8192, OOB size: 640 [0.683748] sunxi_nand 1c03000.nand: ECC init failed: -22 [0.687839] sunxi_nand 1c03000.nand: failed to init nand chips [0.692440] sunxi_nand: probe of 1c03000.nand failed with error -22 [0.697500] initcall sunxi_nfc_driver_init+0x0/0x10 returned 0 after 52642 usecs cubieboard2: [0.666766] calling nand_base_init+0x0/0x20 @ 1 [0.666777] initcall nand_base_init+0x0/0x20 returned 0 after 3 usecs [0.666790] calling sunxi_nfc_driver_init+0x0/0x10 @ 1 [0.683003] nand: Could not find valid JEDEC parameter page; aborting [0.688159] nand: device found, Manufacturer ID: 0xec, Chip ID: 0xd7 [0.693201] nand: Samsung NAND 4GiB 3,3V 8-bit [0.696349] nand: 4096MiB, MLC, page size: 8192, OOB size: 640 [0.700956] sunxi_nand 1c03000.nand: ECC init failed: -22 [0.705060] sunxi_nand 1c03000.nand: failed to init nand chips [0.709658] sunxi_nand: probe of 1c03000.nand failed with error -22 [0.714768] initcall sunxi_nfc_driver_init+0x0/0x10 returned 0 after 46833 usecs Is this expected or does somebody have the driver working on some device? As Henrik already answered, it seems that your NAND chip is not properly defined in the nand_ids table [1]. Read your NAND datasheet and add a new entry (take a look at this one [2] as an example). You should also fill the correct timing mode, though mode 0 should work correctly on all recent NANDs. The nand chip says Samsung 222 K9GBG08U0A SCB0 Is there some document on filling out his table? It seems that 0xec 0xd7 matches info on top op page 80 of http://www.datasheet4u.com/datasheet-pdf/Samsung/K9GBG08U0A/pdf.php?id=704185 But that table lists 0xec, 0xd7, 0x94, 0x76, 0x64, 0x43 and additional debug output shows that the chip sends Manufacturer ID: 0xec, Chip ID: 0xd7; 0x94 0x7a 0x54 0x43 0xec 0xd7 the last two bytes possibly being wrap-around of the first two. However, that document lists multitudes of identification strings. Which one is used where in the table? The document lists that there is 8k page and 640 oob which matches existing output. It also says that that ecc is 40bit (1k + 80byte) on page 5 which looks like value obtained by dividing that 640 oob data by 8 to get oob amount per 1k - no staggering new information. Some timing information is presented on pages 18-19 but the provided table has way more data than a nand entry in the kernel table. Thanks Michal -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [PATCH v2 04/13] rc: sunxi-cir: Add support for an optional reset controller
Hi,
On Thu, Dec 18, 2014 at 1:18 AM, Hans de Goede hdego...@redhat.com wrote:
On sun6i the cir block is attached to the reset controller, add support
for de-asserting the reset if a reset controller is specified in dt.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Mauro Carvalho Chehab mche...@osg.samsung.com
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../devicetree/bindings/media/sunxi-ir.txt | 2 ++
drivers/media/rc/sunxi-cir.c | 25
--
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt
b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 23dd5ad..6b70b9b 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -10,6 +10,7 @@ Required properties:
Optional properties:
- linux,rc-map-name : Remote control map name.
+- resets : phandle + reset specifier pair
Should it be optional? Or should we use a sun6i compatible with
a mandatory reset phandle? I mean, the driver/hardware is not
going to work with the reset missing on sun6i.
Seems we are doing it one way for some of our drivers, and
the other (optional) way for more generic ones, like USB.
ChenYu
Example:
@@ -17,6 +18,7 @@ ir0: ir@01c21800 {
compatible = allwinner,sun4i-a10-ir;
clocks = apb0_gates 6, ir0_clk;
clock-names = apb, ir;
+ resets = apb0_rst 1;
interrupts = 0 5 1;
reg = 0x01C21800 0x40;
linux,rc-map-name = rc-rc6-mce;
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 340f7f5..06170e0 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -23,6 +23,7 @@
#include linux/interrupt.h
#include linux/module.h
#include linux/of_platform.h
+#include linux/reset.h
#include media/rc-core.h
#define SUNXI_IR_DEV sunxi-ir
@@ -95,6 +96,7 @@ struct sunxi_ir {
int irq;
struct clk *clk;
struct clk *apb_clk;
+ struct reset_control *rst;
const char *map_name;
};
@@ -166,15 +168,29 @@ static int sunxi_ir_probe(struct platform_device *pdev)
return PTR_ERR(ir-clk);
}
+ /* Reset (optional) */
+ ir-rst = devm_reset_control_get_optional(dev, NULL);
+ if (IS_ERR(ir-rst)) {
+ ret = PTR_ERR(ir-rst);
+ if (ret == -EPROBE_DEFER)
+ return ret;
+ ir-rst = NULL;
+ } else {
+ ret = reset_control_deassert(ir-rst);
+ if (ret)
+ return ret;
+ }
+
ret = clk_set_rate(ir-clk, SUNXI_IR_BASE_CLK);
if (ret) {
dev_err(dev, set ir base clock failed!\n);
- return ret;
+ goto exit_reset_assert;
}
if (clk_prepare_enable(ir-apb_clk)) {
dev_err(dev, try to enable apb_ir_clk failed\n);
- return -EINVAL;
+ ret = -EINVAL;
+ goto exit_reset_assert;
}
if (clk_prepare_enable(ir-clk)) {
@@ -271,6 +287,9 @@ exit_clkdisable_clk:
clk_disable_unprepare(ir-clk);
exit_clkdisable_apb_clk:
clk_disable_unprepare(ir-apb_clk);
+exit_reset_assert:
+ if (ir-rst)
+ reset_control_assert(ir-rst);
return ret;
}
@@ -282,6 +301,8 @@ static int sunxi_ir_remove(struct platform_device *pdev)
clk_disable_unprepare(ir-clk);
clk_disable_unprepare(ir-apb_clk);
+ if (ir-rst)
+ reset_control_assert(ir-rst);
spin_lock_irqsave(ir-ir_lock, flags);
/* disable IR IRQ */
--
2.1.0
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[linux-sunxi] [PATCH v2 04/11] ARM: dts: sun9i: Add clock-indices property for bus gate clocks
of_clk_get_parent_name() uses the clock-indices property to resolve clock phandle arguments in case that the argument index does not match the clock-output-names sequence. This is the case on sunxi, where we use the actual bit index as the argument to the phandle. Add the clock-indices property so that of_clk_get_parent_name() resolves the names correctly. Signed-off-by: Chen-Yu Tsai w...@csie.org --- arch/arm/boot/dts/sun9i-a80.dtsi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index b595d9e..eb3f91b 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -256,6 +256,9 @@ compatible = allwinner,sun9i-a80-ahb0-gates-clk; reg = 0x06000580 0x4; clocks = ahb0; + clock-indices = 0, 1, 3, 5, 8, 12, 13, + 14, 15, 16, 18, 20, 21, + 22, 23; clock-output-names = ahb0_fd, ahb0_ve, ahb0_gpu, ahb0_ss, ahb0_sd, ahb0_nand1, ahb0_nand0, ahb0_sdram, @@ -269,6 +272,7 @@ compatible = allwinner,sun9i-a80-ahb1-gates-clk; reg = 0x06000584 0x4; clocks = ahb1; + clock-indices = 0, 1, 17, 21, 22, 23, 24; clock-output-names = ahb1_usbotg, ahb1_usbhci, ahb1_gmac, ahb1_msgbox, ahb1_spinlock, ahb1_hstimer, @@ -280,6 +284,8 @@ compatible = allwinner,sun9i-a80-ahb2-gates-clk; reg = 0x06000588 0x4; clocks = ahb2; + clock-indices = 0, 1, 2, 4, 5, 7, 8, + 11; clock-output-names = ahb2_lcd0, ahb2_lcd1, ahb2_edp, ahb2_csi, ahb2_hdmi, ahb2_de, ahb2_mp, ahb2_mipi_dsi; @@ -290,6 +296,8 @@ compatible = allwinner,sun9i-a80-apb0-gates-clk; reg = 0x06000590 0x4; clocks = apb0; + clock-indices = 1, 5, 11, 12, 13, 15, + 17, 18, 19; clock-output-names = apb0_spdif, apb0_pio, apb0_ac97, apb0_i2s0, apb0_i2s1, apb0_lradc, apb0_gpadc, apb0_twd, @@ -301,6 +309,8 @@ compatible = allwinner,sun9i-a80-apb1-gates-clk; reg = 0x06000594 0x4; clocks = apb1; + clock-indices = 0, 1, 2, 3, 4, + 16, 17, 18, 19, 20, 21; clock-output-names = apb1_i2c0, apb1_i2c1, apb1_i2c2, apb1_i2c3, apb1_i2c4, apb1_uart0, apb1_uart1, -- 2.1.3 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v2 09/11] ARM: dts: sun9i: Enable mmc0 on A80 Optimus Board
Enable the micro-sd slot on the A80 Optimus Board, which is connected to
mmc0. This adds the card-detect gpio and enables mmc0.
This patch also adds a 3V fixed regulator, which is the default I/O
voltage level.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Signed-off-by: Andreas Färber afaer...@suse.de
---
arch/arm/boot/dts/sun9i-a80-optimus.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts
b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 506948f..4c94aff 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -49,6 +49,7 @@
/dts-v1/;
/include/ sun9i-a80.dtsi
+/include/ sunxi-common-regulators.dtsi
/ {
model = Merrii A80 Optimus Board;
@@ -59,6 +60,16 @@
};
soc {
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = default;
+ pinctrl-0 = mmc0_pins, mmc0_cd_pin_optimus;
+ vmmc-supply = reg_vcc3v0;
+ bus-width = 4;
+ cd-gpios = pio 7 18 0; /* PH8 */
+ cd-inverted;
+ status = okay;
+ };
+
pio: pinctrl@06000800 {
i2c3_pins_a: i2c3@0 {
/* Enable internal pull-up */
@@ -72,6 +83,13 @@
allwinner,pull = 0;
};
+ mmc0_cd_pin_optimus: mmc0_cd_pin@0 {
+ allwinner,pins = PH18;
+ allwinner,function = gpio_in;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
+
uart4_pins_a: uart4@0 {
/* Enable internal pull-up */
allwinner,pull = 1;
--
2.1.3
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[linux-sunxi] [PATCH v2 01/11] clk: sunxi: Add mod0 and mmc module clock support for A80
The module 0 style clocks, or storage module clocks as named in the
official SDK, are almost the same as the module 0 clocks on earlier
Allwinner SoCs. The only difference is wider mux register bits.
As with earlier Allwinner SoCs, mmc module clocks are a special case
of mod0 clocks, with phase controls for 2 child clocks, output and
sample.
This patch adds support for both.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 7 +-
drivers/clk/sunxi/clk-mod0.c | 99 +++
2 files changed, 104 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 8c60433..b660bdb 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -56,7 +56,9 @@ Required properties:
allwinner,sun8i-a23-apb2-gates-clk - for the APB2 gates on A23
allwinner,sun5i-a13-mbus-clk - for the MBUS clock on A13
allwinner,sun4i-a10-mmc-clk - for the MMC clock
+ allwinner,sun9i-a80-mmc-clk - for mmc module clocks on A80
allwinner,sun4i-a10-mod0-clk - for the module 0 family of clocks
+ allwinner,sun9i-a80-mod0-clk - for module 0 (storage) clocks on A80
allwinner,sun8i-a23-mbus-clk - for the MBUS clock on A23
allwinner,sun7i-a20-out-clk - for the external output clocks
allwinner,sun7i-a20-gmac-clk - for the GMAC clock module on A20/A31
@@ -72,7 +74,8 @@ Required properties for all clocks:
- #clock-cells : from common clock binding; shall be set to 0 except for
the following compatibles where it shall be set to 1:
allwinner,*-gates-clk, allwinner,sun4i-pll5-clk,
- allwinner,sun4i-pll6-clk, allwinner,sun6i-a31-pll6-clk
+ allwinner,sun4i-pll6-clk, allwinner,sun6i-a31-pll6-clk,
+ allwinner,*-usb-clk, allwinner,*-mmc-clk
- clock-output-names : shall be the corresponding names of the outputs.
If the clock module only has one output, the name shall be the
module name.
@@ -94,7 +97,7 @@ For allwinner,sun6i-a31-pll6-clk, there are 2 outputs. The
first output
is the normal PLL6 output, or pll6. The second output is rate doubled
PLL6, or pll6x2.
-The allwinner,sun4i-a10-mmc-clk has three different outputs: the
+The allwinner,*-mmc-clk clocks have three different outputs: the
main clock, with the ID 0, and the output and sample clocks, with the
IDs 1 and 2, respectively.
diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c
index 4ac52c7..ef36e89 100644
--- a/drivers/clk/sunxi/clk-mod0.c
+++ b/drivers/clk/sunxi/clk-mod0.c
@@ -93,6 +93,30 @@ static void __init sun4i_a10_mod0_setup(struct device_node
*node)
}
CLK_OF_DECLARE(sun4i_a10_mod0, allwinner,sun4i-a10-mod0-clk,
sun4i_a10_mod0_setup);
+static const struct factors_data sun9i_a80_mod0_data __initconst = {
+ .enable = 31,
+ .mux = 24,
+ .muxmask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
+ .table = sun4i_a10_mod0_config,
+ .getter = sun4i_a10_get_mod0_factors,
+};
+
+static void __init sun9i_a80_mod0_setup(struct device_node *node)
+{
+ void __iomem *reg;
+
+ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+ if (!reg) {
+ pr_err(Could not get registers for mod0-clk: %s\n,
+ node-name);
+ return;
+ }
+
+ sunxi_factors_register(node, sun9i_a80_mod0_data,
+ sun4i_a10_mod0_lock, reg);
+}
+CLK_OF_DECLARE(sun9i_a80_mod0, allwinner,sun9i-a80-mod0-clk,
sun9i_a80_mod0_setup);
+
static DEFINE_SPINLOCK(sun5i_a13_mbus_lock);
static void __init sun5i_a13_mbus_setup(struct device_node *node)
@@ -309,3 +333,78 @@ err_free_data:
kfree(clk_data);
}
CLK_OF_DECLARE(sun4i_a10_mmc, allwinner,sun4i-a10-mmc-clk,
sun4i_a10_mmc_setup);
+
+static DEFINE_SPINLOCK(sun9i_a80_mmc_lock);
+
+static void __init sun9i_a80_mmc_setup(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ const char *parent;
+ void __iomem *reg;
+ int i;
+
+ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+ if (IS_ERR(reg)) {
+ pr_err(Couldn't map the %s clock registers\n, node-name);
+ return;
+ }
+
+ clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
+ if (!clk_data)
+ return;
+
+ clk_data-clks = kcalloc(3, sizeof(*clk_data-clks), GFP_KERNEL);
+ if (!clk_data-clks)
+ goto err_free_data;
+
+ clk_data-clk_num = 3;
+ clk_data-clks[0] = sunxi_factors_register(node,
+ sun9i_a80_mod0_data,
+ sun9i_a80_mmc_lock, reg);
+ if (!clk_data-clks[0])
+ goto err_free_clks;
+
+ parent = __clk_get_name(clk_data-clks[0]);
+
+ for
[linux-sunxi] [PATCH v2 08/11] ARM: dts: sun9i: Add pinmux setting for mmc0
mmc0 is only available on port F, and is always used with a 4 bit wide
bus for the onboard micro-sd slot.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Signed-off-by: Andreas Färber afaer...@suse.de
---
arch/arm/boot/dts/sun9i-a80.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 87198b1..b42e2e7 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -466,6 +466,14 @@
allwinner,pull = 0;
};
+ mmc0_pins: mmc0 {
+ allwinner,pins = PF0, PF1 ,PF2, PF3,
+PF4, PF5;
+ allwinner,function = mmc0;
+ allwinner,drive = 2;
+ allwinner,pull = 0;
+ };
+
uart0_pins_a: uart0@0 {
allwinner,pins = PH12, PH13;
allwinner,function = uart0;
--
2.1.3
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[linux-sunxi] [PATCH v2 11/11] ARM: dts: sun9i: Enable mmc2 on A80 Optimus Board
The A80 Optimus Board has a 16GB eMMC connected to mmc2, with 8 bit
wide data bus.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Signed-off-by: Andreas Färber afaer...@suse.de
---
arch/arm/boot/dts/sun9i-a80-optimus.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts
b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 4c94aff..2d0d490 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -70,6 +70,15 @@
status = okay;
};
+ mmc2: mmc@01c11000 {
+ pinctrl-names = default;
+ pinctrl-0 = mmc2_8bit_pins;
+ vmmc-supply = reg_vcc3v0;
+ bus-width = 8;
+ non-removable;
+ status = okay;
+ };
+
pio: pinctrl@06000800 {
i2c3_pins_a: i2c3@0 {
/* Enable internal pull-up */
--
2.1.3
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[linux-sunxi] [PATCH v2 06/11] ARM: dts: sunxi: Use label to reference pio in sunxi-common-regulators
Use the label to reference the pin controller node, so that we can use
sunxi-common-regulators with sunxi families that don't share the same
address space mappings, such as sun9i.
This patch is mostly space changes due to the reduction of node parents.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sunxi-common-regulators.dtsi | 54 +-
1 file changed, 26 insertions(+), 28 deletions(-)
diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi
b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
index d887663..4bfb0c0 100644
--- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi
+++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
@@ -47,39 +47,37 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-/ {
- soc@01c0 {
- pio: pinctrl@01c20800 {
- ahci_pwr_pin_a: ahci_pwr_pin@0 {
- allwinner,pins = PB8;
- allwinner,function = gpio_out;
- allwinner,drive = 0;
- allwinner,pull = 0;
- };
+pio {
+ ahci_pwr_pin_a: ahci_pwr_pin@0 {
+ allwinner,pins = PB8;
+ allwinner,function = gpio_out;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
- usb0_vbus_pin_a: usb0_vbus_pin@0 {
- allwinner,pins = PB9;
- allwinner,function = gpio_out;
- allwinner,drive = 0;
- allwinner,pull = 0;
- };
+ usb0_vbus_pin_a: usb0_vbus_pin@0 {
+ allwinner,pins = PB9;
+ allwinner,function = gpio_out;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
- usb1_vbus_pin_a: usb1_vbus_pin@0 {
- allwinner,pins = PH6;
- allwinner,function = gpio_out;
- allwinner,drive = 0;
- allwinner,pull = 0;
- };
+ usb1_vbus_pin_a: usb1_vbus_pin@0 {
+ allwinner,pins = PH6;
+ allwinner,function = gpio_out;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
- usb2_vbus_pin_a: usb2_vbus_pin@0 {
- allwinner,pins = PH3;
- allwinner,function = gpio_out;
- allwinner,drive = 0;
- allwinner,pull = 0;
- };
- };
+ usb2_vbus_pin_a: usb2_vbus_pin@0 {
+ allwinner,pins = PH3;
+ allwinner,function = gpio_out;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
};
+};
+/ {
reg_ahci_5v: ahci-5v {
compatible = regulator-fixed;
pinctrl-names = default;
--
2.1.3
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[linux-sunxi] [PATCH v2 07/11] ARM: dts: sun9i: Add mmc controller nodes to the A80 dtsi
The A80 has 4 mmc controllers.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Signed-off-by: Andreas Färber afaer...@suse.de
---
arch/arm/boot/dts/sun9i-a80.dtsi | 48
1 file changed, 48 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index cd09de2..87198b1 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -329,6 +329,54 @@
*/
ranges = 0 0 0 0x2000;
+ mmc0: mmc@01c0f000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c0f000 0x1000;
+ clocks = mmc_config_clk 0, mmc0_clk 0,
+mmc0_clk 1, mmc0_clk 2;
+ clock-names = ahb, mmc, output, sample;
+ resets = mmc_config_clk 0;
+ reset-names = ahb;
+ interrupts = 0 60 4;
+ status = disabled;
+ };
+
+ mmc1: mmc@01c1 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c1 0x1000;
+ clocks = mmc_config_clk 1, mmc1_clk 0,
+mmc1_clk 1, mmc1_clk 2;
+ clock-names = ahb, mmc, output, sample;
+ resets = mmc_config_clk 1;
+ reset-names = ahb;
+ interrupts = 0 61 4;
+ status = disabled;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c11000 0x1000;
+ clocks = mmc_config_clk 2, mmc2_clk 0,
+mmc2_clk 1, mmc2_clk 2;
+ clock-names = ahb, mmc, output, sample;
+ resets = mmc_config_clk 2;
+ reset-names = ahb;
+ interrupts = 0 62 4;
+ status = disabled;
+ };
+
+ mmc3: mmc@01c12000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c12000 0x1000;
+ clocks = mmc_config_clk 3, mmc3_clk 0,
+mmc3_clk 1, mmc3_clk 2;
+ clock-names = ahb, mmc, output, sample;
+ resets = mmc_config_clk 3;
+ reset-names = ahb;
+ interrupts = 0 63 4;
+ status = disabled;
+ };
+
mmc_config_clk: clk@01c13000 {
compatible = allwinner,sun9i-a80-mmc-config-clk;
reg = 0x01c13000 0x10;
--
2.1.3
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[linux-sunxi] [PATCH v2 10/11] ARM: dts: sun9i: Add 8 bit mmc pinmux setting for mmc2
mmc2 is available on port C. Add a pinmux setting for 8 bit wide eMMC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Signed-off-by: Andreas Färber afaer...@suse.de
---
arch/arm/boot/dts/sun9i-a80.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index b42e2e7..7dc09e7 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -474,6 +474,15 @@
allwinner,pull = 0;
};
+ mmc2_8bit_pins: mmc2_8bit {
+ allwinner,pins = PC6, PC7, PC8, PC9,
+PC10, PC11, PC12,
+PC13, PC14, PC15;
+ allwinner,function = mmc2;
+ allwinner,drive = 2;
+ allwinner,pull = 1;
+ };
+
uart0_pins_a: uart0@0 {
allwinner,pins = PH12, PH13;
allwinner,function = uart0;
--
2.1.3
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[linux-sunxi] [PATCH v2 05/11] ARM: dts: sun9i: Add mmc config clock nodes
Add the device tree nodes for the mmc config clock nodes.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun9i-a80.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index eb3f91b..cd09de2 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -329,6 +329,19 @@
*/
ranges = 0 0 0 0x2000;
+ mmc_config_clk: clk@01c13000 {
+ compatible = allwinner,sun9i-a80-mmc-config-clk;
+ reg = 0x01c13000 0x10;
+ clocks = ahb0_gates 8;
+ clock-names = ahb;
+ resets = ahb0_resets 8;
+ reset-names = ahb;
+ #clock-cells = 1;
+ #reset-cells = 1;
+ clock-output-names = mmc0_config, mmc1_config,
+mmc2_config, mmc3_config;
+ };
+
gic: interrupt-controller@01c41000 {
compatible = arm,cortex-a7-gic, arm,cortex-a15-gic;
reg = 0x01c41000 0x1000,
--
2.1.3
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[linux-sunxi] [PATCH v2 02/11] ARM: dts: sun9i: Add mmc module clock nodes for A80
The mmc module clocks are A80 specific module 0 (storage) type clocks.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Signed-off-by: Andreas Färber afaer...@suse.de
---
arch/arm/boot/dts/sun9i-a80.dtsi | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 494714f..b595d9e 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -215,6 +215,42 @@
clock-output-names = cci400;
};
+ mmc0_clk: clk@06000410 {
+ #clock-cells = 1;
+ compatible = allwinner,sun9i-a80-mmc-clk;
+ reg = 0x06000410 0x4;
+ clocks = osc24M, pll4;
+ clock-output-names = mmc0, mmc0_output,
+mmc0_sample;
+ };
+
+ mmc1_clk: clk@06000414 {
+ #clock-cells = 1;
+ compatible = allwinner,sun9i-a80-mmc-clk;
+ reg = 0x06000414 0x4;
+ clocks = osc24M, pll4;
+ clock-output-names = mmc1, mmc1_output,
+mmc1_sample;
+ };
+
+ mmc2_clk: clk@06000418 {
+ #clock-cells = 1;
+ compatible = allwinner,sun9i-a80-mmc-clk;
+ reg = 0x06000418 0x4;
+ clocks = osc24M, pll4;
+ clock-output-names = mmc2, mmc2_output,
+mmc2_sample;
+ };
+
+ mmc3_clk: clk@0600041c {
+ #clock-cells = 1;
+ compatible = allwinner,sun9i-a80-mmc-clk;
+ reg = 0x0600041c 0x4;
+ clocks = osc24M, pll4;
+ clock-output-names = mmc3, mmc3_output,
+mmc3_sample;
+ };
+
ahb0_gates: clk@06000580 {
#clock-cells = 1;
compatible = allwinner,sun9i-a80-ahb0-gates-clk;
--
2.1.3
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[linux-sunxi] [PATCH v2 00/11] ARM: sun9i: Enable MMC support on Allwinner A80
Hi Maxime, This is v2 of the sun9i mmc series. It is based on your v2 of your sunxi mmc phase clocks series. The clock bits will conflict with Hans' work on the mod0 clock. The DT bits might conflict with your header conversion series. Assuming this series is OK, how would you like to proceed? This series enables MMC support on the A80 using existing drivers we have. The A80 has 4 MMC controllers. These controllers share a common clock gate and reset control, which are then sub-divided to each controller. The phase clocks are the same as the older SoCs, so it should be straight forward to add them with the rest of the sunxi family. I did find that Allwinner's kernel uses different delay values for the A80, but so far I've not run into any issues using the mainline kernel. Patch 1 adds module 0 type clock support for the A80. These are essentially the same as mod0 clocks on other Allwinner SoCs, except for the wider mux bits. Patch 2 adds mmc mod clocks to the DTSI. Patch 3 adds support for the mmc config (term from user manual) clocks. This is the part that breaks out the clock gates and reset controls for each controller. This is implemented as a platform driver, as the shared reset control must be de-asserted for any of either this or the mmc blocks to work. Patch 4 adds clock-indices properties to the AHB/APB gate clocks. This is needed for of_clk_get_parent_name to work properly, as we use bit indices instead of counting the entries. Patch 5 adds the mmc config clock nodes to the DTSI. Patch 6 changes sunxi-common-regulators.dtsi to use labels to reference the pio node. Patch 7 adds the mmc controller nodes to the DTSI. Patch 8 and 10 add the pinmux settings for mmc0 and mmc2. Patch 9 and 11 enable mmc0 and mmc2 on the A80 Optimus Board. Kudos to Andreas for figuring out all the DT bits. His SoB is on the relevant patches. Changes since v1: - Use sunxi-common-regulators.dtsi for vmmc regulator - Rebased onto sunxi mmc phase clock series v2 - Use new multi-output mmc module clock style - Rename sun9i mmc config clock name and compatible - Make mmc2_pins include all pins needed, and change name to mmc2_8bit_pins - Add spaces between pin names in mmc pins - Add clk_prepare_enable()/clk_disable_unprepare() calls to reset control ops for the mmc config clock - Use DIV_ROUND_UP when calculating number of clocks in sun9i mmc config clock probe function - Add required properties and outputs section for sun9i mmc config clock in bindings doc; also add an example Cheers ChenYu Tsai Chen-Yu Tsai (11): clk: sunxi: Add mod0 and mmc module clock support for A80 ARM: dts: sun9i: Add mmc module clock nodes for A80 clk: sunxi: Add driver for A80 MMC config clocks/resets ARM: dts: sun9i: Add clock-indices property for bus gate clocks ARM: dts: sun9i: Add mmc config clock nodes ARM: dts: sunxi: Use label to reference pio in sunxi-common-regulators ARM: dts: sun9i: Add mmc controller nodes to the A80 dtsi ARM: dts: sun9i: Add pinmux setting for mmc0 ARM: dts: sun9i: Enable mmc0 on A80 Optimus Board ARM: dts: sun9i: Add 8 bit mmc pinmux setting for mmc2 ARM: dts: sun9i: Enable mmc2 on A80 Optimus Board Documentation/devicetree/bindings/clock/sunxi.txt | 30 ++- arch/arm/boot/dts/sun9i-a80-optimus.dts | 27 +++ arch/arm/boot/dts/sun9i-a80.dtsi | 124 arch/arm/boot/dts/sunxi-common-regulators.dtsi| 54 +++--- drivers/clk/sunxi/Makefile| 1 + drivers/clk/sunxi/clk-mod0.c | 99 ++ drivers/clk/sunxi/clk-sun9i-mmc.c | 222 ++ 7 files changed, 527 insertions(+), 30 deletions(-) create mode 100644 drivers/clk/sunxi/clk-sun9i-mmc.c -- 2.1.3 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: mainline NAND
Hi Michal
add the following to the nand id table
{K9GBG08U0A 32G 3.3V 8-bit,
{ .id = {0xec, 0xd7, 0x94, 0x7a, 0x54, 0x43} },
SZ_8K, SZ_4K, SZ_1M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K),
0 },
http://lxr.free-electrons.com/source/include/linux/mtd/nand.h#L787
On Thu, Dec 18, 2014 at 5:07 AM, Michal Suchanek hramr...@gmail.com wrote:
Hello,
On 17 December 2014 at 11:40, Boris BREZILLON b.brezillon@gmail.com
wrote:
Hi Michal
Le mardi 16 décembre 2014 19:01:58 UTC+1, Michal Suchanek a écrit :
Hello,
I tried to rebase the v7 patchset on top of 3.18 and add the DT
bindings on cubieboard:
https://github.com/hramrach/linux-sunxi/commit/a946d593ddcf443b0f035f6d39fe0c558189dacc
The nand driver fails equally on both cubieboard versions:
cubieboard:
[0.643554] calling nand_base_init+0x0/0x20 @ 1
[0.643565] initcall nand_base_init+0x0/0x20 returned 0 after 3 usecs
[0.643578] calling sunxi_nfc_driver_init+0x0/0x10 @ 1
[0.665751] nand: Could not find valid JEDEC parameter page; aborting
[0.670907] nand: device found, Manufacturer ID: 0xec, Chip ID: 0xd7
[0.675949] nand: Samsung NAND 4GiB 3,3V 8-bit
[0.679098] nand: 4096MiB, MLC, page size: 8192, OOB size: 640
[0.683748] sunxi_nand 1c03000.nand: ECC init failed: -22
[0.687839] sunxi_nand 1c03000.nand: failed to init nand chips
[0.692440] sunxi_nand: probe of 1c03000.nand failed with error -22
[0.697500] initcall sunxi_nfc_driver_init+0x0/0x10 returned 0
after 52642 usecs
cubieboard2:
[0.666766] calling nand_base_init+0x0/0x20 @ 1
[0.666777] initcall nand_base_init+0x0/0x20 returned 0 after 3 usecs
[0.666790] calling sunxi_nfc_driver_init+0x0/0x10 @ 1
[0.683003] nand: Could not find valid JEDEC parameter page; aborting
[0.688159] nand: device found, Manufacturer ID: 0xec, Chip ID: 0xd7
[0.693201] nand: Samsung NAND 4GiB 3,3V 8-bit
[0.696349] nand: 4096MiB, MLC, page size: 8192, OOB size: 640
[0.700956] sunxi_nand 1c03000.nand: ECC init failed: -22
[0.705060] sunxi_nand 1c03000.nand: failed to init nand chips
[0.709658] sunxi_nand: probe of 1c03000.nand failed with error -22
[0.714768] initcall sunxi_nfc_driver_init+0x0/0x10 returned 0
after 46833 usecs
Is this expected or does somebody have the driver working on some
device?
As Henrik already answered, it seems that your NAND chip is not properly
defined in the nand_ids table [1].
Read your NAND datasheet and add a new entry (take a look at this one
[2] as
an example).
You should also fill the correct timing mode, though mode 0 should work
correctly on all recent NANDs.
The nand chip says Samsung 222 K9GBG08U0A SCB0
Is there some document on filling out his table?
It seems that 0xec 0xd7 matches info on top op page 80 of
http://www.datasheet4u.com/datasheet-pdf/Samsung/K9GBG08U0A/pdf.php?id=704185
But that table lists 0xec, 0xd7, 0x94, 0x76, 0x64, 0x43 and additional
debug output shows that the chip sends Manufacturer ID: 0xec, Chip
ID: 0xd7; 0x94 0x7a 0x54 0x43 0xec 0xd7 the last two bytes possibly
being wrap-around of the first two.
However, that document lists multitudes of identification strings.
Which one is used where in the table?
The document lists that there is 8k page and 640 oob which matches
existing output. It also says that that ecc is 40bit (1k + 80byte) on
page 5 which looks like value obtained by dividing that 640 oob data
by 8 to get oob amount per 1k - no staggering new information.
Some timing information is presented on pages 18-19 but the provided
table has way more data than a nand entry in the kernel table.
Thanks
Michal
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