[linux-sunxi] Re: [PATCH v6 1/5] clk: Add a basic multiplier clock

[Maxime Ripard]

On Tue, Oct 20, 2015 at 09:29:39AM -0700, Michael Turquette wrote:
> Quoting Maxime Ripard (2015-10-20 07:40:47)
> > Hi Mike,
> > 
> > On Tue, Oct 20, 2015 at 06:43:43AM -0700, Michael Turquette wrote:
> > > Hi Maxime,
> > > 
> > > Quoting Maxime Ripard (2015-10-20 00:36:45)
> > > > +struct clk *clk_register_multiplier(struct device *dev, const char 
> > > > *name,
> > > > +   const char *parent_name,
> > > > +   unsigned long flags,
> > > > +   void __iomem *reg, u8 shift, u8 
> > > > width,
> > > > +   u8 clk_mult_flags, spinlock_t *lock)
> > > > +{
> > > 
> > > Patch looks good in general. However this is a good opportunity to stop
> > > the madness around the registration functions in these basic clock
> > > types.
> > > 
> > > clk_register is really all that we need since we've had struct
> > > clk_init_data for a while. Initializing a multiplier should be as simple
> > > as:
> > > 
> > >   struct clk_multiplier clk_foo = {
> > >   .hw.init = &(struct clk_init_data){
> > >   .name = "foo",
> > >   .parent_names = (const char *[]){
> > >   "bar",
> > >   },
> > >   .num_parents = 1;
> > >   .ops = _multiplier_ops,
> > >   },
> > >   .reg = 0xd34db33f,
> > >   .shift = 1,
> > >   .width = 2,
> > >   };
> > > 
> > >   clk_register(dev, _foo.hw);
> > > 
> > > This is nice since it turns these basic clocks into even more of a
> > > library and less of a poor mans driver.
> > > 
> > > (I really hope the above works. I did not test it)
> > > 
> > > Is it possible you can convert to using this method, and if it is
> > > correct for you then just remove clk_multiplier_register altogether? (In
> > > fact you might not use the registration function at all since you use
> > > the composite clock...)
> > 
> > This chunk of code has been here since v2, which has been first posted
> > in May, two and half kernel releases ago.
> > 
> > In the meantime, we had a full-blown DMA driver and a quite unusual
> > ASoC driver merged. For some reason, this is the only piece of the
> > audio support that is missing for us, while at the same time it's the
> > most trivial.
> > 
> > If that's the only issue you have with this patch, I'm fine with
> > sending a subsequent patch this week. But I'd be really unhappy with
> > sending yet another version for a single change, while you had 5
> > monthes to review it, and we discussed it several times on IRC and
> > face to face.
> 
> The change can go in later. It's not a prerequisite. I had a feeling
> you'd be grumpy about me asking but I thought I'd try anyways. I won't
> even ask if you got sign-off from Jim on whether this works for his
> platforms ;-)

I asked several times, he never replied... :/

> The copy/paste nature of these basic clock types really sucks and it is
> one of many reasons that I am hesitant to accept them and slow to merge
> them...

I guess we cover all cases now? So it shouldn't grow that much.

> Anyways it seems that you are not using the registration function at all
> so I might just follow up with a patch to remove it.
> 
> I can pick these 5 patches directly, or do you plan to send a PR?

I have a pull request coming for you with a single patch, I can apply
them on that branch and send you the PR later today if it's okay?

Thanks,
Maxime

-- 
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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Re: [linux-sunxi] [PATCH v2 1/1] dts: sun6i: yones toptech bs1078 v2: Add AXP221 support to dts

[Maxime Ripard]

Hi Chen-Yu,

On Mon, Oct 19, 2015 at 05:59:20PM +0800, Chen-Yu Tsai wrote:
> > +/* Voltage source for I2C pullup resistors for I2C Bus 0 */
> > +_dldo3 {
> > +   regulator-always-on;
> > +   regulator-min-microvolt = <280>;
> > +   regulator-max-microvolt = <280>;
> > +   regulator-name = "vcc-csi";
> 
> This should probably be named "vddio-csi".
> 
> I think Maxime and Hans were still debating whether the camera VDDIO
> regulator should be defined independently as "always-on", instead of
> having the I2C subsystem do some kind of power sequencing.
> 
> I wonder if the power domain stuff would work for this.

Probably not, power domains are more targeted for in-SoC supplies
(like when you can gate the power controler by controler).

This is for external signals.

Maxime

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[linux-sunxi] Re: [PATCH v6 1/5] clk: Add a basic multiplier clock

[Michael Turquette]

Quoting Maxime Ripard (2015-10-21 07:53:35)
> On Tue, Oct 20, 2015 at 09:29:39AM -0700, Michael Turquette wrote:
> > Quoting Maxime Ripard (2015-10-20 07:40:47)
> > > Hi Mike,
> > > 
> > > On Tue, Oct 20, 2015 at 06:43:43AM -0700, Michael Turquette wrote:
> > > > Hi Maxime,
> > > > 
> > > > Quoting Maxime Ripard (2015-10-20 00:36:45)
> > > > > +struct clk *clk_register_multiplier(struct device *dev, const char 
> > > > > *name,
> > > > > +   const char *parent_name,
> > > > > +   unsigned long flags,
> > > > > +   void __iomem *reg, u8 shift, u8 
> > > > > width,
> > > > > +   u8 clk_mult_flags, spinlock_t 
> > > > > *lock)
> > > > > +{
> > > > 
> > > > Patch looks good in general. However this is a good opportunity to stop
> > > > the madness around the registration functions in these basic clock
> > > > types.
> > > > 
> > > > clk_register is really all that we need since we've had struct
> > > > clk_init_data for a while. Initializing a multiplier should be as simple
> > > > as:
> > > > 
> > > >   struct clk_multiplier clk_foo = {
> > > >   .hw.init = &(struct clk_init_data){
> > > >   .name = "foo",
> > > >   .parent_names = (const char *[]){
> > > >   "bar",
> > > >   },
> > > >   .num_parents = 1;
> > > >   .ops = _multiplier_ops,
> > > >   },
> > > >   .reg = 0xd34db33f,
> > > >   .shift = 1,
> > > >   .width = 2,
> > > >   };
> > > > 
> > > >   clk_register(dev, _foo.hw);
> > > > 
> > > > This is nice since it turns these basic clocks into even more of a
> > > > library and less of a poor mans driver.
> > > > 
> > > > (I really hope the above works. I did not test it)
> > > > 
> > > > Is it possible you can convert to using this method, and if it is
> > > > correct for you then just remove clk_multiplier_register altogether? (In
> > > > fact you might not use the registration function at all since you use
> > > > the composite clock...)
> > > 
> > > This chunk of code has been here since v2, which has been first posted
> > > in May, two and half kernel releases ago.
> > > 
> > > In the meantime, we had a full-blown DMA driver and a quite unusual
> > > ASoC driver merged. For some reason, this is the only piece of the
> > > audio support that is missing for us, while at the same time it's the
> > > most trivial.
> > > 
> > > If that's the only issue you have with this patch, I'm fine with
> > > sending a subsequent patch this week. But I'd be really unhappy with
> > > sending yet another version for a single change, while you had 5
> > > monthes to review it, and we discussed it several times on IRC and
> > > face to face.
> > 
> > The change can go in later. It's not a prerequisite. I had a feeling
> > you'd be grumpy about me asking but I thought I'd try anyways. I won't
> > even ask if you got sign-off from Jim on whether this works for his
> > platforms ;-)
> 
> I asked several times, he never replied... :/
> 
> > The copy/paste nature of these basic clock types really sucks and it is
> > one of many reasons that I am hesitant to accept them and slow to merge
> > them...
> 
> I guess we cover all cases now? So it shouldn't grow that much.
> 
> > Anyways it seems that you are not using the registration function at all
> > so I might just follow up with a patch to remove it.
> > 
> > I can pick these 5 patches directly, or do you plan to send a PR?
> 
> I have a pull request coming for you with a single patch, I can apply
> them on that branch and send you the PR later today if it's okay?

Sounds good to me.

Regards,
Mike

> 
> Thanks,
> Maxime
> 
> -- 
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

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Re: [linux-sunxi] [PATCH v2 1/1] dts: sun6i: yones toptech bs1078 v2: Add AXP221 support to dts

[Lawrence Yu]

On Mon, Oct 19, 2015 at 2:59 AM, Chen-Yu Tsai  wrote:
> On Mon, Oct 19, 2015 at 2:07 AM, Lawrence Yu  wrote:
>> Enable the axp221 PMIC chip in the dts file.
>>
>> Allows board to power off correctly from the poweroff command
>>
>> This board requires dc1sw to be enabled in order to provide a power source
>> for the 5V DCDC converter that powers USB2 and the LCD backlight
>>
>> This board uses dldo1 for 3.3V wifi power
>>
>> This board requires dldo3 to be enabled at 2.8V in order to provide voltage
>> to the pullup resistors for the i2c0 bus.
>>
>> ---
>>
>> Changes since v1
>>
>> - Use axp22x.dtsi to standardize the register names
>> - Change wifi power regulator to dldo1 instead of incorrect aldo1
>> - Remove unnecessary gpio pin PH27 for wifi power, since this board uses
>>   the axp221 chip to control power to the wifi chip.
>>
>> Signed-off-by: Lawrence Yu 
>> ---
>>  .../dts/sun6i-a31s-yones-toptech-bs1078-v2.dts | 98 
>> +++---
>>  1 file changed, 88 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts 
>> b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
>> index b199020..98d0a83 100644
>> --- a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
>> +++ b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
>> @@ -113,22 +113,100 @@
>> allwinner,pull = ;
>>  };
>>
>> -_usb1_vbus {
>> -   gpio = < 7 27 GPIO_ACTIVE_HIGH>;
>> + {
>> +   pinctrl-names = "default";
>> +   pinctrl-0 = <_pins_a>;
>> status = "okay";
>>  };
>>
>> -_vbus_pin_a {
>> -   allwinner,pins = "PH27";
>> + {
>> +   status = "okay";
>> +
>> +   axp22x: pmic@68 {
>> +   compatible = "x-powers,axp221";
>> +   reg = <0x68>;
>> +   interrupt-parent = <_intc>;
>> +   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
>> +   };
>>  };
>>
>> - {
>> -   usb1_vbus-supply = <_usb1_vbus>;
>> -   status = "okay";
>> +#include "axp22x.dtsi"
>> +
>> + {
>> +   regulators {
>> +   /* Used by LCD backlight and USB2 */
>> +   reg_dc1sw: dc1sw {
>> +   regulator-name = "dc1sw";
>> +   regulator-min-microvolt = <300>;
>> +   regulator-max-microvolt = <300>;
>> +   regulator-name = "vcc-dc1sw";
>
> I would use "vcc-lcd-usb2". Or just "vcc-lcd" if it proves it has nothing
> to do with USB. Plus there's 2 "regulator-name" entries here.
>

I will remove the extra regulator-name (not sure how I did not see
that) and use "vcc-lcd-usb2" as the regulator name.  I have an
explanation as to why I believe dc1sw also controls power to usb2
below.

>> +   };
>> +   };
>>  };
>>
>> - {
>> -   pinctrl-names = "default";
>> -   pinctrl-0 = <_pins_a>;
>> +_aldo3 {
>> +   regulator-always-on;
>> +   regulator-min-microvolt = <270>;
>> +   regulator-max-microvolt = <330>;
>> +   regulator-name = "avcc";
>> +};
>> +
>> +_dc5ldo {
>> +   regulator-min-microvolt = <70>;
>> +   regulator-max-microvolt = <132>;
>> +   regulator-name = "vdd-cpus";
>> +};
>> +
>> +_dcdc1 {
>> +   regulator-always-on;
>> +   regulator-min-microvolt = <300>;
>> +   regulator-max-microvolt = <300>;
>> +   regulator-name = "vcc-3v0";
>> +};
>> +
>> +_dcdc2 {
>> +   regulator-min-microvolt = <70>;
>> +   regulator-max-microvolt = <132>;
>> +   regulator-name = "vdd-gpu";
>> +};
>> +
>> +_dcdc3 {
>> +   regulator-always-on;
>> +   regulator-min-microvolt = <70>;
>> +   regulator-max-microvolt = <132>;
>> +   regulator-name = "vdd-cpu";
>> +};
>> +
>> +_dcdc4 {
>> +   regulator-always-on;
>> +   regulator-min-microvolt = <70>;
>> +   regulator-max-microvolt = <132>;
>> +   regulator-name = "vdd-sys-dll";
>> +};
>> +
>> +_dcdc5 {
>> +   regulator-always-on;
>> +   regulator-min-microvolt = <150>;
>> +   regulator-max-microvolt = <150>;
>> +   regulator-name = "vcc-dram";
>> +};
>> +
>> +_dldo1 {
>> +   regulator-min-microvolt = <330>;
>> +   regulator-max-microvolt = <330>;
>> +   regulator-name = "vcc-wifi";
>> +};
>> +
>> +/* Voltage source for I2C pullup resistors for I2C Bus 0 */
>> +_dldo3 {
>> +   regulator-always-on;
>> +   regulator-min-microvolt = <280>;
>> +   regulator-max-microvolt = <280>;
>> +   regulator-name = "vcc-csi";
>
> This should probably be named "vddio-csi".

I will change the name of the regulator to "vddio-csi".  I did not
realize that dldo3 was connected to the io vdd of the cameras until
you pointed it out, the A31 reference schematic also verifies this.

>
> I think Maxime and Hans were still debating whether the camera VDDIO
> regulator should be defined independently as "always-on", instead of
> having the 

[linux-sunxi] [PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets

[Jens Kuske]

Adding a new compatible allows us to define SoC specific behaviour
if necessary, for example forcing a particular device out of reset
even if no driver is actually using it.

Signed-off-by: Jens Kuske 
---
 Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt | 1 +
 drivers/reset/reset-sunxi.c | 1 +
 2 files changed, 2 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt 
b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt
index c8f7757..e11f023 100644
--- a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt
+++ b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt
@@ -8,6 +8,7 @@ Required properties:
 - compatible: Should be one of the following:
   "allwinner,sun6i-a31-ahb1-reset"
   "allwinner,sun6i-a31-clock-reset"
+  "allwinner,sun8i-h3-bus-reset"
 - reg: should be register base and length as documented in the
   datasheet
 - #reset-cells: 1, see below
diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c
index 3d95c87..6f12b5c 100644
--- a/drivers/reset/reset-sunxi.c
+++ b/drivers/reset/reset-sunxi.c
@@ -124,6 +124,7 @@ err_alloc:
  */
 static const struct of_device_id sunxi_early_reset_dt_ids[] __initdata = {
{ .compatible = "allwinner,sun6i-a31-ahb1-reset", },
+   { .compatible = "allwinner,sun8i-h3-bus-reset", },
{ /* sentinel */ },
 };
 
-- 
2.6.1

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[linux-sunxi] [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

[Jens Kuske]

The Allwinner H3 is a home entertainment system oriented SoC with
four Cortex-A7 cores and a Mali-400MP2 GPU.

Signed-off-by: Jens Kuske 
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 499 
 1 file changed, 499 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
new file mode 100644
index 000..4114e17
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -0,0 +1,499 @@
+/*
+ * Copyright (C) 2015 Jens Kuske 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+
+#include 
+#include 
+
+/ {
+   interrupt-parent = <>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0>;
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <1>;
+   };
+
+   cpu@2 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <2>;
+   };
+
+   cpu@3 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <3>;
+   };
+   };
+
+   timer {
+   compatible = "arm,armv7-timer";
+   interrupts = ,
+,
+,
+;
+   clock-frequency = <2400>;
+   arm,cpu-registers-not-fw-configured;
+   };
+
+   memory {
+   reg = <0x4000 0x8000>;
+   };
+
+   clocks {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   osc24M: osc24M_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   clock-output-names = "osc24M";
+   };
+
+   osc32k: osc32k_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   clock-output-names = "osc32k";
+   };
+
+   pll1: clk@01c2 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun8i-a23-pll1-clk";
+   reg = <0x01c2 0x4>;
+   clocks = <>;
+   clock-output-names = "pll1";
+   };
+
+   /* dummy clock until actually implemented */
+   pll5: pll5_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+  

[linux-sunxi] [PATCH 2/6] clk: sunxi: Add H3 clocks support

[Jens Kuske]

The H3 clock control unit is similar to the those of other sun8i family
members like the A23.

It adds a new bus gates clock similar to the simple gates, but with a
different parent clock for each single gate.
Some of the gates use the new AHB2 clock as parent, whose clock source
is muxable between AHB1 and PLL6/2. The documentation isn't totally clear
about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it
is mostly based on Allwinner kernel source code.

Signed-off-by: Jens Kuske 
---
 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +
 drivers/clk/sunxi/Makefile|   1 +
 drivers/clk/sunxi/clk-bus-gates.c | 105 ++
 drivers/clk/sunxi/clk-sunxi.c |  12 ++-
 4 files changed, 117 insertions(+), 3 deletions(-)
 create mode 100644 drivers/clk/sunxi/clk-bus-gates.c

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 8a47b77..d303dec 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -28,6 +28,7 @@ Required properties:
"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
+   "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
@@ -55,6 +56,7 @@ Required properties:
"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
+   "allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index f5a35b8..ecaff7f 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -5,6 +5,7 @@
 obj-y += clk-sunxi.o clk-factors.o
 obj-y += clk-a10-hosc.o
 obj-y += clk-a20-gmac.o
+obj-y += clk-bus-gates.o
 obj-y += clk-mod0.o
 obj-y += clk-simple-gates.o
 obj-y += clk-sun8i-mbus.o
diff --git a/drivers/clk/sunxi/clk-bus-gates.c 
b/drivers/clk/sunxi/clk-bus-gates.c
new file mode 100644
index 000..5bba0b9
--- /dev/null
+++ b/drivers/clk/sunxi/clk-bus-gates.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2015 Jens Kuske 
+ *
+ * Based on clk-simple-gates.c, which is:
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static DEFINE_SPINLOCK(gates_lock);
+
+static void __init sunxi_bus_gates_setup(struct device_node *node,
+const int protected[],
+int nprotected)
+{
+   struct clk_onecell_data *clk_data;
+   const char *clk_parent, *clk_name;
+   struct property *prop;
+   struct resource res;
+   void __iomem *clk_reg;
+   void __iomem *reg;
+   const __be32 *p;
+   int number, i = 0, j;
+   u8 clk_bit;
+   u32 index;
+
+   reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+   if (IS_ERR(reg))
+   return;
+
+   clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
+   if (!clk_data)
+   goto err_unmap;
+
+   number = of_property_count_u32_elems(node, "clock-indices");
+   of_property_read_u32_index(node, "clock-indices", number - 1, );
+
+   clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
+   if (!clk_data->clks)
+   goto err_free_data;
+
+   of_property_for_each_u32(node, "clock-indices", prop, p, index) {
+   of_property_read_string_index(node, "clock-output-names",
+ i, _name);
+
+   clk_parent = of_clk_get_parent_name(node, i);
+
+   clk_reg = reg + 4 * (index / 32);
+   clk_bit = index % 32;
+
+ 

[linux-sunxi] [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support

[Jens Kuske]

Hi everyone,

This is v3 of my patch series introducing basic kernel support for Allwinner's
H3 SoC. It mainly adds basic clocks and pinctrl. It also adds interrupts,
timers, watchdog, RTC, dmaengine, MMC and UARTs, which are mostly compatible
to those in earlier SoCs like A23 and A31, and can simply be reused.

These patches are based on Maxime's sunxi/for-next branch from
git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux.git


Patch 1 improves the sunxi divs clock to read the name of the base factor clock
from devicetree instead of hardcoding it, which allows us to reuse sun6i-pll6
for our pll8.

Patch 2 adds support for the basic clocks.

Patch 3 adds the pin sets for the H3 main PIO.

Patch 4 adds a new compatible for the H3 reset controller

Patch 5 adds the DTSI for the H3.

Patch 6 adds a DTS for the Orange Pi Plus SBC, which these patches
were developed and tested with.


Changes since v2:
- add mbus clock
- add Maxime's suggestion to take the substring up to the first "_" as name
  for the divs base clock
- use A31 pll6 for H3 pll6
- use a clock similar to the new simple gates for H3 bus gates
- drop the pinctrl-as-module patch since pinctrl and gpio don't seem to be
  ready for removable drivers
- documentation and machine support are merged already
  
Changes since v1:
- Update sunxi README in Documentation
- Add the multiple parents gates and use them for bus-gates instead of
  ahb1, ahb2, apb1 and apb2 gates
- Merge the pll8 clock with sun6i pll6
- Merge the ahb12, apb1 and apb2 resets to bus-resets with own compatible
- Add sun6i_timer_init to sun8i machine
- Remove the single SoC names from machine definition, its sun8i family
- Make the pinctrl driver tristate and put its Kconfig entry in the right order
- Rename pinctrl "scr" to "sim" and clock "sim" to "scr" to match user manual
- Remove the address paragraph from GPL in dts and dtsi
- Some style cleanup and line wrapping in dtsi
- Add ARM architected timers
- dmaengine isn't included anymore, it is merged already

Best Regards,
Jens


Jens Kuske (6):
  clk: sunxi: Let divs clocks read the base factor clock name from
devicetree
  clk: sunxi: Add H3 clocks support
  pinctrl: sunxi: Add H3 PIO controller support
  reset: sunxi: Add compatible for Allwinner H3 bus resets
  ARM: dts: sunxi: Add Allwinner H3 DTSI
  ARM: dts: sun8i: Add Orange Pi Plus support

 Documentation/devicetree/bindings/clock/sunxi.txt  |   2 +
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 .../bindings/reset/allwinner,sunxi-clock-reset.txt |   1 +
 arch/arm/boot/dts/Makefile |   3 +-
 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts   |  77 +++
 arch/arm/boot/dts/sun8i-h3.dtsi| 499 
 drivers/clk/sunxi/Makefile |   1 +
 drivers/clk/sunxi/clk-bus-gates.c  | 105 +
 drivers/clk/sunxi/clk-sunxi.c  |  47 +-
 drivers/pinctrl/sunxi/Kconfig  |   4 +
 drivers/pinctrl/sunxi/Makefile |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c   | 516 +
 drivers/reset/reset-sunxi.c|   1 +
 13 files changed, 1245 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
 create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi
 create mode 100644 drivers/clk/sunxi/clk-bus-gates.c
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c

-- 
2.6.1

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[linux-sunxi] [PATCH 6/6] ARM: dts: sun8i: Add Orange Pi Plus support

[Jens Kuske]

The Orange Pi Plus is a SBC based on the Allwinner H3 SoC
with 8GB eMMC, multiple USB ports through a USB hub chip, SATA through
a USB-SATA bridge, one uSD slot, a 10/100/1000M ethernet port,
WiFi, HDMI, headphone jack, IR receiver, a microphone, a CSI connector
and a 40-pin GPIO header.

Signed-off-by: Jens Kuske 
---
 arch/arm/boot/dts/Makefile   |  3 +-
 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 77 
 2 files changed, 79 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 35a3cf4..bedf51b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -643,7 +643,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-ippo-q8h-v1.2.dtb \
sun8i-a33-q8-tablet.dtb \
-   sun8i-a33-sinlinx-sina33.dtb
+   sun8i-a33-sinlinx-sina33.dtb \
+   sun8i-h3-orangepi-plus.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts 
b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
new file mode 100644
index 000..e67df59
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2015 Jens Kuske 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include 
+#include 
+
+/ {
+   model = "Xunlong Orange Pi Plus";
+   compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>, <_cd_pin>;
+   vmmc-supply = <_vcc3v3>;
+   bus-width = <4>;
+   cd-gpios = < 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+   cd-inverted;
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   status = "okay";
+};
-- 
2.6.1

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[linux-sunxi] [PATCH 3/6] pinctrl: sunxi: Add H3 PIO controller support

[Jens Kuske]

The H3 uses the same pin controller as previous SoC's from Allwinner.
Add support for the pins controlled by the main PIO controller.

Signed-off-by: Jens Kuske 
---
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 drivers/pinctrl/sunxi/Kconfig  |   4 +
 drivers/pinctrl/sunxi/Makefile |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c   | 516 +
 4 files changed, 522 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c

diff --git 
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 3c821cd..094451c 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -17,6 +17,7 @@ Required properties:
   "allwinner,sun8i-a23-pinctrl"
   "allwinner,sun8i-a23-r-pinctrl"
   "allwinner,sun8i-a33-pinctrl"
+  "allwinner,sun8i-h3-pinctrl"
 
 - reg: Should contain the register physical address and length for the
   pin controller.
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index ae27872..f161e4c 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -47,6 +47,10 @@ config PINCTRL_SUN8I_A23_R
depends on RESET_CONTROLLER
select PINCTRL_SUNXI_COMMON
 
+config PINCTRL_SUN8I_H3
+   def_bool MACH_SUN8I
+   select PINCTRL_SUNXI_COMMON
+
 config PINCTRL_SUN9I_A80
def_bool MACH_SUN9I
select PINCTRL_SUNXI_COMMON
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 227a121..ca19592 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -12,4 +12,5 @@ obj-$(CONFIG_PINCTRL_SUN7I_A20)   += 
pinctrl-sun7i-a20.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23)+= pinctrl-sun8i-a23.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23_R)  += pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
+obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80)+= pinctrl-sun9i-a80.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c 
b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
new file mode 100644
index 000..98d465d
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
@@ -0,0 +1,516 @@
+/*
+ * Allwinner H3 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2015 Jens Kuske 
+ *
+ * Based on pinctrl-sun8i-a23.c, which is:
+ * Copyright (C) 2014 Chen-Yu Tsai 
+ * Copyright (C) 2014 Maxime Ripard 
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun8i_h3_pins[] = {
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* TX */
+ SUNXI_FUNCTION(0x3, "jtag"),  /* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PA_EINT0 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RX */
+ SUNXI_FUNCTION(0x3, "jtag"),  /* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PA_EINT1 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
+ SUNXI_FUNCTION(0x3, "jtag"),  /* DO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PA_EINT2 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
+ SUNXI_FUNCTION(0x3, "jtag"),  /* DI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PA_EINT3 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart0"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PA_EINT4 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart0"), /* RX */
+ SUNXI_FUNCTION(0x3, "pwm0"),
+

Re: [linux-sunxi] [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support

[Code Kipper]

On 21 October 2015 at 18:13, Jens Kuske  wrote:
> Hi everyone,
>
> This is v3 of my patch series introducing basic kernel support for Allwinner's
> H3 SoC. It mainly adds basic clocks and pinctrl. It also adds interrupts,
> timers, watchdog, RTC, dmaengine, MMC and UARTs, which are mostly compatible
> to those in earlier SoCs like A23 and A31, and can simply be reused.
>
> These patches are based on Maxime's sunxi/for-next branch from
> git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux.git

Thanks for the update...just seconds ago managed to get some chatter
after the "Starting Kernel" prompt on my Orange Pi 2 using the patch
from http://moinejf.free.fr/opi2/ but I will switch over to these new
ones to verify. I'm also using your u-boot so there has been some
progress in the Kipper household this evening.

Thanks again,
CK

>
>
> Patch 1 improves the sunxi divs clock to read the name of the base factor 
> clock
> from devicetree instead of hardcoding it, which allows us to reuse sun6i-pll6
> for our pll8.
>
> Patch 2 adds support for the basic clocks.
>
> Patch 3 adds the pin sets for the H3 main PIO.
>
> Patch 4 adds a new compatible for the H3 reset controller
>
> Patch 5 adds the DTSI for the H3.
>
> Patch 6 adds a DTS for the Orange Pi Plus SBC, which these patches
> were developed and tested with.
>
>
> Changes since v2:
> - add mbus clock
> - add Maxime's suggestion to take the substring up to the first "_" as name
>   for the divs base clock
> - use A31 pll6 for H3 pll6
> - use a clock similar to the new simple gates for H3 bus gates
> - drop the pinctrl-as-module patch since pinctrl and gpio don't seem to be
>   ready for removable drivers
> - documentation and machine support are merged already
>
> Changes since v1:
> - Update sunxi README in Documentation
> - Add the multiple parents gates and use them for bus-gates instead of
>   ahb1, ahb2, apb1 and apb2 gates
> - Merge the pll8 clock with sun6i pll6
> - Merge the ahb12, apb1 and apb2 resets to bus-resets with own compatible
> - Add sun6i_timer_init to sun8i machine
> - Remove the single SoC names from machine definition, its sun8i family
> - Make the pinctrl driver tristate and put its Kconfig entry in the right 
> order
> - Rename pinctrl "scr" to "sim" and clock "sim" to "scr" to match user manual
> - Remove the address paragraph from GPL in dts and dtsi
> - Some style cleanup and line wrapping in dtsi
> - Add ARM architected timers
> - dmaengine isn't included anymore, it is merged already
>
> Best Regards,
> Jens
>
>
> Jens Kuske (6):
>   clk: sunxi: Let divs clocks read the base factor clock name from
> devicetree
>   clk: sunxi: Add H3 clocks support
>   pinctrl: sunxi: Add H3 PIO controller support
>   reset: sunxi: Add compatible for Allwinner H3 bus resets
>   ARM: dts: sunxi: Add Allwinner H3 DTSI
>   ARM: dts: sun8i: Add Orange Pi Plus support
>
>  Documentation/devicetree/bindings/clock/sunxi.txt  |   2 +
>  .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
>  .../bindings/reset/allwinner,sunxi-clock-reset.txt |   1 +
>  arch/arm/boot/dts/Makefile |   3 +-
>  arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts   |  77 +++
>  arch/arm/boot/dts/sun8i-h3.dtsi| 499 
>  drivers/clk/sunxi/Makefile |   1 +
>  drivers/clk/sunxi/clk-bus-gates.c  | 105 +
>  drivers/clk/sunxi/clk-sunxi.c  |  47 +-
>  drivers/pinctrl/sunxi/Kconfig  |   4 +
>  drivers/pinctrl/sunxi/Makefile |   1 +
>  drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c   | 516 
> +
>  drivers/reset/reset-sunxi.c|   1 +
>  13 files changed, 1245 insertions(+), 13 deletions(-)
>  create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
>  create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi
>  create mode 100644 drivers/clk/sunxi/clk-bus-gates.c
>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
>
> --
> 2.6.1
>
> --
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Re: [linux-sunxi] [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support

[Code Kipper]

On 21 October 2015 at 19:11, Code Kipper  wrote:
> On 21 October 2015 at 18:13, Jens Kuske  wrote:
>> Hi everyone,
>>
>> This is v3 of my patch series introducing basic kernel support for 
>> Allwinner's
>> H3 SoC. It mainly adds basic clocks and pinctrl. It also adds interrupts,
>> timers, watchdog, RTC, dmaengine, MMC and UARTs, which are mostly compatible
>> to those in earlier SoCs like A23 and A31, and can simply be reused.
>>
>> These patches are based on Maxime's sunxi/for-next branch from
>> git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux.git
>
> Thanks for the update...just seconds ago managed to get some chatter
> after the "Starting Kernel" prompt on my Orange Pi 2 using the patch
> from http://moinejf.free.fr/opi2/ but I will switch over to these new
> ones to verify. I'm also using your u-boot so there has been some
> progress in the Kipper household this evening.
>
> Thanks again,
> CK
Cooolit's booting...now to find me a rootfs!
CK
>
>>
>>
>> Patch 1 improves the sunxi divs clock to read the name of the base factor 
>> clock
>> from devicetree instead of hardcoding it, which allows us to reuse sun6i-pll6
>> for our pll8.
>>
>> Patch 2 adds support for the basic clocks.
>>
>> Patch 3 adds the pin sets for the H3 main PIO.
>>
>> Patch 4 adds a new compatible for the H3 reset controller
>>
>> Patch 5 adds the DTSI for the H3.
>>
>> Patch 6 adds a DTS for the Orange Pi Plus SBC, which these patches
>> were developed and tested with.
>>
>>
>> Changes since v2:
>> - add mbus clock
>> - add Maxime's suggestion to take the substring up to the first "_" as name
>>   for the divs base clock
>> - use A31 pll6 for H3 pll6
>> - use a clock similar to the new simple gates for H3 bus gates
>> - drop the pinctrl-as-module patch since pinctrl and gpio don't seem to be
>>   ready for removable drivers
>> - documentation and machine support are merged already
>>
>> Changes since v1:
>> - Update sunxi README in Documentation
>> - Add the multiple parents gates and use them for bus-gates instead of
>>   ahb1, ahb2, apb1 and apb2 gates
>> - Merge the pll8 clock with sun6i pll6
>> - Merge the ahb12, apb1 and apb2 resets to bus-resets with own compatible
>> - Add sun6i_timer_init to sun8i machine
>> - Remove the single SoC names from machine definition, its sun8i family
>> - Make the pinctrl driver tristate and put its Kconfig entry in the right 
>> order
>> - Rename pinctrl "scr" to "sim" and clock "sim" to "scr" to match user manual
>> - Remove the address paragraph from GPL in dts and dtsi
>> - Some style cleanup and line wrapping in dtsi
>> - Add ARM architected timers
>> - dmaengine isn't included anymore, it is merged already
>>
>> Best Regards,
>> Jens
>>
>>
>> Jens Kuske (6):
>>   clk: sunxi: Let divs clocks read the base factor clock name from
>> devicetree
>>   clk: sunxi: Add H3 clocks support
>>   pinctrl: sunxi: Add H3 PIO controller support
>>   reset: sunxi: Add compatible for Allwinner H3 bus resets
>>   ARM: dts: sunxi: Add Allwinner H3 DTSI
>>   ARM: dts: sun8i: Add Orange Pi Plus support
>>
>>  Documentation/devicetree/bindings/clock/sunxi.txt  |   2 +
>>  .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
>>  .../bindings/reset/allwinner,sunxi-clock-reset.txt |   1 +
>>  arch/arm/boot/dts/Makefile |   3 +-
>>  arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts   |  77 +++
>>  arch/arm/boot/dts/sun8i-h3.dtsi| 499 
>> 
>>  drivers/clk/sunxi/Makefile |   1 +
>>  drivers/clk/sunxi/clk-bus-gates.c  | 105 +
>>  drivers/clk/sunxi/clk-sunxi.c  |  47 +-
>>  drivers/pinctrl/sunxi/Kconfig  |   4 +
>>  drivers/pinctrl/sunxi/Makefile |   1 +
>>  drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c   | 516 
>> +
>>  drivers/reset/reset-sunxi.c|   1 +
>>  13 files changed, 1245 insertions(+), 13 deletions(-)
>>  create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
>>  create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi
>>  create mode 100644 drivers/clk/sunxi/clk-bus-gates.c
>>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
>>
>> --
>> 2.6.1
>>
>> --
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[linux-sunxi] Re: [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support

[Hans de Goede]

Hi,

On 21-10-15 18:13, Jens Kuske wrote:

Hi everyone,

This is v3 of my patch series introducing basic kernel support for Allwinner's
H3 SoC. It mainly adds basic clocks and pinctrl. It also adds interrupts,
timers, watchdog, RTC, dmaengine, MMC and UARTs, which are mostly compatible
to those in earlier SoCs like A23 and A31, and can simply be reused.

These patches are based on Maxime's sunxi/for-next branch from
git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux.git


p.s.

For the next version you will want to base these on the sunxi-next branch of:

https://github.com/linux-sunxi/linux-sunxi.git

There is at least a conflict with the pio driver due to the addition of
the a83 pio driver which mripard/linux/sunxi/for-next does not have, where
as linux-sunxi/sunxi-next does have that merged in.

Regards,

Hans

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[linux-sunxi] [PATCH] a31s: Add board for Yones TopTech BS1078 v2

[Lawrence Yu]

This is the fex file for the Yones TopTech BS1078 v2 board.

A31s SOC, 1024x600 LCD, 1GB RAM, 8GB NAND, rtl8723as wifi

Device Page: http://linux-sunxi.org/Yones_Toptech_BS1078_V2
---
 sys_config/a31s/yonestoptech_bs1078_v2.fex | 1065 
 1 file changed, 1065 insertions(+)
 create mode 100644 sys_config/a31s/yonestoptech_bs1078_v2.fex

diff --git a/sys_config/a31s/yonestoptech_bs1078_v2.fex 
b/sys_config/a31s/yonestoptech_bs1078_v2.fex
new file mode 100644
index 000..27e703d
--- /dev/null
+++ b/sys_config/a31s/yonestoptech_bs1078_v2.fex
@@ -0,0 +1,1065 @@
+[product]
+version = "100"
+machine = "bs1078"
+
+[platform]
+eraseflag = 1
+
+[target]
+boot_clock = 1008
+storage_type = -1
+
+[power_sply]
+dcdc1_vol = 3000
+dcdc2_vol = 1200
+dcdc3_vol = 1260
+dcdc4_vol = 1240
+dcdc5_vol = 1500
+aldo2_vol = 1800
+aldo3_vol = 3000
+eldo3_vol = 1200
+
+[card_boot]
+logical_start = 40960
+sprite_gpio0 =
+
+[pm_para]
+standby_mode = 1
+
+[card0_boot_para]
+card_ctrl = 0
+card_high_speed = 1
+card_line = 4
+sdc_d1 = port:PF00<2><1>
+sdc_d0 = port:PF01<2><1>
+sdc_clk = port:PF02<2><1>
+sdc_cmd = port:PF03<2><1>
+sdc_d3 = port:PF04<2><1>
+sdc_d2 = port:PF05<2><1>
+
+[card2_boot_para]
+card_ctrl = 2
+card_high_speed = 1
+card_line = 4
+sdc_cmd = port:PC06<3><1>
+sdc_clk = port:PC07<3><1>
+sdc_d0 = port:PC08<3><1>
+sdc_d1 = port:PC09<3><1>
+sdc_d2 = port:PC10<3><1>
+sdc_d3 = port:PC11<3><1>
+
+[twi_para]
+twi_port = 0
+twi_scl = port:PH14<2>
+twi_sda = port:PH15<2>
+
+[uart_para]
+uart_debug_port = 0
+uart_debug_tx = port:PH20<2><1>
+uart_debug_rx = port:PH21<2><1>
+
+[jtag_para]
+jtag_enable = 1
+jtag_ms = port:PH09<3>
+jtag_ck = port:PH10<3>
+jtag_do = port:PH11<3>
+jtag_di = port:PH12<3>
+
+[clock]
+pll3 = 297
+pll4 = 300
+pll6 = 600
+pll7 = 297
+pll8 = 360
+pll9 = 297
+pll10 = 702
+
+[dram_para]
+dram_clk = 420
+dram_type = 3
+dram_zq = 0xfb
+dram_odt_en = 0
+dram_para1 = 284427264
+dram_para2 = 4353
+dram_mr0 = 6736
+dram_mr1 = 4
+dram_mr2 = 24
+dram_mr3 = 0
+dram_tpr0 = 0x0
+dram_tpr1 = 0x8800
+dram_tpr2 = 0x39a70140
+dram_tpr3 = 0xa092e74c
+dram_tpr4 = 0x2948c209
+dram_tpr5 = 0x8944422c
+dram_tpr6 = 0x30028480
+dram_tpr7 = 0x2a3297
+dram_tpr8 = 0x5034fa8
+dram_tpr9 = 0x36353d8
+dram_tpr10 = 0x0
+dram_tpr11 = 0x0
+dram_tpr12 = 0x0
+dram_tpr13 = 0x1
+
+[pm_para]
+standby_mode = 1
+
+[wakeup_src_para]
+cpu_en = 0
+cpu_freq = 48
+pll_ratio = 273
+dram_selfresh_en = 1
+dram_freq = 36
+wakeup_src0 = port:PL05<2><1>
+
+[gmac_para]
+gmac_used = 0
+gmac_txd0 = port:PA00<2>
+gmac_txd1 = port:PA01<2>
+gmac_txd2 = port:PA02<2>
+gmac_txd3 = port:PA03<2>
+gmac_txd4 = port:PA04<2>
+gmac_txd5 = port:PA05<2>
+gmac_txd6 = port:PA06<2>
+gmac_txd7 = port:PA07<2>
+gmac_txclk = port:PA08<2>
+gmac_txen = port:PA09<2>
+gmac_gtxclk = port:PA10<2>
+gmac_rxd0 = port:PA11<2>
+gmac_rxd1 = port:PA12<2>
+gmac_rxd2 = port:PA13<2>
+gmac_rxd3 = port:PA14<2>
+gmac_rxd4 = port:PA15<2>
+gmac_rxd5 = port:PA16<2>
+gmac_rxd6 = port:PA17<2>
+gmac_rxd7 = port:PA18<2>
+gmac_rxdv = port:PA19<2>
+gmac_rxclk = port:PA20<2>
+gmac_txerr = port:PA21<2>
+gmac_rxerr = port:PA22<2>
+gmac_col = port:PA23<2>
+gmac_crs = port:PA24<2>
+gmac_clkin = port:PA25<2>
+gmac_mdc = port:PA26<2>
+gmac_mdio = port:PA27<2>
+
+[twi0_para]
+twi_used = 1
+twi_scl = port:PH14<2>
+twi_sda = port:PH15<2>
+
+[twi1_para]
+twi_used = 1
+twi_scl = port:PH16<2>
+twi_sda = port:PH17<2>
+
+[twi2_para]
+twi_used = 1
+twi_scl = port:PH18<2>
+twi_sda = port:PH19<2>
+
+[twi3_para]
+twi_used = 1
+twi_scl = port:PG10<2>
+twi_sda = port:PG11<2>
+
+[uart_para0]
+uart_used = 1
+uart_port = 0
+uart_type = 2
+uart_tx = port:PH20<2><1>
+uart_rx = port:PH21<2><1>
+
+[uart_para1]
+uart_used = 0
+uart_port = 1
+uart_type = 4
+uart_tx = port:PA04<4><1>
+uart_rx = port:PA05<4><1>
+uart_rts = port:PA06<4><1>
+uart_cts = port:PA07<4><1>
+
+[uart_para2]
+uart_used = 0
+uart_port = 2
+uart_type = 4
+uart_tx = port:PG06<2><1>
+uart_rx = port:PG07<2><1>
+uart_rts = port:PG08<2><1>
+uart_cts = port:PG09<2><1>
+
+[uart_para3]
+uart_used = 0
+uart_port = 3
+uart_type = 4
+uart_tx = port:PB05<3><1>
+uart_rx = port:PB06<3><1>
+uart_rts = port:PB04<3><1>
+uart_cts = port:PB00<3><1>
+
+[uart_para4]
+uart_used = 0
+uart_port = 4
+uart_type = 2
+uart_tx = port:PG17<2><1>
+uart_rx = port:PG18<2><1>
+uart_rts = port:PB04<3><1>
+uart_cts = port:PB00<3><1>
+
+[uart_para5]
+uart_used = 0
+uart_port = 5
+uart_type = 4
+uart_tx = port:PE04<3><1>
+uart_rx = port:PE05<3><1>
+uart_rts = port:PE06<3><1>
+uart_cts = port:PE07<3><1>
+
+[spi0_para]
+spi_used = 0
+spi_cs_bitmap = 1
+spi_cs0 = port:PC27<3><1>
+spi_sclk = port:PC02<3>
+spi_mosi = port:PC00<3>
+spi_miso = port:PC01<3>
+
+[spi1_para]
+spi_used = 0
+spi_cs_bitmap = 1
+spi_cs1 = port:PG12<2><1>
+spi_cs0 = port:PG13<2><1>
+spi_sclk = port:PG14<2>
+spi_mosi = port:PG15<2>
+spi_miso = port:PG16<2>
+
+[spi2_para]
+spi_used = 0
+spi_cs_bitmap = 1
+spi_cs0 = port:PH09<2>
+spi_sclk = port:PH10<2>
+spi_mosi = port:PH11<2>
+spi_miso = port:PH12<2>
+

Re: [linux-sunxi] [PATCH 2/6] clk: sunxi: Add H3 clocks support

[Julian Calaby]

Hi Jens,

On Thu, Oct 22, 2015 at 3:13 AM, Jens Kuske  wrote:
> The H3 clock control unit is similar to the those of other sun8i family
> members like the A23.
>
> It adds a new bus gates clock similar to the simple gates, but with a
> different parent clock for each single gate.
> Some of the gates use the new AHB2 clock as parent, whose clock source
> is muxable between AHB1 and PLL6/2. The documentation isn't totally clear
> about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it
> is mostly based on Allwinner kernel source code.
>
> Signed-off-by: Jens Kuske 
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |   2 +
>  drivers/clk/sunxi/Makefile|   1 +
>  drivers/clk/sunxi/clk-bus-gates.c | 105 
> ++
>  drivers/clk/sunxi/clk-sunxi.c |  12 ++-
>  4 files changed, 117 insertions(+), 3 deletions(-)
>  create mode 100644 drivers/clk/sunxi/clk-bus-gates.c
>
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 7c4aee0..6293c65 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c

This hunk should be in patch 1:

> @@ -1000,9 +1005,8 @@ static void __init sunxi_divs_clk_setup(struct 
> device_node *node,
>
> for (i = 0; i < SUNXI_DIVS_BASE_NAME_MAX_LEN - 1 &&
> clk_name[i] != '_' &&
> -   clk_name[i] != '\0'; i++) {
> +   clk_name[i] != '\0'; i++)
> base_name[i] = clk_name[i];
> -   }
>
> base_name[i] = '\0';
> factors.name = base_name;

Thanks,

-- 
Julian Calaby

Email: julian.cal...@gmail.com
Profile: http://www.google.com/profiles/julian.calaby/

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[linux-sunxi] Re: [PATCH resend] net: sun4i-emac: Properly free resources on probe failure and remove

[David Miller]

From: Hans de Goede 
Date: Tue, 20 Oct 2015 10:42:24 +0200

> Fix sun4i-emac not releasing the following resources:
> -iomapped memory not released on probe-failure nor on remove
> -clock not getting disabled on probe-failure nor on remove
> -sram not being released on remove
> 
> And while at it also add error checking to the clk_prepare_enable call
> done on probe.
> 
> Signed-off-by: Hans de Goede 

Applied.

[linux-sunxi] [PATCH] bus: sunxi-rsb: Allow building sunxi-rsb as a module

[Chen-Yu Tsai]

Allwinner Reduced Serial Bus support is only needed for sun[89]i
platforms. Having it built-in for multi-platform kernels leads to
a bigger kernel image, without any benefit for non sun[89]i systems.

The driver already exports the needed symbols and supports module
loading/unloading. Change the Kconfig symbol to tristate to allow
the user to build it as a module.

Signed-off-by: Chen-Yu Tsai 
---

Hi Arnd,

Maxime requested we make the RSB driver and subsequent PMIC drivers
tristate. Please squash this patch into patch 2 of the RSB series
when you apply them.


Thanks
ChenYu

---
 drivers/bus/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index e921b8c72f8c..78382de19ed9 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -122,7 +122,7 @@ config SIMPLE_PM_BUS
  "External Bus Interface") as found on several Renesas ARM SoCs.
 
 config SUNXI_RSB
-   bool "Allwinner sunXi Reduced Serial Bus Driver"
+   tristate "Allwinner sunXi Reduced Serial Bus Driver"
  default MACH_SUN8I || MACH_SUN9I
  depends on ARCH_SUNXI
  select REGMAP
-- 
2.6.1

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[linux-sunxi] Re: Kernel 3.4.103 serial8250: too much work for irq34

[Petar Dimitrijevic]

On Tuesday, October 20, 2015 at 10:59:37 AM UTC+2, Petar Dimitrijevic wrote:
>
> Hi all, 
>
> I'm in need of help and advice. 
>
> I'm working on a project for reading MBus data (hardware attached on 
> /dev/ttyS7) and sending it over modem attached to /dev/ttyS1. 
> Data is read from python script while the modem is controlled with wvdial 
> running in the background. 
> Board used for is olimex A20-SOM with EVB. 
> Due to concerns with quality of SD cards the entire system runs from NAND. 
> Due to this the kernel used is legacy 3.4. 
> The kernel is sunxi-3.4 (linux 3.4.103) and the OS is Ubuntu 14.04.2. 
> The system is read only and has been running for few weeks now. 
>
> While the system is in working condition everything is fine. 
> However sometimes when it loses power and reboots the message that starts 
> repeating continuously is: 
>
> [  127.382023] serial8250: too much work for irq34 
>
> After some time: 
>
> [  137.387765] sunxi:nand: Dma operation finish timeout 
>
> is displayed. 
>
> And then after some time: 
>
> [LOGICCTL_ERR] Get page data failed when read logical page! Err:0xfff2 
>  PHY_PageRead : read timeout 
>
> After these messages regarding NAND none further are displayed. Only 
> continuous output of too much work for irq 34 continues. 
> This also happens for irq 52 as well. These are irqs for /dev/ttyS1 and 
> /dev/ttyS7 respectively. 
>
> I've tried searching for similar problems but nothing comes up. 
>
> Has maybe anyone had any experience with something like this ? 
>
> I would appreciate any pointers in which direction to look. 
>
> I'm aware that probably best solution is to port everything to mainline 
> kernel but I've been having trouble making the device boot from NAND. 
>
> Thank you, 
> Petar


To answer my own issue.

The problem is not related to NAND. It is strictly related to DesignWare 
UART IP that is used in A20. 
It is also used in A10, A13. I'm not sure for other Allwinner SOCs.

This is a well known issue with DesignWare and the specific revision of 
their IP. If the device is configured
with UART_16550_COMPATIBLE=NO or in versions prior to the introduction of 
this option, the UART will ignore writes
to the LCR if the UART is busy.
Basically this means that communication parameters baud rate, stop bits, 
etc., can't be set when the device
is receiving something.

The current driver in the sunxi-3.4 tree doesn't solve this issue and it 
can lock the kernel rendering the system unusable.
I won't go into technical details but if someone is interested I can 
elaborate in more detail.
General description can be found here: 
http://permalink.gmane.org/gmane.linux.serial/12672.

Long story short I ended up back porting some parts of 8250_dw driver from 
the mainline kernel. 
With this solution IRQ overflow occurs very rarely because the triage code 
is moved away 
from the IRQ handler. From my tests this happened in 1 of 60 reboots. 
Previously it was 4 from 10 reboots.
This can however be handled with watchdog on application level.

As things are at this moment this issue can't be completely resolved 
because it's a HW problem 
and can lead to problems when there is a device attached to the serial port 
which non-stop sends data. 
More info: https://lkml.org/lkml/2015/3/6/941.

I will perform more tests to ensure that this is working as advertised. 
Don't know if they are accepted any more, but if everything is fine I will 
release patches for 3.4 kernel.

Best,
Petar

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