Re: [linux-sunxi] Re: [PATCH v3 1/2] phy-sun4i-usb: Use of_match_node to get model specific config data
On Thu, Nov 26, 2015 at 12:22:59PM +0800, Chen-Yu Tsai wrote:
> On Thu, Nov 26, 2015 at 12:50 AM, Hans de Goede wrote:
> > +
> > static const unsigned int sun4i_usb_phy0_cable[] = {
> > EXTCON_USB,
> > EXTCON_USB_HOST,
> > @@ -511,10 +578,16 @@ static int sun4i_usb_phy_probe(struct platform_device
> > *pdev)
> > struct device *dev = &pdev->dev;
> > struct device_node *np = dev->of_node;
> > struct phy_provider *phy_provider;
> > - bool dedicated_clocks;
> > + const struct of_device_id *match;
> > struct resource *res;
> > int i, ret;
> >
> > + match = of_match_node(sun4i_usb_phy_of_match, dev->of_node);
>
> You can use of_device_get_match_data() for slightly less code. This
> will also let you keep the of_device_id table where it was, at the
> bottom.
>
> > + if (!match) {
>
> I'm working on something similar in the axp20x driver. Is there any
> case of_match_node or of_device_get_match_data can fail?
>
>
Hello
I am working on some patch for that case and the conclusion was that case is
possible.
See https://lkml.org/lkml/2015/11/12/97
So it is better to check it.
Regards
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[linux-sunxi] Re: USB OTG: not enough bandwidth
Yes, visible. Dne sreda, 25. november 2015 21.30.44 UTC+1 je oseba ditma...@gmail.com napisala: > > Is this device visible with lsusb at the otg port ? -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v3 1/2] phy-sun4i-usb: Use of_match_node to get model specific config data
On Thu, Nov 26, 2015 at 12:50 AM, Hans de Goede wrote:
> Use of_match_node instead of calling of_device_is_compatible a ton of
> times to get model specific config data.
>
> Signed-off-by: Hans de Goede
> ---
> Changes in v3:
> -New patch in v3 of this patch-set
> ---
> drivers/phy/phy-sun4i-usb.c | 130
> +---
> 1 file changed, 85 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
> index b12964b..1d8f85d 100644
> --- a/drivers/phy/phy-sun4i-usb.c
> +++ b/drivers/phy/phy-sun4i-usb.c
> @@ -88,12 +88,22 @@
> #define DEBOUNCE_TIME msecs_to_jiffies(50)
> #define POLL_TIME msecs_to_jiffies(250)
>
> +enum sun4i_usb_phy_type {
> + sun4i_a10_phy,
> + sun8i_a33_phy,
> +};
> +
> +struct sun4i_usb_phy_cfg {
> + int num_phys;
> + u32 disc_thresh;
> + enum sun4i_usb_phy_type type;
> + bool dedicated_clocks;
> +};
> +
> struct sun4i_usb_phy_data {
> void __iomem *base;
> + const struct sun4i_usb_phy_cfg *cfg;
> struct mutex mutex;
> - int num_phys;
> - u32 disc_thresh;
> - bool has_a33_phyctl;
> struct sun4i_usb_phy {
> struct phy *phy;
> void __iomem *pmu;
> @@ -164,12 +174,15 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy
> *phy, u32 addr, u32 data,
>
> mutex_lock(&phy_data->mutex);
>
> - if (phy_data->has_a33_phyctl) {
> + switch (phy_data->cfg->type) {
> + case sun4i_a10_phy:
> + phyctl = phy_data->base + REG_PHYCTL_A10;
Any reason why this offset isn't incorporated into phy_data?
> + break;
> + case sun8i_a33_phy:
> phyctl = phy_data->base + REG_PHYCTL_A33;
> /* A33 needs us to set phyctl to 0 explicitly */
> writel(0, phyctl);
> - } else {
> - phyctl = phy_data->base + REG_PHYCTL_A10;
> + break;
> }
>
> for (i = 0; i < len; i++) {
> @@ -249,7 +262,8 @@ static int sun4i_usb_phy_init(struct phy *_phy)
> sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
>
> /* Disconnect threshold adjustment */
> - sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data->disc_thresh, 2);
> + sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
> + data->cfg->disc_thresh, 2);
>
> sun4i_usb_phy_passby(phy, 1);
>
> @@ -476,7 +490,7 @@ static struct phy *sun4i_usb_phy_xlate(struct device *dev,
> {
> struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
>
> - if (args->args[0] >= data->num_phys)
> + if (args->args[0] >= data->cfg->num_phys)
> return ERR_PTR(-ENODEV);
>
> return data->phys[args->args[0]].phy;
> @@ -499,6 +513,59 @@ static int sun4i_usb_phy_remove(struct platform_device
> *pdev)
> return 0;
> }
>
> +static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
> + .num_phys = 3,
> + .disc_thresh = 3,
> + .type = sun4i_a10_phy,
> + .dedicated_clocks = false,
> +};
> +
> +static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
> + .num_phys = 2,
> + .disc_thresh = 2,
> + .type = sun4i_a10_phy,
> + .dedicated_clocks = false,
> +};
> +
> +static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
> + .num_phys = 3,
> + .disc_thresh = 3,
> + .type = sun4i_a10_phy,
> + .dedicated_clocks = true,
> +};
> +
> +static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
> + .num_phys = 3,
> + .disc_thresh = 2,
> + .type = sun4i_a10_phy,
> + .dedicated_clocks = false,
> +};
> +
> +static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
> + .num_phys = 2,
> + .disc_thresh = 3,
> + .type = sun4i_a10_phy,
> + .dedicated_clocks = true,
> +};
> +
> +static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
> + .num_phys = 2,
> + .disc_thresh = 3,
> + .type = sun8i_a33_phy,
> + .dedicated_clocks = true,
> +};
> +
> +static const struct of_device_id sun4i_usb_phy_of_match[] = {
> + { .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg
> },
> + { .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg
> },
> + { .compatible = "allwinner,sun6i-a31-usb-phy", .data = &sun6i_a31_cfg
> },
> + { .compatible = "allwinner,sun7i-a20-usb-phy", .data = &sun7i_a20_cfg
> },
> + { .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg
> },
> + { .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg
> },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
> +
> static const unsigned int sun4i_usb_phy0_cable[] = {
> EXTCON_USB,
> EXTCON_USB_HOST,
> @@ -511,10 +578,16 @@ static int sun4i_usb_phy_probe(struct platform_device
> *pdev)
> struct device *dev = &pdev->d
[linux-sunxi] Re: [PATCH v3 2/2] phy-sun4i-usb: Add support for the host usb-phys found on the H3 SoC
On Wed, Nov 25, 2015 at 05:50:02PM +0100, Hans de Goede wrote:
> From: Reinder de Haan
>
> Note this commit only adds support for phys 1-3, phy 0, the otg phy, is
> not yet (fully) supported after this commit.
Shouldn't the OTG phy have a different compatible string?
>
> Signed-off-by: Reinder de Haan
> Signed-off-by: Hans de Goede
> ---
> Changes in v2:
> -Change break; after dev_err() to return, as intended, fixing a compiler
> warning (the dev_err case should never be reached)
> Changes in v3:
> -Use of_match_node to get model specific config data
> ---
> .../devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
> drivers/phy/phy-sun4i-usb.c| 46
> +-
> 2 files changed, 38 insertions(+), 9 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> index 0cebf74..95736d7 100644
> --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> @@ -9,6 +9,7 @@ Required properties:
>* allwinner,sun7i-a20-usb-phy
>* allwinner,sun8i-a23-usb-phy
>* allwinner,sun8i-a33-usb-phy
> + * allwinner,sun8i-h3-usb-phy
> - reg : a list of offset + length pairs
> - reg-names :
>* "phy_ctrl"
> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
> index 1d8f85d..2aed482 100644
> --- a/drivers/phy/phy-sun4i-usb.c
> +++ b/drivers/phy/phy-sun4i-usb.c
> @@ -46,6 +46,9 @@
> #define REG_PHYBIST 0x08
> #define REG_PHYTUNE 0x0c
> #define REG_PHYCTL_A33 0x10
> +#define REG_PHY_UNK_H3 0x20
> +
> +#define REG_PMU_UNK_H3 0x10
>
> #define PHYCTL_DATA BIT(7)
>
> @@ -79,7 +82,7 @@
> #define PHY_DISCON_TH_SEL0x2a
> #define PHY_SQUELCH_DETECT 0x3c
>
> -#define MAX_PHYS 3
> +#define MAX_PHYS 4
>
> /*
> * Note do not raise the debounce time, we must report Vusb high within 100ms
> @@ -91,6 +94,7 @@
> enum sun4i_usb_phy_type {
> sun4i_a10_phy,
> sun8i_a33_phy,
> + sun8i_h3_phy,
> };
>
> struct sun4i_usb_phy_cfg {
> @@ -101,6 +105,7 @@ struct sun4i_usb_phy_cfg {
> };
>
> struct sun4i_usb_phy_data {
> + struct device *dev;
> void __iomem *base;
> const struct sun4i_usb_phy_cfg *cfg;
> struct mutex mutex;
> @@ -183,6 +188,9 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy
> *phy, u32 addr, u32 data,
> /* A33 needs us to set phyctl to 0 explicitly */
> writel(0, phyctl);
> break;
> + case sun8i_h3_phy:
> + dev_err(phy_data->dev, "H3 usb_phy_write is not supported\n");
> + return;
> }
>
> for (i = 0; i < len; i++) {
> @@ -243,6 +251,7 @@ static int sun4i_usb_phy_init(struct phy *_phy)
> struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
> struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
> int ret;
> + u32 val;
>
> ret = clk_prepare_enable(phy->clk);
> if (ret)
> @@ -254,16 +263,26 @@ static int sun4i_usb_phy_init(struct phy *_phy)
> return ret;
> }
>
> - /* Enable USB 45 Ohm resistor calibration */
> - if (phy->index == 0)
> - sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
> + if (data->cfg->type == sun8i_h3_phy) {
> + if (phy->index == 0) {
> + val = readl(data->base + REG_PHY_UNK_H3);
> + writel(val & ~1, data->base + REG_PHY_UNK_H3);
> + }
>
> - /* Adjust PHY's magnitude and rate */
> - sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
> + val = readl(phy->pmu + REG_PMU_UNK_H3);
> + writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
> + } else {
> + /* Enable USB 45 Ohm resistor calibration */
> + if (phy->index == 0)
> + sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
>
> - /* Disconnect threshold adjustment */
> - sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
> - data->cfg->disc_thresh, 2);
> + /* Adjust PHY's magnitude and rate */
> + sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
> +
> + /* Disconnect threshold adjustment */
> + sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
> + data->cfg->disc_thresh, 2);
> + }
>
> sun4i_usb_phy_passby(phy, 1);
>
> @@ -555,6 +574,13 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
> .dedicated_clocks = true,
> };
>
> +static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
> + .num_phys = 4,
> + .disc_thresh = 3,
> + .type = sun8i_h3_phy,
> + .dedicated_clocks = true,
> +};
> +
> static const struct of_device_id sun4i_us
[linux-sunxi] USB OTG: not enough bandwidth
Is this device visible with lsusb at the otg port ? -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] USB OTG: not enough bandwidth
I am trying to connect a DAC via OTG port in host mode to Banana PI. Of course I am using powered HUB and some devices works fine. Among them one DAC (M2Tech Hiface). But I have a problem with another one (Oppo DAC 2.0). It refuses to work with (3.4.109 / 4.3.0) while* it works on a normal USB port*. Is there any hope / hint? Igor *Additional info:* cannot submit datapipe for urb 0, error -28: not enough bandwidth cannot submit urb 0, error -28: not enough bandwidth Kernel config for 4.3: http://pastebin.com/ngzS44Wb aplay -L http://pastebin.com/muvjzCHK -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v3 3/5] clk: sunxi: Add sun9i A80 cpus (cpu special) clock support
Hi, On Tue, Nov 24, 2015 at 05:32:14PM +0800, Chen-Yu Tsai wrote: > The "cpus" clock is the clock for the embedded processor in the A80. > It is also part of the PRCM clock tree. This clock includes a pre- > divider on one of its inputs. For now we are using a custom clock > driver for it. In the future we may want to develop a generalized > driver for these types of clocks, which also includes the AHB clock > driver on sun[5678]i. > > Signed-off-by: Chen-Yu Tsai > --- > > Hi Maxime, > > I'll do the factors clock refactoring mentioned during the discussion > around v2 later on. I have no idea what you are talking about :) > > --- > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + > drivers/clk/sunxi/Makefile| 1 + > drivers/clk/sunxi/clk-sun9i-cpus.c| 240 > ++ > 3 files changed, 242 insertions(+) > create mode 100644 drivers/clk/sunxi/clk-sun9i-cpus.c > > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt > b/Documentation/devicetree/bindings/clock/sunxi.txt > index b6859ed6913f..153ac72869e8 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt > @@ -27,6 +27,7 @@ Required properties: > "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s > "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20 > "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31 > + "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80 > "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31 > "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 > "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 > diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile > index 121333ce34ea..07d914c3f6d1 100644 > --- a/drivers/clk/sunxi/Makefile > +++ b/drivers/clk/sunxi/Makefile > @@ -13,6 +13,7 @@ obj-y += clk-simple-gates.o > obj-y += clk-sun8i-apb0.o > obj-y += clk-sun8i-mbus.o > obj-y += clk-sun9i-core.o > +obj-y += clk-sun9i-cpus.o Same thing here, if it's only used in the A80, just compile it when ARCH_SUN9I is compiled. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: Digital signature
[linux-sunxi] [PATCH v3 2/2] phy-sun4i-usb: Add support for the host usb-phys found on the H3 SoC
From: Reinder de Haan
Note this commit only adds support for phys 1-3, phy 0, the otg phy, is
not yet (fully) supported after this commit.
Signed-off-by: Reinder de Haan
Signed-off-by: Hans de Goede
---
Changes in v2:
-Change break; after dev_err() to return, as intended, fixing a compiler
warning (the dev_err case should never be reached)
Changes in v3:
-Use of_match_node to get model specific config data
---
.../devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
drivers/phy/phy-sun4i-usb.c| 46 +-
2 files changed, 38 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index 0cebf74..95736d7 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -9,6 +9,7 @@ Required properties:
* allwinner,sun7i-a20-usb-phy
* allwinner,sun8i-a23-usb-phy
* allwinner,sun8i-a33-usb-phy
+ * allwinner,sun8i-h3-usb-phy
- reg : a list of offset + length pairs
- reg-names :
* "phy_ctrl"
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index 1d8f85d..2aed482 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -46,6 +46,9 @@
#define REG_PHYBIST0x08
#define REG_PHYTUNE0x0c
#define REG_PHYCTL_A33 0x10
+#define REG_PHY_UNK_H3 0x20
+
+#define REG_PMU_UNK_H3 0x10
#define PHYCTL_DATABIT(7)
@@ -79,7 +82,7 @@
#define PHY_DISCON_TH_SEL 0x2a
#define PHY_SQUELCH_DETECT 0x3c
-#define MAX_PHYS 3
+#define MAX_PHYS 4
/*
* Note do not raise the debounce time, we must report Vusb high within 100ms
@@ -91,6 +94,7 @@
enum sun4i_usb_phy_type {
sun4i_a10_phy,
sun8i_a33_phy,
+ sun8i_h3_phy,
};
struct sun4i_usb_phy_cfg {
@@ -101,6 +105,7 @@ struct sun4i_usb_phy_cfg {
};
struct sun4i_usb_phy_data {
+ struct device *dev;
void __iomem *base;
const struct sun4i_usb_phy_cfg *cfg;
struct mutex mutex;
@@ -183,6 +188,9 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy,
u32 addr, u32 data,
/* A33 needs us to set phyctl to 0 explicitly */
writel(0, phyctl);
break;
+ case sun8i_h3_phy:
+ dev_err(phy_data->dev, "H3 usb_phy_write is not supported\n");
+ return;
}
for (i = 0; i < len; i++) {
@@ -243,6 +251,7 @@ static int sun4i_usb_phy_init(struct phy *_phy)
struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
int ret;
+ u32 val;
ret = clk_prepare_enable(phy->clk);
if (ret)
@@ -254,16 +263,26 @@ static int sun4i_usb_phy_init(struct phy *_phy)
return ret;
}
- /* Enable USB 45 Ohm resistor calibration */
- if (phy->index == 0)
- sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
+ if (data->cfg->type == sun8i_h3_phy) {
+ if (phy->index == 0) {
+ val = readl(data->base + REG_PHY_UNK_H3);
+ writel(val & ~1, data->base + REG_PHY_UNK_H3);
+ }
- /* Adjust PHY's magnitude and rate */
- sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
+ val = readl(phy->pmu + REG_PMU_UNK_H3);
+ writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
+ } else {
+ /* Enable USB 45 Ohm resistor calibration */
+ if (phy->index == 0)
+ sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
- /* Disconnect threshold adjustment */
- sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
- data->cfg->disc_thresh, 2);
+ /* Adjust PHY's magnitude and rate */
+ sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
+
+ /* Disconnect threshold adjustment */
+ sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
+ data->cfg->disc_thresh, 2);
+ }
sun4i_usb_phy_passby(phy, 1);
@@ -555,6 +574,13 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
.dedicated_clocks = true,
};
+static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
+ .num_phys = 4,
+ .disc_thresh = 3,
+ .type = sun8i_h3_phy,
+ .dedicated_clocks = true,
+};
+
static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
@@ -562,6 +588,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] =
{
{ .compatible = "all
[linux-sunxi] [PATCH v3 1/2] phy-sun4i-usb: Use of_match_node to get model specific config data
Use of_match_node instead of calling of_device_is_compatible a ton of
times to get model specific config data.
Signed-off-by: Hans de Goede
---
Changes in v3:
-New patch in v3 of this patch-set
---
drivers/phy/phy-sun4i-usb.c | 130 +---
1 file changed, 85 insertions(+), 45 deletions(-)
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index b12964b..1d8f85d 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -88,12 +88,22 @@
#define DEBOUNCE_TIME msecs_to_jiffies(50)
#define POLL_TIME msecs_to_jiffies(250)
+enum sun4i_usb_phy_type {
+ sun4i_a10_phy,
+ sun8i_a33_phy,
+};
+
+struct sun4i_usb_phy_cfg {
+ int num_phys;
+ u32 disc_thresh;
+ enum sun4i_usb_phy_type type;
+ bool dedicated_clocks;
+};
+
struct sun4i_usb_phy_data {
void __iomem *base;
+ const struct sun4i_usb_phy_cfg *cfg;
struct mutex mutex;
- int num_phys;
- u32 disc_thresh;
- bool has_a33_phyctl;
struct sun4i_usb_phy {
struct phy *phy;
void __iomem *pmu;
@@ -164,12 +174,15 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy
*phy, u32 addr, u32 data,
mutex_lock(&phy_data->mutex);
- if (phy_data->has_a33_phyctl) {
+ switch (phy_data->cfg->type) {
+ case sun4i_a10_phy:
+ phyctl = phy_data->base + REG_PHYCTL_A10;
+ break;
+ case sun8i_a33_phy:
phyctl = phy_data->base + REG_PHYCTL_A33;
/* A33 needs us to set phyctl to 0 explicitly */
writel(0, phyctl);
- } else {
- phyctl = phy_data->base + REG_PHYCTL_A10;
+ break;
}
for (i = 0; i < len; i++) {
@@ -249,7 +262,8 @@ static int sun4i_usb_phy_init(struct phy *_phy)
sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
/* Disconnect threshold adjustment */
- sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data->disc_thresh, 2);
+ sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
+ data->cfg->disc_thresh, 2);
sun4i_usb_phy_passby(phy, 1);
@@ -476,7 +490,7 @@ static struct phy *sun4i_usb_phy_xlate(struct device *dev,
{
struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
- if (args->args[0] >= data->num_phys)
+ if (args->args[0] >= data->cfg->num_phys)
return ERR_PTR(-ENODEV);
return data->phys[args->args[0]].phy;
@@ -499,6 +513,59 @@ static int sun4i_usb_phy_remove(struct platform_device
*pdev)
return 0;
}
+static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
+ .num_phys = 3,
+ .disc_thresh = 3,
+ .type = sun4i_a10_phy,
+ .dedicated_clocks = false,
+};
+
+static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
+ .num_phys = 2,
+ .disc_thresh = 2,
+ .type = sun4i_a10_phy,
+ .dedicated_clocks = false,
+};
+
+static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
+ .num_phys = 3,
+ .disc_thresh = 3,
+ .type = sun4i_a10_phy,
+ .dedicated_clocks = true,
+};
+
+static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
+ .num_phys = 3,
+ .disc_thresh = 2,
+ .type = sun4i_a10_phy,
+ .dedicated_clocks = false,
+};
+
+static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
+ .num_phys = 2,
+ .disc_thresh = 3,
+ .type = sun4i_a10_phy,
+ .dedicated_clocks = true,
+};
+
+static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
+ .num_phys = 2,
+ .disc_thresh = 3,
+ .type = sun8i_a33_phy,
+ .dedicated_clocks = true,
+};
+
+static const struct of_device_id sun4i_usb_phy_of_match[] = {
+ { .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
+ { .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
+ { .compatible = "allwinner,sun6i-a31-usb-phy", .data = &sun6i_a31_cfg },
+ { .compatible = "allwinner,sun7i-a20-usb-phy", .data = &sun7i_a20_cfg },
+ { .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
+ { .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
+ { },
+};
+MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
+
static const unsigned int sun4i_usb_phy0_cable[] = {
EXTCON_USB,
EXTCON_USB_HOST,
@@ -511,10 +578,16 @@ static int sun4i_usb_phy_probe(struct platform_device
*pdev)
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct phy_provider *phy_provider;
- bool dedicated_clocks;
+ const struct of_device_id *match;
struct resource *res;
int i, ret;
+ match = of_match_node(sun4i_usb_phy_of_match, dev->of_node);
+ if (!match) {
+ dev_err(dev, "of_match_node() failed\n");
+ return -EINVAL;
+
[linux-sunxi] Re: [PATCH v3 1/5] clk: sunxi: Add CLK_OF_DECLARE support for sun8i-a23-apb0-clk driver
On Tue, Nov 24, 2015 at 05:32:12PM +0800, Chen-Yu Tsai wrote:
> The APBS clock on sun9i is the same as the APB0 clock on sun8i. With
> sun9i we are supporting the PRCM clocks by using CLK_OF_DECLARE,
> instead of through a PRCM mfd device and subdevices for each clock
> and reset control. As such we need a CLK_OF_DECLARE version of
> the sun8i-a23-apb0-clk driver.
>
> Also, build it for all Allwinner/sunxi platforms, and not just for
> configurations with MFD_SUN6I_PRCM enabled.
>
> Signed-off-by: Chen-Yu Tsai
> ---
> drivers/clk/sunxi/Makefile | 4 ++--
> drivers/clk/sunxi/clk-sun8i-apb0.c | 43
> ++
> 2 files changed, 45 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index cb4c299214ce..121333ce34ea 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -10,11 +10,11 @@ obj-y += clk-a10-pll2.o
> obj-y += clk-a20-gmac.o
> obj-y += clk-mod0.o
> obj-y += clk-simple-gates.o
> +obj-y += clk-sun8i-apb0.o
> obj-y += clk-sun8i-mbus.o
> obj-y += clk-sun9i-core.o
> obj-y += clk-sun9i-mmc.o
> obj-y += clk-usb.o
>
> obj-$(CONFIG_MFD_SUN6I_PRCM) += \
> - clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
> - clk-sun8i-apb0.o
> + clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o
I'd really prefer not to build a driver that is used only on a few
SoCs if the support for these SoCs are not even enabled.
> diff --git a/drivers/clk/sunxi/clk-sun8i-apb0.c
> b/drivers/clk/sunxi/clk-sun8i-apb0.c
> index 7ae5d2c2cde1..11b2f2fde245 100644
> --- a/drivers/clk/sunxi/clk-sun8i-apb0.c
> +++ b/drivers/clk/sunxi/clk-sun8i-apb0.c
> @@ -17,8 +17,51 @@
> #include
> #include
> #include
> +#include
> #include
>
> +static void sun8i_a23_apb0_setup(struct device_node *node)
> +{
> + const char *clk_name = node->name;
> + const char *clk_parent;
> + void __iomem *reg;
> + struct resource res;
> + struct clk *clk;
> + int ret;
> +
> + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> + if (IS_ERR(reg))
> + return;
> +
> + clk_parent = of_clk_get_parent_name(node, 0);
> + if (!clk_parent)
> + goto err_unmap;
> +
> + of_property_read_string(node, "clock-output-names", &clk_name);
> +
> + /* The A23 APB0 clock is a standard 2 bit wide divider clock */
> + clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg,
> +0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
> + if (IS_ERR(clk))
> + goto err_unmap;
> +
> + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
> + if (ret)
> + goto err_unregister;
> +
> + return;
> +
> +err_unregister:
> + clk_unregister_divider(clk);
> +
> +err_unmap:
> + iounmap(reg);
> + of_address_to_resource(node, 0, &res);
> + release_mem_region(res.start, resource_size(&res));
> +}
> +CLK_OF_DECLARE(sun8i_a23_apb0, "allwinner,sun8i-a23-apb0-clk",
> +sun8i_a23_apb0_setup);
So, beside the memory request / mapping, everything else is
duplicated? Can't you just create a common function and call it from
both?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Re: [linux-sunxi] A20 higher External interrupr (EINT22-EINT31)
DTS FIXED: Per http://www.serverphorums.com/read.php?12,1260131 Add a proper interrupt xlate function, that uses the same description than the GPIOs ( ), that will make things less confusing. Corrected example interrupt-parent = <&pio>; interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: [PATCH v2 3/5] thermal: Add a driver for the Allwinner THS sensor
November 24 2015 9:43 AM, "Maxime Ripard" wrote: > On Mon, Nov 23, 2015 at 09:02:50AM +0100, Josef Gajdusek wrote: > >> This patch adds support for the Sunxi thermal sensor on the Allwinner H3. > > You can drop the sunxi here. > >> Should be easily extendable for the A33/A83T/... as they have similar but >> not completely identical sensors. >> >> Signed-off-by: Josef Gajdusek >> --- >> drivers/thermal/Kconfig | 7 + >> drivers/thermal/Makefile | 1 + >> drivers/thermal/sun8i_ths.c | 365 >> >> 3 files changed, 373 insertions(+) >> create mode 100644 drivers/thermal/sun8i_ths.c >> >> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig >> index c463c89..2b41147 100644 >> --- a/drivers/thermal/Kconfig >> +++ b/drivers/thermal/Kconfig >> @@ -365,6 +365,13 @@ config INTEL_PCH_THERMAL >> Thermal reporting device will provide temperature reading, >> programmable trip points and other information. >> >> +config SUN8I_THS >> + tristate "sun8i THS driver" >> + depends on MACH_SUN8I >> + depends on OF >> + help >> + Enable this to support thermal reporting on some newer Allwinner SoCs. >> + >> menu "Texas Instruments thermal drivers" >> depends on ARCH_HAS_BANDGAP || COMPILE_TEST >> source "drivers/thermal/ti-soc-thermal/Kconfig" >> diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile >> index cfae6a6..227e1a1 100644 >> --- a/drivers/thermal/Makefile >> +++ b/drivers/thermal/Makefile >> @@ -48,3 +48,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o >> obj-$(CONFIG_ST_THERMAL) += st/ >> obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o >> obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o >> +obj-$(CONFIG_SUN8I_THS) += sun8i_ths.o >> diff --git a/drivers/thermal/sun8i_ths.c b/drivers/thermal/sun8i_ths.c >> new file mode 100644 >> index 000..2c976ac >> --- /dev/null >> +++ b/drivers/thermal/sun8i_ths.c >> @@ -0,0 +1,365 @@ >> +/* >> + * Sunxi THS driver > > sun8i Thermal Sensor Driver > >> + * Copyright (C) 2015 Josef Gajdusek >> + * >> + * This software is licensed under the terms of the GNU General Public >> + * License version 2, as published by the Free Software Foundation, and >> + * may be copied, distributed, and modified under those terms. >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + */ >> + >> +#include >> +#include > > Are you using this header? > >> +#include >> +#include >> +#include > > You probably don't need this one too. > >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#define THS_H3_CTRL0 0x00 >> +#define THS_H3_CTRL1 0x04 >> +#define THS_H3_CDAT 0x14 >> +#define THS_H3_CTRL2 0x40 >> +#define THS_H3_INT_CTRL 0x44 >> +#define THS_H3_STAT 0x48 >> +#define THS_H3_ALARM_CTRL 0x50 >> +#define THS_H3_SHUTDOWN_CTRL 0x60 >> +#define THS_H3_FILTER 0x70 >> +#define THS_H3_CDATA 0x74 >> +#define THS_H3_DATA 0x80 >> + >> +#define THS_H3_CTRL0_SENSOR_ACQ0_OFFS 0 >> +#define THS_H3_CTRL0_SENSOR_ACQ0(x) \ >> + ((x) << THS_H3_CTRL0_SENSOR_ACQ0_OFFS) >> +#define THS_H3_CTRL1_ADC_CALI_EN_OFFS 17 >> +#define THS_H3_CTRL1_ADC_CALI_EN \ >> + BIT(THS_H3_CTRL1_ADC_CALI_EN_OFFS) >> +#define THS_H3_CTRL1_OP_BIAS_OFFS 20 >> +#define THS_H3_CTRL1_OP_BIAS(x) \ >> + ((x) << THS_H3_CTRL1_OP_BIAS_OFFS) >> +#define THS_H3_CTRL2_SENSE_EN_OFFS 0 >> +#define THS_H3_CTRL2_SENSE_EN \ >> + BIT(THS_H3_CTRL2_SENSE_EN_OFFS) >> +#define THS_H3_CTRL2_SENSOR_ACQ1_OFFS 16 >> +#define THS_H3_CTRL2_SENSOR_ACQ1(x) \ >> + ((x) << THS_H3_CTRL2_SENSOR_ACQ1_OFFS) >> + >> +#define THS_H3_INT_CTRL_ALARM_INT_EN_OFFS 0 >> +#define THS_H3_INT_CTRL_ALARM_INT_EN \ >> + BIT(THS_H3_INT_CTRL_ALARM_INT_EN_OFFS) >> +#define THS_H3_INT_CTRL_SHUT_INT_EN_OFFS 4 >> +#define THS_H3_INT_CTRL_SHUT_INT_EN \ >> + BIT(THS_H3_INT_CTRL_SHUT_INT_EN_OFFS) >> +#define THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS 8 >> +#define THS_H3_INT_CTRL_DATA_IRQ_EN \ >> + BIT(THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS) >> +#define THS_H3_INT_CTRL_THERMAL_PER_OFFS 12 >> +#define THS_H3_INT_CTRL_THERMAL_PER(x) \ >> + ((x) << THS_H3_INT_CTRL_THERMAL_PER_OFFS) >> + >> +#define THS_H3_STAT_ALARM_INT_STS_OFFS 0 >> +#define THS_H3_STAT_ALARM_INT_STS \ >> + BIT(THS_H3_STAT_ALARM_INT_STS_OFFS) >> +#define THS_H3_STAT_SHUT_INT_STS_OFFS 4 >> +#define THS_H3_STAT_SHUT_INT_STS \ >> + BIT(THS_H3_STAT_SHUT_INT_STS_OFFS) >> +#define THS_H3_STAT_DATA_IRQ_STS_OFFS 8 >> +#define THS_H3_STAT_DATA_IRQ_STS \ >> + BIT(THS_H3_STAT_DATA_IRQ_STS_OFFS) >> +#define THS_H3_STAT_ALARM_OFF_STS_OFFS 12 >> +#define THS_H3_STAT_ALARM_OFF_STS \ >> + BIT(THS_H3_STAT_ALARM_OFF_STS_OFFS) >> + >> +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS 0 >> +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST(x) \ >> + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS) >> +#define TH
