[linux-sunxi] Re: [PATCH] musb: sunxi-glue: Fix sunxi-musb driver not auto-loading
On Mon, Mar 21, 2016 at 7:13 PM, Hans de Goede wrote: > Add a missing MODULE_DEVICE_TABLE() line which was causing the > sunxi-musb glue to not auto-load when build as a module. > > Signed-off-by: Hans de Goede > --- Reviewed-by: Javier Martinez Canillas Best regards, Javier -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: [PATCH v7] ARM: dts: sun8i: Add leds and switches on Orangepi Plus boards
Hi,
On 21-03-16 08:59, Maxime Ripard wrote:
Hi,
On Sun, Mar 20, 2016 at 07:55:02PM +0100, Hans de Goede wrote:
From: Krzysztof Adamski
OrangePi Plus board has two leds - green ("pwr") and red ("status")
and two switches ("sw4" and "sw2"). This patch describes them in
devicetree.
Signed-off-by: Krzysztof Adamski
Signed-off-by: Hans de Goede
An earlier version has already been sent for 4.6, please base your
changes on top of this one.
And there's a bunch of things I didn't catch at that time :/
As promised I will send a fixup patch for this, I was wondering
if you can push your current queue, where you've already merged
my other orangepi-plus patches somewhere, so that I can base this
fixup patch on top of it ?
Regards,
Hans
---
Changes in v6 (hdegoede):
-Merge leds and r_leds nodes into one
-Fix led labels to be in :: form
-Alphabetically sort the added nodes
-Add support for sw2 (this is the small reset-like button)
Changes in v7 (hdegoede):
-Use PL3 / PL4 in the pinctrl node, not PL03 / PL04
---
arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 63
1 file changed, 63 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
index a680b1f..9d8c038 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
@@ -45,6 +45,7 @@
#include "sunxi-common-regulators.dtsi"
#include
+#include
#include
/ {
@@ -59,6 +60,43 @@
stdout-path = "serial0:115200n8";
};
+ gpio_keys {
+ compatible = "gpio-keys";
+ input-name = "sw4";
This is an undocumented (and apparently unused) property
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_r_opc>;
+
+ sw2@0 {
You shouldn't have a unit-address here
+ label = "sw2";
+ linux,code = ;
+ gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>;
+ };
+
+ sw4@0 {
Ditto.
Thanks!
Maxime
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[linux-sunxi] [PATCH] musb: sunxi-glue: Fix sunxi-musb driver not auto-loading
Add a missing MODULE_DEVICE_TABLE() line which was causing the
sunxi-musb glue to not auto-load when build as a module.
Signed-off-by: Hans de Goede
---
drivers/usb/musb/sunxi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
index 4b472b8..9af9431 100644
--- a/drivers/usb/musb/sunxi.c
+++ b/drivers/usb/musb/sunxi.c
@@ -756,6 +756,7 @@ static const struct of_device_id sunxi_musb_match[] = {
{ .compatible = "allwinner,sun8i-a33-musb", },
{}
};
+MODULE_DEVICE_TABLE(of, sunxi_musb_match);
static struct platform_driver sunxi_musb_driver = {
.probe = sunxi_musb_probe,
--
2.7.3
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[linux-sunxi] [PATCH sunxi-tools v2 0/2] fel: Minor fixes
Changes in v2: - Rebased to current master - Added some formatting adjustments - Added a second patch that simplifies hexdump() Bernhard Nortmann (2): fel: Minor fixes fel: Simplify hexdump() single character output, using putchar() fel.c | 43 --- 1 file changed, 20 insertions(+), 23 deletions(-) -- 2.4.10 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH sunxi-tools v2 2/2] fel: Simplify hexdump() single character output, using putchar()
Signed-off-by: Bernhard Nortmann
---
fel.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/fel.c b/fel.c
index 616cd05..da006ac 100644
--- a/fel.c
+++ b/fel.c
@@ -322,16 +322,14 @@ void hexdump(void *data, uint32_t offset, size_t size)
else
printf("__ ");
}
- printf(" ");
+ putchar(' ');
for (i = 0; i < 16; i++) {
if (j+i >= size)
- printf(".");
- else if (isprint(buf[j+i]))
- printf("%c", buf[j+i]);
+ putchar('.');
else
- printf(".");
+ putchar(isprint(buf[j+i]) ? buf[j+i] : '.');
}
- printf("\n");
+ putchar('\n');
}
}
--
2.4.10
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[linux-sunxi] [PATCH sunxi-tools v2 1/2] fel: Minor fixes
- Do a clean shutdown / exit(0) after printing usage help,
instead of continuing execution. This avoids the "ERROR:
Allwinner USB FEL device not found!" when doing a plain
./sunxi-fel without any arguments.
- Convert C++ style comments for a uniform coding style.
- Some small formatting adjustments.
Signed-off-by: Bernhard Nortmann
---
fel.c | 35 +--
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/fel.c b/fel.c
index dedde55..616cd05 100644
--- a/fel.c
+++ b/fel.c
@@ -80,7 +80,7 @@ static void pr_info(const char *fmt, ...)
}
}
-static const int AW_USB_MAX_BULK_SEND = 4 * 1024 * 1024; // 4 MiB per bulk
request
+static const int AW_USB_MAX_BULK_SEND = 4 * 1024 * 1024; /* 4 MiB per bulk
request */
void usb_bulk_send(libusb_device_handle *usb, int ep, const void *data,
size_t length, bool progress)
@@ -105,7 +105,7 @@ void usb_bulk_send(libusb_device_handle *usb, int ep, const
void *data,
data += sent;
if (progress)
- progress_update(sent); // notification after each chunk
+ progress_update(sent); /* notification after each chunk
*/
}
}
@@ -317,21 +317,19 @@ void hexdump(void *data, uint32_t offset, size_t size)
size_t i;
printf("%08lx: ",(long int)offset + j);
for (i = 0; i < 16; i++) {
- if ((j+i) < size) {
+ if ((j+i) < size)
printf("%02x ", buf[j+i]);
- } else {
+ else
printf("__ ");
- }
}
printf(" ");
for (i = 0; i < 16; i++) {
- if (j+i >= size) {
+ if (j+i >= size)
printf(".");
- } else if (isprint(buf[j+i])) {
+ else if (isprint(buf[j+i]))
printf("%c", buf[j+i]);
- } else {
+ else
printf(".");
- }
}
printf("\n");
}
@@ -380,7 +378,7 @@ void *load_file(const char *name, size_t *size)
exit(1);
}
- while(1) {
+ while (1) {
ssize_t len = bufsize - offset;
ssize_t n = fread(buf+offset, 1, len, in);
offset += n;
@@ -1075,7 +1073,7 @@ void aw_fel_write_and_execute_spl(libusb_device_handle
*usb,
}
/* re-enable the MMU if it was enabled by BROM */
- if(tt != NULL)
+ if (tt != NULL)
aw_restore_and_enable_mmu(usb, sram_info, tt);
}
@@ -1237,7 +1235,7 @@ static int aw_fel_get_endpoint(libusb_device_handle *usb)
const struct libusb_endpoint_descriptor *ep =
setting->endpoint + ep_idx;
- // Test for bulk transfer endpoint
+ /* Test for bulk transfer endpoint */
if ((ep->bmAttributes &
LIBUSB_TRANSFER_TYPE_MASK) !=
LIBUSB_TRANSFER_TYPE_BULK)
continue;
@@ -1272,7 +1270,7 @@ static unsigned int file_upload(libusb_device_handle
*handle, size_t count,
for (i = 0; i < count; i++)
size += file_size(argv[i * 2 + 1]);
- progress_start(progress, size); // set total size and progress callback
+ progress_start(progress, size); /* set total size and progress callback
*/
/* now transfer each file in turn */
for (i = 0; i < count; i++) {
@@ -1281,14 +1279,14 @@ static unsigned int file_upload(libusb_device_handle
*handle, size_t count,
uint32_t offset = strtoul(argv[i * 2], NULL, 0);
aw_write_buffer(handle, buf, offset, size, true);
- // If we transferred a script, try to inform U-Boot
about its address.
+ /* If we transferred a script, try to inform U-Boot
about its address. */
if (get_image_type(buf, size) == IH_TYPE_SCRIPT)
pass_fel_information(handle, offset);
}
free(buf);
}
- return i; // return number of files that were processed
+ return i; /* return number of files that were processed */
}
/* open libusb handle to desired FEL device */
@@ -1369,8 +1367,6 @@ int main(int argc, char **argv)
libusb_device_handle *handle;
int busnum = -1, devnum = -1;
int iface_detached = -1;
- int rc = libusb_init(NULL);
- assert(rc == 0);
if (argc <= 1) {
printf("Usage: %s [options] command argumen
[linux-sunxi][PATCH v3 5/8] ARM: dts: sun4i: Add the SPDIF block to the A10
From: Marcus Cooper
Add the SPDIF transceiver controller block to the A10 dtsi.
Signed-off-by: Marcus Cooper
---
arch/arm/boot/dts/sun4i-a10.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 5747522..7171a27 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -1052,6 +1052,19 @@
status = "disabled";
};
+ spdif: spdif@01c21000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun4i-a10-spdif";
+ reg = <0x01c21000 0x400>;
+ interrupts = <13>;
+ clocks = <&apb0_gates 1>, <&spdif_clk>;
+ clock-names = "apb", "spdif";
+ dmas = <&dma SUN4I_DMA_NORMAL 2>,
+ <&dma SUN4I_DMA_NORMAL 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
ir0: ir@01c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <&apb0_gates 6>, <&ir0_clk>;
--
2.7.4
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[linux-sunxi][PATCH v3 8/8] ARM: dts: sun7i: Add SPDIF to the Itead Ibox
From: Marcus Cooper
Enable the S/PDIF transmitter that is present on the Itead Ibox.
Signed-off-by: Marcus Cooper
---
arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
index a512581..9542865 100644
--- a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
+++ b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
@@ -65,6 +65,24 @@
default-state = "on";
};
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "On-board SPDIF";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ };
};
&ahci {
@@ -131,6 +149,12 @@
status = "okay";
};
+&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx_pins_a>;
+ status = "okay";
+};
+
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
--
2.7.4
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[linux-sunxi][PATCH v3 1/8] ARM: dts :sunxi: Add SPDIF TX pin to the A10
From: Marcus Cooper
Add the SPDIF TX pin to the A10 dtsi.
Signed-off-by: Marcus Cooper
---
arch/arm/boot/dts/sun4i-a10.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 2c8f5e6..62fcef9 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -1006,6 +1006,13 @@
allwinner,drive = ;
allwinner,pull = ;
};
+
+ spdif_tx_pins_a: spdif@0 {
+ allwinner,pins = "PB13";
+ allwinner,function = "spdif";
+ allwinner,drive = ;
+ allwinner,pull = ;
+ };
};
timer@01c20c00 {
--
2.7.4
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[linux-sunxi][PATCH v3 2/8] ARM: dts :sun7i: Add SPDIF TX pin to the A20
From: Marcus Cooper
Add the SPDIF TX pin to the A20 dtsi.
Signed-off-by: Marcus Cooper
---
arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 0940a78..0c207d0 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -1193,6 +1193,13 @@
allwinner,drive = ;
allwinner,pull = ;
};
+
+ spdif_tx_pins_a: spdif@0 {
+ allwinner,pins = "PB13";
+ allwinner,function = "spdif";
+ allwinner,drive = ;
+ allwinner,pull = ;
+ };
};
timer@01c20c00 {
--
2.7.4
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[linux-sunxi][PATCH v3 4/8] ARM: dts: sun7i: Add the SPDIF clk to the A20
From: Marcus Cooper
Add the SPDIF clock to the A20 dtsi.
Signed-off-by: Marcus Cooper
---
arch/arm/boot/dts/sun7i-a20.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 0c207d0..108cad4 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -476,6 +476,17 @@
clock-output-names = "ir1";
};
+ spdif_clk: clk@01c200c0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod1-clk";
+ reg = <0x01c200c0 0x4>;
+ clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+<&pll2 SUN4I_A10_PLL2_4X>,
+<&pll2 SUN4I_A10_PLL2_2X>,
+<&pll2 SUN4I_A10_PLL2_1X>;
+ clock-output-names = "spdif";
+ };
+
keypad_clk: clk@01c200c4 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
--
2.7.4
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[linux-sunxi][PATCH v3 6/8] ARM: dts: sun7i: Add the SPDIF block to the A20
From: Marcus Cooper
Add the SPDIF transceiver controller block to the A20 dtsi.
Signed-off-by: Marcus Cooper
---
arch/arm/boot/dts/sun7i-a20.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 108cad4..9944496 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -1244,6 +1244,19 @@
status = "disabled";
};
+ spdif: spdif@01c21000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun4i-a10-spdif";
+ reg = <0x01c21000 0x400>;
+ interrupts = ;
+ clocks = <&apb0_gates 1>, <&spdif_clk>;
+ clock-names = "apb", "spdif";
+ dmas = <&dma SUN4I_DMA_NORMAL 2>,
+ <&dma SUN4I_DMA_NORMAL 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
ir0: ir@01c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <&apb0_gates 6>, <&ir0_clk>;
--
2.7.4
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[linux-sunxi][PATCH v3 7/8] ARM: dts: sun4i: Add SPDIF to the Mele A1000
From: Marcus Cooper
Enable the S/PDIF transmitter that is present on the A1000.
Signed-off-by: Marcus Cooper
---
arch/arm/boot/dts/sun4i-a10-a1000.dts | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts
b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index 97570cb..c92a1ae 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -87,6 +87,24 @@
enable-active-high;
gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>;
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "On-board SPDIF";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ };
};
&ahci {
@@ -188,6 +206,12 @@
status = "okay";
};
+&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx_pins_a>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
--
2.7.4
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[linux-sunxi][PATCH v3 3/8] ARM: dts: sun4i: Add the SPDIF clk to the A10
From: Marcus Cooper
Add the SPDIF clock to the A10 dtsi.
Signed-off-by: Marcus Cooper
---
arch/arm/boot/dts/sun4i-a10.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 62fcef9..5747522 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -477,6 +477,17 @@
clock-output-names = "ir1";
};
+ spdif_clk: clk@01c200c0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod1-clk";
+ reg = <0x01c200c0 0x4>;
+ clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+<&pll2 SUN4I_A10_PLL2_4X>,
+<&pll2 SUN4I_A10_PLL2_2X>,
+<&pll2 SUN4I_A10_PLL2_1X>;
+ clock-output-names = "spdif";
+ };
+
usb_clk: clk@01c200cc {
#clock-cells = <1>;
#reset-cells = <1>;
--
2.7.4
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[linux-sunxi][PATCH v3 0/8] ARM: sunxi: Add SPDIF playback support
From: Marcus Cooper Hi All, now that the sun4i-spdif driver has made it into linux-next then this patch series completes what is needed to have SPDIF working on both A10 and A20 devices. Enjoy, CK --- Changes since v2: - Split the patches up, added and removed some newlines, removed unused spdif pins Changes since v1: - Added defines to the dma properties and changed reg length to cover the entire spdif memory area. Marcus Cooper (8): ARM: dts :sunxi: Add SPDIF TX pin to the A10 ARM: dts :sun7i: Add SPDIF TX pin to the A20 ARM: dts: sun4i: Add the SPDIF clk to the A10 ARM: dts: sun7i: Add the SPDIF clk to the A20 ARM: dts: sun4i: Add the SPDIF block to the A10 ARM: dts: sun7i: Add the SPDIF block to the A20 ARM: dts: sun4i: Add SPDIF to the Mele A1000 ARM: dts: sun7i: Add SPDIF to the Itead Ibox arch/arm/boot/dts/sun4i-a10-a1000.dts | 24 +++ arch/arm/boot/dts/sun4i-a10.dtsi | 31 ++ arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 24 +++ arch/arm/boot/dts/sun7i-a20.dtsi | 31 ++ 4 files changed, 110 insertions(+) -- 2.7.4 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [PATCH 1/2] fel: only read MMU control registers if MMU is enabled
On 21/03/16 19:22, Siarhei Siamashka wrote:
> On Mon, 21 Mar 2016 14:24:14 +0100
> Jens Kuske wrote:
>
>> This workaround is necessary for A80, which sometimes
>> fails at reading DACR.
>>
>> Signed-off-by: Jens Kuske
>> ---
>> fel.c | 9 +
>> 1 file changed, 5 insertions(+), 4 deletions(-)
>>
>> diff --git a/fel.c b/fel.c
>> index a905ad5..ba58105 100644
>> --- a/fel.c
>> +++ b/fel.c
>> @@ -767,10 +767,7 @@ uint32_t
>> *aw_backup_and_disable_mmu(libusb_device_handle *usb,
>> soc_sram_info *sram_info)
>> {
>> uint32_t *tt = NULL;
>> -uint32_t ttbr0 = aw_get_ttbr0(usb, sram_info);
>> -uint32_t sctlr = aw_get_sctlr(usb, sram_info);
>> -uint32_t ttbcr = aw_get_ttbcr(usb, sram_info);
>> -uint32_t dacr = aw_get_dacr(usb, sram_info);
>> +uint32_t sctlr, ttbr0, ttbcr, dacr;
>> uint32_t i;
>>
>> uint32_t arm_code[] = {
>> @@ -796,6 +793,7 @@ uint32_t *aw_backup_and_disable_mmu(libusb_device_handle
>> *usb,
>> */
>>
>> /* Basically, ignore M/Z/I bits and expect no TEX remap */
>> +sctlr = aw_get_sctlr(usb, sram_info);
>> if ((sctlr & ~((1 << 12) | (1 << 11) | 1)) != 0x00C52078) {
>> fprintf(stderr, "Unexpected SCTLR (%08X)\n", sctlr);
>> exit(1);
>> @@ -806,16 +804,19 @@ uint32_t
>> *aw_backup_and_disable_mmu(libusb_device_handle *usb,
>> return NULL;
>> }
>>
>> +dacr = aw_get_dacr(usb, sram_info);
>> if (dacr != 0x) {
>> fprintf(stderr, "Unexpected DACR (%08X)\n", dacr);
>> exit(1);
>> }
>>
>> +ttbcr = aw_get_ttbcr(usb, sram_info);
>> if (ttbcr != 0x) {
>> fprintf(stderr, "Unexpected TTBCR (%08X)\n", ttbcr);
>> exit(1);
>> }
>>
>> +ttbr0 = aw_get_ttbr0(usb, sram_info);
>> if (ttbr0 & 0x3FFF) {
>> fprintf(stderr, "Unexpected TTBR0 (%08X)\n", ttbr0);
>> exit(1);
>
> As we discussed on IRC earlier, having this patch is reasonable as
> it workarounds A80 problems and makes FEL boot usable on it. So
> Reviewed-by: Siarhei Siamashka
>
> I have already pushed it to github, thanks!
>
> Too bad that we still don't know what's going on. We can probably add a
> comment to the Notes column in the SoC support status table and warn
> the users, so that they watch out and report any possible
> irregularities: https://linux-sunxi.org/FEL/USBBoot#SoC_support_status
>
> Can you probably try to read the MIDR register to check if the A80
> SoC initially boots on a Cortex A15 or a Cortex A7 core? If it is A7,
> then something is really odd. But if it is A15, then aggressive
> instructions reordering may be exposing a missing barrier instruction
> here or there. There are also some configuration knobs in the A15 too,
> which allow to partially enforce in-order behaviour:
>http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABGHIBG.html
>
Hi Siarhei,
the MIDR register reads 0x410fc075, looks like it is a Cortex A7.
I've tried various things like reordering the reads, leaving out some
reads or adding additional ones for random registers, it always fails at
DACR. I have no idea what that means...
Sometimes it randomly works after reset, but not very often (maybe 5%).
I've given up investigating this any further for now, I haven't seen any
problems after this patch anymore.
Regards,
Jens
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Re: [linux-sunxi] [PATCH 2/2] fel: add fel spl support for Allwinner A80
On Mon, 21 Mar 2016 14:24:15 +0100
Jens Kuske wrote:
> The A80 has the V bit in SCTLR set to 0 because of the BROM
> being at 0x now, so the SCTLR check has to be relaxed.
>
> Signed-off-by: Jens Kuske
Thanks!
> ---
> fel.c | 21 +++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/fel.c b/fel.c
> index ba58105..dedde55 100644
> --- a/fel.c
> +++ b/fel.c
> @@ -489,6 +489,16 @@ sram_swap_buffers a31_sram_swap_buffers[] = {
> { 0 } /* End of the table */
> };
>
> +/*
> + * A80 has 40KiB SRAM A1 at 0x1 where the SPL has to be loaded to. The
> + * secure SRAM B at 0x2 is used as backup area for FEL stacks and data.
> + */
> +sram_swap_buffers a80_sram_swap_buffers[] = {
> + { .buf1 = 0x11800, .buf2 = 0x2, .size = 0x800 },
> + { .buf1 = 0x15400, .buf2 = 0x20800, .size = 0x18000 - 0x15400 },
> + { 0 } /* End of the table */
> +};
> +
> soc_sram_info soc_sram_info_table[] = {
> {
> .soc_id = 0x1623, /* Allwinner A10 */
> @@ -541,6 +551,13 @@ soc_sram_info soc_sram_info_table[] = {
> .thunk_addr = 0x46E00, .thunk_size = 0x200,
> .swap_buffers = a31_sram_swap_buffers,
> },
> + {
> + .soc_id = 0x1639, /* Allwinner A80 */
> + .spl_addr = 0x1,
> + .scratch_addr = 0x12000,
We have a reason to use 0x11000 instead of 0x12000 here:
http://permalink.gmane.org/gmane.comp.hardware.netbook.arm.sunxi/21153
But I'll just add this change into my old patch and re-send an updated
version of it.
> + .thunk_addr = 0x23400, .thunk_size = 0x200,
> + .swap_buffers = a80_sram_swap_buffers,
> + },
> { 0 } /* End of the table */
> };
>
> @@ -792,9 +809,9 @@ uint32_t *aw_backup_and_disable_mmu(libusb_device_handle
> *usb,
>* checks needs to be relaxed).
>*/
>
> - /* Basically, ignore M/Z/I bits and expect no TEX remap */
> + /* Basically, ignore M/Z/I/V bits and expect no TEX remap */
> sctlr = aw_get_sctlr(usb, sram_info);
> - if ((sctlr & ~((1 << 12) | (1 << 11) | 1)) != 0x00C52078) {
> + if ((sctlr & ~((0x7 << 11) | 1)) != 0x00C50078) {
> fprintf(stderr, "Unexpected SCTLR (%08X)\n", sctlr);
> exit(1);
> }
Reviewed-by: Siarhei Siamashka
And pushed to github.
--
Best regards,
Siarhei Siamashka
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Re: [linux-sunxi][PATCH v2 1/5] clk: sunxi: mod1 clock should modify it's parent
On Mon, Mar 21, 2016 at 05:10:38PM +0100, codekip...@gmail.com wrote: > From: Andrea Venturi > > add CLK_SET_RATE_PARENT to modify the rate on clk upstream > > Signed-off-by: Marcus Cooper Applied, thanks Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: Digital signature
Re: [linux-sunxi] [PATCH 1/2] fel: only read MMU control registers if MMU is enabled
On Mon, 21 Mar 2016 14:24:14 +0100
Jens Kuske wrote:
> This workaround is necessary for A80, which sometimes
> fails at reading DACR.
>
> Signed-off-by: Jens Kuske
> ---
> fel.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/fel.c b/fel.c
> index a905ad5..ba58105 100644
> --- a/fel.c
> +++ b/fel.c
> @@ -767,10 +767,7 @@ uint32_t *aw_backup_and_disable_mmu(libusb_device_handle
> *usb,
> soc_sram_info *sram_info)
> {
> uint32_t *tt = NULL;
> - uint32_t ttbr0 = aw_get_ttbr0(usb, sram_info);
> - uint32_t sctlr = aw_get_sctlr(usb, sram_info);
> - uint32_t ttbcr = aw_get_ttbcr(usb, sram_info);
> - uint32_t dacr = aw_get_dacr(usb, sram_info);
> + uint32_t sctlr, ttbr0, ttbcr, dacr;
> uint32_t i;
>
> uint32_t arm_code[] = {
> @@ -796,6 +793,7 @@ uint32_t *aw_backup_and_disable_mmu(libusb_device_handle
> *usb,
>*/
>
> /* Basically, ignore M/Z/I bits and expect no TEX remap */
> + sctlr = aw_get_sctlr(usb, sram_info);
> if ((sctlr & ~((1 << 12) | (1 << 11) | 1)) != 0x00C52078) {
> fprintf(stderr, "Unexpected SCTLR (%08X)\n", sctlr);
> exit(1);
> @@ -806,16 +804,19 @@ uint32_t
> *aw_backup_and_disable_mmu(libusb_device_handle *usb,
> return NULL;
> }
>
> + dacr = aw_get_dacr(usb, sram_info);
> if (dacr != 0x) {
> fprintf(stderr, "Unexpected DACR (%08X)\n", dacr);
> exit(1);
> }
>
> + ttbcr = aw_get_ttbcr(usb, sram_info);
> if (ttbcr != 0x) {
> fprintf(stderr, "Unexpected TTBCR (%08X)\n", ttbcr);
> exit(1);
> }
>
> + ttbr0 = aw_get_ttbr0(usb, sram_info);
> if (ttbr0 & 0x3FFF) {
> fprintf(stderr, "Unexpected TTBR0 (%08X)\n", ttbr0);
> exit(1);
As we discussed on IRC earlier, having this patch is reasonable as
it workarounds A80 problems and makes FEL boot usable on it. So
Reviewed-by: Siarhei Siamashka
I have already pushed it to github, thanks!
Too bad that we still don't know what's going on. We can probably add a
comment to the Notes column in the SoC support status table and warn
the users, so that they watch out and report any possible
irregularities: https://linux-sunxi.org/FEL/USBBoot#SoC_support_status
Can you probably try to read the MIDR register to check if the A80
SoC initially boots on a Cortex A15 or a Cortex A7 core? If it is A7,
then something is really odd. But if it is A15, then aggressive
instructions reordering may be exposing a missing barrier instruction
here or there. There are also some configuration knobs in the A15 too,
which allow to partially enforce in-order behaviour:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABGHIBG.html
--
Best regards,
Siarhei Siamashka
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Re: [linux-sunxi][PATCH v2 4/5] ARM: dts: sun4i: Add SPDIF to the Mele A1000
On Mon, Mar 21, 2016 at 05:10:41PM +0100, codekip...@gmail.com wrote:
> From: Marcus Cooper
>
> Enable the S/PDIF transmitter that is present on the A1000.
>
> Signed-off-by: Marcus Cooper
> ---
> arch/arm/boot/dts/sun4i-a10-a1000.dts | 23 +++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts
> b/arch/arm/boot/dts/sun4i-a10-a1000.dts
> index 97570cb..aaf5605 100644
> --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
> @@ -87,6 +87,23 @@
> enable-active-high;
> gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>;
> };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "On-board SPDIF";
Please add a newline here.
> + simple-audio-card,cpu {
> + sound-dai = <&spdif>;
> + };
> +
> + simple-audio-card,codec {
> + sound-dai = <&spdif_out>;
> + };
> + };
> +
> + spdif_out: spdif-out {
> + #sound-dai-cells = <0>;
> + compatible = "linux,spdif-dit";
> + };
> };
>
> &ahci {
> @@ -188,6 +205,12 @@
> status = "okay";
> };
>
> +&spdif {
> + pinctrl-names = "default";
> + pinctrl-0 = <&spdif_tx_pins_a>;
> + status = "okay";
> +};
> +
> &uart0 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart0_pins_a>;
> --
> 2.7.4
>
Thanks!
Maxime
--
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http://free-electrons.com
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Re: [linux-sunxi][PATCH v2 2/5] ARM: dts :sunxi: Add SPDIF pins to A10 and A20
On Mon, Mar 21, 2016 at 05:10:39PM +0100, codekip...@gmail.com wrote:
> From: Marcus Cooper
>
> Add the SPDIF pins to the A10 and A20 dtsi.
>
> Signed-off-by: Marcus Cooper
> ---
> arch/arm/boot/dts/sun4i-a10.dtsi | 21 +
> arch/arm/boot/dts/sun7i-a20.dtsi | 21 +
> 2 files changed, 42 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi
> b/arch/arm/boot/dts/sun4i-a10.dtsi
> index 2c8f5e6..0483640 100644
> --- a/arch/arm/boot/dts/sun4i-a10.dtsi
> +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
> @@ -1006,6 +1006,27 @@
> allwinner,drive = ;
> allwinner,pull = ;
> };
> +
> + spdif_tx_pins_a: spdif@0 {
> + allwinner,pins = "PB13";
> + allwinner,function = "spdif";
> + allwinner,drive = ;
> + allwinner,pull = ;
> + };
> +
> + spdif_rx_pins_a: spdif@1 {
> + allwinner,pins = "PB12";
> + allwinner,function = "spdif";
> + allwinner,drive = ;
> + allwinner,pull = ;
> + };
> +
> + spdif_mclk_pins_a: spdif@2 {
> + allwinner,pins = "PB3";
> + allwinner,function = "spdif";
> + allwinner,drive = ;
> + allwinner,pull = ;
> + };
If you're not going to use these pins, please don't add them yet.
In order to avoid bloating the DT uselessly, we try to not add unused nodes.
Thanks!
Maxime
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Re: [linux-sunxi][PATCH v2 3/5] ARM: dts: sunxi: Add the SPDIF to the A10 and A20
On Mon, Mar 21, 2016 at 05:10:40PM +0100, codekip...@gmail.com wrote: > From: Marcus Cooper > > Add the SPDIF transceiver controller and clock to the A10 and > A20 dtsi. > > Signed-off-by: Marcus Cooper > > --- > arch/arm/boot/dts/sun4i-a10.dtsi | 24 > arch/arm/boot/dts/sun7i-a20.dtsi | 24 Sorry, I missed that earlier, but please make separate patches for those two DTS. It also applies for the other patches. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: Digital signature
Re: [linux-sunxi] Re: [PATCH v8 2/2] ASoc: sun4i-codec: Add FM, Line and Mic inputs
On Mon, Mar 21, 2016 at 07:06:05PM +0100, Maxime Ripard wrote: > I don't think you should focus too much on alsamixer, there's other > tools to modify the configuration. The expectation is that most users will use something like UCM and only system integrators will see the full control set in normal operation. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
Re: [linux-sunxi] Re: [PATCH v8 2/2] ASoc: sun4i-codec: Add FM, Line and Mic inputs
On Sat, Mar 19, 2016 at 05:51:24PM +0100, Danny Milosavljevic wrote: > Hi Maxime, > > > IIRC, in order to have shared controls, you just needed to share the > > controls structure. > > Yeah. I did this and it actually works in a way, but in doesn't do all that I > want. > > There are two different kinds of sharing I mean: > > The one kind with the controls structure causes the control to rename itself > to not state its mixer but there's still just one slider in the end. > So instead of "Left Mixer Left XXX" it will just say "Left XXX" if you put it > inside Left Mixer and Right Mixer and share the entry - for this hardware, > that's of doubtful use. > > But what I would like to have is that the same Mic Playback Volume (the very > same bits) be used for different sliders > (1) Mic1 Left Channel Playback Volume > (2) Mic1 Right Channel Playback Volume > (3) Mic2 Left Channel Playback Volume (!!) > (4) Mic2 Right Channel Playback Volume > > Additionally, Mic1 Playback and Mic2 Playback have two mutes each in the > hardware (all separately switchable). > > Now if we could make the alsamixer selems look like the following, > that would be nice: > > Mic1_Playback Mic2_Playback > > MM MM > ii ii > cc cc > > PP PP > ll ll > aa aa > yy yy > bb bb > aa aa > cc cc > kk kk > > VV VV > oo oo > ll ll > uu uu > mm mm > ee ee > > [Mm][Nn] >^ ^^-- so are those, separately >+-- this one is a different muter :-) > > Where the text is the same, it's supposed to signify the same bits > in the hardware. > > Right now in v8 it's (and that's going to take a lot of horizontal space, > sorry - I know E-Mails like this aren't so nice to read): > > Mic_Playback_Volume Left_Mic1_Playback_Switch Right_Mic1_Playback_Switch > Left_Mic2_Playback_Switch Right_Mic2_Playback_Switch > > MM > ii > cc > > PP > ll > aa > yy > bb > aa > cc > kk > > VV > oo > ll > uu > mm > ee > > [MM] [NN] [OO] > [PP] > ^- WTF ^- WTF ^- > WTF ^- WTF > > (Actually, it's worse - believe it or not, that's how the simplified > explanation looks) I don't think you should focus too much on alsamixer, there's other tools to modify the configuration. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: Digital signature
Re: [linux-sunxi] Re: [PATCH v8 2/2] ASoc: sun4i-codec: Add FM, Line and Mic inputs
On Sat, Mar 19, 2016 at 05:13:36PM +0100, Danny Milosavljevic wrote: > Hi Mark, > > my question is whether it's possible to group together the left and > right channel into one selem, and also if it's possible to reuse > volumes then. For example: > > For sun4i-codec Mic there's right now: > - Left Mixer Mic1 Playback Switch > - Left Mixer Mic2 Playback Switch > - Right Mixer Mic1 Playback Switch > - Right Mixer Mic2 Playback Switch > - Mic Playback Volume > > If possible, it could also then be collected together as: > - Mic1 Playback: > Left Mixer Mic1 Playback Switch, > Right Mixer Mic1 Playback Switch, > Mic Playback Volume > - Mic2 Playback: > Left Mixer Mic2 Playback Switch, > Right Mixer Mic2 Playback Switch, > Mic Playback Volume [note: there it is again] > > ... where each outer group (f.e. "- Mic1 Playback:") is a selem > (slider with two mutes in alsamixer). > > alsamixer has support for seperate left and right channel muting so > it would cut down a lot on the number of visible controls. > > But as you can see, Mic Playback Volume is also shared. > > Is it possible to group them together like this? How? > > Right now, while everything technically works, it's overwhelming to > use alsamixer with sun4i-codec as a user - you have to *scroll* for > quite a while. > > Additionally, while I'm at it: > > There's one capture volume right in front of the ADC. Whatever it is > you capture, this tells you the gain for the ADC. But for some > inputs, there are additional preamps. Right now in the v8 patch we > don't distinguish between preamps and ADC gains (because I don't > think it's possible), although the user has to kinda distinguish > them in his head because for inputs which have preamps only the > preamp and the adc gain *together* specify the total gain in the > end. > > E.g. in the hardware it's > > Mic In -> | Mic Preamp | -> | ADC Gain | -> | ADC | > > while in alsamixer it's: > > [Capture Controls:] > > | Mic Preamp | | Capture Volume | | xyz Preamp | | abc Preamp | | qrs > Preamp | > ^--- ADC Gain > > Is it possible to somehow distinguish those in alsamixer? Do we want > to? As I recall it, we were mostly discussing the how to deal with the ADC muxer that muxes both left and right at the same time (so shared controls), but with different source on each channel. For example, some valid values are: 4: left channel Mic 1, right channel mic 2 5: left and right channel are Mic1 and Mic2 mixed As I understand it, you can have shared controls by sharing the kcontrols structure, but then, you can't different labels. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: Digital signature
[linux-sunxi][PATCH v2 5/5] ARM: dts: sun7i: Add SPDIF to Itead Ibox
From: Marcus Cooper
Enable the S/PDIF transmitter that is present on the Itead Ibox.
Signed-off-by: Marcus Cooper
---
arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
index a512581..df76b74 100644
--- a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
+++ b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
@@ -65,6 +65,23 @@
default-state = "on";
};
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "On-board SPDIF";
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ };
};
&ahci {
@@ -131,6 +148,13 @@
status = "okay";
};
+
+&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx_pins_a>;
+ status = "okay";
+};
+
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
--
2.7.4
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[linux-sunxi][PATCH v2 4/5] ARM: dts: sun4i: Add SPDIF to the Mele A1000
From: Marcus Cooper
Enable the S/PDIF transmitter that is present on the A1000.
Signed-off-by: Marcus Cooper
---
arch/arm/boot/dts/sun4i-a10-a1000.dts | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts
b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index 97570cb..aaf5605 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -87,6 +87,23 @@
enable-active-high;
gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>;
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "On-board SPDIF";
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ };
};
&ahci {
@@ -188,6 +205,12 @@
status = "okay";
};
+&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx_pins_a>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
--
2.7.4
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[linux-sunxi][PATCH v2 1/5] clk: sunxi: mod1 clock should modify it's parent
From: Andrea Venturi add CLK_SET_RATE_PARENT to modify the rate on clk upstream Signed-off-by: Marcus Cooper --- drivers/clk/sunxi/clk-a10-mod1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi/clk-a10-mod1.c b/drivers/clk/sunxi/clk-a10-mod1.c index e9d870d..e2819fa 100644 --- a/drivers/clk/sunxi/clk-a10-mod1.c +++ b/drivers/clk/sunxi/clk-a10-mod1.c @@ -62,7 +62,7 @@ static void __init sun4i_mod1_clk_setup(struct device_node *node) clk = clk_register_composite(NULL, clk_name, parents, i, &mux->hw, &clk_mux_ops, NULL, NULL, -&gate->hw, &clk_gate_ops, 0); +&gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT); if (IS_ERR(clk)) goto err_free_gate; -- 2.7.4 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi][PATCH v2 3/5] ARM: dts: sunxi: Add the SPDIF to the A10 and A20
From: Marcus Cooper
Add the SPDIF transceiver controller and clock to the A10 and
A20 dtsi.
Signed-off-by: Marcus Cooper
---
arch/arm/boot/dts/sun4i-a10.dtsi | 24
arch/arm/boot/dts/sun7i-a20.dtsi | 24
2 files changed, 48 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 0483640..be5f2b2 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -477,6 +477,17 @@
clock-output-names = "ir1";
};
+ spdif_clk: clk@01c200c0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod1-clk";
+ reg = <0x01c200c0 0x4>;
+ clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+<&pll2 SUN4I_A10_PLL2_4X>,
+<&pll2 SUN4I_A10_PLL2_2X>,
+<&pll2 SUN4I_A10_PLL2_1X>;
+ clock-output-names = "spdif";
+ };
+
usb_clk: clk@01c200cc {
#clock-cells = <1>;
#reset-cells = <1>;
@@ -1055,6 +1066,19 @@
status = "disabled";
};
+ spdif: spdif@01c21000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun4i-a10-spdif";
+ reg = <0x01c21000 0x400>;
+ interrupts = <13>;
+ clocks = <&apb0_gates 1>, <&spdif_clk>;
+ clock-names = "apb", "spdif";
+ dmas = <&dma SUN4I_DMA_NORMAL 2>,
+ <&dma SUN4I_DMA_NORMAL 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
ir0: ir@01c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <&apb0_gates 6>, <&ir0_clk>;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 7264d5e..ebce332 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -476,6 +476,17 @@
clock-output-names = "ir1";
};
+ spdif_clk: clk@01c200c0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod1-clk";
+ reg = <0x01c200c0 0x4>;
+ clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+<&pll2 SUN4I_A10_PLL2_4X>,
+<&pll2 SUN4I_A10_PLL2_2X>,
+<&pll2 SUN4I_A10_PLL2_1X>;
+ clock-output-names = "spdif";
+ };
+
keypad_clk: clk@01c200c4 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
@@ -1247,6 +1258,19 @@
status = "disabled";
};
+ spdif: spdif@01c21000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun4i-a10-spdif";
+ reg = <0x01c21000 0x400>;
+ interrupts = ;
+ clocks = <&apb0_gates 1>, <&spdif_clk>;
+ clock-names = "apb", "spdif";
+ dmas = <&dma SUN4I_DMA_NORMAL 2>,
+ <&dma SUN4I_DMA_NORMAL 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
ir0: ir@01c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <&apb0_gates 6>, <&ir0_clk>;
--
2.7.4
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[linux-sunxi][PATCH v2 2/5] ARM: dts :sunxi: Add SPDIF pins to A10 and A20
From: Marcus Cooper
Add the SPDIF pins to the A10 and A20 dtsi.
Signed-off-by: Marcus Cooper
---
arch/arm/boot/dts/sun4i-a10.dtsi | 21 +
arch/arm/boot/dts/sun7i-a20.dtsi | 21 +
2 files changed, 42 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 2c8f5e6..0483640 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -1006,6 +1006,27 @@
allwinner,drive = ;
allwinner,pull = ;
};
+
+ spdif_tx_pins_a: spdif@0 {
+ allwinner,pins = "PB13";
+ allwinner,function = "spdif";
+ allwinner,drive = ;
+ allwinner,pull = ;
+ };
+
+ spdif_rx_pins_a: spdif@1 {
+ allwinner,pins = "PB12";
+ allwinner,function = "spdif";
+ allwinner,drive = ;
+ allwinner,pull = ;
+ };
+
+ spdif_mclk_pins_a: spdif@2 {
+ allwinner,pins = "PB3";
+ allwinner,function = "spdif";
+ allwinner,drive = ;
+ allwinner,pull = ;
+ };
};
timer@01c20c00 {
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 0940a78..7264d5e 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -1193,6 +1193,27 @@
allwinner,drive = ;
allwinner,pull = ;
};
+
+ spdif_tx_pins_a: spdif@0 {
+ allwinner,pins = "PB13";
+ allwinner,function = "spdif";
+ allwinner,drive = ;
+ allwinner,pull = ;
+ };
+
+ spdif_rx_pins_a: spdif@1 {
+ allwinner,pins = "PB12";
+ allwinner,function = "spdif";
+ allwinner,drive = ;
+ allwinner,pull = ;
+ };
+
+ spdif_mclk_pins_a: spdif@2 {
+ allwinner,pins = "PB3";
+ allwinner,function = "spdif";
+ allwinner,drive = ;
+ allwinner,pull = ;
+ };
};
timer@01c20c00 {
--
2.7.4
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[linux-sunxi][PATCH v2 0/5] ARM: sunxi: Add SPDIF playback support
From: Marcus Cooper Hi All, now that the sun4i-spdif driver has made it into linux-next then this patch series completes what is needed to have SPDIF working on both A10 and A20 devices. Enjoy, CK --- Changes since v1: - Added defines to the dma properties and changed reg length to cover the entire spdif memory area. Andrea Venturi (1): clk: sunxi: mod1 clock should modify it's parent Marcus Cooper (4): ARM: dts :sunxi: Add SPDIF pins to A10 and A20 ARM: dts: sunxi: Add the SPDIF to the A10 and A20 ARM: dts: sun4i: Add SPDIF to the Mele A1000 ARM: dts: sun7i: Add SPDIF to Itead Ibox arch/arm/boot/dts/sun4i-a10-a1000.dts | 23 +++ arch/arm/boot/dts/sun4i-a10.dtsi | 45 ++ arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 24 arch/arm/boot/dts/sun7i-a20.dtsi | 45 ++ drivers/clk/sunxi/clk-a10-mod1.c | 2 +- 5 files changed, 138 insertions(+), 1 deletion(-) -- 2.7.4 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH 4/7] scatterlist: add sg_alloc_table_from_buf() helper
On Tue, 8 Mar 2016 12:15:12 +0100
Boris Brezillon wrote:
> sg_alloc_table_from_buf() provides an easy solution to create an sg_table
> from a virtual address pointer. This function takes care of dealing with
> vmallocated buffers, buffer alignment, or DMA engine limitations (maximum
> DMA transfer size).
>
> Signed-off-by: Boris Brezillon
> ---
> include/linux/scatterlist.h | 24
> lib/scatterlist.c | 142
>
> 2 files changed, 166 insertions(+)
>
> diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h
> index 556ec1e..4a75362 100644
> --- a/include/linux/scatterlist.h
> +++ b/include/linux/scatterlist.h
> @@ -41,6 +41,27 @@ struct sg_table {
> unsigned int orig_nents;/* original size of list */
> };
>
> +/**
> + * struct sg_constraints - SG constraints structure
> + *
> + * @max_chunk_len: maximum chunk buffer length. Each SG entry has to be
> smaller
> + * than this value. Zero means no constraint.
> + * @required_alignment: minimum alignment. Is used for both size and pointer
> + * alignment. If this constraint is not met, the function
> + * should return -EINVAL.
> + * @preferred_alignment: preferred alignment. Mainly used to optimize
> + *throughput when the DMA engine performs better when
> + *doing aligned accesses.
> + *
> + * This structure is here to help sg_alloc_table_from_buf() create the
> optimal
> + * SG list based on DMA engine constraints.
> + */
> +struct sg_constraints {
> + size_t max_chunk_len;
> + size_t required_alignment;
> + size_t preferred_alignment;
> +};
> +
Hm, we seem to have another case in NAND controller drivers. Some
drivers do not support scattergather accesses and have to provide a
single physically contiguous memory region to transfer the whole
NAND page.
Could we add a ->max_entries field to the sg_contraints struct to allow
those drivers to use the generic mtd_map_buf() function, and fallback
to a bounce buffer approach (or PIO access approach) when
sg_alloc_table_from_buf() fails to fulfill this constraint.
We could also define another 'non-sg' function to do the 'physically
contiguous' check, but in any case, I'd like to avoid letting each
driver code its own checking function.
What do you think?
> /*
> * Notes on SG table design.
> *
> @@ -265,6 +286,9 @@ int sg_alloc_table_from_pages(struct sg_table *sgt,
> struct page **pages, unsigned int n_pages,
> unsigned long offset, unsigned long size,
> gfp_t gfp_mask);
> +int sg_alloc_table_from_buf(struct sg_table *sgt, const void *buf, size_t
> len,
> + const struct sg_constraints *constraints,
> + gfp_t gfp_mask);
>
> size_t sg_copy_buffer(struct scatterlist *sgl, unsigned int nents, void *buf,
> size_t buflen, off_t skip, bool to_buffer);
> diff --git a/lib/scatterlist.c b/lib/scatterlist.c
> index bafa993..706b583 100644
> --- a/lib/scatterlist.c
> +++ b/lib/scatterlist.c
> @@ -433,6 +433,148 @@ int sg_alloc_table_from_pages(struct sg_table *sgt,
> }
> EXPORT_SYMBOL(sg_alloc_table_from_pages);
>
> +static size_t sg_buf_chunk_len(const void *buf, size_t len,
> +const struct sg_constraints *cons)
> +{
> + size_t chunk_len = len;
> +
> + if (cons->max_chunk_len)
> + chunk_len = min_t(size_t, chunk_len, cons->max_chunk_len);
> +
> + if (is_vmalloc_addr(buf))
> + chunk_len = min_t(size_t, chunk_len,
> + PAGE_SIZE - offset_in_page(buf));
> +
> + if (!IS_ALIGNED((unsigned long)buf, cons->preferred_alignment)) {
> + const void *aligned_buf = PTR_ALIGN(buf,
> + cons->preferred_alignment);
> + size_t unaligned_len = (unsigned long)(aligned_buf - buf);
> +
> + chunk_len = min_t(size_t, chunk_len, unaligned_len);
> + } else if (chunk_len > cons->preferred_alignment) {
> + chunk_len &= ~(cons->preferred_alignment - 1);
> + }
> +
> + return chunk_len;
> +}
> +
> +#define sg_for_each_chunk_in_buf(buf, len, chunk_len, constraints) \
> + for (chunk_len = sg_buf_chunk_len(buf, len, constraints); \
> + len; \
> + len -= chunk_len, buf += chunk_len,\
> + chunk_len = sg_buf_chunk_len(buf, len, constraints))
> +
> +static int sg_check_constraints(struct sg_constraints *cons,
> + const void *buf, size_t len)
> +{
> + if (!cons->required_alignment)
> + cons->required_alignment = 1;
> +
> + if (!cons->preferred_alignment)
> + cons->preferred_alignment = cons->required_alignment;
> +
> + /* Test if buf and len are properly aligned. */
> + if (!IS_ALI
Re: [linux-sunxi] Re: [PATCH v8 2/2] ASoc: sun4i-codec: Add FM, Line and Mic inputs
On Sat, Mar 19, 2016 at 05:13:36PM +0100, Danny Milosavljevic wrote: > Hi Mark, > my question is whether it's possible to group together the left and right > channel into one selem, and also if it's possible to reuse volumes then. For > example: Please fix your mail client to word wrap within paragraphs at something substantially less than 80 columns. Doing this makes your messages much easier to read and reply to. This is particularly important for large walls of text like this. > Is it possible to group them together like this? How? This is something you'd need to change in alsamixer and the control naming standards. None of this stuff is really supposed to be directly edited by normal users, they should mostly be using a UCM configuration, so at the minute this is essentially bikeshedding. > Is it possible to somehow distinguish those in alsamixer? Do we want to? I think you're looking for something that exports routing to userspace. Doing that would also help with reducing the faff with naming rules. Currently nobody is working on that but I think people would be very happy if someone were to work on it. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] [PATCH 1/2] fel: only read MMU control registers if MMU is enabled
This workaround is necessary for A80, which sometimes
fails at reading DACR.
Signed-off-by: Jens Kuske
---
fel.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/fel.c b/fel.c
index a905ad5..ba58105 100644
--- a/fel.c
+++ b/fel.c
@@ -767,10 +767,7 @@ uint32_t *aw_backup_and_disable_mmu(libusb_device_handle
*usb,
soc_sram_info *sram_info)
{
uint32_t *tt = NULL;
- uint32_t ttbr0 = aw_get_ttbr0(usb, sram_info);
- uint32_t sctlr = aw_get_sctlr(usb, sram_info);
- uint32_t ttbcr = aw_get_ttbcr(usb, sram_info);
- uint32_t dacr = aw_get_dacr(usb, sram_info);
+ uint32_t sctlr, ttbr0, ttbcr, dacr;
uint32_t i;
uint32_t arm_code[] = {
@@ -796,6 +793,7 @@ uint32_t *aw_backup_and_disable_mmu(libusb_device_handle
*usb,
*/
/* Basically, ignore M/Z/I bits and expect no TEX remap */
+ sctlr = aw_get_sctlr(usb, sram_info);
if ((sctlr & ~((1 << 12) | (1 << 11) | 1)) != 0x00C52078) {
fprintf(stderr, "Unexpected SCTLR (%08X)\n", sctlr);
exit(1);
@@ -806,16 +804,19 @@ uint32_t *aw_backup_and_disable_mmu(libusb_device_handle
*usb,
return NULL;
}
+ dacr = aw_get_dacr(usb, sram_info);
if (dacr != 0x) {
fprintf(stderr, "Unexpected DACR (%08X)\n", dacr);
exit(1);
}
+ ttbcr = aw_get_ttbcr(usb, sram_info);
if (ttbcr != 0x) {
fprintf(stderr, "Unexpected TTBCR (%08X)\n", ttbcr);
exit(1);
}
+ ttbr0 = aw_get_ttbr0(usb, sram_info);
if (ttbr0 & 0x3FFF) {
fprintf(stderr, "Unexpected TTBR0 (%08X)\n", ttbr0);
exit(1);
--
2.7.4
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[linux-sunxi] [PATCH 2/2] fel: add fel spl support for Allwinner A80
The A80 has the V bit in SCTLR set to 0 because of the BROM
being at 0x now, so the SCTLR check has to be relaxed.
Signed-off-by: Jens Kuske
---
fel.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/fel.c b/fel.c
index ba58105..dedde55 100644
--- a/fel.c
+++ b/fel.c
@@ -489,6 +489,16 @@ sram_swap_buffers a31_sram_swap_buffers[] = {
{ 0 } /* End of the table */
};
+/*
+ * A80 has 40KiB SRAM A1 at 0x1 where the SPL has to be loaded to. The
+ * secure SRAM B at 0x2 is used as backup area for FEL stacks and data.
+ */
+sram_swap_buffers a80_sram_swap_buffers[] = {
+ { .buf1 = 0x11800, .buf2 = 0x2, .size = 0x800 },
+ { .buf1 = 0x15400, .buf2 = 0x20800, .size = 0x18000 - 0x15400 },
+ { 0 } /* End of the table */
+};
+
soc_sram_info soc_sram_info_table[] = {
{
.soc_id = 0x1623, /* Allwinner A10 */
@@ -541,6 +551,13 @@ soc_sram_info soc_sram_info_table[] = {
.thunk_addr = 0x46E00, .thunk_size = 0x200,
.swap_buffers = a31_sram_swap_buffers,
},
+ {
+ .soc_id = 0x1639, /* Allwinner A80 */
+ .spl_addr = 0x1,
+ .scratch_addr = 0x12000,
+ .thunk_addr = 0x23400, .thunk_size = 0x200,
+ .swap_buffers = a80_sram_swap_buffers,
+ },
{ 0 } /* End of the table */
};
@@ -792,9 +809,9 @@ uint32_t *aw_backup_and_disable_mmu(libusb_device_handle
*usb,
* checks needs to be relaxed).
*/
- /* Basically, ignore M/Z/I bits and expect no TEX remap */
+ /* Basically, ignore M/Z/I/V bits and expect no TEX remap */
sctlr = aw_get_sctlr(usb, sram_info);
- if ((sctlr & ~((1 << 12) | (1 << 11) | 1)) != 0x00C52078) {
+ if ((sctlr & ~((0x7 << 11) | 1)) != 0x00C50078) {
fprintf(stderr, "Unexpected SCTLR (%08X)\n", sctlr);
exit(1);
}
--
2.7.4
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Re: [linux-sunxi] About A83T/H3 EMAC Driver Separation
Hi, On 21-03-16 12:49, Chen-Yu Tsai wrote: Hi, I've been looking at the new EMAC driver and help cleaning up the platform related (probe/remove/DT) bits. The new hardware has the same glue layer like we had with earlier SoCs with the GMAC. So for the A83T we could just re-use the clock driver for that bit. With the H3's internal PHY things get complicated. The controls for the PHY are mapped to the upper bits of the same register. Should we just map the whole register in the EMAC driver, and not use the clock driver in this case? (Maybe the clock approach for the GMAC was bad?) Or try to share the register with a regmap or syscon? The latter has its own difficulties in the kernel. Or maybe a generic PHY driver that also exports the clock? Either way I think we'll end up with more than 1 way to deal with the GMAC/EMAC clock settings. Any suggestions? I think that a phy driver which also registers a clock is probably the best solution. Note that the orangepi plus has an external gbit mac connected to the H3, let me know if you want me to run some tests on that one. Regards, Hans -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: [PATCH v7] ARM: dts: sun8i: Add leds and switches on Orangepi Plus boards
Hi,
On 21-03-16 08:59, Maxime Ripard wrote:
Hi,
On Sun, Mar 20, 2016 at 07:55:02PM +0100, Hans de Goede wrote:
From: Krzysztof Adamski
OrangePi Plus board has two leds - green ("pwr") and red ("status")
and two switches ("sw4" and "sw2"). This patch describes them in
devicetree.
Signed-off-by: Krzysztof Adamski
Signed-off-by: Hans de Goede
An earlier version has already been sent for 4.6, please base your
changes on top of this one.
Ah, I missed that one because it is not in your for-next branch!
It is only in sunxi-dt-for-4.6.
And there's a bunch of things I didn't catch at that time :/
I'll cherry-pick the patch you've in sunxi-dt-for-4.6 into
my tree and send a fixup patch to apply on top.
Regards,
Hans
---
Changes in v6 (hdegoede):
-Merge leds and r_leds nodes into one
-Fix led labels to be in :: form
-Alphabetically sort the added nodes
-Add support for sw2 (this is the small reset-like button)
Changes in v7 (hdegoede):
-Use PL3 / PL4 in the pinctrl node, not PL03 / PL04
---
arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 63
1 file changed, 63 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
index a680b1f..9d8c038 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
@@ -45,6 +45,7 @@
#include "sunxi-common-regulators.dtsi"
#include
+#include
#include
/ {
@@ -59,6 +60,43 @@
stdout-path = "serial0:115200n8";
};
+ gpio_keys {
+ compatible = "gpio-keys";
+ input-name = "sw4";
This is an undocumented (and apparently unused) property
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_r_opc>;
+
+ sw2@0 {
You shouldn't have a unit-address here
+ label = "sw2";
+ linux,code = ;
+ gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>;
+ };
+
+ sw4@0 {
Ditto.
Thanks!
Maxime
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[linux-sunxi] Re: [PATCH 2/4] mfd: axp20x: Add AXP209 GPIO driver to the mfd
On Wed, 09 Mar 2016, Maxime Ripard wrote:
> Now that we have a GPIO driver for the AXP209, we can add it to our MFD.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/mfd/axp20x.c | 3 +++
> 1 file changed, 3 insertions(+)
Applied, thanks.
> diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
> index a57d6e940610..89518ee3be33 100644
> --- a/drivers/mfd/axp20x.c
> +++ b/drivers/mfd/axp20x.c
> @@ -430,6 +430,9 @@ static const struct regmap_irq_chip
> axp288_regmap_irq_chip = {
>
> static struct mfd_cell axp20x_cells[] = {
> {
> + .name = "axp20x-gpio",
> + .of_compatible = "x-powers,axp209-gpio",
> + }, {
> .name = "axp20x-pek",
> .num_resources = ARRAY_SIZE(axp20x_pek_resources),
> .resources = axp20x_pek_resources,
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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[linux-sunxi] About A83T/H3 EMAC Driver Separation
Hi, I've been looking at the new EMAC driver and help cleaning up the platform related (probe/remove/DT) bits. The new hardware has the same glue layer like we had with earlier SoCs with the GMAC. So for the A83T we could just re-use the clock driver for that bit. With the H3's internal PHY things get complicated. The controls for the PHY are mapped to the upper bits of the same register. Should we just map the whole register in the EMAC driver, and not use the clock driver in this case? (Maybe the clock approach for the GMAC was bad?) Or try to share the register with a regmap or syscon? The latter has its own difficulties in the kernel. Or maybe a generic PHY driver that also exports the clock? Either way I think we'll end up with more than 1 way to deal with the GMAC/EMAC clock settings. Any suggestions? Regards ChenYu -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH sunxi-tools 6/7] fel: Add "readl" and "writel" commands
On Sun, 20 Mar 2016 16:09:40 +0100 Bernhard Nortmann wrote: > Hi Siarhei! > > Am 20.03.2016 um 15:49 schrieb Siarhei Siamashka: > > This patch is just unsafe if pushed alone, that's why it implicitly > > depends on the other "fel: Move the temporary scratch buffer under the > > IRQ stack" patch. > > I see. My impression was that while "unclean" on its own, it's still > functional - at least to a degree where stuff like "sunxi-fel sid" might > actually allow device identification before doing more complicated stuff > (in a second sunxi-fel invocation). But of course it's preferable to > properly resolve the dependenices first. It is functional as long as you are fine with corrupting memory at 0x2000 as a side effect. This address 0x2000 is special because it is the usual location where sunxi-fel users are supposed to upload their code for execution, as instructed by many existing examples and tutorials. Consider the following shell code: if [ "`sunxi-fel ver | grep \(A10\)`" ] ; then sunxi-fel write 0x2000 some_code_for_a10_soc if [ "`sunxi-fel sid | grep 16236747-80728452-50574848-064163D5`" ] ; then sunxi-fel exe 0x2000 else echo "Oh, wrong device, nevermind" fi else echo "Oh, wrong SoC type, nevermind" fi > > And instead of cluttering the documentation with the "Use these commands > > with caution!" warnings (which many people will miss or ignore anyway), > > it's better to do a proper job in the first place. > > It would simply give us something to point users to, if they try antics > like "./sunxi-fel readl 0x" and come back complaining "That > always fails with: libusb usb_bulk_send error -7". (Just like you) I > suspect people will do this anyway, no matter where / how we put up > warning signs in the first place... :-P The user may run into a trouble by using the documented functionality in a wrong way. But this is relatively easy to debug and makes the user learn his lesson pretty fast. But running into a trouble because of an undocumented (or poorly documented) side effect is entirely different. Such problems are usually much harder to debug. Check the https://en.wikipedia.org/wiki/Principle_of_least_astonishment Corrupting memory at 0x2000 clearly violates this principle, even if we bother to document this behaviour somewhere. Still I don't understand why we are even discussing this. A simple patch to address this issue already exists. -- Best regards, Siarhei Siamashka -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: Latest U-boot branch not booting on Hummingbird A31
Hi,
On Mon, Mar 21, 2016 at 6:18 PM, Hans de Goede wrote:
> Hi,
>
>
> On 21-03-16 11:06, Chen-Yu Tsai wrote:
>>
>> Hi,
>>
>> On Mon, Mar 21, 2016 at 5:57 PM, Hans de Goede
>> wrote:
>>>
>>> HI,
>>>
>>>
>>> On 21-03-16 10:49, wens Tsai wrote:
Hi Hans,
I updated U-boot on my boards to your latest sunxi-wip branch:
f965340 ("sunxi: Enable support for the eMMC found on the orangepi
plus")
My Hummingbird A31 fails to boot after this. See log:
HELLO! BOOT0 is starting!
boot0 version : 3.0.0
reg_addr 0x01f00100 =0x
reg_addr 0x01f00104 =0x
reg_addr 0x01f00108 =0x
reg_addr 0x01f0010c =0x
reg_addr 0x01f00110 =0x
reg_addr 0x01f00114 =0x
[DRAM]ver 1.03 clk = 312
cpu 0 pmu 0
dram size =1024
sum=0x31776fa8
src_sum=0x31776fa8
Ready to disable icache.
Jump to secend Boot.
[ 0.209]
U-Boot 2011.09-rc1 (Jun 17 2014 - 17:30:56) Allwinner Technology
[ 0.217]version: 1.1.0
[ 0.220]pmbus: ready
[ 0.222]PMU: AXP221
[ 0.225]PMU: AXP22x found
[ 0.227]PMU: bat ratio = 100
[ 0.231]PMU: dcdc3 1260
[ 0.233]PMU: pll1 1008 Mhz
dcdc1_vol = 3000
dcdc2_vol = 1200
dcdc3_vol = 1260
dcdc4_vol = 1200
dcdc5_vol = 1500
aldo1_vol = 3000
aldo2_vol = 1800
aldo3_vol = 3000
eldo3_vol = 1800
find power_sply to end
fel key old mode
run key detect
no key found
no key input
dram_para_set start
dram_para_set end
[ 0.277]DRAM: 1 GiB
relocation Offset is: 15b25000
donn't initialize ther user_gpio (main_key:boot_init_gpio)
deu_mode1 not exist.
lcdgamma4iep for lcd1 not exist.
DRV_DISP_Init: opened
[ 0.542]fetch script data boot_disp.output_type fail
[ 0.547]fetch script data boot_disp.output_mode fail
[ 0.552]fetch script data boot_disp.auto_hpd fail
[ 0.557]lcd0_para.lcd_used=1
workmode = 0
[ 0.603]NAND: NAND_UbootInit
NB1 : enter NAND_LogicInit
not burn nand partition table!
NB1 : nftl num: 2
init nftl: 0
NB1 : NAND_LogicInit ok, result = 0x0
[ 1.268]sunxi flash init ok
probe mmc0 if exist
SUNXI SD/MMC: 0
Man 1d4144 Snr d3602657
SD
0.2
boot0 capacity: 0KB,boot1 capacity: 0KB
boot0 magic = eGON.BT0蜡讕
set next system status
DRV_DISP_Exit: closed
sunxi_board_close_source
NAND_UbootExit
NB1 : NAND_LogicExit
reset cpu
HELLO! BOOT0 is starting!
boot0 version : 3.0.0
reg_addr 0x01f00100 =0x7347
reg_addr 0x01f00104 =0x703b
reg_addr 0x01f00108 =0x5aa5a55a
reg_addr 0x01f0010c =0x00ff
reg_addr 0x01f00110 =0x00ff
reg_addr 0x01f00114 =0x00ff
eraly jump fel
U-Boot SPL 2016.03-00320-geeea041 (Mar 21 2016 - 15:16:34)
DRAM: 1024 MiB
Trying to boot from MMC1
and hangs...
geeea041 is the SinA31s patch I have on top of your sunxi-wip branch.
I bisected it down to 107fb76 ("sunxi: Fix gmac not working due to
cpu_eth_init no longer being called"). Not sure why this commit fails
though.
>>>
>>>
>>>
>>> Hmm, can you try commenting out these 2 lines in
>>> arch/arm/cpu/armv7/sunxi/board.c :
>>>
>>> #ifdef CONFIG_MACPWR
>>> gpio_request(CONFIG_MACPWR, "macpwr");
>>> gpio_direction_output(CONFIG_MACPWR, 1);
>>> #endif
>>>
>>> Around line 103 ? That is the only bit which has changed in
>>> the SPL path due to this patch.
>>
>>
>> This fixes the problem. Thanks.
>>
>> I'm guessing it's a bad idea to call the generic GPIO
>> functions, which are DM based, in SPL?
>
>
> When building the SPL CONFIG_DM_GPIO is not set, and there
> are non DM implementations for the SPL in drivers/gpio/sunxi_gpio.c
>
> So the functions should work, and the fact that you get to
>
> "Trying to boot from MMC1"
>
> Shows that at least the SPL does not crash at this code, because
> that is done way earlier (before the first message is printed
> on the serial console, the same function also sets up the uart
> muxing).
>
> So I do not believe that the problem is actually calling the
> gpio_request() (nop in non DM mode) nor gpio_direction_output()
> in general.
>
> Which would lead to the conclusion that the problem is the
> changing of the gpio pin value before u-boot proper has loaded,
> which is a bit weird.
>
> Note that commenting out these lines will likely lead to a non
> working ethernet on the board. If it does not then you do not
> need CONFIG_MACPWR and it could be that you're driving some
> $random pin high causing issues.
Ethernet works with these 2 lines commented. The schematics show
an external pull-up on the PHY reset pin, so this GPIO is only
used to reset the PHY by driving it low. Driving it high sho
Re: [linux-sunxi] Re: Latest U-boot branch not booting on Hummingbird A31
Hi,
On 21-03-16 11:06, Chen-Yu Tsai wrote:
Hi,
On Mon, Mar 21, 2016 at 5:57 PM, Hans de Goede wrote:
HI,
On 21-03-16 10:49, wens Tsai wrote:
Hi Hans,
I updated U-boot on my boards to your latest sunxi-wip branch:
f965340 ("sunxi: Enable support for the eMMC found on the orangepi
plus")
My Hummingbird A31 fails to boot after this. See log:
HELLO! BOOT0 is starting!
boot0 version : 3.0.0
reg_addr 0x01f00100 =0x
reg_addr 0x01f00104 =0x
reg_addr 0x01f00108 =0x
reg_addr 0x01f0010c =0x
reg_addr 0x01f00110 =0x
reg_addr 0x01f00114 =0x
[DRAM]ver 1.03 clk = 312
cpu 0 pmu 0
dram size =1024
sum=0x31776fa8
src_sum=0x31776fa8
Ready to disable icache.
Jump to secend Boot.
[ 0.209]
U-Boot 2011.09-rc1 (Jun 17 2014 - 17:30:56) Allwinner Technology
[ 0.217]version: 1.1.0
[ 0.220]pmbus: ready
[ 0.222]PMU: AXP221
[ 0.225]PMU: AXP22x found
[ 0.227]PMU: bat ratio = 100
[ 0.231]PMU: dcdc3 1260
[ 0.233]PMU: pll1 1008 Mhz
dcdc1_vol = 3000
dcdc2_vol = 1200
dcdc3_vol = 1260
dcdc4_vol = 1200
dcdc5_vol = 1500
aldo1_vol = 3000
aldo2_vol = 1800
aldo3_vol = 3000
eldo3_vol = 1800
find power_sply to end
fel key old mode
run key detect
no key found
no key input
dram_para_set start
dram_para_set end
[ 0.277]DRAM: 1 GiB
relocation Offset is: 15b25000
donn't initialize ther user_gpio (main_key:boot_init_gpio)
deu_mode1 not exist.
lcdgamma4iep for lcd1 not exist.
DRV_DISP_Init: opened
[ 0.542]fetch script data boot_disp.output_type fail
[ 0.547]fetch script data boot_disp.output_mode fail
[ 0.552]fetch script data boot_disp.auto_hpd fail
[ 0.557]lcd0_para.lcd_used=1
workmode = 0
[ 0.603]NAND: NAND_UbootInit
NB1 : enter NAND_LogicInit
not burn nand partition table!
NB1 : nftl num: 2
init nftl: 0
NB1 : NAND_LogicInit ok, result = 0x0
[ 1.268]sunxi flash init ok
probe mmc0 if exist
SUNXI SD/MMC: 0
Man 1d4144 Snr d3602657
SD
0.2
boot0 capacity: 0KB,boot1 capacity: 0KB
boot0 magic = eGON.BT0蜡讕
set next system status
DRV_DISP_Exit: closed
sunxi_board_close_source
NAND_UbootExit
NB1 : NAND_LogicExit
reset cpu
HELLO! BOOT0 is starting!
boot0 version : 3.0.0
reg_addr 0x01f00100 =0x7347
reg_addr 0x01f00104 =0x703b
reg_addr 0x01f00108 =0x5aa5a55a
reg_addr 0x01f0010c =0x00ff
reg_addr 0x01f00110 =0x00ff
reg_addr 0x01f00114 =0x00ff
eraly jump fel
U-Boot SPL 2016.03-00320-geeea041 (Mar 21 2016 - 15:16:34)
DRAM: 1024 MiB
Trying to boot from MMC1
and hangs...
geeea041 is the SinA31s patch I have on top of your sunxi-wip branch.
I bisected it down to 107fb76 ("sunxi: Fix gmac not working due to
cpu_eth_init no longer being called"). Not sure why this commit fails
though.
Hmm, can you try commenting out these 2 lines in
arch/arm/cpu/armv7/sunxi/board.c :
#ifdef CONFIG_MACPWR
gpio_request(CONFIG_MACPWR, "macpwr");
gpio_direction_output(CONFIG_MACPWR, 1);
#endif
Around line 103 ? That is the only bit which has changed in
the SPL path due to this patch.
This fixes the problem. Thanks.
I'm guessing it's a bad idea to call the generic GPIO
functions, which are DM based, in SPL?
When building the SPL CONFIG_DM_GPIO is not set, and there
are non DM implementations for the SPL in drivers/gpio/sunxi_gpio.c
So the functions should work, and the fact that you get to
"Trying to boot from MMC1"
Shows that at least the SPL does not crash at this code, because
that is done way earlier (before the first message is printed
on the serial console, the same function also sets up the uart
muxing).
So I do not believe that the problem is actually calling the
gpio_request() (nop in non DM mode) nor gpio_direction_output()
in general.
Which would lead to the conclusion that the problem is the
changing of the gpio pin value before u-boot proper has loaded,
which is a bit weird.
Note that commenting out these lines will likely lead to a non
working ethernet on the board. If it does not then you do not
need CONFIG_MACPWR and it could be that you're driving some
$random pin high causing issues.
If the commenting out does lead to a non working ethernet
we could try to fix things by changing the #ifdef to:
#if !defined CONFIG_SPL_BUILD && defined CONFIG_MACPWR
Which would cause us to only turn on the gpio when initializing
gpio-s in u-boot proper and not in the SPL.
Regards,
Hans
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[linux-sunxi] Re: Latest U-boot branch not booting on Hummingbird A31
Hi,
On Mon, Mar 21, 2016 at 5:57 PM, Hans de Goede wrote:
> HI,
>
>
> On 21-03-16 10:49, wens Tsai wrote:
>>
>> Hi Hans,
>>
>> I updated U-boot on my boards to your latest sunxi-wip branch:
>>
>> f965340 ("sunxi: Enable support for the eMMC found on the orangepi
>> plus")
>>
>> My Hummingbird A31 fails to boot after this. See log:
>>
>> HELLO! BOOT0 is starting!
>> boot0 version : 3.0.0
>> reg_addr 0x01f00100 =0x
>> reg_addr 0x01f00104 =0x
>> reg_addr 0x01f00108 =0x
>> reg_addr 0x01f0010c =0x
>> reg_addr 0x01f00110 =0x
>> reg_addr 0x01f00114 =0x
>> [DRAM]ver 1.03 clk = 312
>> cpu 0 pmu 0
>> dram size =1024
>> sum=0x31776fa8
>> src_sum=0x31776fa8
>> Ready to disable icache.
>> Jump to secend Boot.
>> [ 0.209]
>>
>> U-Boot 2011.09-rc1 (Jun 17 2014 - 17:30:56) Allwinner Technology
>>
>> [ 0.217]version: 1.1.0
>> [ 0.220]pmbus: ready
>> [ 0.222]PMU: AXP221
>> [ 0.225]PMU: AXP22x found
>> [ 0.227]PMU: bat ratio = 100
>> [ 0.231]PMU: dcdc3 1260
>> [ 0.233]PMU: pll1 1008 Mhz
>> dcdc1_vol = 3000
>> dcdc2_vol = 1200
>> dcdc3_vol = 1260
>> dcdc4_vol = 1200
>> dcdc5_vol = 1500
>> aldo1_vol = 3000
>> aldo2_vol = 1800
>> aldo3_vol = 3000
>> eldo3_vol = 1800
>> find power_sply to end
>> fel key old mode
>> run key detect
>> no key found
>> no key input
>> dram_para_set start
>> dram_para_set end
>> [ 0.277]DRAM: 1 GiB
>> relocation Offset is: 15b25000
>> donn't initialize ther user_gpio (main_key:boot_init_gpio)
>> deu_mode1 not exist.
>> lcdgamma4iep for lcd1 not exist.
>> DRV_DISP_Init: opened
>> [ 0.542]fetch script data boot_disp.output_type fail
>> [ 0.547]fetch script data boot_disp.output_mode fail
>> [ 0.552]fetch script data boot_disp.auto_hpd fail
>> [ 0.557]lcd0_para.lcd_used=1
>> workmode = 0
>> [ 0.603]NAND: NAND_UbootInit
>> NB1 : enter NAND_LogicInit
>> not burn nand partition table!
>> NB1 : nftl num: 2
>> init nftl: 0
>> NB1 : NAND_LogicInit ok, result = 0x0
>> [ 1.268]sunxi flash init ok
>> probe mmc0 if exist
>> SUNXI SD/MMC: 0
>> Man 1d4144 Snr d3602657
>> SD
>> 0.2
>> boot0 capacity: 0KB,boot1 capacity: 0KB
>> boot0 magic = eGON.BT0蜡讕
>> set next system status
>> DRV_DISP_Exit: closed
>> sunxi_board_close_source
>> NAND_UbootExit
>> NB1 : NAND_LogicExit
>> reset cpu
>> HELLO! BOOT0 is starting!
>> boot0 version : 3.0.0
>> reg_addr 0x01f00100 =0x7347
>> reg_addr 0x01f00104 =0x703b
>> reg_addr 0x01f00108 =0x5aa5a55a
>> reg_addr 0x01f0010c =0x00ff
>> reg_addr 0x01f00110 =0x00ff
>> reg_addr 0x01f00114 =0x00ff
>> eraly jump fel
>>
>> U-Boot SPL 2016.03-00320-geeea041 (Mar 21 2016 - 15:16:34)
>> DRAM: 1024 MiB
>> Trying to boot from MMC1
>>
>>
>> and hangs...
>>
>> geeea041 is the SinA31s patch I have on top of your sunxi-wip branch.
>>
>> I bisected it down to 107fb76 ("sunxi: Fix gmac not working due to
>> cpu_eth_init no longer being called"). Not sure why this commit fails
>> though.
>
>
> Hmm, can you try commenting out these 2 lines in
> arch/arm/cpu/armv7/sunxi/board.c :
>
> #ifdef CONFIG_MACPWR
> gpio_request(CONFIG_MACPWR, "macpwr");
> gpio_direction_output(CONFIG_MACPWR, 1);
> #endif
>
> Around line 103 ? That is the only bit which has changed in
> the SPL path due to this patch.
This fixes the problem. Thanks.
I'm guessing it's a bad idea to call the generic GPIO
functions, which are DM based, in SPL?
ChenYu
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[linux-sunxi] Re: Latest U-boot branch not booting on Hummingbird A31
HI,
On 21-03-16 10:49, wens Tsai wrote:
Hi Hans,
I updated U-boot on my boards to your latest sunxi-wip branch:
f965340 ("sunxi: Enable support for the eMMC found on the orangepi plus")
My Hummingbird A31 fails to boot after this. See log:
HELLO! BOOT0 is starting!
boot0 version : 3.0.0
reg_addr 0x01f00100 =0x
reg_addr 0x01f00104 =0x
reg_addr 0x01f00108 =0x
reg_addr 0x01f0010c =0x
reg_addr 0x01f00110 =0x
reg_addr 0x01f00114 =0x
[DRAM]ver 1.03 clk = 312
cpu 0 pmu 0
dram size =1024
sum=0x31776fa8
src_sum=0x31776fa8
Ready to disable icache.
Jump to secend Boot.
[ 0.209]
U-Boot 2011.09-rc1 (Jun 17 2014 - 17:30:56) Allwinner Technology
[ 0.217]version: 1.1.0
[ 0.220]pmbus: ready
[ 0.222]PMU: AXP221
[ 0.225]PMU: AXP22x found
[ 0.227]PMU: bat ratio = 100
[ 0.231]PMU: dcdc3 1260
[ 0.233]PMU: pll1 1008 Mhz
dcdc1_vol = 3000
dcdc2_vol = 1200
dcdc3_vol = 1260
dcdc4_vol = 1200
dcdc5_vol = 1500
aldo1_vol = 3000
aldo2_vol = 1800
aldo3_vol = 3000
eldo3_vol = 1800
find power_sply to end
fel key old mode
run key detect
no key found
no key input
dram_para_set start
dram_para_set end
[ 0.277]DRAM: 1 GiB
relocation Offset is: 15b25000
donn't initialize ther user_gpio (main_key:boot_init_gpio)
deu_mode1 not exist.
lcdgamma4iep for lcd1 not exist.
DRV_DISP_Init: opened
[ 0.542]fetch script data boot_disp.output_type fail
[ 0.547]fetch script data boot_disp.output_mode fail
[ 0.552]fetch script data boot_disp.auto_hpd fail
[ 0.557]lcd0_para.lcd_used=1
workmode = 0
[ 0.603]NAND: NAND_UbootInit
NB1 : enter NAND_LogicInit
not burn nand partition table!
NB1 : nftl num: 2
init nftl: 0
NB1 : NAND_LogicInit ok, result = 0x0
[ 1.268]sunxi flash init ok
probe mmc0 if exist
SUNXI SD/MMC: 0
Man 1d4144 Snr d3602657
SD
0.2
boot0 capacity: 0KB,boot1 capacity: 0KB
boot0 magic = eGON.BT0蜡讕
set next system status
DRV_DISP_Exit: closed
sunxi_board_close_source
NAND_UbootExit
NB1 : NAND_LogicExit
reset cpu
HELLO! BOOT0 is starting!
boot0 version : 3.0.0
reg_addr 0x01f00100 =0x7347
reg_addr 0x01f00104 =0x703b
reg_addr 0x01f00108 =0x5aa5a55a
reg_addr 0x01f0010c =0x00ff
reg_addr 0x01f00110 =0x00ff
reg_addr 0x01f00114 =0x00ff
eraly jump fel
U-Boot SPL 2016.03-00320-geeea041 (Mar 21 2016 - 15:16:34)
DRAM: 1024 MiB
Trying to boot from MMC1
and hangs...
geeea041 is the SinA31s patch I have on top of your sunxi-wip branch.
I bisected it down to 107fb76 ("sunxi: Fix gmac not working due to
cpu_eth_init no longer being called"). Not sure why this commit fails though.
Hmm, can you try commenting out these 2 lines in
arch/arm/cpu/armv7/sunxi/board.c :
#ifdef CONFIG_MACPWR
gpio_request(CONFIG_MACPWR, "macpwr");
gpio_direction_output(CONFIG_MACPWR, 1);
#endif
Around line 103 ? That is the only bit which has changed in
the SPL path due to this patch.
Regards,
Hans
Regards
ChenYu
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[linux-sunxi] Latest U-boot branch not booting on Hummingbird A31
Hi Hans,
I updated U-boot on my boards to your latest sunxi-wip branch:
f965340 ("sunxi: Enable support for the eMMC found on the orangepi plus")
My Hummingbird A31 fails to boot after this. See log:
HELLO! BOOT0 is starting!
boot0 version : 3.0.0
reg_addr 0x01f00100 =0x
reg_addr 0x01f00104 =0x
reg_addr 0x01f00108 =0x
reg_addr 0x01f0010c =0x
reg_addr 0x01f00110 =0x
reg_addr 0x01f00114 =0x
[DRAM]ver 1.03 clk = 312
cpu 0 pmu 0
dram size =1024
sum=0x31776fa8
src_sum=0x31776fa8
Ready to disable icache.
Jump to secend Boot.
[ 0.209]
U-Boot 2011.09-rc1 (Jun 17 2014 - 17:30:56) Allwinner Technology
[ 0.217]version: 1.1.0
[ 0.220]pmbus: ready
[ 0.222]PMU: AXP221
[ 0.225]PMU: AXP22x found
[ 0.227]PMU: bat ratio = 100
[ 0.231]PMU: dcdc3 1260
[ 0.233]PMU: pll1 1008 Mhz
dcdc1_vol = 3000
dcdc2_vol = 1200
dcdc3_vol = 1260
dcdc4_vol = 1200
dcdc5_vol = 1500
aldo1_vol = 3000
aldo2_vol = 1800
aldo3_vol = 3000
eldo3_vol = 1800
find power_sply to end
fel key old mode
run key detect
no key found
no key input
dram_para_set start
dram_para_set end
[ 0.277]DRAM: 1 GiB
relocation Offset is: 15b25000
donn't initialize ther user_gpio (main_key:boot_init_gpio)
deu_mode1 not exist.
lcdgamma4iep for lcd1 not exist.
DRV_DISP_Init: opened
[ 0.542]fetch script data boot_disp.output_type fail
[ 0.547]fetch script data boot_disp.output_mode fail
[ 0.552]fetch script data boot_disp.auto_hpd fail
[ 0.557]lcd0_para.lcd_used=1
workmode = 0
[ 0.603]NAND: NAND_UbootInit
NB1 : enter NAND_LogicInit
not burn nand partition table!
NB1 : nftl num: 2
init nftl: 0
NB1 : NAND_LogicInit ok, result = 0x0
[ 1.268]sunxi flash init ok
probe mmc0 if exist
SUNXI SD/MMC: 0
Man 1d4144 Snr d3602657
SD
0.2
boot0 capacity: 0KB,boot1 capacity: 0KB
boot0 magic = eGON.BT0蜡讕
set next system status
DRV_DISP_Exit: closed
sunxi_board_close_source
NAND_UbootExit
NB1 : NAND_LogicExit
reset cpu
HELLO! BOOT0 is starting!
boot0 version : 3.0.0
reg_addr 0x01f00100 =0x7347
reg_addr 0x01f00104 =0x703b
reg_addr 0x01f00108 =0x5aa5a55a
reg_addr 0x01f0010c =0x00ff
reg_addr 0x01f00110 =0x00ff
reg_addr 0x01f00114 =0x00ff
eraly jump fel
U-Boot SPL 2016.03-00320-geeea041 (Mar 21 2016 - 15:16:34)
DRAM: 1024 MiB
Trying to boot from MMC1
and hangs...
geeea041 is the SinA31s patch I have on top of your sunxi-wip branch.
I bisected it down to 107fb76 ("sunxi: Fix gmac not working due to
cpu_eth_init no longer being called"). Not sure why this commit fails though.
Regards
ChenYu
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[linux-sunxi] Re: [PATCH] clk: sunxi: Add CSI (camera's Sensors Interface) module clock driver for sun[457]i
On Thu, Mar 17, 2016 at 07:43:42PM +1100, yassinjaf...@gmail.com wrote: > From: Yassin Jaffer > > This patch adds a composite clock type consisting of > a clock gate, mux, configurable dividers, and a reset control. > > Signed-off-by: Yassin Jaffer > --- > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + I wish someone would just add all the sunxi clocks in one pass instead of one by one. Acked-by: Rob Herring > drivers/clk/sunxi/Makefile| 1 + > drivers/clk/sunxi/clk-a10-csi.c | 188 > ++ > 3 files changed, 190 insertions(+) > create mode 100644 drivers/clk/sunxi/clk-a10-csi.c -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH] clk: sunxi: Add CSI (camera's Sensors Interface) module clock driver for sun[457]i
Hi Yassin,
On Thu, Mar 17, 2016 at 07:43:42PM +1100, yassinjaf...@gmail.com wrote:
> From: Yassin Jaffer
>
> This patch adds a composite clock type consisting of
> a clock gate, mux, configurable dividers, and a reset control.
>
> Signed-off-by: Yassin Jaffer
> ---
> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
> drivers/clk/sunxi/Makefile| 1 +
> drivers/clk/sunxi/clk-a10-csi.c | 188
> ++
> 3 files changed, 190 insertions(+)
> create mode 100644 drivers/clk/sunxi/clk-a10-csi.c
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
> b/Documentation/devicetree/bindings/clock/sunxi.txt
> index e59f57b..c3826f7 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -77,6 +77,7 @@ Required properties:
> "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
> "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
> "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
> + "allwinner,sun4i-a10-csi-clk" - for the CSI module
>
> Required properties for all clocks:
> - reg : shall be the control register address for the clock.
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index 3fd7901..42ce752 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -7,6 +7,7 @@ obj-y += clk-a10-codec.o
> obj-y += clk-a10-hosc.o
> obj-y += clk-a10-mod1.o
> obj-y += clk-a10-pll2.o
> +obj-y += clk-a10-csi.o
> obj-y += clk-a10-ve.o
> obj-y += clk-a20-gmac.o
> obj-y += clk-mod0.o
> diff --git a/drivers/clk/sunxi/clk-a10-csi.c b/drivers/clk/sunxi/clk-a10-csi.c
> new file mode 100644
> index 000..f17d206
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-a10-csi.c
> @@ -0,0 +1,188 @@
> +/*
> + * Copyright 2016 Yassin Jaffer
> + *
> + * Yassin Jaffer
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +static DEFINE_SPINLOCK(sun4i_csi_lock);
> +
> +#define SUN4I_CSI_PARENTS 5
> +#define SUN4I_CSI_GATE_BIT 31
> +#define SUN4I_CSI_RESET_BIT 30
> +#define SUN4I_CSI_MUX_SHIFT 24
> +#define SUN4I_CSI_DIV_WIDTH 5
> +#define SUN4I_CSI_DIV_SHIFT 0
> +
> +static u32 sun4i_csi_mux_table[SUN4I_CSI_PARENTS] = {
> + 0x0,
> + 0x1,
> + 0x2,
> + 0x5,
> + 0x6,
> +};
> +
> +struct csi_reset_data {
> + void __iomem*reg;
> + spinlock_t *lock; /* lock for reset handling */
> + struct reset_controller_dev rcdev;
> +};
> +
> +static int sun4i_csi_assert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct csi_reset_data *data = container_of(rcdev,
> + struct csi_reset_data,
> + rcdev);
> + unsigned long flags;
> + u32 reg;
> +
> + spin_lock_irqsave(data->lock, flags);
> +
> + reg = readl(data->reg);
> + writel(reg & ~BIT(SUN4I_CSI_RESET_BIT), data->reg);
> +
> + spin_unlock_irqrestore(data->lock, flags);
> +
> + return 0;
> +}
> +
> +static int sun4i_csi_deassert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct csi_reset_data *data = container_of(rcdev,
> + struct csi_reset_data,
> + rcdev);
> + unsigned long flags;
> + u32 reg;
> +
> + spin_lock_irqsave(data->lock, flags);
> +
> + reg = readl(data->reg);
> + writel(reg | BIT(SUN4I_CSI_RESET_BIT), data->reg);
> +
> + spin_unlock_irqrestore(data->lock, flags);
> +
> + return 0;
> +}
> +
> +static int sun4i_csi_of_xlate(struct reset_controller_dev *rcdev,
> + const struct of_phandle_args *reset_spec)
> +{
> + if (WARN_ON(reset_spec->args_count != 0))
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +static struct reset_control_ops sun4i_csi_reset_ops = {
> + .assert = sun4i_csi_assert,
> + .deassert = sun4i_csi_deassert,
> +};
> +
> +static void __init sun4i_csi_clk_setup(struct device_node *node)
> +{
> + const char *parents[SUN4I_CSI_PARENTS];
> + const char *clk_name = node->name;
> + struct csi_reset_data *reset_data;
> + struct clk_divider *div;
>
[linux-sunxi] Re: How to use socketcan in android application layer
On Wednesday, December 18, 2013 at 2:46:27 PM UTC+5:30, Peter Chen wrote: > hey, guys. > I'v finished sunxi CAN drive in the socketcan mode.And I write a C program > proved it works.I can send and receive packet correctlly. > Since I'm not an android app developer, I wonder how can I write a demo app > by using the socketcan method.Can anyone give me some suggestions.Thaks. Hi Peter, Can you elaborate please how you have implemented SocketCan in Android. if possible then please share source code over blog. I am finding a way to implement SocketCan in android but I could not bale to find any sufficient document. Thanks. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH] sunxi: Add defconfig for Sinlinx SinA31s
The Sinlinx A31s SDK is a A31s based module/baseboard development kit. The core module has the SoC, PMIC, DRAM, eMMC and supporting components. There are also pads for UART0, JTAG and I2S. The baseboard has 100 Mbps Ethernet, 5x USB 2.0 host ports via a USB 2.0 hub chip, MMC, HDMI, SPDIF, CIR, audio jacks, 2 tablet-like volume buttons, RS232 style UART and USB OTG (though VBUS is not connected). Various headers are available for other addon modules, such as SDIO WiFi, LCD display, camera sensor, UARTs, I2C, SPI and GPIOs. Signed-off-by: Chen-Yu Tsai --- board/sunxi/MAINTAINERS | 6 ++ configs/Sinlinx_SinA31s_defconfig | 21 + 2 files changed, 27 insertions(+) create mode 100644 configs/Sinlinx_SinA31s_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 5ae5ce6..8cb9051 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -191,6 +191,12 @@ M: Siarhei Siamashka S: Maintained F: configs/MSI_Primo81_defconfig +SINLINX SINA31s BOARD +M: Chen-Yu Tsai +S: Maintained +F: configs/Sinlinx_SinA31s_defconfig +W: http://linux-sunxi.org/Sinlinx_SinA31s + SINLINX SINA33 BOARD M: Chen-Yu Tsai S: Maintained diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig new file mode 100644 index 000..9254bb2 --- /dev/null +++ b/configs/Sinlinx_SinA31s_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN6I=y +CONFIG_DRAM_CLK=432 +CONFIG_DRAM_ZQ=251 +CONFIG_MMC0_CD_PIN="PA4" +CONFIG_MMC3_PINS="PC" +CONFIG_MMC_SUNXI_SLOT_EXTRA=3 +CONFIG_USB1_VBUS_PIN="" +CONFIG_USB2_VBUS_PIN="" +CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sina31s" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_ETH_DESIGNWARE=y +CONFIG_AXP_DLDO1_VOLT=3300 +CONFIG_USB_EHCI_HCD=y -- 2.7.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH 0/8] ARM: dts: sun8i: Orangepi Plus dts improvements
On Sun, Mar 20, 2016 at 05:00:28PM +0100, Hans de Goede wrote: > Hi Maxime and Chen-Yu, > > Here is a series with various improvements for the Orangepi Plus dts. > Some (most) of these patches have been submitted before, esp. the USB > ones have multiple revisions before. But I lost count of their version, > so I'm posting this as a "new" set. > > About the USB patches, these rely on the patches to add support for > multiple-reset controllers to ohci-platform / ehci-platform. These > patches are all acked up and will go upstream as soon as v4.6-rc1 is > released (they depend on changes which will go into v4.6-rc1). > > The old ohci-platform / ehci-platform will only look at the first reset > specified in the dt and as such will fail to load with the new dt nodes > (because they cannot talk to the controller). > > I've also included a v6 of Krzysztof Adamski leds / switches > patch, fixing the comments you had in your review of v5. I've done this > to avoid conflicts with my other patches. Applied all but patch 6, which was in already. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: Digital signature
[linux-sunxi] Re: [PATCH v7] ARM: dts: sun8i: Add leds and switches on Orangepi Plus boards
Hi,
On Sun, Mar 20, 2016 at 07:55:02PM +0100, Hans de Goede wrote:
> From: Krzysztof Adamski
>
> OrangePi Plus board has two leds - green ("pwr") and red ("status")
> and two switches ("sw4" and "sw2"). This patch describes them in
> devicetree.
>
> Signed-off-by: Krzysztof Adamski
> Signed-off-by: Hans de Goede
An earlier version has already been sent for 4.6, please base your
changes on top of this one.
And there's a bunch of things I didn't catch at that time :/
> ---
> Changes in v6 (hdegoede):
> -Merge leds and r_leds nodes into one
> -Fix led labels to be in :: form
> -Alphabetically sort the added nodes
> -Add support for sw2 (this is the small reset-like button)
> Changes in v7 (hdegoede):
> -Use PL3 / PL4 in the pinctrl node, not PL03 / PL04
> ---
> arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 63
>
> 1 file changed, 63 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
> b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
> index a680b1f..9d8c038 100644
> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
> @@ -45,6 +45,7 @@
> #include "sunxi-common-regulators.dtsi"
>
> #include
> +#include
> #include
>
> / {
> @@ -59,6 +60,43 @@
> stdout-path = "serial0:115200n8";
> };
>
> + gpio_keys {
> + compatible = "gpio-keys";
> + input-name = "sw4";
This is an undocumented (and apparently unused) property
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&sw_r_opc>;
> +
> + sw2@0 {
You shouldn't have a unit-address here
> + label = "sw2";
> + linux,code = ;
> + gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>;
> + };
> +
> + sw4@0 {
Ditto.
Thanks!
Maxime
--
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[linux-sunxi] Re: [PATCH] ARM: dts: Add dts file for Dserve DSRV9703C tablet
On Sat, Mar 19, 2016 at 11:18:59PM +0800, Chen-Yu Tsai wrote: > On Sat, Mar 19, 2016 at 3:53 PM, Hans de Goede wrote: > > The Dserve DSRV9703C is a 9.7" A10 tablet with a 1024x768 ips LCD, > > 1G RAM, 4GB flash, a Focaltech FT5406EE8 touchscreen and rtl8188ctv wifi. > > > > Signed-off-by: Hans de Goede > > Acked-by: Chen-Yu Tsai Applied, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: Digital signature
Re: [linux-sunxi] Re: [PATCH] ARM: dts: sun6i: Add serial0 alias and stdout-path to a31s-primo81.dts
On Sat, Mar 19, 2016 at 10:13:47AM +0100, Hans de Goede wrote: > Hi, > > On 18-03-16 18:48, Maxime Ripard wrote: > >On Thu, Mar 17, 2016 at 02:28:03PM +0800, Chen-Yu Tsai wrote: > >>On Wed, Mar 16, 2016 at 10:19 PM, Hans de Goede wrote: > >>>u-boot uses the kernel as the canonical source for its sunxi dts files > >>>and u-boot needs these. > >>> > >>>Signed-off-by: Hans de Goede > >> > >>Acked-by: Chen-Yu Tsai > > > >Queued, thanks! > > I just got an of-list mail from Karsten Merker that you nacked the addition > if this during the initial submission, because there are no accessible uart > test pads on this tablet. > > In that case the proper fix would be to change the u-boot defconfig to have: > > # CONFIG_REQUIRE_SERIAL_CONSOLE is not set > > Which will stop u-boot from panicking (with nowhere to print the panic msg) > when it has no stdout-path. > > Can you unqueue this one until we've figured out what the best fix is ? Done, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: Digital signature
