[linux-sunxi] Re: [RFC PATCH] mfd: AXP20x: Add support for basic voltage/current/temperature ADCs

[Chen-Yu Tsai]

On Mon, Dec 19, 2016 at 10:58 PM, Corentin Labbe
 wrote:
> AXP202 and AXP209 can report voltages and current readings for its
> various power inputs, the LiPo battery, and also the chip's internal
> temperature.
> This patch add basic support for these sensors.
>
> Signed-off-by: Chen-Yu Tsai 
> Signed-off-by: Corentin Labbe 

First of all, thanks for the renewed interest on this.

You might have noticed Quentin from Free Electrons posted a series
with IIO support for the ADCs and power supply drivers for ACIN
and battery.

IMO the IIO approach is better, as it allows centralized control
of the ADC channels, which are then exported so other sub-devices
can use them. This avoids the various drivers enabling ADC on
their own, and potentially stepping on each other. The IIO
channels can also be exported to HWMON, though IIRC the naming
leaves something to be desired.

Regards
ChenYu

> ---
>  drivers/mfd/Kconfig|  11 ++
>  drivers/mfd/Makefile   |   1 +
>  drivers/mfd/axp20x-hwmon.c | 265 
> +
>  3 files changed, 277 insertions(+)
>  create mode 100644 drivers/mfd/axp20x-hwmon.c
>
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index 1ed0584..e0a3944 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -150,6 +150,17 @@ config MFD_AXP20X_RSB
>   components like regulators or the PEK (Power Enable Key) under the
>   corresponding menus.
>
> +config MFD_AXP20X_HWMON
> +   tristate "X-POWERS AXP20X PMIC hwmon"
> +   depends on MFD_AXP20X
> +   depends on HWMON
> +   help
> + If you say yes here you get support for the hardware
> + monitoring features of the AXP20X series of PMICs.
> +
> + This driver can also be built as a module.  If so, the module
> + will be called axp20x-hwmon.
> +
>  config MFD_CROS_EC
> tristate "ChromeOS Embedded Controller"
> select MFD_CORE
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 7bb5a501..91b43bd 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -120,6 +120,7 @@ obj-$(CONFIG_MFD_AC100) += ac100.o
>  obj-$(CONFIG_MFD_AXP20X)   += axp20x.o
>  obj-$(CONFIG_MFD_AXP20X_I2C)   += axp20x-i2c.o
>  obj-$(CONFIG_MFD_AXP20X_RSB)   += axp20x-rsb.o
> +obj-$(CONFIG_MFD_AXP20X_HWMON) += axp20x-hwmon.o
>
>  obj-$(CONFIG_MFD_LP3943)   += lp3943.o
>  obj-$(CONFIG_MFD_LP8788)   += lp8788.o lp8788-irq.o
> diff --git a/drivers/mfd/axp20x-hwmon.c b/drivers/mfd/axp20x-hwmon.c
> new file mode 100644
> index 000..02b4028
> --- /dev/null
> +++ b/drivers/mfd/axp20x-hwmon.c
> @@ -0,0 +1,265 @@
> +/*
> + * axp20x ADC hwmon driver.
> + *
> + * Copyright (C) 2013 Chen-Yu Tsai 
> + *
> + * This file is subject to the terms and conditions of the GNU General
> + * Public License. See the file "COPYING" in the main directory of this
> + * archive for more details.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +/* valid bits for ADC enable registers */
> +#define AXP20X_ADC_EN1_MASK0xff
> +#define AXP20X_ADC_EN2_MASK0x8c
> +
> +/* default values from the datasheet */
> +#define AXP20X_ADC_EN1_DEFAULT 0x83
> +#define AXP20X_ADC_EN2_DEFAULT 0x80
> +
> +/* enable bits for basic ADCs */
> +#define AXP20X_ADC_EN1_BASIC   0xfe
> +#define AXP20X_ADC_EN2_BASIC   0x80
> +
> +/* Use MSB register offset as index */
> +static const char * const input_names[] = {
> +   [AXP20X_ACIN_V_ADC_H]   = "ACIN",
> +   [AXP20X_ACIN_I_ADC_H]   = "ACIN",
> +   [AXP20X_VBUS_V_ADC_H]   = "VBUS",
> +   [AXP20X_VBUS_I_ADC_H]   = "VBUS",
> +   [AXP20X_TEMP_ADC_H] = "CHIP",
> +   [AXP20X_TS_IN_H]= "TS",
> +   [AXP20X_GPIO0_V_ADC_H]  = "GPIO0",
> +   [AXP20X_GPIO1_V_ADC_H]  = "GPIO1",
> +   [AXP20X_PWR_BATT_H] = "BATT",
> +   [AXP20X_BATT_V_H]   = "BATT",
> +   [AXP20X_BATT_CHRG_I_H]  = "BATT_CHRG",
> +   [AXP20X_BATT_DISCHRG_I_H] = "BATT_DISCHRG",
> +   [AXP20X_IPSOUT_V_HIGH_H]= "APS",
> +};
> +
> +static const int input_step[] = {
> +   [AXP20X_ACIN_V_ADC_H]   = 1700,
> +   [AXP20X_ACIN_I_ADC_H]   = 625,
> +   [AXP20X_VBUS_V_ADC_H]   = 1700,
> +   [AXP20X_VBUS_I_ADC_H]   = 375,
> +   [AXP20X_TEMP_ADC_H] = 100,
> +   [AXP20X_TS_IN_H]= 800,
> +   [AXP20X_GPIO0_V_ADC_H]  = 500,
> +   [AXP20X_GPIO1_V_ADC_H]  = 500,
> +   [AXP20X_PWR_BATT_H] = 1100,
> +   [AXP20X_BATT_V_H]   = 1100,
> +   [AXP20X_BATT_CHRG_I_H]  = 500,
> +   [AXP20X_BATT_DISCHRG_I_H] = 

Re: [linux-sunxi][PATCH 3/3] ARM: dts: sun6i: Add SPDIF to the Mele I7

[Chen-Yu Tsai]

On Tue, Dec 20, 2016 at 6:40 PM,   wrote:
> From: Marcus Cooper 
>
> Enable the S/PDIF transmitter that is present on the Mele I7.
>
> Signed-off-by: Marcus Cooper 

Acked-by: Chen-Yu Tsai 

This patch should be ready to be merged. The associated clk
and dtsi changes are already in Maxime's tree.

> ---
>  arch/arm/boot/dts/sun6i-a31-i7.dts | 24 
>  1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun6i-a31-i7.dts 
> b/arch/arm/boot/dts/sun6i-a31-i7.dts
> index a2193309a199..2bc57d2dcd80 100644
> --- a/arch/arm/boot/dts/sun6i-a31-i7.dts
> +++ b/arch/arm/boot/dts/sun6i-a31-i7.dts
> @@ -69,6 +69,23 @@
> gpios = < 7 13 GPIO_ACTIVE_HIGH>;
> };
> };
> +
> +   sound {
> +   compatible = "simple-audio-card";
> +   simple-audio-card,name = "On-board SPDIF";
> +   simple-audio-card,cpu {
> +   sound-dai = <>;
> +   };
> +
> +   simple-audio-card,codec {
> +   sound-dai = <_out>;
> +   };
> +   };
> +
> +   spdif_out: spdif-out {
> +   #sound-dai-cells = <0>;
> +   compatible = "linux,spdif-dit";
> +   };
>  };
>
>   {
> @@ -138,6 +155,13 @@
> status = "okay";
>  };
>
> + {
> +   pinctrl-names = "default";
> +   pinctrl-0 = <_pins_a>;
> +   spdif-out = "okay";
> +   status = "okay";
> +};
> +
>   {
> pinctrl-names = "default";
> pinctrl-0 = <_pins_a>;
> --
> 2.11.0
>
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Re: [linux-sunxi] [PATCH] ASoC: sunxi: spdif: Fix SPDIF playback formats

[Chen-Yu Tsai]

Hi,

On Sat, Jan 7, 2017 at 1:41 AM,   wrote:
> From: Hanspeter Portner 
>
> Change SPDIF playback formats from wrongly used enumerators
> SNDRV_PCM_FORMAT_* to proper SNDRV_PCM_FMTBIT_* bitfields.
>
> Signed-off-by: Hanspeter Portner 

Please send the patch to the maintainers and mailing lists
given by scripts/get_maintainers.pl.

ChenYu

> ---
>  sound/soc/sunxi/sun4i-spdif.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/sound/soc/sunxi/sun4i-spdif.c b/sound/soc/sunxi/sun4i-spdif.c
> index 88fbb3a1..8583987c 100644
> --- a/sound/soc/sunxi/sun4i-spdif.c
> +++ b/sound/soc/sunxi/sun4i-spdif.c
> @@ -387,9 +387,9 @@ static const struct regmap_config 
> sun4i_spdif_regmap_config = {
>
>  #define SUN4I_RATESSNDRV_PCM_RATE_8000_192000
>
> -#define SUN4I_FORMATS  (SNDRV_PCM_FORMAT_S16_LE | \
> -   SNDRV_PCM_FORMAT_S20_3LE | \
> -   SNDRV_PCM_FORMAT_S24_LE)
> +#define SUN4I_FORMATS  (SNDRV_PCM_FMTBIT_S16_LE | \
> +   SNDRV_PCM_FMTBIT_S20_3LE | \
> +   SNDRV_PCM_FMTBIT_S24_LE)
>
>  static struct snd_soc_dai_driver sun4i_spdif_dai = {
> .playback = {
> --
> 2.11.0
>
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[linux-sunxi] [PATCH resend v3] ASoC: sun4i-codec: Add "Right Mixer" to "Line Out Mono Diff." route

[Chen-Yu Tsai]

The mono differential output for "Line Out" downmixes the stereo audio
from the mixer, instead of just taking the left channel.

Add a route from the "Right Mixer" to "Line Out Source Playback Route"
through the "Mono Differential" path, so DAPM doesn't shut down
everything if the left channel is muted.

Fixes: 0f909f98d7cb ("ASoC: sun4i-codec: Add support for A31 Line Out
  playback")
Signed-off-by: Chen-Yu Tsai 
Acked-by: Maxime Ripard 
---

Last sent 2016/11/24. Resending with Maxime's ack.

---
 sound/soc/sunxi/sun4i-codec.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sound/soc/sunxi/sun4i-codec.c b/sound/soc/sunxi/sun4i-codec.c
index 848af01692a0..c3aab10fa085 100644
--- a/sound/soc/sunxi/sun4i-codec.c
+++ b/sound/soc/sunxi/sun4i-codec.c
@@ -1058,6 +1058,7 @@ static const struct snd_soc_dapm_route 
sun6i_codec_codec_dapm_routes[] = {
{ "Line Out Source Playback Route", "Stereo", "Left Mixer" },
{ "Line Out Source Playback Route", "Stereo", "Right Mixer" },
{ "Line Out Source Playback Route", "Mono Differential", "Left Mixer" },
+   { "Line Out Source Playback Route", "Mono Differential", "Right Mixer" 
},
{ "LINEOUT", NULL, "Line Out Source Playback Route" },
 
/* ADC Routes */
-- 
2.11.0

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Re: [linux-sunxi] Olimex A20 SOM EVB + DRM + LCD panel, a (someway working) experience..

[Luc Verhaegen]

On Wed, Jan 04, 2017 at 03:44:29PM +0200, Priit Laes wrote:
> On Tue, 2017-01-03 at 23:02 -0800, Steffie Chou wrote:
> > i compiled with the default defconfig for this Graperain [xxx] EVB
> > board and booted.
> 

Ok, so this user should be moderated then.

Luc Verhaegen.

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Re: [linux-sunxi] [PATCH] clk: sunxi-ng: fix PLL_CPUX adjusting on H3

[Ondřej Jirman]

Maxime,

Dne 25.11.2016 v 01:28 meg...@megous.com napsal(a):
> From: Ondrej Jirman 
> 
> When adjusting PLL_CPUX on H3, the PLL is temporarily driven
> too high, and the system becomes unstable (oopses or hangs).
> 
> Add a notifier to avoid this situation by temporarily switching
> to a known stable 24 MHz oscillator.

I have done more thorough testing on H3 and this approach with switching
to 24MHz oscillator does not work. Motivation being that my Orange Pi
One still gets lockups even with this patch under certain circumstances.

So I have created a small test program for CPUS (additional OpenRISC CPU
on the SoC) which randomly changes PLL_CPUX settings while main CPU is
running a loop that sends messages to CPUS via msgbox.

Assumption being that while CPUS is successfully receiving messages via
msgbox, the main CPU didn't lock up, yet.

With this I am able to quickly and thoroughly test various PLL_CPUX
change and factor selection algorithms.

Results are that bypassing CPUX clock by switching to 24 MHz oscillator
does not work at all. Main CPU locks up in about 1 second into the test.
Don't ask me why.

What works is selecting NKMP factors so that M is always 1 and P is
anything other than /1 only for frequencies under 288MHz. As mandated by
the H3 datasheet. Mainline ccu_nkmp_find_best doesn't respect these
conditions. With that I can change CPUX frequencies randomly 20x a
second so far indefinitely without the main CPU ever locking up.

Please drop or revert this patch. It is not a correct approach to the
problem. I'd suggest dropping the entire clock notifier mechanism, too,
unless it can be proven to work reliably. The bypass makes some
intuitive sense, but for some reason it doesn't work in practice (on H3
at least).

Aside from this, uboot also needs to be changed to set that it uses M
and P factors correctly.

Whatever else I try, I always hit lockups sooner or later with the test
program. I tried 24MHz bypass and staged application of multipliers and
dividers as discussed before.

I'll send a proper patch for nkmp clock driver and u-boot later.

regards,
  o.

> Signed-off-by: Ondrej Jirman 
> Tested-by: Lutz Sammer 
> ---
>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 10 ++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c 
> b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> index 614d47c..cf266c9 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> @@ -809,6 +809,13 @@ static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
>   .num_resets = ARRAY_SIZE(sun8i_h3_ccu_resets),
>  };
>  
> +static struct ccu_mux_nb sun8i_h3_cpu_nb = {
> + .common = _clk.common,
> + .cm = _clk.mux,
> + .delay_us   = 1, /* > 8 clock cycles at 24 MHz */
> + .bypass_index   = 1, /* index of 24 MHz oscillator */
> +};
> +
>  static void __init sun8i_h3_ccu_setup(struct device_node *node)
>  {
>   void __iomem *reg;
> @@ -827,6 +834,9 @@ static void __init sun8i_h3_ccu_setup(struct device_node 
> *node)
>   writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
>  
>   sunxi_ccu_probe(node, reg, _h3_ccu_desc);
> +
> + ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
> +   _h3_cpu_nb);
>  }
>  CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",
>  sun8i_h3_ccu_setup);
> 

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