Re: [linux-sunxi] Re: [PATCH 04/21] ARM: sun8i: dt: Add DT bindings documentation for Allwinner dwmac-sun8i
2017年2月17日 04:58于 Florian Fainelli 写道：
>
> On 02/16/2017 04:48 AM, Corentin Labbe wrote:
> > This patch adds documentation for Device-Tree bindings for the
> > Allwinner dwmac-sun8i driver.
> >
> > Signed-off-by: Corentin Labbe
> > ---
> > .../devicetree/bindings/net/dwmac-sun8i.txt | 86
> >++
> > 1 file changed, 86 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> >
> > diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > new file mode 100644
> > index 000..ac806c6
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > @@ -0,0 +1,86 @@
> > +* Allwinner sun8i GMAC ethernet controller
> > +
> > +This device is a platform glue layer for stmmac.
> > +Please see stmmac.txt for the other unchanged properties.
> > +
> > +Required properties:
> > +- compatible: should be one of the following string:
> > + "allwinner,sun8i-a83t-emac"
> > + "allwinner,sun8i-h3-emac"
> > + "allwinner,sun50i-a64-emac"
> > +- reg: address and length of the register for the device.
> > +- interrupts: interrupt for the device
> > +- interrupt-names: should be "macirq"
> > +- clocks: A phandle to the reference clock for this device
> > +- clock-names: should be "stmmaceth"
> > +- resets: A phandle to the reset control for this device
> > +- reset-names: should be "stmmaceth"
> > +- phy-mode: See ethernet.txt
> > +- phy-handle: See ethernet.txt
> > +- #address-cells: shall be 1
> > +- #size-cells: shall be 0
> > +- syscon: A phandle to the syscon of the SoC with one of the following
> > + compatible string:
> > + - allwinner,sun8i-h3-system-controller
> > + - allwinner,sun8i-a64-system-controller
> > + - allwinner,sun8i-a83t-system-controller
> > +
> > +Optional properties:
> > +- allwinner,tx-delay: TX clock delay chain value. Range value is 0-0x07.
> > Default is 0)
> > +- allwinner,rx-delay: RX clock delay chain value. Range value is 0-0x1F.
> > Default is 0)
>
> Delays should be specified in nanosecond units, and should not be a
> value that maps directly to a HW register value, you need to convert the
> property value into the appropriate register value.
>
> > +Both delay properties does not have units, there are arbitrary value.
> > +The TX/RX clock delay chain settings are board specific and could be found
> > +in vendor FEX files.
> > +
> > +Optional properties for "allwinner,sun8i-h3-emac":
> > +- allwinner,leds-active-low: EPHY LEDs are active low
>
> Are you sure this is appropriate at the MAC node level and this is not
> something that follows the PHY instead?
I think it's in fact for the internal MII PHY.
Allwinner H3/H5/V3s features a internal PHY in the SoC (V3s even lacks an
external MII interface), which is also handled in this driver.
>
> > +
> > +Required child node of emac:
> > +- mdio bus node: should be named mdio
> > +
> > +Required properties of the mdio node:
> > +- #address-cells: shall be 1
> > +- #size-cells: shall be 0
> > +
> > +The device node referenced by "phy" or "phy-handle" should be a child node
> > +of the mdio node. See phy.txt for the generic PHY bindings.
> > +
> > +Required properties of the phy node with "allwinner,sun8i-h3-emac":
> > +- clocks: an extra phandle to the reference clock for the EPHY
>
> s/an extra/a phandle/
>
> > +- resets: an extra phandle to the reset control for the EPHY
> > +
> > +Required properties for the system controller:
> > +- reg: address and length of the register for the device.
> > +- compatible: should be "syscon" and one of the following string:
> > + "allwinner,sun8i-h3-system-controller"
> > + "allwinner,sun8i-a64-system-controller"
> > + "allwinner,sun8i-a83t-system-controller"
> > +
> > +Example:
> > +
> > +emac: ethernet@1c0b000 {
> > + compatible = "allwinner,sun8i-h3-emac";
> > + syscon = <&syscon>;
> > + reg = <0x01c0b000 0x104>;
> > + interrupts = ;
> > + interrupt-names = "macirq";
> > + resets = <&ccu RST_BUS_EMAC>;
> > + reset-names = "stmmaceth";
> > + clocks = <&ccu CLK_BUS_EMAC>;
> > + clock-names = "stmmaceth";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + phy = <&int_mii_phy>;
> > + phy-mode = "mii";
> > + allwinner,leds-active-low;
> > + mdio: mdio {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + int_mii_phy: ethernet-phy@1 {
> > + reg = <1>;
> > + clocks = <&ccu CLK_BUS_EPHY>;
> > + resets = <&ccu RST_BUS_EPHY>;
> > + };
> > + };
> > +};
> >
>
>
> --
> Florian
>
> --
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Re: [linux-sunxi] Re: [PATCH 20/21] ARM: sunxi: Enable dwmac-sun8i driver on sunxi_defconfig
2017年2月17日 16:55于 Corentin Labbe 写道： > > On Thu, Feb 16, 2017 at 08:08:27PM +0100, Maxime Ripard wrote: > > Hi, > > > > On Thu, Feb 16, 2017 at 01:48:58PM +0100, Corentin Labbe wrote: > > > From: LABBE Corentin > > > > > > Enable the dwmac-sun8i driver in the sunxi default configuration > > > > > > Signed-off-by: Corentin Labbe > > > --- > > > arch/arm/configs/sunxi_defconfig | 1 + > > > 1 file changed, 1 insertion(+) > > > > > > diff --git a/arch/arm/configs/sunxi_defconfig > > > b/arch/arm/configs/sunxi_defconfig > > > index da92c25..33bde86 100644 > > > --- a/arch/arm/configs/sunxi_defconfig > > > +++ b/arch/arm/configs/sunxi_defconfig > > > @@ -40,6 +40,7 @@ CONFIG_ATA=y > > > CONFIG_AHCI_SUNXI=y > > > CONFIG_NETDEVICES=y > > > CONFIG_SUN4I_EMAC=y > > > +CONFIG_DWMAC_SUN8I=m > > > > I think I'd prefer to have it compiled statically, just like the other > > net drivers, and drivers in general. > > > > Thanks! > > Maxime > > > > In previous sun8i-emac, someone request that CONFIG must be set as module > because kernel went too big. > But I do not care to set it statically. This is sunxi_defconfig, not multi_v7_config. I remember the complain is for multi_v7_config. For multi_v7_config it's proper to make it =m. > > Regards > Corentin Labbe > > -- > You received this message because you are subscribed to the Google Groups > "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to linux-sunxi+unsubscr...@googlegroups.com. > For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [RFC PATCH 5/9] ARM: dts: sun8i: add DTSI file for R40 SoC
On 17/02/17 17:37, Icenowy Zheng wrote:
> R40 is a new SoC by Allwinner, with peripherals as rich as A20, and quad
> core Cortex-A7.
>
> Add a DTSI file for it.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm/boot/dts/sun8i-r40.dtsi | 404
> +++
> 1 file changed, 404 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
>
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
> b/arch/arm/boot/dts/sun8i-r40.dtsi
> new file mode 100644
> index ..df48c87237f3
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -0,0 +1,404 @@
> +/*
> + * Copyright 2017 Chen-Yu Tsai
> + * Copyright 2017 Icenowy Zheng
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include
> +#include
> +#include
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <&gic>;
> +
> + aliases {
> + };
> +
> + chosen {
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + osc24M: osc24M {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <2400>;
> + };
> +
> + osc32k: osc32k {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "osc32k";
> + };
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <1>;
> + };
> +
> + cpu@2 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <2>;
> + };
> +
> + cpu@3 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <3>;
> + };
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0x4000 0x8000>;
> + };
> +
> + soc@01c0 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + nmi_intc: interrupt-controller@01c00030 {
> + compatible = "allwinner,sun7i-a20-sc-nmi";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + reg = <0x01c00030 0x0c>;
> + interrupts = ;
> + };
> +
> + m
[linux-sunxi] [RFC PATCH 6/9] ARM: dts: sun8i: add DTS file for Banana Pi M2 Ultra
Banana Pi M2 Ultra is a new board by Sinovoip (BPi), with R40 SoC,
AXP221 PMIC, 2GiB DRAM, 8GiB eMMC, a 40-pin RPi-like GPIO connector, a
HDMI connector, a SATA connector (native in SoC) as well as its power
supply, a Headphone jack, two USB ports, a 1000Mbps Ethernet port
(with RTL8211E PHY), a MicroSD slot, a battery connector, a DSI
connector and a CSI connector.
Add support for the board.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 161 ++
2 files changed, 162 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 011808490fed..29367442cda4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -876,6 +876,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-orangepi-plus.dtb \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-r16-parrot.dtb \
+ sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
new file mode 100644
index ..1d824830a1ad
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -0,0 +1,161 @@
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai
+ * Copyright (C) 2017 Icenowy Zheng
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-r40.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+ model = "Banana Pi BPI-M2-Ultra";
+ compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ axp22x: pmic@68 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp22x.dtsi"
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <270>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "avcc";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <300>;
+ regulator-max-microvolt = <300>;
+ regulator-name = "vcc-3v0";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <100>;
+ regulator-max-microvolt = <130>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <100>;
+ regulator-max-microvolt = <130>;
+ regulator-name = "vdd-sys";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+
[linux-sunxi] [RFC PATCH 5/9] ARM: dts: sun8i: add DTSI file for R40 SoC
R40 is a new SoC by Allwinner, with peripherals as rich as A20, and quad
core Cortex-A7.
Add a DTSI file for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40.dtsi | 404 +++
1 file changed, 404 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
new file mode 100644
index ..df48c87237f3
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -0,0 +1,404 @@
+/*
+ * Copyright 2017 Chen-Yu Tsai
+ * Copyright 2017 Icenowy Zheng
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ aliases {
+ };
+
+ chosen {
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ };
+
+ osc32k: osc32k {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x4000 0x8000>;
+ };
+
+ soc@01c0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ nmi_intc: interrupt-controller@01c00030 {
+ compatible = "allwinner,sun7i-a20-sc-nmi";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01c00030 0x0c>;
+ interrupts = ;
+ };
+
+ mmc0: mmc@1c0f000 {
+ compatible = "allwinner,sun50i-a64-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>
[linux-sunxi] [RFC PATCH 9/9] ARM: dts: sun8i: enable USB host for Banana Pi M2 Ultra
Banana Pi M2 Ultra board features two USB host ports, connected to the
two USB host ports on the SoC.
Add support for them.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 1d824830a1ad..672fb7f0f393 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -63,6 +63,14 @@
};
};
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
@@ -154,8 +162,23 @@
status = "okay";
};
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_0>;
status = "okay";
};
+
+&usbphy {
+ pinctrl-names = "default";
+ usb1_vbus-supply = <®_vcc5v0>;
+ usb2_vbus-supply = <®_vcc5v0>;
+ status = "okay";
+};
--
2.11.1
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[linux-sunxi] [RFC PATCH 8/9] ARM: dts: sun8i: add USB nodes for R40
Allwinner R40 SoC features a USB OTG port and two USB HOST ports.
Add support for the ports in the DTSI file.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40.dtsi | 89
1 file changed, 89 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index df48c87237f3..052badc2dd3c 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -179,6 +179,95 @@
#size-cells = <0>;
};
+ usb_otg: usb@01c13000 {
+ compatible = "allwinner,sun8i-a33-musb";
+ reg = <0x01c13000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = ;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ status = "disabled";
+ };
+
+ usbphy: phy@01c13400 {
+ compatible = "allwinner,sun8i-r40-usb-phy";
+ reg = <0x01c13400 0x14>,
+ <0x01c19800 0x4>,
+ <0x01c1c800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu1",
+ "pmu2";
+ clocks = <&ccu CLK_USB_PHY0>,
+<&ccu CLK_USB_PHY1>,
+<&ccu CLK_USB_PHY2>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy";
+ resets = <&ccu RST_USB_PHY0>,
+<&ccu RST_USB_PHY1>,
+<&ccu RST_USB_PHY2>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci1: usb@01c19000 {
+ compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
+ reg = <0x01c19000 0x100>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+<&ccu CLK_BUS_EHCI1>,
+<&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>,
+<&ccu RST_BUS_EHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@01c19400 {
+ compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
+ reg = <0x01c19400 0x100>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+<&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci2: usb@01c1c000 {
+ compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
+ reg = <0x01c1c000 0x100>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_OHCI2>,
+<&ccu CLK_BUS_EHCI2>,
+<&ccu CLK_USB_OHCI2>;
+ resets = <&ccu RST_BUS_OHCI2>,
+<&ccu RST_BUS_EHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci2: usb@01c1c400 {
+ compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
+ reg = <0x01c1c400 0x100>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_OHCI2>,
+<&ccu CLK_USB_OHCI2>;
+ resets = <&ccu RST_BUS_OHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
ccu: clock@01c2 {
compatible = "allwinner,sun8i-r40-ccu";
reg = <0x01c2 0x400>;
--
2.11.1
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[linux-sunxi] [PATCH 7/9] phy: sun4i-usb: add support for R40 USB PHY
Allwinner R40 features a USB PHY like the one in A64, but with 3 ports.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
drivers/phy/phy-sun4i-usb.c | 17 +
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index e42334258185..184a1d7af352 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -11,6 +11,7 @@ Required properties:
* allwinner,sun8i-a33-usb-phy
* allwinner,sun8i-h3-usb-phy
* allwinner,sun8i-v3s-usb-phy
+ * allwinner,sun8i-r40-usb-phy
* allwinner,sun50i-a64-usb-phy
- reg : a list of offset + length pairs
- reg-names :
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index a21b5f24a340..3c6ddd6750dd 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -100,6 +100,7 @@ enum sun4i_usb_phy_type {
sun8i_a33_phy,
sun8i_h3_phy,
sun8i_v3s_phy,
+ sun8i_r40_phy,
sun50i_a64_phy,
};
@@ -188,10 +189,8 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy,
u32 addr, u32 data,
spin_lock_irqsave(&phy_data->reg_lock, flags);
- if (phy_data->cfg->type == sun8i_a33_phy ||
- phy_data->cfg->type == sun50i_a64_phy ||
- phy_data->cfg->type == sun8i_v3s_phy) {
- /* A33 or A64 needs us to set phyctl to 0 explicitly */
+ if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
+ /* A33-style phyctl register needs to be set to 0 explicitly */
writel(0, phyctl);
}
@@ -845,6 +844,15 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
.enable_pmu_unk1 = true,
};
+static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
+ .num_phys = 3,
+ .type = sun8i_r40_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A33,
+ .dedicated_clocks = true,
+ .enable_pmu_unk1 = true,
+};
+
static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
@@ -854,6 +862,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] =
{
{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg },
+ { .compatible = "allwinner,sun8i-r40-usb-phy", .data = &sun8i_r40_cfg },
{ .compatible = "allwinner,sun50i-a64-usb-phy",
.data = &sun50i_a64_cfg},
{ },
--
2.11.1
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[linux-sunxi] [RFC PATCH 4/9] clk: sunxi-ng: support R40 SoC
Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. As the user manual is still not available, this driver is made with knowledge from clk-sun8iw11.c in the BSP kernel source. --- drivers/clk/sunxi-ng/Kconfig | 10 + drivers/clk/sunxi-ng/Makefile |1 + drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 1140 + drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 68 ++ include/dt-bindings/clock/sun8i-r40-ccu.h | 189 + include/dt-bindings/reset/sun8i-r40-ccu.h | 128 6 files changed, 1536 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 695bbf9ef428..31d005051b6e 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -131,6 +131,16 @@ config SUN8I_V3S_CCU select SUNXI_CCU_PHASE default MACH_SUN8I +config SUN8I_R40_CCU + bool "Support for the Allwinner R40 CCU" + select SUNXI_CCU_DIV + select SUNXI_CCU_NK + select SUNXI_CCU_NKM + select SUNXI_CCU_NKMP + select SUNXI_CCU_NM + select SUNXI_CCU_MP + default MACH_SUN8I + config SUN9I_A80_CCU bool "Support for the Allwinner A80 CCU" select SUNXI_CCU_DIV diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 6feaac0c5600..3a512b1adcf7 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o obj-$(CONFIG_SUN8I_A33_CCU)+= ccu-sun8i-a33.o obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o obj-$(CONFIG_SUN8I_V3S_CCU)+= ccu-sun8i-v3s.o +obj-$(CONFIG_SUN8I_R40_CCU)+= ccu-sun8i-r40.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-de.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-usb.o diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c new file mode 100644 index ..150e086e9765 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c @@ -0,0 +1,1140 @@ +/* + * Copyright (c) 2016 Icenowy Zheng + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nk.h" +#include "ccu_nkm.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" +#include "ccu_phase.h" + +#include "ccu-sun8i-r40.h" + +static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu", +"osc24M", 0x000, +8, 5, /* N */ +4, 2, /* K */ +0, 2, /* M */ +16, 2, /* P */ +BIT(31), /* gate */ +BIT(28), /* lock */ +0); + +/* + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from + * the base (2x, 4x and 8x), and one variable divider (the one true + * pll audio). + * + * We don't have any need for the variable divider for now, so we just + * hardcode it to match with the clock names + */ +#define SUN8I_R40_PLL_AUDIO_REG0x008 + +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + "osc24M", 0x008, + 8, 7,/* N */ + 0, 5,/* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", + "osc24M", 0x0010, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24),/* frac enable */ + BIT(25),/* frac select */ + 27000, /* frac rate 0 */ + 29700, /* frac rate 1 *
[linux-sunxi] [PATCH 3/9] pinctrl: sunxi: add support for R40 pinctrl
Allwinner R40 have a pin controller similar to A20, only added 8-bit
eMMC function to mmc2 at PC bank.
Add support for it in the already renamed sunxi-a20-r40 driver via
variant framework.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sunxi-a20-r40.c | 161 --
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +
2 files changed, 125 insertions(+), 38 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi-a20-r40.c
b/drivers/pinctrl/sunxi/pinctrl-sunxi-a20-r40.c
index b6f4c68ffb39..a925e6b835bc 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi-a20-r40.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi-a20-r40.c
@@ -18,7 +18,7 @@
#include "pinctrl-sunxi.h"
-static const struct sunxi_desc_pin sun7i_a20_pins[] = {
+static const struct sunxi_desc_pin sunxi_a20_r40_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -146,7 +146,10 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
+ SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
+ SUNXI_FUNCTION_VARIANT(0x3,
+"pll-lock-dbg",
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -154,11 +157,21 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
+ SUNXI_FUNCTION_VARIANT(0x2,
+"pwm", /* PWM0 */
+PINCTRL_SUN7I_A20),
+ SUNXI_FUNCTION_VARIANT(0x3,
+"pwm", /* PWM0 */
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "ir0"), /* TX */
+ SUNXI_FUNCTION_VARIANT(0x2,
+"ir0", /* TX */
+PINCTRL_SUN7I_A20),
+ SUNXI_FUNCTION_VARIANT(0x3,
+"pwm", /* PWM1 */
+PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "spdif")),/* MCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -187,11 +200,17 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "i2s0")), /* DO1 */
+ SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
+ SUNXI_FUNCTION_VARIANT(0x4,
+"pwm", /* PWM6 */
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "i2s0")), /* DO2 */
+ SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
+ SUNXI_FUNCTION_VARIANT(0x4,
+"pwm", /* PWM7 */
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -201,12 +220,16 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DI */
SUNXI_FUNCTION(0x3, "ac97"), /* DI */
- SUNXI_FUNCTION(0x4, "spdif")),/* DI */
+ SUNXI_FUNCTION_VARIANT(0x4,
+"spdif", /* DI */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
- SUNXI_FUNCTION(0x4, "spdif")),/* DO */
+ SUNXI_FUNCTION_VARIANT(0x4,
+"spdif", /* DO
[linux-sunxi] [PATCH 2/9] pinctrl: sunxi: rename sun7i-a20 driver to sunxi-a20-r40
The new R40 SoC come with a largely similar version of the pin
controller in A20.
Rename the driver, in order to extend it with R40 support.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/Kconfig | 2 +-
drivers/pinctrl/sunxi/Makefile | 2 +-
drivers/pinctrl/sunxi/{pinctrl-sun7i-a20.c => pinctrl-sunxi-a20-r40.c} | 0
3 files changed, 2 insertions(+), 2 deletions(-)
rename drivers/pinctrl/sunxi/{pinctrl-sun7i-a20.c => pinctrl-sunxi-a20-r40.c}
(100%)
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 92d845827577..6552cfd5c057 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -26,7 +26,7 @@ config PINCTRL_SUN6I_A31_R
depends on RESET_CONTROLLER
select PINCTRL_SUNXI
-config PINCTRL_SUN7I_A20
+config PINCTRL_SUNXI_A20_R40
def_bool MACH_SUN7I
select PINCTRL_SUNXI
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index f9a3855c42f1..6ceab91c3834 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -7,7 +7,7 @@ obj-$(CONFIG_PINCTRL_SUN5I) += pinctrl-sun5i.o
obj-$(CONFIG_PINCTRL_SUN6I_A31)+= pinctrl-sun6i-a31.o
obj-$(CONFIG_PINCTRL_SUN6I_A31S) += pinctrl-sun6i-a31s.o
obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
-obj-$(CONFIG_PINCTRL_SUN7I_A20)+= pinctrl-sun7i-a20.o
+obj-$(CONFIG_PINCTRL_SUNXI_A20_R40)+= pinctrl-sunxi-a20-r40.o
obj-$(CONFIG_PINCTRL_SUN8I_A23)+= pinctrl-sun8i-a23.o
obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
b/drivers/pinctrl/sunxi/pinctrl-sunxi-a20-r40.c
similarity index 100%
rename from drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
rename to drivers/pinctrl/sunxi/pinctrl-sunxi-a20-r40.c
--
2.11.1
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[linux-sunxi] [PATCH 1/9] arm: sunxi: add support for R40 SoC
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Documentation/arm/sunxi/README | 4
arch/arm/mach-sunxi/sunxi.c| 1 +
2 files changed, 5 insertions(+)
diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index d7b1f016bd62..25c814adcd47 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -75,6 +75,10 @@ SunXi family
+ Datasheet
http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf
+ - Allwinner R40 (sun8i)
++ Datasheet Draft
+ http://linux-sunxi.org/File:Allwinner_R40_Datasheet_V0.1.pdf
+
* Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
- Allwinner A80
+ Datasheet
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index f44e3acb5c90..aea616759451 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -66,6 +66,7 @@ static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-h2-plus",
"allwinner,sun8i-h3",
"allwinner,sun8i-v3s",
+ "allwinner,sun8i-r40",
NULL,
};
--
2.11.1
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[linux-sunxi] [RFC PATCH 0/9] Add support for Allwinner R40 SoC
This patchset is an experiment to add R40 support to mainline Linux.
As we have still no user manual for R40, the patchset is developed
by reading the BSP source code and device tree, educated guess and
try and error.
Note: the PATCH 1~3 and 7 is not RFC (I want them to be merged now),
but they are sent together as they have functional dependency by
RFC patches.
Icenowy Zheng (9):
arm: sunxi: add support for R40 SoC
pinctrl: sunxi: rename sun7i-a20 driver to sunxi-a20-r40
pinctrl: sunxi: add support for R40 pinctrl
clk: sunxi-ng: support R40 SoC
ARM: dts: sun8i: add DTSI file for R40 SoC
ARM: dts: sun8i: add DTS file for Banana Pi M2 Ultra
phy: sun4i-usb: add support for R40 USB PHY
ARM: dts: sun8i: add USB nodes for R40
ARM: dts: sun8i: enable USB host for Banana Pi M2 Ultra
Documentation/arm/sunxi/README |4 +
.../devicetree/bindings/phy/sun4i-usb-phy.txt |1 +
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 184
arch/arm/boot/dts/sun8i-r40.dtsi | 493 +
arch/arm/mach-sunxi/sunxi.c|1 +
drivers/clk/sunxi-ng/Kconfig | 10 +
drivers/clk/sunxi-ng/Makefile |1 +
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 1140
drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 68 ++
drivers/phy/phy-sun4i-usb.c| 17 +-
drivers/pinctrl/sunxi/Kconfig |2 +-
drivers/pinctrl/sunxi/Makefile |2 +-
...pinctrl-sun7i-a20.c => pinctrl-sunxi-a20-r40.c} | 69 +-
drivers/pinctrl/sunxi/pinctrl-sunxi.h |2 +
include/dt-bindings/clock/sun8i-r40-ccu.h | 189
include/dt-bindings/reset/sun8i-r40-ccu.h | 128 +++
17 files changed, 2286 insertions(+), 26 deletions(-)
create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h
rename drivers/pinctrl/sunxi/{pinctrl-sun7i-a20.c => pinctrl-sunxi-a20-r40.c}
(95%)
create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h
create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h
--
2.11.1
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[linux-sunxi] Re: [PATCH 05/21] net-next: stmmac: Add dwmac-sun8i
On Thu, Feb 16, 2017 at 08:05:24PM +0100, Maxime Ripard wrote:
> Hi,
>
[...]
> > +
> > +struct emac_variant {
> > + u32 default_syscon_value;
>
> Why do you need a default value? Can't you read it from the syscon
> directly?
>
Why not, but you can see the default value as "value for disabled state".
My fear is that something (uboot) modify it (keep it activated) before driver
load.
[...]
> > +static void sun8i_dwmac_dump_regs(void __iomem *ioaddr)
> > +{
> > + int i;
> > +
> > + pr_info(" DMA registers\n");
>
> Logging this as pr_info is bad already...
>
> > + for (i = 0; i < 0xC8; i += 4) {
> > + if (i == 0x32 || i == 0x3C)
> > + continue;
> > + pr_err("Reg 0x%x: 0x%08x\n", i, readl(ioaddr + i));
>
> ... But this is worse.
>
> Why do you need to do that? Can't you create a file in debugfs
> instead?
>
I just do as other glue does. But yes this is uglyi, no excuse.
Reworking all stmmac register dump (ethtool, stmmac_ops->dump_regs and
stmmac_dma_ops->dump_regs) was on my todo list,
but I postponed it.
I will propose something better based on debugfs.
[...]
> > +static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr)
> > +{
> > + u32 v;
> > +
> > + v = readl(ioaddr + EMAC_TX_CTL0);
> > + v |= EMAC_TX_TRANSMITTER_EN;
> > + writel(v, ioaddr + EMAC_TX_CTL0);
> > +
> > + v = readl(ioaddr + EMAC_TX_CTL1);
> > + v |= EMAC_TX_DMA_START;
> > + v |= EMAC_TX_DMA_EN;
> > + writel(v, ioaddr + EMAC_TX_CTL1);
>
> This is a bit worrying. There's not a single lock in your driver,
> while you have a significant number of read / modify / write.
>
> Where is the locking handled?
>
All thoses function are handled by the "stmmac_ops framework", all other glue
drivers does not lock anything.
The few functions that need locking already got it on the calling stmmac side.
[...]
> > +static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
> > +{
> > + struct sunxi_priv_data *gmac = priv;
> > + int ret;
> > +
> > + if (gmac->regulator) {
> > + ret = regulator_enable(gmac->regulator);
> > + if (ret) {
> > + dev_err(&pdev->dev, "Fail to enable regulator\n");
> > + return ret;
> > + }
> > + }
> > +
> > + ret = clk_prepare_enable(gmac->tx_clk);
> > + if (ret) {
> > + dev_err(&pdev->dev, "Could not enable AHB clock\n");
>
> If that call fails, you leave the regulator (if there was any) enabled.
>
I will fix it
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void sun8i_dwmac_core_init(struct mac_device_info *hw, int mtu)
> > +{
> > + void __iomem *ioaddr = hw->pcsr;
> > + u32 v;
> > +
> > + v = (8 << 24);/* burst len */
> > + writel(v, ioaddr + EMAC_BASIC_CTL1);
>
> do you need an intermediate value? you should make a define for that
> too.
>
I will fix it
[...]
> > +static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
> > +{
> > + struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
> > + struct device_node *node = priv->device->of_node;
> > + int ret;
> > + u32 reg, val;
> > +
> > + reg = gmac->variant->default_syscon_value;
> > +
> > + if (gmac->variant->internal_phy) {
> > + if (!gmac->use_internal_phy) {
> > + /* switch to external PHY interface */
> > + reg &= ~H3_EPHY_SELECT;
> > + } else {
> > + reg |= H3_EPHY_SELECT;
> > + reg &= ~H3_EPHY_SHUTDOWN;
> > + dev_info(priv->device, "Select internal_phy %x\n", reg);
>
> The logging level is too high
>
I will reduce it
> > +
> > + if (of_property_read_bool(priv->plat->phy_node,
> > + "allwinner,leds-active-low"))
> > + reg |= H3_EPHY_LED_POL;
> > + else
> > + reg &= ~H3_EPHY_LED_POL;
> > +
> > + ret = of_mdio_parse_addr(priv->device,
> > +priv->plat->phy_node);
> > + if (ret < 0) {
> > + dev_err(priv->device, "Could not parse MDIO
> > addr\n");
> > + return ret;
> > + }
> > + /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
> > +* address. No need to mask it again.
> > +*/
> > + reg |= ret << H3_EPHY_ADDR_SHIFT;
> > + }
> > + }
> > +
> > + if (!of_property_read_u32(node, "allwinner,tx-delay", &val)) {
>
> How do you compute it? Can't this be done through auto-training?
>
The value is the same as used in vendor BSP kernel.
I do not understand what you mean by auto-training.
> > + dev_info(priv->device, "set tx-delay to %x\n", val);
>
> change the logging level here too.
>
I agree
> > + if (val <= SYSCON_ETXDC_MASK) {
> > +
[linux-sunxi] Re: [PATCH 04/21] ARM: sun8i: dt: Add DT bindings documentation for Allwinner dwmac-sun8i
On Thu, Feb 16, 2017 at 07:48:18PM +0100, Maxime Ripard wrote: > Hi, > > On Thu, Feb 16, 2017 at 01:48:42PM +0100, Corentin Labbe wrote: > > This patch adds documentation for Device-Tree bindings for the > > Allwinner dwmac-sun8i driver. > > > > Signed-off-by: Corentin Labbe > > --- > > .../devicetree/bindings/net/dwmac-sun8i.txt| 86 > > ++ > > 1 file changed, 86 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt > > > > diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt > > b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt > > new file mode 100644 > > index 000..ac806c6 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt > > @@ -0,0 +1,86 @@ > > +* Allwinner sun8i GMAC ethernet controller > > + > > +This device is a platform glue layer for stmmac. > > +Please see stmmac.txt for the other unchanged properties. > > + > > +Required properties: > > +- compatible: should be one of the following string: > > + "allwinner,sun8i-a83t-emac" > > + "allwinner,sun8i-h3-emac" > > + "allwinner,sun50i-a64-emac" > > +- reg: address and length of the register for the device. > > +- interrupts: interrupt for the device > > +- interrupt-names: should be "macirq" > > +- clocks: A phandle to the reference clock for this device > > +- clock-names: should be "stmmaceth" > > +- resets: A phandle to the reset control for this device > > +- reset-names: should be "stmmaceth" > > +- phy-mode: See ethernet.txt > > +- phy-handle: See ethernet.txt > > +- #address-cells: shall be 1 > > +- #size-cells: shall be 0 > > +- syscon: A phandle to the syscon of the SoC with one of the following > > + compatible string: > > + - allwinner,sun8i-h3-system-controller > > + - allwinner,sun8i-a64-system-controller > > + - allwinner,sun8i-a83t-system-controller > > + > > +Optional properties: > > +- allwinner,tx-delay: TX clock delay chain value. Range value is 0-0x07. > > Default is 0) > > +- allwinner,rx-delay: RX clock delay chain value. Range value is 0-0x1F. > > Default is 0) > > +Both delay properties does not have units, there are arbitrary value. > > +The TX/RX clock delay chain settings are board specific and could be found > > +in vendor FEX files. > > + > > +Optional properties for "allwinner,sun8i-h3-emac": > > +- allwinner,leds-active-low: EPHY LEDs are active low > > + > > +Required child node of emac: > > +- mdio bus node: should be named mdio > > + > > +Required properties of the mdio node: > > +- #address-cells: shall be 1 > > +- #size-cells: shall be 0 > > + > > +The device node referenced by "phy" or "phy-handle" should be a child node > > +of the mdio node. See phy.txt for the generic PHY bindings. > > + > > +Required properties of the phy node with "allwinner,sun8i-h3-emac": > > +- clocks: an extra phandle to the reference clock for the EPHY > > +- resets: an extra phandle to the reset control for the EPHY > > + > > +Required properties for the system controller: > > +- reg: address and length of the register for the device. > > +- compatible: should be "syscon" and one of the following string: > > + "allwinner,sun8i-h3-system-controller" > > + "allwinner,sun8i-a64-system-controller" > > + "allwinner,sun8i-a83t-system-controller" > > This should be in a separate binding document. > > What does it describe / represent? > > Thanks, > Maxime > I agree, I will split it in two one for syscon, one for emac Thanks Corentin Labbe -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH 08/21] ARM: dts: sun8i-h3: add dwmac-sun8i rgmii pins
On Thu, Feb 16, 2017 at 08:06:32PM +0100, Maxime Ripard wrote:
> On Thu, Feb 16, 2017 at 01:48:46PM +0100, Corentin Labbe wrote:
> > This patch add pinctrl node for dwmac-sun8i on H3.
> >
> > Signed-off-by: Corentin Labbe
> > ---
> > arch/arm/boot/dts/sun8i-h3.dtsi | 11 +++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
> > b/arch/arm/boot/dts/sun8i-h3.dtsi
> > index 61d56d2..59ed40e 100644
> > --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> > @@ -349,6 +349,17 @@
> > function = "i2c2";
> > };
> >
> > + emac_rgmii_pins: emac0@0 {
> > + allwinner,pins = "PD0", "PD1", "PD2", "PD3",
> > + "PD4", "PD5", "PD7",
> > + "PD8", "PD9", "PD10",
> > + "PD12", "PD13", "PD15",
> > + "PD16", "PD17";
> > + allwinner,function = "emac";
>
> Please use the generic pin config properties (ie. pins and functions).
>
> > + allwinner,drive = ;
>
> Why do you need to use 40mA?
>
> > + allwinner,pull = ;
>
> This is the default now.
>
Will fix that in all DT
Thanks
Corentin Labbe
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[linux-sunxi] Re: [PATCH 20/21] ARM: sunxi: Enable dwmac-sun8i driver on sunxi_defconfig
On Thu, Feb 16, 2017 at 08:08:27PM +0100, Maxime Ripard wrote: > Hi, > > On Thu, Feb 16, 2017 at 01:48:58PM +0100, Corentin Labbe wrote: > > From: LABBE Corentin > > > > Enable the dwmac-sun8i driver in the sunxi default configuration > > > > Signed-off-by: Corentin Labbe > > --- > > arch/arm/configs/sunxi_defconfig | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm/configs/sunxi_defconfig > > b/arch/arm/configs/sunxi_defconfig > > index da92c25..33bde86 100644 > > --- a/arch/arm/configs/sunxi_defconfig > > +++ b/arch/arm/configs/sunxi_defconfig > > @@ -40,6 +40,7 @@ CONFIG_ATA=y > > CONFIG_AHCI_SUNXI=y > > CONFIG_NETDEVICES=y > > CONFIG_SUN4I_EMAC=y > > +CONFIG_DWMAC_SUN8I=m > > I think I'd prefer to have it compiled statically, just like the other > net drivers, and drivers in general. > > Thanks! > Maxime > In previous sun8i-emac, someone request that CONFIG must be set as module because kernel went too big. But I do not care to set it statically. Regards Corentin Labbe -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH 08/21] ARM: dts: sun8i-h3: add dwmac-sun8i rgmii pins
On Thu, Feb 16, 2017 at 01:48:46PM +0100, Corentin Labbe wrote:
> This patch add pinctrl node for dwmac-sun8i on H3.
>
> Signed-off-by: Corentin Labbe
> ---
> arch/arm/boot/dts/sun8i-h3.dtsi | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index 61d56d2..59ed40e 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -349,6 +349,17 @@
> function = "i2c2";
> };
>
> + emac_rgmii_pins: emac0@0 {
> + allwinner,pins = "PD0", "PD1", "PD2", "PD3",
> + "PD4", "PD5", "PD7",
> + "PD8", "PD9", "PD10",
> + "PD12", "PD13", "PD15",
> + "PD16", "PD17";
> + allwinner,function = "emac";
Please use the generic pin config properties (ie. pins and functions).
> + allwinner,drive = ;
Why do you need to use 40mA?
> + allwinner,pull = ;
This is the default now.
Thanks!
Maxime
--
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[linux-sunxi] Re: [PATCH v3 2/4] pwm: sunxi: Selectable prescaler table for support sun6i.
On Wed, Feb 15, 2017 at 11:06:05PM +0300, lis8...@gmail.com wrote: > From: Siarhei Volkau > > This patch not introduce new features, just prepare code for adding > sun6i PWM driver in next commit. > > A31 SoC have a different set of prescalers than sun4i > compatible ASoCs, but its position and count in the control > register are the same. > > This patch make the table of prescalers customizable. > > Signed-off-by: Siarhei Volkau Acked-by: Maxime Ripard Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v3 1/4] pwm: sunxi: Code switched to regmap API instead of iomem.
Hi,
On Wed, Feb 15, 2017 at 11:06:04PM +0300, lis8...@gmail.com wrote:
> From: Siarhei Volkau
>
> sun6i PWM has different register map in comparison to sun4i compatible
> SoCs. But bit map of the registers and behavior are very similar.
>
> This patch introduces a uniform way to access PWM registers.
>
> Signed-off-by: Siarhei Volkau
In order to be easier to review (and bisect if needed), could you
split that patch into one to convert to the regmap API, without any
change but to replace the sun4i_pwm_readl/sun4i_pwm_writel calls by
their regmap equivalent, and then convert to the regmap fields the
registers that need to?
> ---
> drivers/pwm/Kconfig | 2 +-
> drivers/pwm/pwm-sun4i.c | 263
> ++--
> 2 files changed, 191 insertions(+), 74 deletions(-)
>
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index 2d0cfaa..6b4dc1a 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -416,7 +416,7 @@ config PWM_STMPE
> config PWM_SUN4I
> tristate "Allwinner PWM support"
> depends on ARCH_SUNXI || COMPILE_TEST
> - depends on HAS_IOMEM && COMMON_CLK
> + depends on REGMAP_MMIO && COMMON_CLK
> help
> Generic PWM framework driver for Allwinner SoCs.
>
> diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> index b0803f6..7291000 100644
> --- a/drivers/pwm/pwm-sun4i.c
> +++ b/drivers/pwm/pwm-sun4i.c
> @@ -9,7 +9,7 @@
> #include
> #include
> #include
> -#include
> +#include
> #include
> #include
> #include
> @@ -26,25 +26,56 @@
> #define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET *
> (ch))
>
> #define PWMCH_OFFSET 15
> -#define PWM_PRESCAL_MASK GENMASK(3, 0)
> -#define PWM_PRESCAL_OFF 0
> -#define PWM_EN BIT(4)
> -#define PWM_ACT_STATEBIT(5)
> -#define PWM_CLK_GATING BIT(6)
> -#define PWM_MODE BIT(7)
> -#define PWM_PULSEBIT(8)
> -#define PWM_BYPASS BIT(9)
> +
> +#define PWM_PRESCAL_LSB 0
> +#define PWM_PRESCAL_MSB 3
> +#define PWM_PRESCAL_MASK GENMASK(PWM_PRESCAL_MSB - PWM_PRESCAL_LSB, 0)
> +
> +#define PWM_EN_BIT 4
> +#define PWM_ACT_STATE_BIT5
> +#define PWM_CLK_GATING_BIT 6
> +#define PWM_MODE_BIT 7
> +#define PWM_PULSE_BIT8
> +#define PWM_BYPASS_BIT 9
>
> #define PWM_RDY_BASE 28
> #define PWM_RDY_OFFSET 1
> -#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
> +#define PWM_RDY_BIT(ch) (PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
>
> #define PWM_PRD(prd) (((prd) - 1) << 16)
> #define PWM_PRD_MASK GENMASK(15, 0)
>
> #define PWM_DTY_MASK GENMASK(15, 0)
>
> -#define BIT_CH(bit, chan)((bit) << ((chan) * PWMCH_OFFSET))
> +#define BIT_CH(bit, chan)((bit) + ((chan) * PWMCH_OFFSET))
> +
> +#define FIELD_PRESCALER 0
> +#define FIELD_POLARITY 1
> +#define FIELD_CLK_GATING 2
> +#define FIELD_READY 3
> +#define NUM_FIELDS 4
> +
> +#define MAX_CHANNELS 2
> +
> +#define SUN4I_REGMAP_FIELDS(chan) {\
> + [FIELD_PRESCALER] = \
> + REG_FIELD(PWM_CTRL_REG, \
> + BIT_CH(PWM_PRESCAL_LSB, chan), \
> + BIT_CH(PWM_PRESCAL_MSB, chan)), \
> + [FIELD_POLARITY] = \
> + REG_FIELD(PWM_CTRL_REG, \
> + BIT_CH(PWM_ACT_STATE_BIT, chan), \
> + BIT_CH(PWM_ACT_STATE_BIT, chan)), \
> + [FIELD_CLK_GATING] = \
> + REG_FIELD(PWM_CTRL_REG, \
> + BIT_CH(PWM_CLK_GATING_BIT, chan), \
> + BIT_CH(PWM_CLK_GATING_BIT, chan)), \
> + [FIELD_READY] = \
> + REG_FIELD(PWM_CTRL_REG, \
> + PWM_RDY_BIT(chan), \
> + PWM_RDY_BIT(chan)), \
> +}
> +
This is not correct, unfortunately. If someone calls that macro with
chan++ or chan--, it will be modified four times instead of one as the
caller would expect.
Thanks!
Maxime
--
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[linux-sunxi] Re: [PATCH 20/21] ARM: sunxi: Enable dwmac-sun8i driver on sunxi_defconfig
Hi, On Thu, Feb 16, 2017 at 01:48:58PM +0100, Corentin Labbe wrote: > From: LABBE Corentin > > Enable the dwmac-sun8i driver in the sunxi default configuration > > Signed-off-by: Corentin Labbe > --- > arch/arm/configs/sunxi_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/configs/sunxi_defconfig > b/arch/arm/configs/sunxi_defconfig > index da92c25..33bde86 100644 > --- a/arch/arm/configs/sunxi_defconfig > +++ b/arch/arm/configs/sunxi_defconfig > @@ -40,6 +40,7 @@ CONFIG_ATA=y > CONFIG_AHCI_SUNXI=y > CONFIG_NETDEVICES=y > CONFIG_SUN4I_EMAC=y > +CONFIG_DWMAC_SUN8I=m I think I'd prefer to have it compiled statically, just like the other net drivers, and drivers in general. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH 04/21] ARM: sun8i: dt: Add DT bindings documentation for Allwinner dwmac-sun8i
Hi, On Thu, Feb 16, 2017 at 01:48:42PM +0100, Corentin Labbe wrote: > This patch adds documentation for Device-Tree bindings for the > Allwinner dwmac-sun8i driver. > > Signed-off-by: Corentin Labbe > --- > .../devicetree/bindings/net/dwmac-sun8i.txt| 86 > ++ > 1 file changed, 86 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt > > diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt > b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt > new file mode 100644 > index 000..ac806c6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt > @@ -0,0 +1,86 @@ > +* Allwinner sun8i GMAC ethernet controller > + > +This device is a platform glue layer for stmmac. > +Please see stmmac.txt for the other unchanged properties. > + > +Required properties: > +- compatible: should be one of the following string: > + "allwinner,sun8i-a83t-emac" > + "allwinner,sun8i-h3-emac" > + "allwinner,sun50i-a64-emac" > +- reg: address and length of the register for the device. > +- interrupts: interrupt for the device > +- interrupt-names: should be "macirq" > +- clocks: A phandle to the reference clock for this device > +- clock-names: should be "stmmaceth" > +- resets: A phandle to the reset control for this device > +- reset-names: should be "stmmaceth" > +- phy-mode: See ethernet.txt > +- phy-handle: See ethernet.txt > +- #address-cells: shall be 1 > +- #size-cells: shall be 0 > +- syscon: A phandle to the syscon of the SoC with one of the following > + compatible string: > + - allwinner,sun8i-h3-system-controller > + - allwinner,sun8i-a64-system-controller > + - allwinner,sun8i-a83t-system-controller > + > +Optional properties: > +- allwinner,tx-delay: TX clock delay chain value. Range value is 0-0x07. > Default is 0) > +- allwinner,rx-delay: RX clock delay chain value. Range value is 0-0x1F. > Default is 0) > +Both delay properties does not have units, there are arbitrary value. > +The TX/RX clock delay chain settings are board specific and could be found > +in vendor FEX files. > + > +Optional properties for "allwinner,sun8i-h3-emac": > +- allwinner,leds-active-low: EPHY LEDs are active low > + > +Required child node of emac: > +- mdio bus node: should be named mdio > + > +Required properties of the mdio node: > +- #address-cells: shall be 1 > +- #size-cells: shall be 0 > + > +The device node referenced by "phy" or "phy-handle" should be a child node > +of the mdio node. See phy.txt for the generic PHY bindings. > + > +Required properties of the phy node with "allwinner,sun8i-h3-emac": > +- clocks: an extra phandle to the reference clock for the EPHY > +- resets: an extra phandle to the reset control for the EPHY > + > +Required properties for the system controller: > +- reg: address and length of the register for the device. > +- compatible: should be "syscon" and one of the following string: > + "allwinner,sun8i-h3-system-controller" > + "allwinner,sun8i-a64-system-controller" > + "allwinner,sun8i-a83t-system-controller" This should be in a separate binding document. What does it describe / represent? Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH 05/21] net-next: stmmac: Add dwmac-sun8i
Hi,
On Thu, Feb 16, 2017 at 01:48:43PM +0100, Corentin Labbe wrote:
> The dwmac-sun8i is a heavy hacked version of stmmac hardware by
> allwinner.
> In fact the only common part is the descriptor management and the first
> register function.
>
> Signed-off-by: Corentin Labbe
> ---
> drivers/net/ethernet/stmicro/stmmac/Kconfig| 11 +
> drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
> drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 892
> +
> .../net/ethernet/stmicro/stmmac/stmmac_ethtool.c | 3 +
> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 27 +-
> .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 9 +-
> include/linux/stmmac.h | 1 +
> 7 files changed, 941 insertions(+), 3 deletions(-)
> create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig
> b/drivers/net/ethernet/stmicro/stmmac/Kconfig
> index cfbe363..85c0e41 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
> +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
> @@ -145,6 +145,17 @@ config DWMAC_SUNXI
> This selects Allwinner SoC glue layer support for the
> stmmac device driver. This driver is used for A20/A31
> GMAC ethernet controller.
> +
> +config DWMAC_SUN8I
> + tristate "Allwinner sun8i GMAC support"
> + default ARCH_SUNXI
> + depends on OF && (ARCH_SUNXI || COMPILE_TEST)
> + ---help---
> + Support for Allwinner H3 A83T A64 EMAC ethernet controllers.
> +
> + This selects Allwinner SoC glue layer support for the
> + stmmac device driver. This driver is used for H3/A83T/A64
> + EMAC ethernet controller.
> endif
>
> config STMMAC_PCI
> diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile
> b/drivers/net/ethernet/stmicro/stmmac/Makefile
> index 700c603..fd4937a 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/Makefile
> +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o
> obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o
> obj-$(CONFIG_DWMAC_STM32)+= dwmac-stm32.o
> obj-$(CONFIG_DWMAC_SUNXI)+= dwmac-sunxi.o
> +obj-$(CONFIG_DWMAC_SUN8I)+= dwmac-sun8i.o
> obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o
> obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o
> stmmac-platform-objs:= stmmac_platform.o
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> new file mode 100644
> index 000..0951eb9
> --- /dev/null
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> @@ -0,0 +1,892 @@
> +/*
> + * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
> + *
> + * Copyright (C) 2017 Corentin Labbe
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "stmmac.h"
> +#include "stmmac_platform.h"
> +
> +struct emac_variant {
> + u32 default_syscon_value;
Why do you need a default value? Can't you read it from the syscon
directly?
> + int internal_phy;
> + bool support_mii;
> + bool support_rmii;
> + bool support_rgmii;
> +};
> +
> +struct sunxi_priv_data {
> + struct clk *tx_clk;
> + struct clk *ephy_clk;
> + struct regulator *regulator;
> + struct reset_control *rst_ephy;
> + const struct emac_variant *variant;
> + bool use_internal_phy;
> + struct regmap *regmap;
> +};
> +
> +static const struct emac_variant emac_variant_h3 = {
> + .default_syscon_value = 0x58000,
> + .internal_phy = PHY_INTERFACE_MODE_MII,
> + .support_mii = true,
> + .support_rmii = true,
> + .support_rgmii = true
> +};
> +
> +static const struct emac_variant emac_variant_a83t = {
> + .default_syscon_value = 0,
> + .internal_phy = 0,
> + .support_mii = true,
> + .support_rgmii = true
> +};
> +
> +static const struct emac_variant emac_variant_a64 = {
> + .default_syscon_value = 0,
> + .internal_phy = 0,
> + .support_mii = true,
> + .support_rmii = true,
> + .support_rgmii = true
> +};
> +
> +#define EMAC_BASIC_CTL0 0x00
> +#define EMAC_BASIC_CTL1 0x04
> +#define EMAC_INT_STA0x08
> +#define EMAC_INT_EN 0x0C
> +#define EMAC_TX_CTL00x10
> +#define EMAC_TX_CTL10x14
> +#define E
Re: [linux-sunxi] [PATCH 03/21] net-next: stmmac: add optional setup function
On Thu, Feb 16, 2017 at 09:38:33PM +0100, Peter Korsgaard wrote: > > "Corentin" == Corentin Labbe writes: > > > Instead of ading more ifthen login for adding a new mac_device_info > > s/login/logic/ > > -- > Bye, Peter Korsgaard Thanks, will fix it. Regards Corentin Labbe -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
