[linux-sunxi] Re: [PATCH v2] iio: adc: sun4i-gpadc-iio: fix parent device being used in devm function
On Thu, May 18, 2017 at 08:36:07AM +0200, Quentin Schulz wrote:
> For the sake of DT binding stability, this IIO driver is a child of an
> MFD driver for Allwinner A10, A13 and A31 because there already exists a
> DT binding for this IP. The MFD driver has a DT node but the IIO driver
> does not.
>
> The IIO device registers the temperature sensor in the thermal framework
> using the DT node of the parent, the MFD device, so the thermal
> framework could match the phandle to the MFD device in the DT and the
> struct device used to register in the thermal framework.
>
> devm_thermal_zone_of_sensor_register was previously used to register the
> thermal sensor with the parent struct device of the IIO device,
> representing the MFD device. By doing so, we registered actually the
> parent in the devm routine and not the actual IIO device.
>
> This lead to the devm unregister function not being called when the IIO
> module driver is removed. It resulted in the thermal framework still
> polling the get_temp function of the IIO module while the device doesn't
> exist anymore, thus generated a kernel panic.
>
> Use the non-devm function instead and do the unregister manually in the
> remove function.
>
> Fixes: d1caa9905538 ("iio: adc: add support for Allwinner SoCs ADC")
>
> Signed-off-by: Quentin Schulz
> Reported-by: Corentin Labbe
Reviewed-by: Maxime Ripard
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[linux-sunxi] [PATCH v2] iio: adc: sun4i-gpadc-iio: fix parent device being used in devm function
For the sake of DT binding stability, this IIO driver is a child of an
MFD driver for Allwinner A10, A13 and A31 because there already exists a
DT binding for this IP. The MFD driver has a DT node but the IIO driver
does not.
The IIO device registers the temperature sensor in the thermal framework
using the DT node of the parent, the MFD device, so the thermal
framework could match the phandle to the MFD device in the DT and the
struct device used to register in the thermal framework.
devm_thermal_zone_of_sensor_register was previously used to register the
thermal sensor with the parent struct device of the IIO device,
representing the MFD device. By doing so, we registered actually the
parent in the devm routine and not the actual IIO device.
This lead to the devm unregister function not being called when the IIO
module driver is removed. It resulted in the thermal framework still
polling the get_temp function of the IIO module while the device doesn't
exist anymore, thus generated a kernel panic.
Use the non-devm function instead and do the unregister manually in the
remove function.
Fixes: d1caa9905538 ("iio: adc: add support for Allwinner SoCs ADC")
Signed-off-by: Quentin Schulz
Reported-by: Corentin Labbe
---
v2:
- save struct device used to register in thermal framework in
sun4i_gpadc_iio,
- use this struct device to unregister from thermal framework instead
of doing a condition on pdev->dev.of_node,
- check if CONFIG_THERMAL_OF is enabled before unregistering from
thermal,
drivers/iio/adc/sun4i-gpadc-iio.c | 36 ++--
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index b23527309088..11f7d7745614 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -105,6 +105,8 @@ struct sun4i_gpadc_iio {
boolno_irq;
/* prevents concurrent reads of temperature and ADC */
struct mutexmutex;
+ struct thermal_zone_device *tzd;
+ struct device *sensor_device;
};
#define SUN4I_GPADC_ADC_CHANNEL(_channel, _name) { \
@@ -502,7 +504,6 @@ static int sun4i_gpadc_probe_dt(struct platform_device
*pdev,
{
struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
const struct of_device_id *of_dev;
- struct thermal_zone_device *tzd;
struct resource *mem;
void __iomem *base;
int ret;
@@ -532,13 +533,14 @@ static int sun4i_gpadc_probe_dt(struct platform_device
*pdev,
if (!IS_ENABLED(CONFIG_THERMAL_OF))
return 0;
- tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, info,
- &sun4i_ts_tz_ops);
- if (IS_ERR(tzd))
+ info->sensor_device = &pdev->dev;
+ info->tzd = thermal_zone_of_sensor_register(info->sensor_device, 0,
+ info, &sun4i_ts_tz_ops);
+ if (IS_ERR(info->tzd))
dev_err(&pdev->dev, "could not register thermal sensor: %ld\n",
- PTR_ERR(tzd));
+ PTR_ERR(info->tzd));
- return PTR_ERR_OR_ZERO(tzd);
+ return PTR_ERR_OR_ZERO(info->tzd);
}
static int sun4i_gpadc_probe_mfd(struct platform_device *pdev,
@@ -584,15 +586,15 @@ static int sun4i_gpadc_probe_mfd(struct platform_device
*pdev,
* of_node, and the device from this driver as third argument to
* return the temperature.
*/
- struct thermal_zone_device *tzd;
- tzd = devm_thermal_zone_of_sensor_register(pdev->dev.parent, 0,
- info,
- &sun4i_ts_tz_ops);
- if (IS_ERR(tzd)) {
+ info->sensor_device = pdev->dev.parent;
+ info->tzd = thermal_zone_of_sensor_register(info->sensor_device,
+ 0, info,
+ &sun4i_ts_tz_ops);
+ if (IS_ERR(info->tzd)) {
dev_err(&pdev->dev,
"could not register thermal sensor: %ld\n",
- PTR_ERR(tzd));
- return PTR_ERR(tzd);
+ PTR_ERR(info->tzd));
+ return PTR_ERR(info->tzd);
}
} else {
indio_dev->num_channels =
@@ -688,7 +690,13 @@ static int sun4i_gpadc_remove(struct platform_device *pdev)
pm_runtime_put(&pdev->dev);
pm_runtime_disable(&pdev->dev);
- if (!info->no_irq && IS_ENABLED(CONFIG_THERMAL_OF))
+
+ if (!IS_ENABLED(CONFIG_THERMAL_OF))
+ return 0;
+
+ thermal_zone_of_sensor_unregister(i
[linux-sunxi] [PATCH v3 4/6] ARM: sun8i: a83t: Add CCU device nodes
Now that we have support for the A83T CCU, add a device node for it,
and replace any existing placeholder clock phandles with the correct
ones.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index c0a1e4f74b89..c9a5d07b2ada 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -162,13 +162,23 @@
#size-cells = <1>;
ranges;
+ ccu: clock@1c2 {
+ compatible = "allwinner,sun8i-a83t-ccu";
+ reg = <0x01c2 0x400>;
+ clocks = <&osc24M>, <&osc16Md512>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
pio: pinctrl@1c20800 {
compatible = "allwinner,sun8i-a83t-pinctrl";
interrupts = ,
,
;
reg = <0x01c20800 0x400>;
- clocks = <&osc24M>;
+ clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
@@ -214,7 +224,8 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc24M>;
+ clocks = <&ccu 53>;
+ resets = <&ccu 40>;
status = "disabled";
};
--
2.11.0
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[linux-sunxi] [PATCH v3 3/6] clk: sunxi-ng: Add driver for A83T CCU
The A83T clock control unit is a hybrid of some new style clock designs
from the A80, and old style layout from the other Allwinner SoCs.
Like the A80, the SoC does not have a low speed 32.768 kHz oscillator.
Unlike the A80, there is no clock input either. The only low speed clock
available is the internal oscillator which runs at around 16 MHz,
divided by 512, yielding a low speed clock around 31.250 kHz.
Also, the MMC2 module clock supports switching to a "new timing" mode.
This mode divides the clock output by half, and disables the CCU based
clock delays. The MMC controller must be configure to the same mode,
and then use its internal clock delays.
This driver does not support runtime switching of the timing modes.
Instead, the new timing mode is enforced at probe time. Consumers can
check which mode is active by trying to get the current phase delay
of the MMC2 phase clocks, which will return -ENOTSUPP if the new
timing mode is active.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/Kconfig | 11 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 910 +
drivers/clk/sunxi-ng/ccu-sun8i-a83t.h | 64 ++
include/dt-bindings/clock/sun8i-a83t-ccu.h | 140 +
include/dt-bindings/reset/sun8i-a83t-ccu.h | 98
6 files changed, 1224 insertions(+)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-a83t.h
create mode 100644 include/dt-bindings/clock/sun8i-a83t-ccu.h
create mode 100644 include/dt-bindings/reset/sun8i-a83t-ccu.h
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 747662565545..e2f14c5d6684 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -116,6 +116,17 @@ config SUN8I_A33_CCU
default MACH_SUN8I
depends on MACH_SUN8I || COMPILE_TEST
+config SUN8I_A83T_CCU
+ bool "Support for the Allwinner A83T CCU"
+ select SUNXI_CCU_DIV
+ select SUNXI_CCU_GATE
+ select SUNXI_CCU_MP
+ select SUNXI_CCU_MUX
+ select SUNXI_CCU_NKMP
+ select SUNXI_CCU_NM
+ select SUNXI_CCU_PHASE
+ default MACH_SUN8I
+
config SUN8I_H3_CCU
bool "Support for the Allwinner H3 CCU"
select SUNXI_CCU_DIV
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index be616279450e..0185c6ffadcb 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o
obj-$(CONFIG_SUN6I_A31_CCU)+= ccu-sun6i-a31.o
obj-$(CONFIG_SUN8I_A23_CCU)+= ccu-sun8i-a23.o
obj-$(CONFIG_SUN8I_A33_CCU)+= ccu-sun8i-a33.o
+obj-$(CONFIG_SUN8I_A83T_CCU) += ccu-sun8i-a83t.o
obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
obj-$(CONFIG_SUN8I_V3S_CCU)+= ccu-sun8i-v3s.o
obj-$(CONFIG_SUN8I_DE2_CCU)+= ccu-sun8i-de2.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
new file mode 100644
index ..b64a9bf1f215
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
@@ -0,0 +1,910 @@
+/*
+ * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mux.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+#include "ccu_phase.h"
+
+#include "ccu-sun8i-a83t.h"
+
+#define CCU_SUN8I_A83T_LOCK_REG0x208
+
+static struct clk_div_table pll_cpux_p_div_table[] = {
+ { .val = 0, .div = 1 },
+ { .val = 1, .div = 4 },
+ { /* Sentinel */ },
+};
+
+/*
+ * The CPU PLLs are actually NP clocks, but P is /1 or /4, so here we
+ * use the NM clocks with a divider table for M.
+ */
+static struct ccu_nm pll_c0cpux_clk = {
+ .enable = BIT(31),
+ .lock = BIT(0),
+ .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
+ .m = _SUNXI_CCU_DIV_TABLE(16, 1, pll_cpux_p_div_table),
+ .common = {
+ .reg= 0x000,
+ .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
+ .features = CCU_FEATURE_LOCK_REG,
+ .hw.init= CLK_HW_INIT("pll-c0cpux", "osc24M",
+ &ccu_nm_ops, CLK_SET_RATE_UNGATE),
+ },
+};
+
+static struct ccu_nm pll_c1cpux_clk = {
+ .enable = BIT(31),
+
[linux-sunxi] [PATCH v3 6/6] ARM: sun8i: a83t: Switch to CCU device tree binding macros
Now that the CCU device tree binding headers have been merged, we can
use the properly named macros in the device tree, instead of raw
numbers.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index e12dd7170b8f..050d3e347740 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -44,6 +44,9 @@
#include
+#include
+#include
+
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
@@ -178,7 +181,7 @@
,
;
reg = <0x01c20800 0x400>;
- clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
@@ -225,8 +228,8 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 53>;
- resets = <&ccu 40>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
--
2.11.0
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[linux-sunxi] [PATCH v3 0/6] clk: sunxi-ng: Add support for A83T CCU
Hi everyone, This is v3 of my A83T CCU series. This is for 4.13. Changes since v2: - Dropped patches "clk: Provide option to query hardware for clk phase" and "clk: sunxi-ng: Add class of phase clocks supporting MMC new timing modes". - Dropped support for MMC new timing mode. This will be added later with MMC support. The goal for this series is to get clk support for the A83t in. This is long overdue. - Explicitly include ccu_mux.h and select SUNXI_CCU_MUX Changes since v1: - Dropped two patches that were merged - Added clk core flag to disable caching of clock phases - Added support for multiple variable pre-dividers - Merged "pll-periph-ahb1" pre-divider clock into "ahb1" clock with multiple variable pre-dividers - Introduced new class of phase clocks that return -ENOTSUPP when the clock is in new timing mode - Force mmc2 clock to new timing mode - Added back mmc2 output and sample clocks - Fixed bit ops for forcing audio PLL configuration - Added requirement for "losc" clock in device tree binding - Stripped leading 0 in device node name - Updated subject prefixes for various patches Patch 1 adds a compatible string for the A83T CCU to the sunxi-ccu bindings. Patch 2 adds support for multiple variable pre-dividers to the sunxi-ng mux class. Patch 3 adds the driver for the A83T CCU. Patch 4 adds the CCU device nodes, and fixes up any existing clock phandles in the dtsi, without using the macros. Patch 5 sets the clock accuracy for the main oscillator. Patch 6 is for the next -rc2, switch the clock indices from raw numbers to macros we introduced with the driver. This will be updated if more peripherals are introduced in the same cycle. Let me know what you think. Cover letter excerpt from v1: This is yet another series that adds support for the A83T CCU. The A83T CCU has a mix of new styled (like the A80) clocks at old (like A3x) offsets. Some differences include: - D1/D2 style PLL clocks - divisible audio module clocks - new timing mode for mmc2 module clock Regards ChenYu Chen-Yu Tsai (6): dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU clk: sunxi-ng: Support multiple variable pre-dividers clk: sunxi-ng: Add driver for A83T CCU ARM: sun8i: a83t: Add CCU device nodes ARM: sun8i: a83t: Set clock accuracy for 24MHz oscillator ARM: sun8i: a83t: Switch to CCU device tree binding macros .../devicetree/bindings/clock/sunxi-ccu.txt| 2 + arch/arm/boot/dts/sun8i-a83t.dtsi | 19 +- drivers/clk/sunxi-ng/Kconfig | 11 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 10 +- drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 10 +- drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 10 +- drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 10 +- drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 910 + drivers/clk/sunxi-ng/ccu-sun8i-a83t.h | 64 ++ drivers/clk/sunxi-ng/ccu-sun8i-h3.c| 10 +- drivers/clk/sunxi-ng/ccu-sun8i-r.c | 10 +- drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 10 +- drivers/clk/sunxi-ng/ccu_mux.c | 15 +- drivers/clk/sunxi-ng/ccu_mux.h | 13 +- include/dt-bindings/clock/sun8i-a83t-ccu.h | 140 include/dt-bindings/reset/sun8i-a83t-ccu.h | 98 +++ 17 files changed, 1294 insertions(+), 49 deletions(-) create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-a83t.h create mode 100644 include/dt-bindings/clock/sun8i-a83t-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-a83t-ccu.h -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v3 5/6] ARM: sun8i: a83t: Set clock accuracy for 24MHz oscillator
The datasheets for Allwinner SoCs set strict requirements on the stability of the external crystal oscillators. Add the accuracy for the main 24MHz oscillator to the device tree. Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a83t.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index c9a5d07b2ada..e12dd7170b8f 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -126,6 +126,7 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <2400>; + clock-accuracy = <5>; clock-output-names = "osc24M"; }; -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v3 2/6] clk: sunxi-ng: Support multiple variable pre-dividers
On the A83T, the AHB1 clock has a shared pre-divider on the two
PLL-PERIPH clock parents. To support such instances of shared
pre-dividers, this patch extends the mux clock type to support
multiple variable pre-dividers.
As the pre-dividers are only used to calculate the rate, but
do not participate in the factorization process, this is fairly
straightforward.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-r.c| 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 10 +-
drivers/clk/sunxi-ng/ccu_mux.c| 15 ---
drivers/clk/sunxi-ng/ccu_mux.h| 13 -
9 files changed, 51 insertions(+), 47 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index f54114c607df..2bb4cabf802f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -211,6 +211,9 @@ static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
"axi", "pll-periph0" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+ { .index = 3, .shift = 6, .width = 2 },
+};
static struct ccu_div ahb1_clk = {
.div= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
@@ -218,11 +221,8 @@ static struct ccu_div ahb1_clk = {
.shift = 12,
.width = 2,
- .variable_prediv= {
- .index = 3,
- .shift = 6,
- .width = 2,
- },
+ .var_predivs= ahb1_predivs,
+ .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
},
.common = {
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
index df97e25aec76..4d6078fca9ac 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -195,6 +195,9 @@ static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu",
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
"axi", "pll-periph" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+ { .index = 3, .shift = 6, .width = 2 },
+};
static struct ccu_div ahb1_clk = {
.div= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
@@ -203,11 +206,8 @@ static struct ccu_div ahb1_clk = {
.shift = 12,
.width = 2,
- .variable_prediv= {
- .index = 3,
- .shift = 6,
- .width = 2,
- },
+ .var_predivs= ahb1_predivs,
+ .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
},
.common = {
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
index 5c6d37bdf247..8a753ed0426d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
@@ -169,6 +169,9 @@ static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
"axi" , "pll-periph" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+ { .index = 3, .shift = 6, .width = 2 },
+};
static struct ccu_div ahb1_clk = {
.div= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
@@ -176,11 +179,8 @@ static struct ccu_div ahb1_clk = {
.shift = 12,
.width = 2,
- .variable_prediv= {
- .index = 3,
- .shift = 6,
- .width = 2,
- },
+ .var_predivs= ahb1_predivs,
+ .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
},
.common = {
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index 8d38e6510e29..10b38dc46f75 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -180,6 +180,9 @@ static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
"axi" , "pll-periph" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+ { .index = 3, .shift = 6, .width = 2 },
+};
static struct ccu_div ahb1_clk = {
.div= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
@@ -187,11 +190,8 @@ static struct ccu_div ahb1_clk = {
.shift = 12
[linux-sunxi] [PATCH v3 1/6] dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU
The A83T clock control unit is a hybrid of some new style clock designs from the A80, and old style layout from the other Allwinner SoCs. Like the A80, the SoC does not have a low speed 32.768 kHz oscillator. Unlike the A80, there is no clock input either. The only low speed clock available is the internal oscillator which runs at around 16 MHz, divided by 512, yielding a low speed clock around 31.250 kHz. Signed-off-by: Chen-Yu Tsai Acked-by: Rob Herring --- Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index e9c5a1d9834a..34b2a9249a94 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -6,6 +6,7 @@ Required properties : - "allwinner,sun6i-a31-ccu" - "allwinner,sun8i-a23-ccu" - "allwinner,sun8i-a33-ccu" + - "allwinner,sun8i-a83t-ccu" - "allwinner,sun8i-h3-ccu" - "allwinner,sun8i-h3-r-ccu" - "allwinner,sun8i-v3s-ccu" @@ -18,6 +19,7 @@ Required properties : - clocks: phandle to the oscillators feeding the CCU. Two are needed: - "hosc": the high frequency oscillator (usually at 24MHz) - "losc": the low frequency oscillator (usually at 32kHz) + On the A83T, this is the internal 16MHz oscillator divided by 512 - clock-names: Must contain the clock names described just above - #clock-cells : must contain 1 - #reset-cells : must contain 1 -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: A33 Suspend
> I updated the instructions on the wiki to update the commit tag. You > shouldn't need to switch branches if the commit tag is correct. It looks > like the old commit tag disappeared. I tested with the new commit tag on > sina-a33 and it appears to work. (make sure to use correct u-boot config > and dtb) If this commit tag disappears, the patch should apply to anything > close to 4.12-rc1 in the sunxi-next branch. If it's anything like linux-next (i.e. it's regularly rebased), the commit on sunxi-next will likely disappear again soon. Stefan -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [RFC PATCH 10/11] ARM: sun8i: h3: add display engine pipeline for TVE
Hi,
Dne sreda, 17. maj 2017 ob 18:43:53 CEST je Icenowy Zheng napisal(a):
> As we have already the support for the TV encoder on Allwinner H3, add
> the display engine pipeline device tree nodes to its DTSI file.
>
> The H5 pipeline has some differences and will be enabled later.
>
> The currently-unused mixer0 and tcon0 are also needed, for the
> completement of the pipeline.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm/boot/dts/sun8i-h3.dtsi | 189
> 1 file changed, 189 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
> b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..20172ef92415 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -41,6 +41,8 @@
> */
>
> #include "sunxi-h3-h5.dtsi"
> +#include
> +#include
>
> / {
> cpus {
> @@ -72,6 +74,193 @@
> };
> };
>
> + de: display-engine {
> + compatible = "allwinner,sun8i-h3-display-engine";
> + allwinner,pipelines = <&mixer0>,
> + <&mixer1>;
> + status = "disabled";
> + };
> +
> + soc {
> + display_clocks: clock@100 {
> + compatible = "allwinner,sun8i-a83t-de2-clk";
> + reg = <0x0100 0x10>;
> + clocks = <&ccu CLK_BUS_DE>,
> + <&ccu CLK_DE>;
> + clock-names = "bus",
> + "mod";
> + resets = <&ccu RST_BUS_DE>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + assigned-clocks = <&ccu CLK_DE>;
> + assigned-clock-parents = <&ccu CLK_PLL_DE>;
> + assigned-clock-rates = <43200>;
> + };
> +
> + mixer0: mixer@110 {
> + compatible = "allwinner,sun8i-h3-de2-mixer0";
> + reg = <0x0110 0x10>;
> + clocks = <&display_clocks CLK_BUS_MIXER0>,
> + <&display_clocks CLK_MIXER0>;
> + clock-names = "bus",
> + "mod";
> + resets = <&display_clocks RST_MIXER0>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mixer0_out: port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + mixer0_out_tcon0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint =
> <&tcon0_in_mixer0>;
> + };
> +
> + mixer0_out_tcon1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint =
> <&tcon1_in_mixer0>;
> + };
> + };
> + };
> + };
> +
> + mixer1: mixer@120 {
> + compatible = "allwinner,sun8i-h3-de2-mixer1";
> + reg = <0x0120 0x10>;
> + clocks = <&display_clocks CLK_BUS_MIXER1>,
> + <&display_clocks CLK_MIXER1>;
> + clock-names = "bus",
> + "mod";
> + resets = <&display_clocks RST_WB>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mixer1_out: port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + mixer1_out_tcon1: endpoint@0 {
> + reg = <0>;
> + remote-endpoint =
> <&tcon1_in_mixer1>;
> + };
> +
> + mixer1_out_tcon0: endpoint@1 {
> + reg = <1>;
> + remote-endpoint =
> <&tcon0_in_mixer1>;
> + };
> + };
> + };
> + };
> +
> + tcon0: lcd-controller@1c0c000 {
> + compatible = "allwinner,sun8i-h3-tcon0";
> + reg = <0x01c0c000 0x1000>;
> + interrupts = ;
> +
Re: [linux-sunxi] [RFC PATCH 06/11] drm: sun4i: add color space correction support for DE2 mixer
Hi,
Dne sreda, 17. maj 2017 ob 18:43:49 CEST je Icenowy Zheng napisal(a):
> The DE2 mixer can do color space correction needed by TV Encoder with
> its DCSC sub-engine.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng
> ---
> drivers/gpu/drm/sun4i/sun8i_mixer.c | 35
> +++ drivers/gpu/drm/sun4i/sun8i_mixer.h |
> 6 +-
> 2 files changed, 40 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
> b/drivers/gpu/drm/sun4i/sun8i_mixer.c index d658a3a8159a..65f86641eca3
> 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
> +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
> @@ -29,6 +29,14 @@
> #include "sun8i_layer.h"
> #include "sunxi_engine.h"
>
> +static const u32 sun8i_rgb2yuv_coef[12] = {
> + 0x0107, 0x0204, 0x0064, 0x4200,
> + 0x1f68, 0x1ed6, 0x01c2, 0x00020200,
> + 0x01c2, 0x1e87, 0x1fb7, 0x00020200,
> +};
> +
> +static const u32 sun8i_rgb2yuv_dcsc_alpha = 0x00020200;
> +
There is no need to set/use alpha. BSP code doesn't set it and 0x00020200
value is default.
Best regards,
Jernej
> static void sun8i_mixer_commit(struct sunxi_engine *engine)
> {
> DRM_DEBUG_DRIVER("Committing changes\n");
> @@ -37,6 +45,31 @@ static void sun8i_mixer_commit(struct sunxi_engine
> *engine) SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
> }
>
> +static void sun8i_mixer_apply_color_correction(struct sunxi_engine *engine)
> +{
> + int i;
> +
> + DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
> +
> + /* Set color correction */
> + regmap_write(engine->regs, SUN8I_MIXER_DCSC_EN, 1);
> +
> + for (i = 0; i < 12; i++)
> + regmap_write(engine->regs, SUN8I_MIXER_DCSC_COEF_REG(i),
> + sun8i_rgb2yuv_coef[i]);
> +
> + regmap_write(engine->regs, SUN8I_MIXER_DCSC_COEF_ALPHA,
> + sun8i_rgb2yuv_dcsc_alpha);
> +}
> +
> +static void sun8i_mixer_disable_color_correction(struct sunxi_engine
> *engine) +{
> + DRM_DEBUG_DRIVER("Disabling color correction\n");
> +
> + /* Disable color correction */
> + regmap_write(engine->regs, SUN8I_MIXER_DCSC_EN, 0);
> +}
> +
> void sun8i_mixer_layer_enable(struct sun8i_mixer *mixer,
> int layer, bool enable)
> {
> @@ -229,6 +262,8 @@ int sun8i_mixer_update_layer_buffer(struct sun8i_mixer
> *mixer, static const struct sunxi_engine_ops sun8i_engine_ops = {
> .commit = sun8i_mixer_commit,
> .layers_init= sun8i_layers_init,
> + .apply_color_correction = sun8i_mixer_apply_color_correction,
> + .disable_color_correction = sun8i_mixer_disable_color_correction,
> };
>
> static struct regmap_config sun8i_mixer_regmap_config = {
> diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h
> b/drivers/gpu/drm/sun4i/sun8i_mixer.h index 4785ac090b8c..d7f7513898b6
> 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
> +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
> @@ -88,6 +88,11 @@
> #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_RGB888 (8 << 8)
> #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_DEF (0xff << 24)
>
> +/* The DCSC sub-engine is used to do color space conversation */
> +#define SUN8I_MIXER_DCSC_EN 0xb
> +#define SUN8I_MIXER_DCSC_COEF_REG(x) (0xb0010 + 0x4 * x)
> +#define SUN8I_MIXER_DCSC_COEF_ALPHA 0xb0040
> +
> /*
> * These sub-engines are still unknown now, the EN registers are here only
> to * be used to disable these sub-engines.
> @@ -102,7 +107,6 @@
> #define SUN8I_MIXER_PEAK_EN 0xa6000
> #define SUN8I_MIXER_ASE_EN 0xa8000
> #define SUN8I_MIXER_FCC_EN 0xaa000
> -#define SUN8I_MIXER_DCSC_EN 0xb
>
> struct sun8i_mixer_cfg {
> int vi_num;
> --
> 2.12.2
>
> --
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[linux-sunxi] Re: [PATCH v8 0/9] Initial Allwinner Display Engine 2.0 Support
于 2017年5月18日 GMT+08:00 上午1:37:39, Maxime Ripard 写到: >On Wed, May 17, 2017 at 10:47:16PM +0800, Icenowy Zheng wrote: >> This patchset is the initial patchset for Allwinner DE2 support. >> >> As the DE2 CCU support is already applied, this patchset now contains >> only DRM changes and device tree changes. >> >> The SoC used to develop this patchset is V3s, as V3s is the simplest >> one of the SoCs that have DE2. >> >> (Allwinner V3s features only one mixer, and its only video output is >> RGB LCD, which is already supported in our TCON driver) >> >> The last patch is only a testing patch, it shouldn't be merged; and >> for the patch to be really usable, the RFC fix of the TCON driver [1] >> is needed. >> >> No HDMI, TV encoder or other internal bridges' support is included >> in this patchset, which makes it currently not usable on H3. >> >> Thanks to Jean-Francois Moine and Jernej Skrabec for their efforts >> to discover the internal of DE2! >> >> [1] >https://lists.freedesktop.org/archives/dri-devel/2016-December/126264.html >> >> Icenowy Zheng (9): >> drm/sun4i: abstract a engine type >> drm/sun4i: add a dedicated module for sun4i-backend and sun4i-layer >> drm/sun4i: add a Kconfig option for sun4i-backend >> drm/sun4i: add support for Allwinner DE2 mixers >> drm/sun4i: Add compatible string for V3s display engine >> drm/sun4i: tcon: add support for V3s TCON > >Applied all those patches... > >> ARM: sun8i: v3s: add device nodes for DE2 display pipeline > >But this one doesn't apply. Please rebase and resend. OK. Will rebase it once all these patches entered linux-next. > >Maxime -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v8 0/9] Initial Allwinner Display Engine 2.0 Support
On Wed, May 17, 2017 at 10:47:16PM +0800, Icenowy Zheng wrote: > This patchset is the initial patchset for Allwinner DE2 support. > > As the DE2 CCU support is already applied, this patchset now contains > only DRM changes and device tree changes. > > The SoC used to develop this patchset is V3s, as V3s is the simplest > one of the SoCs that have DE2. > > (Allwinner V3s features only one mixer, and its only video output is > RGB LCD, which is already supported in our TCON driver) > > The last patch is only a testing patch, it shouldn't be merged; and > for the patch to be really usable, the RFC fix of the TCON driver [1] > is needed. > > No HDMI, TV encoder or other internal bridges' support is included > in this patchset, which makes it currently not usable on H3. > > Thanks to Jean-Francois Moine and Jernej Skrabec for their efforts > to discover the internal of DE2! > > [1] https://lists.freedesktop.org/archives/dri-devel/2016-December/126264.html > > Icenowy Zheng (9): > drm/sun4i: abstract a engine type > drm/sun4i: add a dedicated module for sun4i-backend and sun4i-layer > drm/sun4i: add a Kconfig option for sun4i-backend > drm/sun4i: add support for Allwinner DE2 mixers > drm/sun4i: Add compatible string for V3s display engine > drm/sun4i: tcon: add support for V3s TCON Applied all those patches... > ARM: sun8i: v3s: add device nodes for DE2 display pipeline But this one doesn't apply. Please rebase and resend. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] [RFC PATCH 11/11] [DO NOT MERGE] ARM: sun8i: h3: enable TV output on Orange Pi PC
Orange Pi PC features a 3.5mm jack with TV output in it.
Enable the TV output.
As it currently do not have jack detection feature, do not merge this
patch.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index 1a044b17d6c6..9c50ac3e82f3 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -97,6 +97,10 @@
status = "okay";
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -169,6 +173,14 @@
status = "okay";
};
+&tcon1 {
+ status = "okay";
+};
+
+&tve0 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
--
2.12.2
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[linux-sunxi] [RFC PATCH 10/11] ARM: sun8i: h3: add display engine pipeline for TVE
As we have already the support for the TV encoder on Allwinner H3, add
the display engine pipeline device tree nodes to its DTSI file.
The H5 pipeline has some differences and will be enabled later.
The currently-unused mixer0 and tcon0 are also needed, for the
completement of the pipeline.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3.dtsi | 189
1 file changed, 189 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index b36f9f423c39..20172ef92415 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -41,6 +41,8 @@
*/
#include "sunxi-h3-h5.dtsi"
+#include
+#include
/ {
cpus {
@@ -72,6 +74,193 @@
};
};
+ de: display-engine {
+ compatible = "allwinner,sun8i-h3-display-engine";
+ allwinner,pipelines = <&mixer0>,
+ <&mixer1>;
+ status = "disabled";
+ };
+
+ soc {
+ display_clocks: clock@100 {
+ compatible = "allwinner,sun8i-a83t-de2-clk";
+ reg = <0x0100 0x10>;
+ clocks = <&ccu CLK_BUS_DE>,
+<&ccu CLK_DE>;
+ clock-names = "bus",
+ "mod";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ assigned-clocks = <&ccu CLK_DE>;
+ assigned-clock-parents = <&ccu CLK_PLL_DE>;
+ assigned-clock-rates = <43200>;
+ };
+
+ mixer0: mixer@110 {
+ compatible = "allwinner,sun8i-h3-de2-mixer0";
+ reg = <0x0110 0x10>;
+ clocks = <&display_clocks CLK_BUS_MIXER0>,
+<&display_clocks CLK_MIXER0>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_MIXER0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mixer0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint =
<&tcon0_in_mixer0>;
+ };
+
+ mixer0_out_tcon1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint =
<&tcon1_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ mixer1: mixer@120 {
+ compatible = "allwinner,sun8i-h3-de2-mixer1";
+ reg = <0x0120 0x10>;
+ clocks = <&display_clocks CLK_BUS_MIXER1>,
+<&display_clocks CLK_MIXER1>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_WB>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mixer1_out_tcon1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint =
<&tcon1_in_mixer1>;
+ };
+
+ mixer1_out_tcon0: endpoint@1 {
+ reg = <1>;
+ remote-endpoint =
<&tcon0_in_mixer1>;
+ };
+ };
+ };
+ };
+
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun8i-h3-tcon0";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_TCON0>,
+<&ccu CLK_TCON0>;
+ clock-names = "ahb",
+
[linux-sunxi] [RFC PATCH 09/11] clk: sunxi-ng: export CLK_PLL_DE for H3
The CLK_PLL_DE is needed to be referenced in device tree for H3, for both forcing the parent of PLL_DE. So export it to the device tree binding header. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 3 +-- include/dt-bindings/clock/sun8i-h3-ccu.h | 2 ++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h index 85973d1e8165..7029091a6c9f 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h @@ -33,9 +33,8 @@ #define CLK_PLL_PERIPH0_2X 10 #define CLK_PLL_GPU11 #define CLK_PLL_PERIPH112 -#define CLK_PLL_DE 13 -/* The CPUX clock is exported */ +/* The PLL_DE and CPUX clocks is exported */ #define CLK_AXI15 #define CLK_AHB1 16 diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h index c2afc41d6964..82496a57efd4 100644 --- a/include/dt-bindings/clock/sun8i-h3-ccu.h +++ b/include/dt-bindings/clock/sun8i-h3-ccu.h @@ -43,6 +43,8 @@ #ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_ #define _DT_BINDINGS_CLK_SUN8I_H3_H_ +#define CLK_PLL_DE 13 + #define CLK_CPUX 14 #define CLK_BUS_CE 20 -- 2.12.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [RFC PATCH 08/11] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3
Allwinner H3 features a PLL named CLK_PLL_DE, and a mod clock for the
"Display Engine 2.0" named CLK_DE. As the name indicated, the CLK_PLL_DE
is a PLL for CLK_DE.
Only CLK_DE and CLK_TVE have a parent of CLK_PLL_DE, and CLK_TVE is also
one part of the display clocks.
So allow CLK_DE to set CLK_PLL_DE (add CLK_SET_RATE_PARENT to it).
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 4cbc1b701b7c..6e39ba7cb173 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -439,7 +439,7 @@ static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
-0x104, 0, 4, 24, 3, BIT(31), 0);
+0x104, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static const char * const tcon_parents[] = { "pll-video" };
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
--
2.12.2
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[linux-sunxi] [RFC PATCH 07/11] drm: sun4i: add support for the TV encoder in H3 SoC
Allwinner H3 features a TV encoder similar to the one in earlier SoCs,
but with some different points about clocks:
- It has a mod clock and a bus clock.
- The mod clock must be at a fixed rate to generate signal.
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_tv.c | 65 +---
1 file changed, 61 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index a9cad00d4ee8..c9943103f499 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
@@ -169,14 +170,23 @@ struct tv_mode {
const struct resync_parameters *resync_params;
};
+struct sun4i_tv_quirks {
+ bool has_mod_clk;
+ bool fixed_clock;
+ unsigned long fixed_clock_rate;
+};
+
struct sun4i_tv {
struct drm_connectorconnector;
struct drm_encoder encoder;
struct clk *clk;
+ struct clk *mod_clk;
struct regmap *regs;
struct reset_control*reset;
+ const struct sun4i_tv_quirks *quirks;
+
struct sun4i_drv*drv;
};
@@ -578,6 +588,10 @@ static int sun4i_tv_bind(struct device *dev, struct device
*master,
tv->drv = drv;
dev_set_drvdata(dev, tv);
+ tv->quirks = of_device_get_match_data(dev);
+ if (!tv->quirks)
+ return -EINVAL;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
regs = devm_ioremap_resource(dev, res);
if (IS_ERR(regs)) {
@@ -604,7 +618,10 @@ static int sun4i_tv_bind(struct device *dev, struct device
*master,
return ret;
}
- tv->clk = devm_clk_get(dev, NULL);
+ if (tv->quirks->has_mod_clk)
+ tv->clk = devm_clk_get(dev, "bus");
+ else
+ tv->clk = devm_clk_get(dev, NULL);
if (IS_ERR(tv->clk)) {
dev_err(dev, "Couldn't get the TV encoder clock\n");
ret = PTR_ERR(tv->clk);
@@ -612,6 +629,26 @@ static int sun4i_tv_bind(struct device *dev, struct device
*master,
}
clk_prepare_enable(tv->clk);
+ if (tv->quirks->has_mod_clk) {
+ tv->mod_clk = devm_clk_get(dev, "mod");
+ if (IS_ERR(tv->mod_clk)) {
+ dev_err(dev, "Couldn't get the TV encoder mod clock\n");
+ ret = PTR_ERR(tv->mod_clk);
+ goto err_disable_clk;
+ };
+
+ if (tv->quirks->fixed_clock) {
+ ret = clk_set_rate(tv->mod_clk,
+ tv->quirks->fixed_clock_rate);
+ if (ret) {
+ dev_err(dev, "Couldn't set TV encoder mod clock
rate\n");
+ goto err_disable_clk;
+ }
+ }
+
+ clk_prepare_enable(tv->mod_clk);
+ }
+
drm_encoder_helper_add(&tv->encoder,
&sun4i_tv_helper_funcs);
ret = drm_encoder_init(drm,
@@ -621,14 +658,14 @@ static int sun4i_tv_bind(struct device *dev, struct
device *master,
NULL);
if (ret) {
dev_err(dev, "Couldn't initialise the TV encoder\n");
- goto err_disable_clk;
+ goto err_disable_mod_clk;
}
tv->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
dev->of_node);
if (!tv->encoder.possible_crtcs) {
ret = -EPROBE_DEFER;
- goto err_disable_clk;
+ goto err_disable_mod_clk;
}
drm_connector_helper_add(&tv->connector,
@@ -649,6 +686,9 @@ static int sun4i_tv_bind(struct device *dev, struct device
*master,
err_cleanup_connector:
drm_encoder_cleanup(&tv->encoder);
+err_disable_mod_clk:
+ if (tv->quirks->has_mod_clk)
+ clk_disable_unprepare(tv->mod_clk);
err_disable_clk:
clk_disable_unprepare(tv->clk);
err_assert_reset:
@@ -683,8 +723,25 @@ static int sun4i_tv_remove(struct platform_device *pdev)
return 0;
}
+static const struct sun4i_tv_quirks sun4i_a10_tv_quirks = {
+ /* Nothing special */
+};
+
+static const struct sun4i_tv_quirks sun8i_h3_tv_quirks = {
+ .has_mod_clk = true,
+ .fixed_clock = true,
+ .fixed_clock_rate = 21600UL,
+};
+
static const struct of_device_id sun4i_tv_of_table[] = {
- { .compatible = "allwinner,sun4i-a10-tv-encoder" },
+ {
+ .compatible = "allwinner,sun4i-a10-tv-encoder",
+ .data = &sun4i_a10_tv_quirks,
+ },
+ {
+ .compatible = "allwinner,sun8i-h3-tv-encoder",
+ .data = &sun8i_h3_tv_quirks,
+ },
{ }
};
MODUL
[linux-sunxi] [RFC PATCH 06/11] drm: sun4i: add color space correction support for DE2 mixer
The DE2 mixer can do color space correction needed by TV Encoder with
its DCSC sub-engine.
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 35 +++
drivers/gpu/drm/sun4i/sun8i_mixer.h | 6 +-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index d658a3a8159a..65f86641eca3 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -29,6 +29,14 @@
#include "sun8i_layer.h"
#include "sunxi_engine.h"
+static const u32 sun8i_rgb2yuv_coef[12] = {
+ 0x0107, 0x0204, 0x0064, 0x4200,
+ 0x1f68, 0x1ed6, 0x01c2, 0x00020200,
+ 0x01c2, 0x1e87, 0x1fb7, 0x00020200,
+};
+
+static const u32 sun8i_rgb2yuv_dcsc_alpha = 0x00020200;
+
static void sun8i_mixer_commit(struct sunxi_engine *engine)
{
DRM_DEBUG_DRIVER("Committing changes\n");
@@ -37,6 +45,31 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine)
SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
}
+static void sun8i_mixer_apply_color_correction(struct sunxi_engine *engine)
+{
+ int i;
+
+ DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
+
+ /* Set color correction */
+ regmap_write(engine->regs, SUN8I_MIXER_DCSC_EN, 1);
+
+ for (i = 0; i < 12; i++)
+ regmap_write(engine->regs, SUN8I_MIXER_DCSC_COEF_REG(i),
+sun8i_rgb2yuv_coef[i]);
+
+ regmap_write(engine->regs, SUN8I_MIXER_DCSC_COEF_ALPHA,
+sun8i_rgb2yuv_dcsc_alpha);
+}
+
+static void sun8i_mixer_disable_color_correction(struct sunxi_engine *engine)
+{
+ DRM_DEBUG_DRIVER("Disabling color correction\n");
+
+ /* Disable color correction */
+ regmap_write(engine->regs, SUN8I_MIXER_DCSC_EN, 0);
+}
+
void sun8i_mixer_layer_enable(struct sun8i_mixer *mixer,
int layer, bool enable)
{
@@ -229,6 +262,8 @@ int sun8i_mixer_update_layer_buffer(struct sun8i_mixer
*mixer,
static const struct sunxi_engine_ops sun8i_engine_ops = {
.commit = sun8i_mixer_commit,
.layers_init= sun8i_layers_init,
+ .apply_color_correction = sun8i_mixer_apply_color_correction,
+ .disable_color_correction = sun8i_mixer_disable_color_correction,
};
static struct regmap_config sun8i_mixer_regmap_config = {
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h
b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index 4785ac090b8c..d7f7513898b6 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -88,6 +88,11 @@
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_RGB888(8 << 8)
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_DEF (0xff << 24)
+/* The DCSC sub-engine is used to do color space conversation */
+#define SUN8I_MIXER_DCSC_EN0xb
+#define SUN8I_MIXER_DCSC_COEF_REG(x) (0xb0010 + 0x4 * x)
+#define SUN8I_MIXER_DCSC_COEF_ALPHA0xb0040
+
/*
* These sub-engines are still unknown now, the EN registers are here only to
* be used to disable these sub-engines.
@@ -102,7 +107,6 @@
#define SUN8I_MIXER_PEAK_EN0xa6000
#define SUN8I_MIXER_ASE_EN 0xa8000
#define SUN8I_MIXER_FCC_EN 0xaa000
-#define SUN8I_MIXER_DCSC_EN0xb
struct sun8i_mixer_cfg {
int vi_num;
--
2.12.2
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[linux-sunxi] [RFC PATCH 04/11] drm: sun4i: add support for H3's TCON0/1
From: Icenowy Zheng
Allwinner H3 has two special TCONs, both come without channel0. And the
TCON1 of H3 has no special clocks even for the channel1.
Add support for these kinds of TCON.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 78 --
drivers/gpu/drm/sun4i/sun4i_tcon.h | 3 ++
2 files changed, 61 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 89a215ff2370..7009292f99e4 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -57,6 +57,7 @@ void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int
channel)
{
/* Disable the TCON's channel */
if (channel == 0) {
+ WARN_ON(!tcon->quirks->has_channel_0);
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
SUN4I_TCON0_CTL_TCON_ENABLE, 0);
clk_disable_unprepare(tcon->dclk);
@@ -66,7 +67,8 @@ void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int
channel)
WARN_ON(!tcon->quirks->has_channel_1);
regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
SUN4I_TCON1_CTL_TCON_ENABLE, 0);
- clk_disable_unprepare(tcon->sclk1);
+ if (tcon->quirks->has_channel_1_clk)
+ clk_disable_unprepare(tcon->sclk1);
}
EXPORT_SYMBOL(sun4i_tcon_channel_disable);
@@ -74,6 +76,7 @@ void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int
channel)
{
/* Enable the TCON's channel */
if (channel == 0) {
+ WARN_ON(!tcon->quirks->has_channel_0);
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
SUN4I_TCON0_CTL_TCON_ENABLE,
SUN4I_TCON0_CTL_TCON_ENABLE);
@@ -85,7 +88,8 @@ void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int
channel)
regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
SUN4I_TCON1_CTL_TCON_ENABLE,
SUN4I_TCON1_CTL_TCON_ENABLE);
- clk_prepare_enable(tcon->sclk1);
+ if (tcon->quirks->has_channel_1_clk)
+ clk_prepare_enable(tcon->sclk1);
}
EXPORT_SYMBOL(sun4i_tcon_channel_enable);
@@ -132,6 +136,7 @@ void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
/* Configure the dot clock */
clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
+ WARN_ON(!tcon->quirks->has_channel_0);
/* Adjust clock delay */
clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
@@ -209,7 +214,8 @@ void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
WARN_ON(!tcon->quirks->has_channel_1);
/* Configure the dot clock */
- clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
+ if (tcon->quirks->has_channel_1_clk)
+ clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
/* Adjust clock delay */
clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
@@ -327,13 +333,15 @@ static int sun4i_tcon_init_clocks(struct device *dev,
}
clk_prepare_enable(tcon->clk);
- tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
- if (IS_ERR(tcon->sclk0)) {
- dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
- return PTR_ERR(tcon->sclk0);
+ if (tcon->quirks->has_channel_0) {
+ tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
+ if (IS_ERR(tcon->sclk0)) {
+ dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
+ return PTR_ERR(tcon->sclk0);
+ }
}
- if (tcon->quirks->has_channel_1) {
+ if (tcon->quirks->has_channel_1 && tcon->quirks->has_channel_1_clk) {
tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
if (IS_ERR(tcon->sclk1)) {
dev_err(dev, "Couldn't get the TCON channel 1 clock\n");
@@ -533,10 +541,12 @@ static int sun4i_tcon_bind(struct device *dev, struct
device *master,
goto err_free_clocks;
}
- ret = sun4i_dclk_create(dev, tcon);
- if (ret) {
- dev_err(dev, "Couldn't create our TCON dot clock\n");
- goto err_free_clocks;
+ if (tcon->quirks->has_channel_0) {
+ ret = sun4i_dclk_create(dev, tcon);
+ if (ret) {
+ dev_err(dev, "Couldn't create our TCON dot clock\n");
+ goto err_free_clocks;
+ }
}
ret = sun4i_tcon_init_irq(dev, tcon);
@@ -561,7 +571,8 @@ static int sun4i_tcon_bind(struct device *dev, struct
device *master,
return 0;
err_free_dotclock:
- sun4i_dclk_free(tcon);
+ if (tcon->quirks->has_channel_0)
+ sun4i_dclk_free(tcon);
err_free_clocks:
sun4i_tcon_free_clocks(tcon);
err_assert_reset:
@@ -575,7 +586,9 @@ static void sun4i_tcon_unbind(struc
[linux-sunxi] [RFC PATCH 05/11] drm: sun4i: add compatible for H3 display engine
Add a compatible string for H3 display engine in sun4i_drv code.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 29bf1325ded6..c0de0741c923 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -324,6 +324,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
{ .compatible = "allwinner,sun6i-a31-display-engine" },
{ .compatible = "allwinner,sun6i-a31s-display-engine" },
{ .compatible = "allwinner,sun8i-a33-display-engine" },
+ { .compatible = "allwinner,sun8i-h3-display-engine" },
{ .compatible = "allwinner,sun8i-v3s-display-engine" },
{ }
};
--
2.12.2
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[linux-sunxi] [RFC PATCH 03/11] drm: sun4i: ignore swapped mixer<->tcon connection for DE2
Some SoC's DE2 has two mixers. Defaultly the mixer0 is connected to
tcon0 and mixer1 is connected to tcon1; however by setting a bit
the connection can be swapped.
As we now hardcode the default connection, ignore the bonus endpoint for
the mixer's output and the TCON's input, as they stands for the swapped
connection.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 27 ++
drivers/gpu/drm/sun4i/sun4i_tcon.c | 39 +-
drivers/gpu/drm/sun4i/sun4i_tcon.h | 2 ++
3 files changed, 59 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 1dd1948025d2..29bf1325ded6 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -173,6 +173,13 @@ static bool sun4i_drv_node_is_frontend(struct device_node
*node)
of_device_is_compatible(node,
"allwinner,sun8i-a33-display-frontend");
}
+static bool sun4i_drv_node_is_swappable_de2_mixer(struct device_node *node)
+{
+ /* The V3s has only one mixer-tcon pair, so it's not listed here. */
+ return of_device_is_compatible(node, "allwinner,sun8i-h3-de2-mixer0") ||
+ of_device_is_compatible(node, "allwinner,sun8i-h3-de2-mixer1");
+}
+
static bool sun4i_drv_node_is_tcon(struct device_node *node)
{
return of_device_is_compatible(node, "allwinner,sun5i-a13-tcon") ||
@@ -249,6 +256,26 @@ static int sun4i_drv_add_endpoints(struct device *dev,
}
}
+ /*
+* The second endpoint of the output of a swappable DE2 mixer
+* is the TCON after connection swapping.
+* Ignore it now, as we now hardcode mixer0->tcon0,
+* mixer1->tcon1 connection.
+*/
+ if (sun4i_drv_node_is_swappable_de2_mixer(node)) {
+ struct of_endpoint endpoint;
+
+ if (of_graph_parse_endpoint(ep, &endpoint)) {
+ DRM_DEBUG_DRIVER("Couldn't parse endpoint\n");
+ continue;
+ }
+
+ if (endpoint.id) {
+ DRM_DEBUG_DRIVER("Endpoint is an unused
connection for DE2 mixer... skipping\n");
+ continue;
+ }
+ }
+
/* Walk down our tree */
count += sun4i_drv_add_endpoints(dev, match, remote);
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index f44a37a5993d..89a215ff2370 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -425,7 +425,8 @@ static int sun4i_tcon_init_regmap(struct device *dev,
* requested via the get_id function of the engine.
*/
static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv,
- struct device_node *node)
+ struct device_node *node,
+ bool skip_bonus_ep)
{
struct device_node *port, *ep, *remote;
struct sunxi_engine *engine;
@@ -439,6 +440,20 @@ static struct sunxi_engine *sun4i_tcon_find_engine(struct
sun4i_drv *drv,
if (!remote)
continue;
+ if (skip_bonus_ep) {
+ struct of_endpoint endpoint;
+
+ if (of_graph_parse_endpoint(ep, &endpoint)) {
+ DRM_DEBUG_DRIVER("Couldn't parse endpoint\n");
+ continue;
+ }
+
+ if (endpoint.id) {
+ DRM_DEBUG_DRIVER("Skipping bonus mixer->TCON
connection when searching engine\n");
+ continue;
+ }
+ }
+
/* does this node match any registered engines? */
list_for_each_entry(engine, &drv->engine_list, list) {
if (remote == engine->node) {
@@ -449,7 +464,7 @@ static struct sunxi_engine *sun4i_tcon_find_engine(struct
sun4i_drv *drv,
}
/* keep looking through upstream ports */
- engine = sun4i_tcon_find_engine(drv, remote);
+ engine = sun4i_tcon_find_engine(drv, remote, skip_bonus_ep);
if (!IS_ERR(engine)) {
of_node_put(remote);
of_node_put(port);
@@ -469,21 +484,27 @@ static int sun4i_tcon_bind(struct device *dev, struct
device *master,
struct sun4i_tcon *tcon;
int ret;
- engine = sun4i_tcon_find_engine(drv, dev->of_node);
- if (IS_ERR(engine)) {
- dev_err(dev, "Couldn't find matching engine\n");
- return -EPROBE_DEFER;
- }
-
tcon
[linux-sunxi] [RFC PATCH 02/11] drm: sun4i: add support for H3 mixers
From: Icenowy Zheng
Allwinner H3 SoC has two mixers, one has 1 VI channel and 3 UI channels,
and the other has 1 VI and 1 UI.
Add support for these two variants.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index cb193c5f1686..d658a3a8159a 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -390,11 +390,29 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg =
{
.ui_num = 1,
};
+static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
+ .vi_num = 1,
+ .ui_num = 3,
+};
+
+static const struct sun8i_mixer_cfg sun8i_h3_mixer1_cfg = {
+ .vi_num = 1,
+ .ui_num = 1,
+};
+
static const struct of_device_id sun8i_mixer_of_table[] = {
{
.compatible = "allwinner,sun8i-v3s-de2-mixer",
.data = &sun8i_v3s_mixer_cfg,
},
+ {
+ .compatible = "allwinner,sun8i-h3-de2-mixer0",
+ .data = &sun8i_h3_mixer0_cfg
+ },
+ {
+ .compatible = "allwinner,sun8i-h3-de2-mixer1",
+ .data = &sun8i_h3_mixer1_cfg
+ },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
--
2.12.2
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[linux-sunxi] [RFC PATCH 01/11] dt-bindings: update the binding for Allwinner H3 TVE support
Allwinner H3 features a "DE2.0" and a TV Encoder. Add device tree bindings for the following parts: - H3 TCONs - H3 Mixers - The connection between H3 TCONs and H3 Mixers - H3 TV Encoder - H3 Display engine Signed-off-by: Icenowy Zheng --- .../bindings/display/sunxi/sun4i-drm.txt | 47 -- 1 file changed, 43 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index 66b85a195ef2..52781943713b 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -21,7 +21,9 @@ The TV Encoder supports the composite and VGA output. It is one end of the pipeline. Required properties: - - compatible: value should be "allwinner,sun4i-a10-tv-encoder". + - compatible: value must be either: +* allwinner,sun4i-a10-tv-encoder +* allwinner,sun8i-h3-tv-encoder - reg: base address and size of memory-mapped region - clocks: the clocks driving the TV encoder - resets: phandle to the reset controller driving the encoder @@ -30,6 +32,13 @@ Required properties: Documentation/devicetree/bindings/media/video-interfaces.txt. The first port should be the input endpoint. +For "allwinner,sun4i-a10-tv-encoder", there is only one clock required, +and it's not named. + +For "allwinner,sun8i-h3-tv-encoder", these clocks are needed: +- 'bus': the AHB bus clock of TVE +- 'mod': the mod clock of TVE + TCON @@ -41,29 +50,51 @@ Required properties: * allwinner,sun6i-a31-tcon * allwinner,sun6i-a31s-tcon * allwinner,sun8i-a33-tcon + * allwinner,sun8i-h3-tcon0 + * allwinner,sun8i-h3-tcon1 * allwinner,sun8i-v3s-tcon - reg: base address and size of memory-mapped region - interrupts: interrupt associated to this IP - clocks: phandles to the clocks feeding the TCON. Three are needed: - 'ahb': the interface clocks - - 'tcon-ch0': The clock driving the TCON channel 0 - resets: phandles to the reset controllers driving the encoder - "lcd": the reset line for the TCON channel 0 - clock-names: the clock names mentioned above - reset-names: the reset names mentioned above - - clock-output-names: Name of the pixel clock created - ports: A ports node with endpoint definitions as defined in Documentation/devicetree/bindings/media/video-interfaces.txt. The first port should be the input endpoint, the second one the output + In the situation of Display Engine 2.0 that the connection between + the mixer and the TCON can be swapped, the input should have two + endpoints. The first is the default mixer connected to the TCON, + the second the mixer which will be connected to the TCON if the + swap bit is set. + The output should have two endpoints. The first is the block connected to the TCON channel 0 (usually a panel or a bridge), the second the block connected to the TCON channel 1 (usually the TV encoder) -On SoCs other than the A33 and V3s, there is one more clock required: +For the following compatibles: + * allwinner,sun5i-a13-tcon + * allwinner,sun6i-a31-tcon + * allwinner,sun6i-a31s-tcon + * allwinner,sun8i-a33-tcon + * allwinner,sun8i-v3s-tcon +there is one more clock and one more property required: + - clocks: + - 'tcon-ch0': The clock driving the TCON channel 0 + - clock-output-names: Name of the pixel clock created + +For the following compatibles: + * allwinner,sun5i-a13-tcon + * allwinner,sun6i-a31-tcon + * allwinner,sun6i-a31s-tcon + * allwinner,sun8i-h3-tcon0 +there is one more clock required: - 'tcon-ch1': The clock driving the TCON channel 1 DRC @@ -158,6 +189,8 @@ supported. Required properties: - compatible: value must be one of: * allwinner,sun8i-v3s-de2-mixer +* allwinner,sun8i-h3-de2-mixer0 +* allwinner,sun8i-h3-de2-mixer1 - reg: base address and size of the memory-mapped region. - clocks: phandles to the clocks feeding the mixer * bus: the mixer interface clock @@ -169,6 +202,11 @@ Required properties: Documentation/devicetree/bindings/media/video-interfaces.txt. The first port should be the input endpoints, the second one the output + In the situation of Display Engine 2.0 that the connection between + the mixer and the TCON can be swapped, the output should have two + endpoints. The first is the default TCON connected to the mixer, + the second the TCON which will be connected to the mixer if the + swap bit is set. Display Engine Pipeline --- @@ -183,6 +221,7 @@ Required properties: * allwinner,sun6i-a31-display-engine * allwinner,sun6i-a31s-display-engine * allwinner,sun8i-a33-display-engine +* allwinner,sun8i-h3-display-engine * allwinner,sun8i-v3s-display-engine - allwinner,pipelines: list of phandle to the display engine -- 2.12.2 -- You received this message because you
[linux-sunxi] [RFC PATCH 00/11] Support for H3 Composite Output support
This patchset depends on the DE2 patchset, version 8 of that patchset is available at [1]. Allwinner H3 SoC features a TV Encoder like the one in Allwinner A13, which can only output TV Composite signal. The display pipeline of H3 is also special -- it has two mixers and two TCONs, of which the connection can be swapped. The TCONs do not have channel 0 (as they are all connected to internal bridges, TVE and HDMI TX). Add support for the display pipeline and the TVE in H3, in order to make it possible to display something with mainline kernel with H3. The image quality of TVE is bad, so HDMI is a better output -- this patchset also prepared the mixers and TCONs for HDMI output, and the HDMI controller driver is already done by Jernej Skrabec. Currently the jack detection feature of the TVE is still not so clear -- so it's not implemented in this version. Thus the TV output shouldn't be defaultly enabled now. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2017-May/506806.html Icenowy Zheng (11): dt-bindings: update the binding for Allwinner H3 TVE support drm: sun4i: add support for H3 mixers drm: sun4i: ignore swapped mixer<->tcon connection for DE2 drm: sun4i: add support for H3's TCON0/1 drm: sun4i: add compatible for H3 display engine drm: sun4i: add color space correction support for DE2 mixer drm: sun4i: add support for the TV encoder in H3 SoC clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3 clk: sunxi-ng: export CLK_PLL_DE for H3 ARM: sun8i: h3: add display engine pipeline for TVE [DO NOT MERGE] ARM: sun8i: h3: enable TV output on Orange Pi PC .../bindings/display/sunxi/sun4i-drm.txt | 47 - arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 12 ++ arch/arm/boot/dts/sun8i-h3.dtsi| 189 + drivers/clk/sunxi-ng/ccu-sun8i-h3.c| 2 +- drivers/clk/sunxi-ng/ccu-sun8i-h3.h| 3 +- drivers/gpu/drm/sun4i/sun4i_drv.c | 28 +++ drivers/gpu/drm/sun4i/sun4i_tcon.c | 117 + drivers/gpu/drm/sun4i/sun4i_tcon.h | 5 + drivers/gpu/drm/sun4i/sun4i_tv.c | 65 ++- drivers/gpu/drm/sun4i/sun8i_mixer.c| 53 ++ drivers/gpu/drm/sun4i/sun8i_mixer.h| 6 +- include/dt-bindings/clock/sun8i-h3-ccu.h | 2 + 12 files changed, 488 insertions(+), 41 deletions(-) -- 2.12.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: A33 Suspend
Hi, I updated the instructions on the wiki to update the commit tag. You shouldn't need to switch branches if the commit tag is correct. It looks like the old commit tag disappeared. I tested with the new commit tag on sina-a33 and it appears to work. (make sure to use correct u-boot config and dtb) If this commit tag disappears, the patch should apply to anything close to 4.12-rc1 in the sunxi-next branch. Hope that helps. On Tue, May 16, 2017 at 5:37 AM, Ramesh Nerella wrote: > Hello Lawrence, > > I've got the Sinlinx A33 dev board and trying to follow your instructions. > > Kernel compilation is failing: > > git clone https://github.com/linux-sunxi/linux-sunxi > > cd linux-sunxi > > git checkout cdb41f6bb3262b3c52e788fec9bb6f92a1cabb15 > > > fatal: reference is not a tree: cdb41f6bb3262b3c52e788fec9bb6f92a1cabb15 > > is it the right branch? You mentioned it is sunxi-next branch but you are > cloning linux-sunxi (3.4) branch. > > Also, A33 is Cortex-A7 no? > > Could you please help? > > Thanks, > > > On Wednesday, 12 April 2017 16:42:51 UTC+1, Lawrence Yu wrote: >> >> I have been able to combine the A33 suspend to ram code from the >> Allwinner 3.4 SDK into a recent mainline kernel and make suspend to ram >> work if anyone would like to try it out. I tested it on a A33 GA10H-v1.1 >> tablet and a Sinlinx SIN-A33 dev board. The goal was to see if suspend to >> ram would work (which it does), so the code is not clean enough for >> submission to the kernel. It uses the binary arisc firmware from Allwinner >> which there is no source code for, and the DRAM parameters from the FEX >> file have to be explicitly defined for the device in the dts file for the >> arisc to use. >> >> The patch is too big to post to the mailing list (over 1.5MB) and the >> build instructions are more complicated than building a normal mainline >> kernel so I have written up instructions and posted them on the sunxi wiki >> at https://linux-sunxi.org/A33_Suspend >> >> I don't foresee doing much more development on this, so my hope is that >> this patch and instructions can help some effort in the future to get >> suspend to ram into the mainline kernel. >> >> >> >> >> -- > You received this message because you are subscribed to the Google Groups > "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to linux-sunxi+unsubscr...@googlegroups.com. > For more options, visit https://groups.google.com/d/optout. > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v8 9/9] [DO NOT MERGE] ARM: sun8i: v3s: enable LCD panel of Lichee Pi Zero
A 480x272 QiaoDian QD43003C0-40-7LED panel is available from Lichee Pi.
This commit connects this panel to Lichee Pi Zero.
Lichee Pi also provides a 800x480 panel without accurate model number,
so do not merge this patch. It will finally come as device tree overlay.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 36 +++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
index 387fc2aa546d..7ae72bf63cd0 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
@@ -75,6 +75,28 @@
gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */
};
};
+
+ panel: panel {
+ compatible = "qiaodian,qd43003c0-40", "simple-panel";
+ enable-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* Should be
backlight */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel_input: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_out_lcd>;
+ };
+ };
+ };
+};
+
+&de {
+ status = "okay";
};
&mmc0 {
@@ -86,6 +108,20 @@
status = "okay";
};
+&tcon0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_rgb666_pins>;
+ status = "okay";
+
+};
+
+&tcon0_out {
+ tcon0_out_lcd: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_input>;
+ };
+};
+
&uart0 {
pinctrl-0 = <&uart0_pins_a>;
pinctrl-names = "default";
--
2.12.2
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[linux-sunxi] [PATCH v8 8/9] ARM: sun8i: v3s: add pinmux for LCD pins of V3s SoC
Allwinner V3s SoC features a set of pins that have functionality of RGB
LCD, the pins are at different pin ban than other SoCs.
Add pinctrl node for them.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
---
Changes in v7:
- Dropped the trailing "@0" in rgb666 pinmux node name.
- Added Chen-Yu's ACK.
arch/arm/boot/dts/sun8i-v3s.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index e47a9b29f55c..2dbc9d023adf 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -297,6 +297,15 @@
function = "i2c0";
};
+ lcd_rgb666_pins: lcd_rgb666 {
+ pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+ "PE5", "PE6", "PE7", "PE8", "PE9",
+ "PE10", "PE11", "PE12", "PE13", "PE14",
+ "PE15", "PE16", "PE17", "PE18", "PE19",
+ "PE23", "PE24";
+ function = "lcd";
+ };
+
uart0_pins_a: uart0@0 {
pins = "PB8", "PB9";
function = "uart0";
--
2.12.2
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[linux-sunxi] [PATCH v8 7/9] ARM: sun8i: v3s: add device nodes for DE2 display pipeline
Allwinner V3s SoC features a "Display Engine 2.0" with only one mixer
and only one TCON connected to this mixer, which have RGB LCD output.
Add device nodes for this display pipeline.
Signed-off-by: Icenowy Zheng
---
Changes in v8:
- Changed some label names.
Changes in v7:
- Change DE2 clock compatible to V3s one.
- Mention only one TCON in commit message.
- Changed commit brief.
arch/arm/boot/dts/sun8i-v3s.dtsi | 87
1 file changed, 87 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 71075969e5e6..e47a9b29f55c 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -41,6 +41,10 @@
*/
#include
+#include
+#include
+#include
+#include
/ {
#address-cells = <1>;
@@ -59,6 +63,12 @@
};
};
+ de: display-engine {
+ compatible = "allwinner,sun8i-v3s-display-engine";
+ allwinner,pipelines = <&mixer0>;
+ status = "disabled";
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = ,
@@ -93,6 +103,83 @@
#size-cells = <1>;
ranges;
+ display_clocks: clock@100 {
+ compatible = "allwinner,sun8i-v3s-de2-clk";
+ reg = <0x0100 0x10>;
+ clocks = <&ccu CLK_DE>,
+<&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mixer0: mixer@110 {
+ compatible = "allwinner,sun8i-v3s-de2-mixer";
+ reg = <0x0110 0x10>;
+ clocks = <&display_clocks CLK_MIXER0>,
+<&display_clocks CLK_BUS_MIXER0>;
+ clock-names = "mod",
+ "bus";
+ resets = <&display_clocks RST_MIXER0>;
+ assigned-clocks = <&display_clocks CLK_MIXER0>;
+ assigned-clock-rates = <15000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mixer0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint =
<&tcon0_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun8i-v3s-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_TCON0>,
+<&ccu CLK_TCON0>;
+ clock-names = "ahb",
+ "tcon-ch0";
+ clock-output-names = "tcon-pixel-clock";
+ resets = <&ccu RST_BUS_TCON0>;
+ reset-names = "lcd";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint =
<&mixer0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
+
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
--
2.12.2
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[linux-sunxi] [PATCH v8 6/9] drm/sun4i: tcon: add support for V3s TCON
Allwinner V3s SoC features a TCON without channel 1.
Add support for it.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v7:
- Added Chen-Yu's Reviewed-by.
drivers/gpu/drm/sun4i/sun4i_drv.c | 3 ++-
drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 4a979d17ddaa..1dd1948025d2 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -178,7 +178,8 @@ static bool sun4i_drv_node_is_tcon(struct device_node *node)
return of_device_is_compatible(node, "allwinner,sun5i-a13-tcon") ||
of_device_is_compatible(node, "allwinner,sun6i-a31-tcon") ||
of_device_is_compatible(node, "allwinner,sun6i-a31s-tcon") ||
- of_device_is_compatible(node, "allwinner,sun8i-a33-tcon");
+ of_device_is_compatible(node, "allwinner,sun8i-a33-tcon") ||
+ of_device_is_compatible(node, "allwinner,sun8i-v3s-tcon");
}
static int compare_of(struct device *dev, void *data)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 990c973c0334..f44a37a5993d 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -601,11 +601,16 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
/* nothing is supported */
};
+static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
+ /* nothing is supported */
+};
+
static const struct of_device_id sun4i_tcon_of_table[] = {
{ .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
{ .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
{ .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks
},
{ .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
+ { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
{ }
};
MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
--
2.12.2
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[linux-sunxi] [PATCH v8 3/9] drm/sun4i: add a Kconfig option for sun4i-backend
As sun4i-backend is now a dedicated module, add an Kconfig option for it to make it optional, since some build may only use other engines. Signed-off-by: Icenowy Zheng --- Changes in v7: - Adjusted the position of BACKEND makefile item. (It's now after common codes shared between sun4i-backend and sun8i-mixer.) drivers/gpu/drm/sun4i/Kconfig | 10 ++ drivers/gpu/drm/sun4i/Makefile | 3 ++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig index a4b357db8856..5a8227f37cc4 100644 --- a/drivers/gpu/drm/sun4i/Kconfig +++ b/drivers/gpu/drm/sun4i/Kconfig @@ -12,3 +12,13 @@ config DRM_SUN4I Choose this option if you have an Allwinner SoC with a Display Engine. If M is selected the module will be called sun4i-drm. + +config DRM_SUN4I_BACKEND + tristate "Support for Allwinner A10 Display Engine Backend" + depends on DRM_SUN4I + default DRM_SUN4I + help + Choose this option if you have an Allwinner SoC with the + original Allwinner Display Engine, which has a backend to + do some alpha blending and feed graphics to TCON. If M is + selected the module will be called sun4i-backend. diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile index a251fb36c951..da561d064ab8 100644 --- a/drivers/gpu/drm/sun4i/Makefile +++ b/drivers/gpu/drm/sun4i/Makefile @@ -9,6 +9,7 @@ sun4i-tcon-y += sun4i_crtc.o sun4i-backend-y += sun4i_backend.o sun4i_layer.o obj-$(CONFIG_DRM_SUN4I)+= sun4i-drm.o sun4i-tcon.o -obj-$(CONFIG_DRM_SUN4I)+= sun4i-backend.o obj-$(CONFIG_DRM_SUN4I)+= sun6i_drc.o obj-$(CONFIG_DRM_SUN4I)+= sun4i_tv.o + +obj-$(CONFIG_DRM_SUN4I_BACKEND)+= sun4i-backend.o -- 2.12.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v8 5/9] drm/sun4i: Add compatible string for V3s display engine
Allwinner V3s features the new "Display Engine 2.0", which can now also
be driven with our subdrivers in sun4i-drm.
Add the compatible string for in sun4i_drv.c, in order to make the
display engine and its components probed.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 35cad9cb44c5..4a979d17ddaa 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -296,6 +296,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
{ .compatible = "allwinner,sun6i-a31-display-engine" },
{ .compatible = "allwinner,sun6i-a31s-display-engine" },
{ .compatible = "allwinner,sun8i-a33-display-engine" },
+ { .compatible = "allwinner,sun8i-v3s-display-engine" },
{ }
};
MODULE_DEVICE_TABLE(of, sun4i_drv_of_table);
--
2.12.2
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[linux-sunxi] [PATCH v8 4/9] drm/sun4i: add support for Allwinner DE2 mixers
Allwinner have a new "Display Engine 2.0" in their new SoCs, which comes
with mixers to do graphic processing and feed data to TCON, like the old
backends and frontends.
Add support for the mixer on Allwinner V3s SoC; it's the simplest one.
Currently a lot of functions are still missing -- more investigations
are needed to gain enough information for them.
Signed-off-by: Icenowy Zheng
---
Changes in v8:
- Set id manually to -1.
Changes in v7:
- Small fixed advised by Maxime Ripard.
- Added fixup on CRTC destination coordinate.
Changes in v6:
- Rebased on wens's multi-pipeline patchset.
Changes in v5:
- Changed some code alignment.
- Request real 32-bit DMA (prepare for 64-bit SoCs).
Changes in v4:
- Killed some dead code according to Jernej.
drivers/gpu/drm/sun4i/Kconfig | 10 +
drivers/gpu/drm/sun4i/Makefile | 3 +
drivers/gpu/drm/sun4i/sun8i_layer.c | 134
drivers/gpu/drm/sun4i/sun8i_layer.h | 36
drivers/gpu/drm/sun4i/sun8i_mixer.c | 414
drivers/gpu/drm/sun4i/sun8i_mixer.h | 137
6 files changed, 734 insertions(+)
create mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.c
create mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.h
create mode 100644 drivers/gpu/drm/sun4i/sun8i_mixer.c
create mode 100644 drivers/gpu/drm/sun4i/sun8i_mixer.h
diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index 5a8227f37cc4..978ed5032762 100644
--- a/drivers/gpu/drm/sun4i/Kconfig
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -22,3 +22,13 @@ config DRM_SUN4I_BACKEND
original Allwinner Display Engine, which has a backend to
do some alpha blending and feed graphics to TCON. If M is
selected the module will be called sun4i-backend.
+
+config DRM_SUN8I_MIXER
+ tristate "Support for Allwinner Display Engine 2.0 Mixer"
+ depends on DRM_SUN4I
+ default MACH_SUN8I
+ help
+ Choose this option if you have an Allwinner SoC with the
+ Allwinner Display Engine 2.0, which has a mixer to do some
+ graphics mixture and feed graphics to TCON, If M is
+ selected the module will be called sun8i-mixer.
diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index da561d064ab8..7fce97a6f4b8 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -8,8 +8,11 @@ sun4i-tcon-y += sun4i_crtc.o
sun4i-backend-y += sun4i_backend.o sun4i_layer.o
+sun8i-mixer-y += sun8i_mixer.o sun8i_layer.o
+
obj-$(CONFIG_DRM_SUN4I)+= sun4i-drm.o sun4i-tcon.o
obj-$(CONFIG_DRM_SUN4I)+= sun6i_drc.o
obj-$(CONFIG_DRM_SUN4I)+= sun4i_tv.o
obj-$(CONFIG_DRM_SUN4I_BACKEND)+= sun4i-backend.o
+obj-$(CONFIG_DRM_SUN8I_MIXER) += sun8i-mixer.o
diff --git a/drivers/gpu/drm/sun4i/sun8i_layer.c
b/drivers/gpu/drm/sun4i/sun8i_layer.c
new file mode 100644
index ..e627eeece658
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun8i_layer.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) Icenowy Zheng
+ *
+ * Based on sun4i_layer.h, which is:
+ * Copyright (C) 2015 Free Electrons
+ * Copyright (C) 2015 NextThing Co
+ *
+ * Maxime Ripard
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include
+#include
+#include
+
+#include "sun8i_layer.h"
+#include "sun8i_mixer.h"
+
+struct sun8i_plane_desc {
+ enum drm_plane_type type;
+ const uint32_t *formats;
+ uint32_tnformats;
+};
+
+static void sun8i_mixer_layer_atomic_disable(struct drm_plane *plane,
+ struct drm_plane_state
*old_state)
+{
+ struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+ struct sun8i_mixer *mixer = layer->mixer;
+
+ sun8i_mixer_layer_enable(mixer, layer->id, false);
+}
+
+static void sun8i_mixer_layer_atomic_update(struct drm_plane *plane,
+ struct drm_plane_state *old_state)
+{
+ struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+ struct sun8i_mixer *mixer = layer->mixer;
+
+ sun8i_mixer_update_layer_coord(mixer, layer->id, plane);
+ sun8i_mixer_update_layer_formats(mixer, layer->id, plane);
+ sun8i_mixer_update_layer_buffer(mixer, layer->id, plane);
+ sun8i_mixer_layer_enable(mixer, layer->id, true);
+}
+
+static struct drm_plane_helper_funcs sun8i_mixer_layer_helper_funcs = {
+ .atomic_disable = sun8i_mixer_layer_atomic_disable,
+ .atomic_update = sun8i_mixer_layer_atomic_update,
+};
+
+static const struct drm_plane_funcs sun8i_mixer_layer_funcs = {
+ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
+ .atomic_duplicate_sta
[linux-sunxi] [PATCH v8 2/9] drm/sun4i: add a dedicated module for sun4i-backend and sun4i-layer
Currently the direct call from CRTC code to layer code has disappeared,
instead the layer's init function is called via the backend's ops.
Add a dedicated module for sun4i-backend and sun4i-layer, and drop the
EXPORT_SYMBOL from backend code to layer code.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v7:
- Added Chen-Yu's Reviewed-by.
drivers/gpu/drm/sun4i/Makefile| 5 +++--
drivers/gpu/drm/sun4i/sun4i_backend.c | 4
2 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index 59b757350a1f..a251fb36c951 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -5,9 +5,10 @@ sun4i-tcon-y += sun4i_tcon.o
sun4i-tcon-y += sun4i_rgb.o
sun4i-tcon-y += sun4i_dotclock.o
sun4i-tcon-y += sun4i_crtc.o
-sun4i-tcon-y += sun4i_layer.o
+
+sun4i-backend-y += sun4i_backend.o sun4i_layer.o
obj-$(CONFIG_DRM_SUN4I)+= sun4i-drm.o sun4i-tcon.o
-obj-$(CONFIG_DRM_SUN4I)+= sun4i_backend.o
+obj-$(CONFIG_DRM_SUN4I)+= sun4i-backend.o
obj-$(CONFIG_DRM_SUN4I)+= sun6i_drc.o
obj-$(CONFIG_DRM_SUN4I)+= sun4i_tv.o
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c
b/drivers/gpu/drm/sun4i/sun4i_backend.c
index 4af8ccb10bff..cf480218daa5 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -83,7 +83,6 @@ void sun4i_backend_layer_enable(struct sun4i_backend *backend,
regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
}
-EXPORT_SYMBOL(sun4i_backend_layer_enable);
static int sun4i_backend_drm_format_to_layer(struct drm_plane *plane,
u32 format, u32 *mode)
@@ -170,7 +169,6 @@ int sun4i_backend_update_layer_coord(struct sun4i_backend
*backend,
return 0;
}
-EXPORT_SYMBOL(sun4i_backend_update_layer_coord);
int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
int layer, struct drm_plane *plane)
@@ -205,7 +203,6 @@ int sun4i_backend_update_layer_formats(struct sun4i_backend
*backend,
return 0;
}
-EXPORT_SYMBOL(sun4i_backend_update_layer_formats);
int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
int layer, struct drm_plane *plane)
@@ -246,7 +243,6 @@ int sun4i_backend_update_layer_buffer(struct sun4i_backend
*backend,
return 0;
}
-EXPORT_SYMBOL(sun4i_backend_update_layer_buffer);
static int sun4i_backend_init_sat(struct device *dev) {
struct sun4i_backend *backend = dev_get_drvdata(dev);
--
2.12.2
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[linux-sunxi] [PATCH v8 1/9] drm/sun4i: abstract a engine type
As we are going to add support for the Allwinner DE2 engine in sun4i-drm
driver, we will finally have two types of display engines -- the DE1
backend and the DE2 mixer. They both do some display blending and feed
graphics data to TCON, and is part of the "Display Engine" called by
Allwinner, so I choose to call them both "engine" here.
Abstract the engine type to a new struct with an ops struct, which contains
functions that should be called outside the engine-specified code (in
TCON, CRTC or TV Encoder code).
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v8:
- Changed id into a field in sunxi_engine struct.
Changes in v7:
- Mention "Display Engine" for the name "engine".
- Fixed some small issues found by Chen-Yu and added his ACK.
Changes in v6:
- Rebased on wens's multi-pipeline patchset.
- Split out Makefile changes.
Changes in v5:
- Really made a sunxi_engine struct type, and moved ops pointer
into it.
- Added checked ops wrappers.
- Changed the second parameter of layers_init from crtc to engine.
Changes in v4:
- Comments to tag the color correction functions as optional.
- Check before calling the optional functions.
- Change layers_init to satisfy new PATCH v4 04/11.
drivers/gpu/drm/sun4i/sun4i_backend.c | 74 ++
drivers/gpu/drm/sun4i/sun4i_backend.h | 19 +++
drivers/gpu/drm/sun4i/sun4i_crtc.c| 11 ++--
drivers/gpu/drm/sun4i/sun4i_crtc.h| 4 +-
drivers/gpu/drm/sun4i/sun4i_drv.c | 2 +-
drivers/gpu/drm/sun4i/sun4i_drv.h | 2 +-
drivers/gpu/drm/sun4i/sun4i_layer.c | 9 ++--
drivers/gpu/drm/sun4i/sun4i_layer.h | 4 +-
drivers/gpu/drm/sun4i/sun4i_tcon.c| 38 --
drivers/gpu/drm/sun4i/sun4i_tv.c | 9 ++--
drivers/gpu/drm/sun4i/sunxi_engine.h | 98 +++
11 files changed, 189 insertions(+), 81 deletions(-)
create mode 100644 drivers/gpu/drm/sun4i/sunxi_engine.h
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c
b/drivers/gpu/drm/sun4i/sun4i_backend.c
index e53107418add..4af8ccb10bff 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -25,6 +25,8 @@
#include "sun4i_backend.h"
#include "sun4i_drv.h"
+#include "sun4i_layer.h"
+#include "sunxi_engine.h"
static const u32 sunxi_rgb2yuv_coef[12] = {
0x0107, 0x0204, 0x0064, 0x0108,
@@ -32,41 +34,38 @@ static const u32 sunxi_rgb2yuv_coef[12] = {
0x01c1, 0x3e88, 0x3fb8, 0x0808
};
-void sun4i_backend_apply_color_correction(struct sun4i_backend *backend)
+static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine)
{
int i;
DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
/* Set color correction */
- regmap_write(backend->regs, SUN4I_BACKEND_OCCTL_REG,
+ regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG,
SUN4I_BACKEND_OCCTL_ENABLE);
for (i = 0; i < 12; i++)
- regmap_write(backend->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
+ regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
sunxi_rgb2yuv_coef[i]);
}
-EXPORT_SYMBOL(sun4i_backend_apply_color_correction);
-void sun4i_backend_disable_color_correction(struct sun4i_backend *backend)
+static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine)
{
DRM_DEBUG_DRIVER("Disabling color correction\n");
/* Disable color correction */
- regmap_update_bits(backend->regs, SUN4I_BACKEND_OCCTL_REG,
+ regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG,
SUN4I_BACKEND_OCCTL_ENABLE, 0);
}
-EXPORT_SYMBOL(sun4i_backend_disable_color_correction);
-void sun4i_backend_commit(struct sun4i_backend *backend)
+static void sun4i_backend_commit(struct sunxi_engine *engine)
{
DRM_DEBUG_DRIVER("Committing changes\n");
- regmap_write(backend->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
+ regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS |
SUN4I_BACKEND_REGBUFFCTL_LOADCTL);
}
-EXPORT_SYMBOL(sun4i_backend_commit);
void sun4i_backend_layer_enable(struct sun4i_backend *backend,
int layer, bool enable)
@@ -81,7 +80,7 @@ void sun4i_backend_layer_enable(struct sun4i_backend *backend,
else
val = 0;
- regmap_update_bits(backend->regs, SUN4I_BACKEND_MODCTL_REG,
+ regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
}
EXPORT_SYMBOL(sun4i_backend_layer_enable);
@@ -144,27 +143,28 @@ int sun4i_backend_update_layer_coord(struct sun4i_backend
*backend,
if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H:
%u\n",
state-
[linux-sunxi] [PATCH v8 0/9] Initial Allwinner Display Engine 2.0 Support
This patchset is the initial patchset for Allwinner DE2 support. As the DE2 CCU support is already applied, this patchset now contains only DRM changes and device tree changes. The SoC used to develop this patchset is V3s, as V3s is the simplest one of the SoCs that have DE2. (Allwinner V3s features only one mixer, and its only video output is RGB LCD, which is already supported in our TCON driver) The last patch is only a testing patch, it shouldn't be merged; and for the patch to be really usable, the RFC fix of the TCON driver [1] is needed. No HDMI, TV encoder or other internal bridges' support is included in this patchset, which makes it currently not usable on H3. Thanks to Jean-Francois Moine and Jernej Skrabec for their efforts to discover the internal of DE2! [1] https://lists.freedesktop.org/archives/dri-devel/2016-December/126264.html Icenowy Zheng (9): drm/sun4i: abstract a engine type drm/sun4i: add a dedicated module for sun4i-backend and sun4i-layer drm/sun4i: add a Kconfig option for sun4i-backend drm/sun4i: add support for Allwinner DE2 mixers drm/sun4i: Add compatible string for V3s display engine drm/sun4i: tcon: add support for V3s TCON ARM: sun8i: v3s: add device nodes for DE2 display pipeline ARM: sun8i: v3s: add pinmux for LCD pins of V3s SoC [DO NOT MERGE] ARM: sun8i: v3s: enable LCD panel of Lichee Pi Zero arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 36 +++ arch/arm/boot/dts/sun8i-v3s.dtsi | 96 ++ drivers/gpu/drm/sun4i/Kconfig | 20 ++ drivers/gpu/drm/sun4i/Makefile| 9 +- drivers/gpu/drm/sun4i/sun4i_backend.c | 78 ++--- drivers/gpu/drm/sun4i/sun4i_backend.h | 19 +- drivers/gpu/drm/sun4i/sun4i_crtc.c| 11 +- drivers/gpu/drm/sun4i/sun4i_crtc.h| 4 +- drivers/gpu/drm/sun4i/sun4i_drv.c | 6 +- drivers/gpu/drm/sun4i/sun4i_drv.h | 2 +- drivers/gpu/drm/sun4i/sun4i_layer.c | 9 +- drivers/gpu/drm/sun4i/sun4i_layer.h | 4 +- drivers/gpu/drm/sun4i/sun4i_tcon.c| 43 +-- drivers/gpu/drm/sun4i/sun4i_tv.c | 9 +- drivers/gpu/drm/sun4i/sun8i_layer.c | 134 + drivers/gpu/drm/sun4i/sun8i_layer.h | 36 +++ drivers/gpu/drm/sun4i/sun8i_mixer.c | 414 ++ drivers/gpu/drm/sun4i/sun8i_mixer.h | 137 + drivers/gpu/drm/sun4i/sunxi_engine.h | 98 ++ 19 files changed, 1077 insertions(+), 88 deletions(-) create mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.c create mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.h create mode 100644 drivers/gpu/drm/sun4i/sun8i_mixer.c create mode 100644 drivers/gpu/drm/sun4i/sun8i_mixer.h create mode 100644 drivers/gpu/drm/sun4i/sunxi_engine.h -- 2.12.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCHv6 12/28] net: Add ability to set MAC address via EEPROM
Hi Oliver, On 15 May 2017 at 02:02, Olliver Schinagl wrote: > This patch allows Kconfig to enable and set parameters to make it > possible to read the MAC address from an EEPROM. The net core layer then > uses this information to read MAC addresses from this EEPROM. > > Besides the various tuneables as to how to access the eeprom (bus, > address, addressing mode/length, 2 configurable that are EEPROM generic > (e.g. SPI or some other form of access) which are: > > NET_ETHADDR_EEPROM_OFFSET, indicating where in the EEPROM the start of > the MAC address is. The default is 8 allowing for 8 bytes before the MAC > for other purposes (header MAGIC for example). > > NET_ETHADDR_EEPROM_CRC8, indicating the MAC is appended with a CRC8-CCIT > checksum that should be verified. > > Currently only I2C eeproms have been tested and thus only those options > are available, but shouldn't be a limit. NET_ETHADDR_EEPROM_SPI can be > just as created and added. > > The code currently first checks if there is a non-zero MAC address in > the eeprom. If that fails to be the case, the read_rom_hwaddr can be > used by a board to supply the MAC in other ways. > > If both these fails, the other code is still in place to query the > environent, which then can be used to override the hardware supplied > data. > > Signed-off-by: Olliver Schinagl > --- > arch/arm/mach-sunxi/Kconfig| 8 +-- > configs/A10-OLinuXino-Lime_defconfig | 1 - > configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 - > configs/A20-OLinuXino-Lime2_defconfig | 1 - > configs/A20-OLinuXino-Lime_defconfig | 1 - > configs/A20-OLinuXino_MICRO_defconfig | 1 - > doc/README.enetaddr| 95 > ++ > include/net.h | 14 + > net/Kconfig| 59 +++ > net/eth-uclass.c | 42 +++-- > net/eth_common.c | 37 > net/eth_legacy.c | 2 + > 12 files changed, 231 insertions(+), 31 deletions(-) > Please don't implement this feature in legacy code / legacy I2C. New features should only use DM - otherwise it just makes it harder and harder to ever finish the port. Regards, Simon -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCHv6 24/28] net: dw: Expose designware_eth_start
On 15 May 2017 at 02:02, Olliver Schinagl wrote:
> Commit e72ced234045f ("net: designware: Export the operation functions")
> started to expose some of the net_ops. The sunxi_gmac glue driver also
> needs the start function, so let us expose that as well.
>
> Signed-off-by: Olliver Schinagl
> ---
> drivers/net/designware.c | 2 +-
> drivers/net/designware.h | 1 +
> 2 files changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Simon Glass
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Re: [linux-sunxi] linux-sunxi.org down
On Wed, May 17, 2017 at 12:20:20PM +0200, Luc Verhaegen wrote: > On Wed, May 17, 2017 at 09:01:30AM +0200, Benjamin Henrion wrote: > > Hi, > > > > Just to let you know that linux-sunxi.org seems to be down. > > > > Best, > > Hetzner moved the server, the xen images for the different vms were not > loaded, looking into it. > > Luc Verhaegen. Back. Luc Verhaegen. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] linux-sunxi.org down
On Wed, May 17, 2017 at 09:01:30AM +0200, Benjamin Henrion wrote: > Hi, > > Just to let you know that linux-sunxi.org seems to be down. > > Best, Hetzner moved the server, the xen images for the different vms were not loaded, looking into it. Luc Verhaegen. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v7 11/13] ARM: sun8i: v3s: add device nodes for DE2 display pipeline
在 2017-05-17 17:27，icen...@aosc.io 写道：
在 2017-05-15 17:24，Maxime Ripard 写道：
On Mon, May 15, 2017 at 12:30:43AM +0800, Icenowy Zheng wrote:
+ de2_clocks: clock@100 {
display_clocks would be better there, we don't have to dissociate de1
with de2
How about de_clocks ? (See A80 DTSI)
Oh I regretted... de here indicates "de1".
display_clocks is better.
+ compatible = "allwinner,sun8i-v3s-de2-clk";
+ reg = <0x0100 0x10>;
+ clocks = <&ccu CLK_DE>,
+<&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ de2_mixer0: mixer@110 {
and mixer0 here is enough too.
Is there several of them? Why not just use mixer if there's only one?
Nope, here it's tagged 0 only for consistency with other SoCs.
+ compatible = "allwinner,sun8i-v3s-de2-mixer";
+ reg = <0x0110 0x10>;
+ clocks = <&de2_clocks CLK_MIXER0>,
+<&de2_clocks CLK_BUS_MIXER0>;
+ clock-names = "mod",
+ "bus";
+ resets = <&de2_clocks RST_MIXER0>;
+ assigned-clocks = <&de2_clocks CLK_MIXER0>;
+ assigned-clock-rates = <15000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mixer0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint =
<&tcon0_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun8i-v3s-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_TCON0>,
+<&ccu CLK_TCON0>;
+ clock-names = "ahb",
+ "tcon-ch0";
+ clock-output-names = "tcon-pixel-clock";
+ resets = <&ccu RST_BUS_TCON0>;
+ reset-names = "lcd";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint =
<&mixer0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
+
You have an extra new line here.
Maxime
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[linux-sunxi] Re: [PATCH v7 11/13] ARM: sun8i: v3s: add device nodes for DE2 display pipeline
在 2017-05-15 17:24，Maxime Ripard 写道：
On Mon, May 15, 2017 at 12:30:43AM +0800, Icenowy Zheng wrote:
+ de2_clocks: clock@100 {
display_clocks would be better there, we don't have to dissociate de1
with de2
How about de_clocks ? (See A80 DTSI)
+ compatible = "allwinner,sun8i-v3s-de2-clk";
+ reg = <0x0100 0x10>;
+ clocks = <&ccu CLK_DE>,
+<&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ de2_mixer0: mixer@110 {
and mixer0 here is enough too.
Is there several of them? Why not just use mixer if there's only one?
Nope, here it's tagged 0 only for consistency with other SoCs.
+ compatible = "allwinner,sun8i-v3s-de2-mixer";
+ reg = <0x0110 0x10>;
+ clocks = <&de2_clocks CLK_MIXER0>,
+<&de2_clocks CLK_BUS_MIXER0>;
+ clock-names = "mod",
+ "bus";
+ resets = <&de2_clocks RST_MIXER0>;
+ assigned-clocks = <&de2_clocks CLK_MIXER0>;
+ assigned-clock-rates = <15000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mixer0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint =
<&tcon0_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun8i-v3s-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_TCON0>,
+<&ccu CLK_TCON0>;
+ clock-names = "ahb",
+ "tcon-ch0";
+ clock-output-names = "tcon-pixel-clock";
+ resets = <&ccu RST_BUS_TCON0>;
+ reset-names = "lcd";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint =
<&mixer0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
+
You have an extra new line here.
Maxime
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[linux-sunxi] Re: Final discussion on a dedicated thermal sensor driver for Allwinner H3/A64/H5/A83T/R40
On Mon, May 15, 2017 at 12:06:49PM +0800, Icenowy Zheng wrote: > >> P.S. Maybe the A33 thermal sensor also shouldn't go into IIO > >framework, > >> for the first reason mentioned above. > > > >I still haven't seen any compelling argument, and until I see one, I > >will oppose any thing like that, for the reasons above. > > Totally you are thinking reusing the full GPADC driver on H3+. > However, the only reusable code is in fact very few. But that code is _already_ _there_. You were saying that it would take 200+ lines, maybe, but that's still 200 lines that are duplicated. Really, this whole thing *is* a final decision. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] linux-sunxi.org down
Hi, Just to let you know that linux-sunxi.org seems to be down. Best, -- Benjamin Henrion FFII Brussels - +32-484-566109 - +32-2-3500762 "In July 2005, after several failed attempts to legalise software patents in Europe, the patent establishment changed its strategy. Instead of explicitly seeking to sanction the patentability of software, they are now seeking to create a central European patent court, which would establish and enforce patentability rules in their favor, without any possibility of correction by competing courts or democratically elected legislators." -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
