[linux-sunxi] Re: [PATCH v4 0/8] Allwinner H6 Mali GPU support
On 16/05/2019 00:22, Rob Herring wrote: On Wed, May 15, 2019 at 5:06 PM Clément Péron wrote: Hi Robin, On Tue, 14 May 2019 at 23:57, Robin Murphy wrote: On 2019-05-14 10:22 pm, Clément Péron wrote: Hi, On Tue, 14 May 2019 at 17:17, Clément Péron wrote: Hi, On Tue, 14 May 2019 at 12:29, Neil Armstrong wrote: Hi, On 13/05/2019 17:14, Daniel Vetter wrote: On Sun, May 12, 2019 at 07:46:00PM +0200, peron.c...@gmail.com wrote: From: Clément Péron Hi, The Allwinner H6 has a Mali-T720 MP2. The drivers are out-of-tree so this series only introduce the dt-bindings. We do have an in-tree midgard driver now (since 5.2). Does this stuff work together with your dt changes here? No, but it should be easy to add. I will give it a try and let you know. Added the bus_clock and a ramp delay to the gpu_vdd but the driver fail at probe. [3.052919] panfrost 180.gpu: clock rate = 43200 [3.058278] panfrost 180.gpu: bus_clock rate = 1 [3.179772] panfrost 180.gpu: mali-t720 id 0x720 major 0x1 minor 0x1 status 0x0 [3.187432] panfrost 180.gpu: features: ,10309e40, issues: ,21054400 [3.195531] panfrost 180.gpu: Features: L2:0x07110206 Shader:0x Tiler:0x0809 Mem:0x1 MMU:0x2821 AS:0xf JS:0x7 [3.207178] panfrost 180.gpu: shader_present=0x3 l2_present=0x1 [3.238257] panfrost 180.gpu: Fatal error during GPU init [3.244165] panfrost: probe of 180.gpu failed with error -12 The ENOMEM is coming from "panfrost_mmu_init" alloc_io_pgtable_ops(ARM_MALI_LPAE, >mmu->pgtbl_cfg, pfdev); Which is due to a check in the pgtable alloc "cfg->ias != 48" arm-lpae io-pgtable: arm_mali_lpae_alloc_pgtable cfg->ias 33 cfg->oas 40 DRI stack is totally new for me, could you give me a little clue about this issue ? Heh, this is probably the one bit which doesn't really count as "DRI stack". That's merely a somewhat-conservative sanity check - I'm pretty sure it *should* be fine to change the test to "cfg->ias > 48" (io-pgtable itself ought to cope). You'll just get to be the first to actually test a non-48-bit configuration here :) Thanks a lot, the probe seems fine now :) I try to run glmark2 : # glmark2-es2-drm === glmark2 2017.07 === OpenGL Information GL_VENDOR: panfrost GL_RENDERER: panfrost GL_VERSION:OpenGL ES 2.0 Mesa 19.1.0-rc2 === [build] use-vbo=false: But it seems that H6 is not so easy to add :(. [ 345.204813] panfrost 180.gpu: mmu irq status=1 [ 345.209617] panfrost 180.gpu: Unhandled Page fault in AS0 at VA 0x02400400 [ 345.209617] Reason: TODO [ 345.209617] raw fault status: 0x82C1 [ 345.209617] decoded fault status: SLAVE FAULT [ 345.209617] exception type 0xC1: TRANSLATION_FAULT_LEVEL1 [ 345.209617] access type 0x2: READ [ 345.209617] source id 0x8000 [ 345.729957] panfrost 180.gpu: gpu sched timeout, js=0, status=0x8, head=0x2400400, tail=0x2400400, sched_job=9e204de9 [ 346.055876] panfrost 180.gpu: mmu irq status=1 [ 346.060680] panfrost 180.gpu: Unhandled Page fault in AS0 at VA 0x02C00A00 [ 346.060680] Reason: TODO [ 346.060680] raw fault status: 0x810002C1 [ 346.060680] decoded fault status: SLAVE FAULT [ 346.060680] exception type 0xC1: TRANSLATION_FAULT_LEVEL1 [ 346.060680] access type 0x2: READ [ 346.060680] source id 0x8100 [ 346.561955] panfrost 180.gpu: gpu sched timeout, js=1, status=0x8, head=0x2c00a00, tail=0x2c00a00, sched_job=b55a9a85 [ 346.573913] panfrost 180.gpu: mmu irq status=1 [ 346.578707] panfrost 180.gpu: Unhandled Page fault in AS0 at VA 0x02C00B80 [ 346.578707] Reason: TODO [ 346.578707] raw fault status: 0x82C1 [ 346.578707] decoded fault status: SLAVE FAULT [ 346.578707] exception type 0xC1: TRANSLATION_FAULT_LEVEL1 [ 346.578707] access type 0x2: READ [ 346.578707] source id 0x8000 [ 347.073947] panfrost 180.gpu: gpu sched timeout, js=0, status=0x8, head=0x2c00b80, tail=0x2c00b80, sched_job=cf6af8e8 [ 347.104125] panfrost 180.gpu: mmu irq status=1 [ 347.108930] panfrost 180.gpu: Unhandled Page fault in AS0 at VA 0x02800900 [ 347.108930] Reason: TODO [ 347.108930] raw fault status: 0x810002C1 [ 347.108930] decoded faultn thi status: SLAVE FAULT [ 347.108930] exception type 0xC1: TRANSLATION_FAULT_LEVEL1 [ 347.108930] access type 0x2: READ [ 347.108930] source id 0x8100 [ 347.617950] panfrost 180.gpu: gpu sched timeout, js=1, status=0x8, head=0x2800900, tail=0x2800900, sched_job=9325fdb7 [ 347.629902] panfrost 180.gpu: mmu irq status=1 [ 347.634696] panfrost 180.gpu: Unhandled Page fault in AS0 at VA 0x02800A80 Is this 32 or 64 bit userspace? I think 64-bit does not
Re: [linux-sunxi] [PATCH 2/6] sunxi: gpio: Enable support for H6 pin controller
On Thu, 16 May 2019 10:34:38 +0800
Icenowy Zheng wrote:
Hi Icenowy,
thanks for having a look!
> 于 2019年5月16日 GMT+08:00 上午9:26:29, Andre Przywara 写到:
> >The Allwinner H6 pin controller is not really special, at least not
> >when it comes to normal GPIO operation.
> >
> >Add the H6 compatible strings to the list of recognised strings, to
> >make GPIOs work for H6 boards.
> >
> >Signed-off-by: Andre Przywara
> >---
> > drivers/gpio/sunxi_gpio.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> >diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
> >index cbed8d42b7..780c39962a 100644
> >--- a/drivers/gpio/sunxi_gpio.c
> >+++ b/drivers/gpio/sunxi_gpio.c
> >@@ -354,12 +354,14 @@ static const struct udevice_id sunxi_gpio_ids[] =
> >{
> > ID("allwinner,sun8i-v3s-pinctrl", a_all),
> > ID("allwinner,sun9i-a80-pinctrl", a_all),
> > ID("allwinner,sun50i-a64-pinctrl", a_all),
> >+ID("allwinner,sun50i-h6-pinctrl", a_all),
> > ID("allwinner,sun6i-a31-r-pinctrl", l_2),
> > ID("allwinner,sun8i-a23-r-pinctrl", l_1),
> > ID("allwinner,sun8i-a83t-r-pinctrl",l_1),
> > ID("allwinner,sun8i-h3-r-pinctrl", l_1),
> > ID("allwinner,sun9i-a80-r-pinctrl", l_3),
> > ID("allwinner,sun50i-a64-r-pinctrl",l_1),
> >+ID("allwinner,sun50i-h6-r-pinctrl", l_1),
>
> Should be l_2 because H6 has PM bank.
Oh, indeed, I totally missed that. Thanks for pointing this out!
Cheers,
Andre
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Re: [linux-sunxi] SPL uboot and A64
Thank for your reply. But I try to work with "official" image if I try to boot armbian (Armbian_5.83_Bananapim64_Debian_stretch_next_4.19.38) nothing boot but if I use a oder image like (simpleimage-pine64-latest.img) it boot. I don't understand why boot0.bin start and sunxi-spl.bin don't start (and had working some time ago) Philippe Le mercredi 15 mai 2019 17:48:58 UTC+2, Clément Péron a écrit : > > Hi, > > SPL_TEXT_BASE move to Kconfig > You need to set it. > > https://patchwork.ozlabs.org/patch/1099637/ > > Regards, > Clement > > On Wed, 15 May 2019 at 17:33, Philippe Fouquet > wrote: > > > > Hello > > > > I work with A64 (bpi M64). > > For a moment I use to U-boot ( SPL build into 32 bit and u-boot in 64 > bit) and all worked well I had flash sd, eMMC or I booted with fel mode all > are ok. > > But I stoped my work for some weeks and now nothing boot any more. > > > > I try to explain my self, if I flash a sd with old image (that use > boot0.bin) all boot (I try three different image). But if I flash some new > one (with uboot SPL) nothing start (no log, no print on UART0). > > > > Some body know what can be wrong in my system? > > > > Thank by advance > > Philippe > > > > -- > > You received this message because you are subscribed to the Google > Groups "linux-sunxi" group. > > To unsubscribe from this group and stop receiving emails from it, send > an email to linux...@googlegroups.com . > > To view this discussion on the web, visit > https://groups.google.com/d/msgid/linux-sunxi/096739ac-dd50-48f0-a003-019d7bac89be%40googlegroups.com. > > > > For more options, visit https://groups.google.com/d/optout. > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/dcf145c9-ae4b-4dad-afea-b50a78dfa2dc%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v10 0/2] drm/sun4i: sun6i_mipi_dsi: Fixes/updates
On Mon, May 13, 2019 at 12:11:25AM +0530, Jagan Teki wrote: > This is v10 for the previous series[1] and few pathes are dropped > as part of this series since it would require separate rework same > will send in separately or another series. APplied both, thanks Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190516091105.er6oeyrnompwik3j%40flea. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v2] arm64: dts: allwinner: a64: orangepi-win: Add wifi and bluetooth nodes
On Tue, May 14, 2019 at 10:54:45PM +0200, Jernej Skrabec wrote: > The AP6212 is based on the Broadcom BCM43430 or BCM43438. The WiFi side > identifies as BCM43430, while the Bluetooth side identifies as BCM43438. > > WiFi is connected to mmc1 and the Bluetooth side is connected to UART1 > in a 4 wire configuration. Same as the WiFi side, due to being the same > chip and package, DLDO2 provides overall power via VBAT, and DLDO4 > provides I/O power via VDDIO. The RTC clock output provides the LPO low > power clock at 32.768 kHz. > > This patch enables WiFi and Bluetooth on OrangePi Win boards and adds > missing LPO clock on the WiFi side. PCM connection also exists for > Bluetooth audio, but it's not used here. > > Bluetooth UART speed is set to 1.5 MBaud in order to be able transmit > audio. While module supports even higher speeds, currently sunxi clock > driver doesn't support higher speed. > > Signed-off-by: Jernej Skrabec Queued for 5.3, thanks Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190516085257.tbli227f7mm3daac%40flea. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH 0/2] drm/sun4i: Fix sun8i HDMI PHY initialization
On Tue, May 14, 2019 at 10:43:35PM +0200, Jernej Skrabec wrote: > I received a report that 4K resolution doesn't work if U-Boot video > driver is disabled. It turns out that HDMI PHY clock driver was > initialized prematurely, before reset line was deasserted and clocks > enabled. U-Boot video driver masked the issue because it set pixel > clock correctly. > > In the process of researching the bug, I also found out that few bits > in HDMI PHY registers were not set correctly. While there is no > noticeable change (4K resolution works with both settings), I've > added fix anyway, to be conformant with vendor documentation. Applied both, thanks Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190516083104.rr2ewg3dd4aej67b%40flea. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [U-Boot] [PATCH 2/2] sunxi: Pine64: DTS: enable USB PHY 0 for HCI0
On Thu, May 16, 2019 at 1:47 AM Andre Przywara wrote:
>
> The first USB controller on the A64 SoC shares a PHY with the OTG
> controller. Reportedly to avoid problems with the VBUS regulator under
> Linux, we don't link OHCI0/EHCI0 to the USB PHY in the A64 .dtsi file.
>
> However on boards which can't use peripheral mode (because they have an
> always-on VBUS supply on an USB-A socket) we don't need this trick, and
> can properly connect host controller 0 to the PHY 0.
>
> Amend the Pine64 and SoPine/LTS .dts to reflect this. This enables the
> upper USB port in U-Boot on those boards.
>
> Signed-off-by: Andre Przywara
> ---
> arch/arm/dts/sun50i-a64-pine64.dts | 5 -
> arch/arm/dts/sun50i-a64-sopine-baseboard.dts | 5 -
> 2 files changed, 8 insertions(+), 2 deletions(-)
Are these changes going to go upstream to Linux too? If not it's
probably best to add it to a u-boot.dtsi so the changes don't get lost
when the DT files are re-synced from Linux. Same with the similar
patches for the H6 boards.
Peter
> diff --git a/arch/arm/dts/sun50i-a64-pine64.dts
> b/arch/arm/dts/sun50i-a64-pine64.dts
> index c077b6c1f4..523a4d5bff 100644
> --- a/arch/arm/dts/sun50i-a64-pine64.dts
> +++ b/arch/arm/dts/sun50i-a64-pine64.dts
> @@ -80,6 +80,8 @@
> };
>
> {
> + phys = < 0>;
> + phy-names = "usb";
> status = "okay";
> };
>
> @@ -136,6 +138,8 @@
> };
>
> {
> + phys = < 0>;
> + phy-names = "usb";
> status = "okay";
> };
>
> @@ -301,7 +305,6 @@
>
> _otg {
> dr_mode = "host";
> - status = "okay";
> };
>
> {
> diff --git a/arch/arm/dts/sun50i-a64-sopine-baseboard.dts
> b/arch/arm/dts/sun50i-a64-sopine-baseboard.dts
> index 53fcc9098d..1986897177 100644
> --- a/arch/arm/dts/sun50i-a64-sopine-baseboard.dts
> +++ b/arch/arm/dts/sun50i-a64-sopine-baseboard.dts
> @@ -85,6 +85,8 @@
> };
>
> {
> + phys = < 0>;
> + phy-names = "usb";
> status = "okay";
> };
>
> @@ -131,6 +133,8 @@
> };
>
> {
> + phys = < 0>;
> + phy-names = "usb";
> status = "okay";
> };
>
> @@ -172,7 +176,6 @@
>
> _otg {
> dr_mode = "host";
> - status = "okay";
> };
>
> {
> --
> 2.14.5
>
> ___
> U-Boot mailing list
> u-b...@lists.denx.de
> https://lists.denx.de/listinfo/u-boot
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