[linux-sunxi] Re: [PATCH v3 0/6] PWM support for allwinner sun8i R40/T3/V40 SOCs.

2021-10-27 Thread Hao Zhang 
Never mind, you can continue it.

Icenowy Zheng  于2021年7月22日周四 上午9:03写道：
>
> Hao,
>
> Would you mind me to continue on this work? Newer Allwinner SoCs have
> PWM controllers similar to the R40 one.
>
> Yours sincerely,
> Icenowy Zheng
>
>
> 在 2018-11-26星期一的 00:18 +0800，Hao Zhang写道：
> > PWM support for allwinner sun8i R40/T3/V40 SOCs.
> >
> > The sun8i R40/T3/V40 PWM has 8 PWM channals and divides to 4 PWM
> > pairs,
> > each PWM pair built-in 1 clock module, 2 timer logic module and 1
> > programmable dead-time generator, it also support waveform capture.
> > It has 2 clock sources OSC24M and APB1, it is different with the
> > sun4i-pwm driver, Therefore add a new driver for it.
> >
> > Some test method:
> > cd /sys/class/pwm/pwmchip0
> > echo 0 > export
> > cd pwm0
> > echo 1000 > period
> > echo 500 > duty_cycle
> > echo 1 > enable
> > then check the PB2 pin with oscilloscope.
> >
> > v3 Changes:
> > 1. fix coding format.
> > 2. use 2/ilog2 instead of divide table
> > 3. remove spinlock.
> > 4. remove sun8i_pwm_data structure and use DT to parse pwm-channals
> > 5. remove inline because complier knows it better.
> > 6. don't hardcode clock source and parse two clock source from dt
> > "mux-0"
> >and "mux-1"
> > 7. remove bypass method.
> > 8. add a method to change clock source when mux-0 is not support the
> >input period it can change to mux-1.
> > 9. add cycle range check.
> > 10. add some variable to make it more readability.
> > 11. add clk_disable_unprepare when some false accur.
> >
> > v2 Changes:
> > 1. change sun8i-r40 symbol to sun8i.
> > 2. change pwm0_pin, pwm0-pin to pwm_ch0_pin, pwm-ch0-pin.
> > 3. remove clk_disable_unprepare(), check !match and IS_ERR(pwm-
> > >regmap).
> >
> > Hao Zhang (6):
> >   Documentation: ARM: sunxi: pwm: add Allwinner sun8i.
> >   ARM: dtsi: add pwm node for sun8i R40.
> >   ARM: dts: add PWM for Bananapi M2 Ultrar board.
> >   DEV: CLK: add function to check the using clock name of driver.
> >   DEV: CLK: sunxi ccu: export clk_apb1 for sun8i-r40 soc pwm.
> >   ARM: PWM: add allwinner sun8i R40/T3/V40 PWM support.
> >
> >  .../devicetree/bindings/pwm/pwm-sun8i.txt  |  24 ++
> >  arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts  |   6 +
> >  arch/arm/boot/dts/sun8i-r40.dtsi   |  17 +
> >  drivers/clk/clk.c  |   6 +
> >  drivers/clk/sunxi-ng/ccu-sun8i-r40.h   |   4 +-
> >  drivers/pwm/Kconfig|  12 +-
> >  drivers/pwm/Makefile   |   1 +
> >  drivers/pwm/pwm-sun8i.c| 418
> > +
> >  include/dt-bindings/clock/sun8i-r40-ccu.h  |   2 +
> >  include/linux/clk-provider.h   |   1 +
> >  10 files changed, 489 insertions(+), 2 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/pwm/pwm-
> > sun8i.txt
> >  create mode 100644 drivers/pwm/pwm-sun8i.c
> >
>

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[linux-sunxi] Re: [PATCH v3 6/6] ARM: PWM: add allwinner sun8i R40/T3/V40 PWM support.

2019-03-11 Thread Hao Zhang 
Thierry Reding  于2018年12月21日周五 上午1:57写道：
>
> On Mon, Nov 26, 2018 at 12:23:19AM +0800, Hao Zhang wrote:
> > The sun8i R40/T3/V40 PWM has 8 PWM channals and divides to 4 PWM pairs,
> > each PWM pair built-in 1 clock module, 2 timer logic module and 1
> > programmable dead-time generator, it also support waveform capture.
> > It has 2 clock sources OSC24M and APB1, it is different with the
> > sun4i-pwm driver, Therefore add a new driver for it.
> >
> > Signed-off-by: Hao Zhang 
> > ---
> >  drivers/pwm/Kconfig |  12 +-
> >  drivers/pwm/Makefile|   1 +
> >  drivers/pwm/pwm-sun8i.c | 418 
> > 
> >  3 files changed, 430 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/pwm/pwm-sun8i.c
> >
> > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> > index 504d252..6105ac8 100644
> > --- a/drivers/pwm/Kconfig
> > +++ b/drivers/pwm/Kconfig
> > @@ -426,7 +426,7 @@ config PWM_STMPE
> > expanders.
> >
> >  config PWM_SUN4I
> > - tristate "Allwinner PWM support"
> > + tristate "Allwinner SUN4I PWM support"
> >   depends on ARCH_SUNXI || COMPILE_TEST
> >   depends on HAS_IOMEM && COMMON_CLK
> >   help
> > @@ -435,6 +435,16 @@ config PWM_SUN4I
> > To compile this driver as a module, choose M here: the module
> > will be called pwm-sun4i.
> >
> > +config PWM_SUN8I
> > + tristate "Allwinner SUN8I (R40/V40/T3) PWM support"
> > + depends on ARCH_SUNXI || COMPILE_TEST
> > + depends on HAS_IOMEM && COMMON_CLK
> > + help
> > +   Generic PWM framework driver for Allwinner R40/V40/T3 SoCs.
> > +
> > +   To compile this driver as a module, choose M here: the module
> > +   will be called pwm-sun8i.
> > +
> >  config PWM_TEGRA
> >   tristate "NVIDIA Tegra PWM support"
> >   depends on ARCH_TEGRA
> > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> > index 9c676a0..32c8d2d 100644
> > --- a/drivers/pwm/Makefile
> > +++ b/drivers/pwm/Makefile
> > @@ -43,6 +43,7 @@ obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
> >  obj-$(CONFIG_PWM_STM32_LP)   += pwm-stm32-lp.o
> >  obj-$(CONFIG_PWM_STMPE)  += pwm-stmpe.o
> >  obj-$(CONFIG_PWM_SUN4I)  += pwm-sun4i.o
> > +obj-$(CONFIG_PWM_SUN8I)  += pwm-sun8i.o
> >  obj-$(CONFIG_PWM_TEGRA)      += pwm-tegra.o
> >  obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o
> >  obj-$(CONFIG_PWM_TIEHRPWM)   += pwm-tiehrpwm.o
> > diff --git a/drivers/pwm/pwm-sun8i.c b/drivers/pwm/pwm-sun8i.c
> > new file mode 100644
> > index 000..d8597e4
> > --- /dev/null
> > +++ b/drivers/pwm/pwm-sun8i.c
> > @@ -0,0 +1,418 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +// Copyright (C) 2018 Hao Zhang 
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#define PWM_IRQ_ENABLE_REG   0x
> > +#define PCIE(ch) BIT(ch)
> > +
> > +#define PWM_IRQ_STATUS_REG   0x0004
> > +#define PIS(ch)  BIT(ch)
> > +
> > +#define CAPTURE_IRQ_ENABLE_REG   0x0010
> > +#define CRIE(ch) BIT((ch) * 2)
> > +#define CFIE(ch) BIT((ch) * 2 + 1)
> > +
> > +#define CAPTURE_IRQ_STATUS_REG   0x0014
> > +#define CRIS(ch) BIT((ch) * 2)
> > +#define CFIS(ch) BIT((ch) * 2 + 1)
> > +
> > +#define CLK_CFG_REG(ch)  (0x0020 + ((ch) >> 1) * 4)
> > +#define CLK_SRC_SEL  GENMASK(8, 7)
> > +#define CLK_SRC_BYPASS_SEC   BIT(6)
> > +#define CLK_SRC_BYPASS_FIR   BIT(5)
> > +#define CLK_GATING   BIT(4)
> > +#define CLK_DIV_MGENMASK(3, 0)
> > +
> > +#define PWM_DZ_CTR_REG(ch)   (0x0030 + ((ch) >> 1) * 4)
> > +#define PWM_DZ_INTV  GENMASK(15, 8)
> > +#define PWM_DZ_ENBIT(0)
> > +
> > +#define PWM_ENABLE_REG   0x0040
> > +#define PWM_EN(ch)   BIT(ch)
> > +
> > +#define CAPTURE_ENABLE_REG   0x0044
> > +#define CAP_EN(ch)   BIT(ch)
> > +
> > +#define PWM_CTR_REG(ch)  (0x0060 + (ch) * 0x20)
> > +#define PWM_PERIOD_RDY   BIT(11)
> > +#def

[linux-sunxi] Fwd: [PATCH v3 1/6] Documentation: ARM: sunxi: pwm: add Allwinner sun8i.

2019-03-11 Thread Hao Zhang 
-- Forwarded message -
From: Hao Zhang 
Date: 2019年3月12日周二 下午12:59
Subject: Re: [PATCH v3 1/6] Documentation: ARM: sunxi: pwm: add Allwinner sun8i.
To: Thierry Reding 


Thierry Reding  于2018年12月21日周五 上午1:50写道：
>
> On Mon, Nov 26, 2018 at 12:18:59AM +0800, Hao Zhang wrote:
> > This patch adds Allwinner sun8i pwm binding document.
> >
> > Signed-off-by: Hao Zhang 
> > ---
> >  .../devicetree/bindings/pwm/pwm-sun8i.txt  | 24 
> > ++
> >  1 file changed, 24 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sun8i.txt
> >
> > diff --git a/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt 
> > b/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt
> > new file mode 100644
> > index 000..7531d85
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt
> > @@ -0,0 +1,24 @@
> > +Allwinner sun8i R40/V40/T3 SoC PWM controller
> > +
> > +Required properties:
> > +  - compatible: Should be one of:
> > +- "allwinner,sun8i-r40-pwm"
> > +  - reg: Physical base address and length of the controller's registers
> > +  - interrupts: Should contain interrupt.
> > +  - clocks: From common clock binding, handle to the parent clock.
> > +  - clock-names: Must contain the clock names described just above.
> > +  - pwm-channels: PWM channels of the controller.
>
> Why do you need this? In the cover letter you say:
>
> "The sun8i R40/T3/V40 PWM has 8 PWM channals ..."
>
> Why does this need to be specified in the DT?

T3 PWM has 8 channals, i think it is necessary to tell user how to
specify it Instead of
hardcode the channal myself :)

Thanks for review :)

>
> Thierry
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[linux-sunxi] [PATCH v3 6/6] ARM: PWM: add allwinner sun8i R40/T3/V40 PWM support.

2018-11-25 Thread Hao Zhang 
The sun8i R40/T3/V40 PWM has 8 PWM channals and divides to 4 PWM pairs,
each PWM pair built-in 1 clock module, 2 timer logic module and 1
programmable dead-time generator, it also support waveform capture.
It has 2 clock sources OSC24M and APB1, it is different with the
sun4i-pwm driver, Therefore add a new driver for it.

Signed-off-by: Hao Zhang 
---
 drivers/pwm/Kconfig |  12 +-
 drivers/pwm/Makefile|   1 +
 drivers/pwm/pwm-sun8i.c | 418 
 3 files changed, 430 insertions(+), 1 deletion(-)
 create mode 100644 drivers/pwm/pwm-sun8i.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 504d252..6105ac8 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -426,7 +426,7 @@ config PWM_STMPE
  expanders.
 
 config PWM_SUN4I
-   tristate "Allwinner PWM support"
+   tristate "Allwinner SUN4I PWM support"
depends on ARCH_SUNXI || COMPILE_TEST
depends on HAS_IOMEM && COMMON_CLK
help
@@ -435,6 +435,16 @@ config PWM_SUN4I
  To compile this driver as a module, choose M here: the module
  will be called pwm-sun4i.
 
+config PWM_SUN8I
+   tristate "Allwinner SUN8I (R40/V40/T3) PWM support"
+   depends on ARCH_SUNXI || COMPILE_TEST
+   depends on HAS_IOMEM && COMMON_CLK
+   help
+ Generic PWM framework driver for Allwinner R40/V40/T3 SoCs.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-sun8i.
+
 config PWM_TEGRA
tristate "NVIDIA Tegra PWM support"
depends on ARCH_TEGRA
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 9c676a0..32c8d2d 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_PWM_STM32)   += pwm-stm32.o
 obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o
 obj-$(CONFIG_PWM_STMPE)+= pwm-stmpe.o
 obj-$(CONFIG_PWM_SUN4I)+= pwm-sun4i.o
+obj-$(CONFIG_PWM_SUN8I)+= pwm-sun8i.o
 obj-$(CONFIG_PWM_TEGRA)+= pwm-tegra.o
 obj-$(CONFIG_PWM_TIECAP)   += pwm-tiecap.o
 obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o
diff --git a/drivers/pwm/pwm-sun8i.c b/drivers/pwm/pwm-sun8i.c
new file mode 100644
index 000..d8597e4
--- /dev/null
+++ b/drivers/pwm/pwm-sun8i.c
@@ -0,0 +1,418 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hao Zhang 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PWM_IRQ_ENABLE_REG 0x
+#define PCIE(ch)   BIT(ch)
+
+#define PWM_IRQ_STATUS_REG 0x0004
+#define PIS(ch)BIT(ch)
+
+#define CAPTURE_IRQ_ENABLE_REG 0x0010
+#define CRIE(ch)   BIT((ch) * 2)
+#define CFIE(ch)   BIT((ch) * 2 + 1)
+
+#define CAPTURE_IRQ_STATUS_REG 0x0014
+#define CRIS(ch)   BIT((ch) * 2)
+#define CFIS(ch)   BIT((ch) * 2 + 1)
+
+#define CLK_CFG_REG(ch)(0x0020 + ((ch) >> 1) * 4)
+#define CLK_SRC_SELGENMASK(8, 7)
+#define CLK_SRC_BYPASS_SEC BIT(6)
+#define CLK_SRC_BYPASS_FIR BIT(5)
+#define CLK_GATING BIT(4)
+#define CLK_DIV_M  GENMASK(3, 0)
+
+#define PWM_DZ_CTR_REG(ch) (0x0030 + ((ch) >> 1) * 4)
+#define PWM_DZ_INTVGENMASK(15, 8)
+#define PWM_DZ_EN  BIT(0)
+
+#define PWM_ENABLE_REG 0x0040
+#define PWM_EN(ch) BIT(ch)
+
+#define CAPTURE_ENABLE_REG 0x0044
+#define CAP_EN(ch) BIT(ch)
+
+#define PWM_CTR_REG(ch)(0x0060 + (ch) * 0x20)
+#define PWM_PERIOD_RDY BIT(11)
+#define PWM_PUL_START  BIT(10)
+#define PWM_MODE   BIT(9)
+#define PWM_ACT_STABIT(8)
+#define PWM_PRESCAL_K  GENMASK(7, 0)
+
+#define PWM_PERIOD_REG(ch) (0x0064 + (ch) * 0x20)
+#define PWM_ENTIRE_CYCLE   GENMASK(31, 16)
+#define PWM_ACT_CYCLE  GENMASK(15, 0)
+
+#define PWM_CNT_REG(ch)(0x0068 + (ch) * 0x20)
+#define PWM_CNT_VALGENMASK(15, 0)
+
+#define CAPTURE_CTR_REG(ch)(0x006c + (ch) * 0x20)
+#define CAPTURE_CRLF   BIT(2)
+#define CAPTURE_CFLF   BIT(1)
+#define CAPINV BIT(0)
+
+#define CAPTURE_RISE_REG(ch)   (0x0070 + (ch) * 0x20)
+#define CAPTURE_CRLR   GENMASK(15, 0)
+
+#define CAPTURE_FALL_REG(ch)   (0x0074 + (ch) * 0x20)
+#define CAPTURE_CFLR   GENMASK(15, 0)
+
+struct sun8i_pwm_chip {
+   struct pwm_chip chip;
+   struct clk *clk;
+   void __iomem *base;
+   const struct sun8i_pwm_data *data;
+   struct regmap *regmap;
+};
+
+static struct sun8i_pwm_chip *to_sun8i_pwm_chip(struct pwm_chip *chip)
+{
+   return container_of(chip, struct sun8i_pwm_chip, chip);
+}
+
+static u32 sun8i_pwm_read(struct sun8i_pwm_chip *sun8i

[linux-sunxi] [PATCH v3 5/6] DEV: CLK: sunxi ccu: export clk_apb1 for sun8i-r40 soc pwm.

2018-11-25 Thread Hao Zhang 
The clock source for sun8i R40 is from apb1, so export it for
dt parses.

Signed-off-by: Hao Zhang 
---
 drivers/clk/sunxi-ng/ccu-sun8i-r40.h  | 4 +++-
 include/dt-bindings/clock/sun8i-r40-ccu.h | 2 ++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.h 
b/drivers/clk/sunxi-ng/ccu-sun8i-r40.h
index db2a124..181ab26 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.h
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.h
@@ -51,7 +51,9 @@
 
 #define CLK_AXI25
 #define CLK_AHB1   26
-#define CLK_APB1   27
+
+/* The APB1 clock is exported */
+
 #define CLK_APB2   28
 
 /* All the bus gates are exported */
diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h 
b/include/dt-bindings/clock/sun8i-r40-ccu.h
index f9e15a2..a2b8f06 100644
--- a/include/dt-bindings/clock/sun8i-r40-ccu.h
+++ b/include/dt-bindings/clock/sun8i-r40-ccu.h
@@ -49,6 +49,8 @@
 
 #define CLK_CPU24
 
+#define CLK_APB127
+
 #define CLK_BUS_MIPI_DSI   29
 #define CLK_BUS_CE 30
 #define CLK_BUS_DMA31
-- 
2.7.4

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[linux-sunxi] [PATCH v3 4/6] DEV: CLK: add function to check the using clock name of driver.

2018-11-25 Thread Hao Zhang 
In some situation we want to check clock whether is we want
and after the driver been probed use to change different clock source.

Signed-off-by: Hao Zhang 
---
 drivers/clk/clk.c| 6 ++
 include/linux/clk-provider.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index d31055a..3d2c2cd 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -3466,6 +3466,12 @@ static int devm_clk_hw_match(struct device *dev, void 
*res, void *data)
return hw == data;
 }
 
+bool devm_clk_name_match(struct clk *clk, const char *string)
+{
+   return match_string(&clk->con_id, 1, string) == 0;
+}
+EXPORT_SYMBOL_GPL(devm_clk_name_match);
+
 /**
  * devm_clk_unregister - resource managed clk_unregister()
  * @clk: clock to unregister
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 08b1aa7..5cd2eed 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -764,6 +764,7 @@ struct clk *devm_clk_register(struct device *dev, struct 
clk_hw *hw);
 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
 
+bool devm_clk_name_match(struct clk *clk, const char *string);
 void clk_unregister(struct clk *clk);
 void devm_clk_unregister(struct device *dev, struct clk *clk);
 
-- 
2.7.4

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[linux-sunxi] [PATCH v3 3/6] ARM: dts: add PWM for Bananapi M2 Ultrar board.

2018-11-25 Thread Hao Zhang 
This patch adds pwm status for Bananapi M2 Ultrar board and the status
also used as LCD-PWM status.

Signed-off-by: Hao Zhang 
---
 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts 
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 438b7b4..d785c9b 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -272,6 +272,12 @@
status = "okay";
 };
 
+&pwm {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pwm_ch0_pin>;
+   status = "okay";
+};
+
 &uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
-- 
2.7.4

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[linux-sunxi] [PATCH v3 2/6] ARM: dtsi: add pwm node for sun8i R40.

2018-11-25 Thread Hao Zhang 
This patch adds pwm node for sun8i R40.

Signed-off-by: Hao Zhang 
---
 arch/arm/boot/dts/sun8i-r40.dtsi | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 6f4c9ca..cc05b2c 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -317,6 +317,7 @@
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
+
};
 
pio: pinctrl@1c20800 {
@@ -373,6 +374,11 @@
bias-pull-up;
};
 
+   pwm_ch0_pin: pwm-ch0-pin {
+   pins = "PB2";
+   function = "pwm";
+   };
+
uart0_pb_pins: uart0-pb-pins {
pins = "PB22", "PB23";
function = "uart0";
@@ -384,6 +390,17 @@
reg = <0x01c20c90 0x10>;
};
 
+   pwm: pwm@1c23400 {
+   compatible = "allwinner,sun8i-r40-pwm";
+   reg = <0x01c23400 0x400>;
+   interrupts = ;
+   clocks = <&osc24M>, <&ccu CLK_APB1>;
+   clock-names = "mux-0", "mux-1";
+   pwm-channels = <8>;
+   #pwm-cells = <3>;
+   status = "disabled";
+   };
+
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
-- 
2.7.4

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[linux-sunxi] [PATCH v3 1/6] Documentation: ARM: sunxi: pwm: add Allwinner sun8i.

2018-11-25 Thread Hao Zhang 
This patch adds Allwinner sun8i pwm binding document.

Signed-off-by: Hao Zhang 
---
 .../devicetree/bindings/pwm/pwm-sun8i.txt  | 24 ++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sun8i.txt

diff --git a/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt 
b/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt
new file mode 100644
index 000..7531d85
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt
@@ -0,0 +1,24 @@
+Allwinner sun8i R40/V40/T3 SoC PWM controller
+
+Required properties:
+  - compatible: Should be one of:
+- "allwinner,sun8i-r40-pwm"
+  - reg: Physical base address and length of the controller's registers
+  - interrupts: Should contain interrupt.
+  - clocks: From common clock binding, handle to the parent clock.
+  - clock-names: Must contain the clock names described just above.
+  - pwm-channels: PWM channels of the controller.
+  - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
+the cells format.
+
+Example:
+
+pwm: pwm@1c23400 {
+compatible = "allwinner,sun8i-r40-pwm";
+reg = <0x01c23400 0x400>;
+interrupts = ;
+clocks = <&osc24M>, <&ccu CLK_APB1>;
+clock-names = "mux-0", "mux-1";
+pwm-channels = <8>;
+#pwm-cells = <3>;
+};
-- 
2.7.4

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[linux-sunxi] [PATCH v3 0/6] PWM support for allwinner sun8i R40/T3/V40 SOCs.

2018-11-25 Thread Hao Zhang 
PWM support for allwinner sun8i R40/T3/V40 SOCs.

The sun8i R40/T3/V40 PWM has 8 PWM channals and divides to 4 PWM pairs,
each PWM pair built-in 1 clock module, 2 timer logic module and 1
programmable dead-time generator, it also support waveform capture.
It has 2 clock sources OSC24M and APB1, it is different with the
sun4i-pwm driver, Therefore add a new driver for it.

Some test method:
cd /sys/class/pwm/pwmchip0
echo 0 > export
cd pwm0
echo 1000 > period
echo 500 > duty_cycle
echo 1 > enable
then check the PB2 pin with oscilloscope.

v3 Changes:
1. fix coding format.
2. use 2/ilog2 instead of divide table
3. remove spinlock.
4. remove sun8i_pwm_data structure and use DT to parse pwm-channals  
5. remove inline because complier knows it better.
6. don't hardcode clock source and parse two clock source from dt "mux-0"
   and "mux-1"
7. remove bypass method.
8. add a method to change clock source when mux-0 is not support the
   input period it can change to mux-1.
9. add cycle range check.
10. add some variable to make it more readability.
11. add clk_disable_unprepare when some false accur.

v2 Changes:
1. change sun8i-r40 symbol to sun8i.
2. change pwm0_pin, pwm0-pin to pwm_ch0_pin, pwm-ch0-pin.
3. remove clk_disable_unprepare(), check !match and IS_ERR(pwm->regmap).

Hao Zhang (6):
  Documentation: ARM: sunxi: pwm: add Allwinner sun8i.
  ARM: dtsi: add pwm node for sun8i R40.
  ARM: dts: add PWM for Bananapi M2 Ultrar board.
  DEV: CLK: add function to check the using clock name of driver.
  DEV: CLK: sunxi ccu: export clk_apb1 for sun8i-r40 soc pwm.
  ARM: PWM: add allwinner sun8i R40/T3/V40 PWM support.

 .../devicetree/bindings/pwm/pwm-sun8i.txt  |  24 ++
 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts  |   6 +
 arch/arm/boot/dts/sun8i-r40.dtsi   |  17 +
 drivers/clk/clk.c  |   6 +
 drivers/clk/sunxi-ng/ccu-sun8i-r40.h   |   4 +-
 drivers/pwm/Kconfig|  12 +-
 drivers/pwm/Makefile   |   1 +
 drivers/pwm/pwm-sun8i.c| 418 +
 include/dt-bindings/clock/sun8i-r40-ccu.h  |   2 +
 include/linux/clk-provider.h   |   1 +
 10 files changed, 489 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sun8i.txt
 create mode 100644 drivers/pwm/pwm-sun8i.c

-- 
2.7.4

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[linux-sunxi] [PATCH v1 2/2] Documentation: ARM: sunxi: Add Allwinner SoC T3.

2018-11-21 Thread Hao Zhang 
Add Allwinner SoC T3 document and fix format.

Signed-off-by: Hao Zhang 
---
 Documentation/devicetree/bindings/arm/sunxi.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt 
b/Documentation/devicetree/bindings/arm/sunxi.txt
index e4beec3..94b9c12 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,7 +14,8 @@ using one of the following compatible strings:
   allwinner,sun8i-a83t
   allwinner,sun8i-h2-plus
   allwinner,sun8i-h3
-  allwinner-sun8i-r40
+  allwinner,sun8i-r40
+  allwinner,sun8i-t3
   allwinner,sun8i-v3s
   allwinner,sun9i-a80
   allwinner,sun50i-a64
-- 
2.7.4

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[linux-sunxi] [PATCH v1 1/2] ARM: dts: sun8i: Add board dts file for t3-cqa3t-bv3.

2018-11-21 Thread Hao Zhang 
The T3/R40/V40 using the same sdk and config file in allwinner
sdk, it seem they are the same SOC just with different name, so
compatible with R40.

The t3-cqa3t-bv3 based on Allwinner T3 SoC, it has various connectors,
leds, buttons, and sell on:
https://item.taobao.com/item.htm?spm=2013.1.w4023-4203040713.25.62704cce7UCgLS&id=557154455330

It features:
 - X-Powers AXP221s PMIC connected to i2c0
 - 1/2 GB DDR3 DRAM
 - 8 GB eMMC
 - 2x USB 2.0 hosts
 - 1x USB 2.0 OTG
 - 2 LVDS connectors
 - 24 bit RGB LCD connector
 - HDMI output
 - DVP camera interface (support 500w cmos camera)
 - GPIO connectors
 - 5 TTL uarts and 2 RS232 uarts
 - 1 RS485 connector
 - support i2c capacitive tp and usb infrared tp
 - boot control, reset and user buttons
 - 3.5mm headphone and 3.5mm mic jack
 - 100M RJ45
 - micro SD card slot
 - DC power jack
 - RCT power slot
 - 1 CVBS TVIN
 - 1 CVBS TVOUT
 - 2 customer leds
 - 1 buzzer
 - 1 minipcie
 - I2C output
 - SPI output
 - PCM output
 - wifi and bt connector reserved.

Board info can find here:
https://github.com/Axl-zhang/Allwinner-V40-T3-R40-manual

Signed-off-by: Hao Zhang 
---
 arch/arm/boot/dts/Makefile   |   1 +
 arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts | 226 +++
 2 files changed, 227 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 2a1a8c6..7ca266a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1053,6 +1053,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-r16-nintendo-super-nes-classic.dtb \
sun8i-r16-parrot.dtb \
sun8i-r40-bananapi-m2-ultra.dtb \
+   sun8i-t3-cqa3t-bv3.dtb \
sun8i-v3s-licheepi-zero.dtb \
sun8i-v3s-licheepi-zero-dock.dtb \
sun8i-v40-bananapi-m2-berry.dtb
diff --git a/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts 
b/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts
new file mode 100644
index 000..6931aaa
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai 
+ * Copyright (C) 2017 Icenowy Zheng 
+ * Copyright (C) 2018 Hao Zhang 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-r40.dtsi"
+
+#include 
+
+/ {
+   model = "t3-cqa3t-bv3";
+   compatible = "qihua,t3-cqa3t-bv3", "allwinner,sun8i-t3",
+"allwinner,sun8i-r40";
+
+   aliases {
+   serial0 = &uart0;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   connector {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con_in: endpoint {
+   remote-endpoint = <&hdmi_out_con>;
+   };
+   };
+   };
+
+   reg_vcc5v0: vcc5v0 {
+

[linux-sunxi] [PATCH v1 0/2] Initial Allwinner T3 support.

2018-11-21 Thread Hao Zhang 
Initial Allwinner T3 support.

Allwinner T3 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU, and a
Mali400 MP2 GPU from ARM. It is a not-pin-compatible quad core sucessor
of the A20). It's also known as the Allwinner R40.

Hao Zhang (2):
  ARM: dts: sun8i: Add board dts file for t3-cqa3t-bv3.
  Documentation: ARM: sunxi: Add Allwinner SoC T3.

 Documentation/devicetree/bindings/arm/sunxi.txt |   3 +-
 arch/arm/boot/dts/Makefile  |   1 +
 arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts| 226 
 3 files changed, 229 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts

-- 
2.7.4

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[linux-sunxi] Only registered users can talk in irc？

2018-11-11 Thread Hao Zhang 
I can‘t talk to #linux-sunxi irc, even though i have registered to 
http://linux-sunxi.org website.
Should i registered to irc or has other ways to register？:\

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[linux-sunxi] Re: [PATCH v2 4/4] ARM: PWM: add allwinner sun8i pwm support.

2018-05-17 Thread Hao Zhang 
2018-05-15 19:17 GMT+08:00 Maxime Ripard :
> Hi,
>
> On Mon, May 14, 2018 at 10:45:44PM +0800, Hao Zhang wrote:
>> 2018-02-26 17:00 GMT+08:00 Maxime Ripard :
>> > Thanks for respinning this serie. It looks mostly good, but you still
>> > have a quite significant number of checkpatch (--strict) warnings that
>> > you should address.
>>
>> Thanks for reviews :) ,i'm sorry for that, it will be fixed next
>> time.  and, besides, in what situation were the checkpatch warning
>> can be ignore？
>
> The only one that can be reasonably be ignored is the long line
> warning, and only if complying to the limit would make it less easy to
> understand.
>
>> >
>> > On Sun, Feb 25, 2018 at 09:53:08PM +0800, hao_zhang wrote:
>> >> +#define CAPTURE_IRQ_ENABLE_REG   0x0010
>> >> +#define CFIE(ch) BIT(ch << 1 + 1)
>> >> +#define CRIE(ch) BIT(ch << 1)
>> >
>> > You should also put your argument between parentheses here (and in all
>> > your other macros).
>>
>> Do you mean like this ?
>> #define CFIE(ch) BIT((ch) << 1 + 1)
>> #define CRIE(ch) BIT((ch) << 1)
>
> Yep, exactly. Otherwise, if you do something like CRIE(1 + 1), the
> result will be BIT(1 + 1 << 1), which will expand to 3, instead of 4.
>
> Also, CFIE looks a bit weird here, is it the offset that is
> incremented, or the value? You should probably have parentheses to
> make it explicit.

The vallue,
BIT(((ch) << 1) + 1) It seem not very nice...

uhmm...
In CAPTURE_IRQ_ENABLE_REG odd number is CFIE, even number is CRIE
each channel has one CFIE and CRIE.

we can also describe like this:
#define CFIE(ch) BIT((ch) * 2 + 1)
#define CRIE(ch) BIT((ch) * 2)

>
>> >
>> >> +static const u16 div_m_table[] = {
>> >> + 1,
>> >> + 2,
>> >> + 4,
>> >> + 8,
>> >> + 16,
>> >> + 32,
>> >> + 64,
>> >> + 128,
>> >> + 256
>> >> +};
>> >
>> > If this is just a power of two, you can use either the power of two /
>> > ilog2 to switch back and forth, instead of using that table.
>>
>> I think using table is more explicit and extended...
>
> If you didn't have a simple mapping between the register values and
> the divider value, then yeah, sure. But it's not the case here.
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Bootlin (formerly Free Electrons)
> Embedded Linux and Kernel engineering
> https://bootlin.com

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Re: [linux-sunxi] [PATCH v2 2/4] ARM: dtsi: add pwm node for sun8i.

2018-05-14 Thread Hao Zhang 
2018-02-28 9:53 GMT+08:00 André Przywara :
> Hi,
>
> The subject line should mention the R40, there are far too many sun8i SoCs.

Okey.

>
> On 25/02/18 13:51, hao_zhang wrote:
>> This patch adds pwm node for sun8i.
>>
>> Signed-off-by: hao_zhang 
>> ---
>>  arch/arm/boot/dts/sun8i-r40.dtsi | 13 +
>>  1 file changed, 13 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi 
>> b/arch/arm/boot/dts/sun8i-r40.dtsi
>> index 173dcc1..99a0261 100644
>> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
>> @@ -295,6 +295,11 @@
>>   bias-pull-up;
>>   };
>>
>> + pwm_ch0_pin: pwm-ch0-pin {
>> + pins = "PB2";
>> + function = "pwm";
>> + };
>> +
>>   uart0_pb_pins: uart0-pb-pins {
>>   pins = "PB22", "PB23";
>>   function = "uart0";
>> @@ -306,6 +311,14 @@
>>   reg = <0x01c20c90 0x10>;
>>   };
>>
>> + pwm: pwm@1c23400 {
>> +  compatible = "allwinner,sun8i-r40-pwm";
>> +  reg = <0x01c23400 0x154>;
>
> Following my comments on the binding document:
> interrupts = ;
>
>> +  clocks = <&osc24M>;
>
> And possibly multiple clocks here (though I fail to find the APB1 clock
> being exposed by our CCU).

It seem CCU dosen't support APB1 clock for R40 PWM...

>
> Cheers,
> Andre.
>
>> +  #pwm-cells = <3>;
>> +  status = "disabled";
>> + };
>> +
>>   uart0: serial@1c28000 {
>>   compatible = "snps,dw-apb-uart";
>>   reg = <0x01c28000 0x400>;
>>
>

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Re: [linux-sunxi] [PATCH v2 4/4] ARM: PWM: add allwinner sun8i pwm support.

2018-05-14 Thread Hao Zhang 
 if (ret) {
>> + spin_unlock(&sun8i_pwm->ctrl_lock);
>> + dev_err(chip->dev, "Failed to config PWM\n");
>> + return ret;
>> + }
>> + }
>> +
>> + if (state->polarity != cstate.polarity)
>> + sun8i_pwm_set_polarity(sun8i_pwm, pwm->hwpwm, state->polarity);
>> +
>> + if (state->enabled) {
>> + sun8i_pwm_set_bit(sun8i_pwm,
>> + CLK_CFG_REG(pwm->hwpwm), CLK_GATING);
>> +
>> + sun8i_pwm_set_bit(sun8i_pwm,
>> + PWM_ENABLE_REG, PWM_EN(pwm->hwpwm));
>> + } else {
>> + sun8i_pwm_clear_bit(sun8i_pwm,
>> + CLK_CFG_REG(pwm->hwpwm), CLK_GATING);
>> +
>> + sun8i_pwm_clear_bit(sun8i_pwm,
>> + PWM_ENABLE_REG, PWM_EN(pwm->hwpwm));
>> + }
>> +
>> + spin_unlock(&sun8i_pwm->ctrl_lock);
>> +
>> + return 0;
>> +}
>> +
>> +static void sun8i_pwm_get_state(struct pwm_chip *chip, struct pwm_device 
>> *pwm,
>> + struct pwm_state *state)
>> +{
>> + struct sun8i_pwm_chip *sun8i_pwm = to_sun8i_pwm_chip(chip);
>> + u64 clk_rate, tmp;
>> + u32 val;
>> + u16 clk_div, act_cycle;
>> + u8 prescal, id;
>
> You might want to add a channel variable to increase readability:
> int channel = pwm->hwpwm;
>

Okey

>> +
>> + clk_rate = clk_get_rate(sun8i_pwm->clk);
>> +
>> + val = sun8i_pwm_read(sun8i_pwm, PWM_CTR_REG(pwm->hwpwm));
>> + if (PWM_ACT_STA & val)
>> + state->polarity = PWM_POLARITY_NORMAL;
>> + else
>> + state->polarity = PWM_POLARITY_INVERSED;
>> +
>> + prescal = PWM_PRESCAL_K & val;
>> +
>> + val = sun8i_pwm_read(sun8i_pwm, PWM_ENABLE_REG);
>> + if (PWM_EN(pwm->hwpwm) & val)
>> + state->enabled = true;
>> + else
>> + state->enabled = false;
>> +
>> + val = sun8i_pwm_read(sun8i_pwm, PWM_PERIOD_REG(pwm->hwpwm));
>> + act_cycle = PWM_ACT_CYCLE & val;
>> + clk_div = val >> 16;
>> +
>> + val = sun8i_pwm_read(sun8i_pwm, CLK_CFG_REG(pwm->hwpwm));
>> + id = CLK_DIV_M & val;
>> +
>> + tmp = act_cycle * prescal * div_m_table[id] * NSEC_PER_SEC;
>> + state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
>> + tmp = clk_div * prescal * div_m_table[id] * NSEC_PER_SEC;
>> + state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
>> +}
>> +
>> +static const struct regmap_config sun8i_pwm_regmap_config = {
>> + .reg_bits = 32,
>> + .reg_stride = 4,
>> + .val_bits = 32,
>> + .max_register = CAPTURE_FALL_REG(7),
>> +};
>> +
>> +static const struct pwm_ops sun8i_pwm_ops = {
>> + .apply = sun8i_pwm_apply,
>> + .get_state = sun8i_pwm_get_state,
>> + .owner = THIS_MODULE,
>> +};
>> +
>> +static const struct sun8i_pwm_data sun8i_pwm_data_r40 = {
>> + .has_prescaler_bypass = false,
>
> This is not needed (see my comment above).

yep.

>
>> + .has_rdy = true,
>
> And this is not used. Copied from sun4i? Where it interestingly isn't
> used either ;-)
>
>> + .npwm = 8,
>
> I would really love to see this being moved to the DT (see my other mail
> to Thierry about the generic property).
>
> This would mean you don't need a SoC specific structure at all.

okey.

>
>> +};
>> +
>> +static const struct of_device_id sun8i_pwm_dt_ids[] = {
>> + {
>> + .compatible = "allwinner,sun8i-r40-pwm",
>> + .data = &sun8i_pwm_data_r40,
>> + },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, sun8i_pwm_dt_ids);
>> +
>> +static int sun8i_pwm_probe(struct platform_device *pdev)
>> +{
>> + struct sun8i_pwm_chip *pwm;
>> + struct resource *res;
>> + int ret;
>> + const struct of_device_id *match;
>> +
>> + match = of_match_device(sun8i_pwm_dt_ids, &pdev->dev);
>> + if (!match) {
>> + dev_err(&pdev->dev, "Error: No device match found\n");
>> + return -ENODEV;
>> + }
>> +
>> + pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
>> + if (!pwm)
>> + return -ENOMEM;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + pwm->base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(pwm->base))
>> + return PTR_ERR(pwm->base);
>> +
>> + pwm->regmap = devm_regmap_init_mmio(&pdev->dev, pwm->base,
>> + &sun8i_pwm_regmap_config);
>> + if (IS_ERR(pwm->regmap)) {
>> + dev_err(&pdev->dev, "Failed to create regmap\n");
>> + return PTR_ERR(pwm->regmap);
>> + }
>> +
>> + pwm->clk = devm_clk_get(&pdev->dev, NULL);
>> + if (IS_ERR(pwm->clk))
>> + return PTR_ERR(pwm->clk);
>
> This would need to be extended to get multiple clocks.

okey.

>
>> +
>> + pwm->data = match->data;
>> + pwm->chip.dev = &pdev->dev;
>> + pwm->chip.ops = &sun8i_pwm_ops;
>> + pwm->chip.base = -1;
>> + pwm->chip.npwm = pwm->data->npwm;
>
> It should be fairly easy to initialise this from some DT property.
>
> That's it for the my first review round. Haven't checked the actual
> algorithm and bit assignments yet.
> Did you manage to test this?

Sure :-)
All has been tested on my T3 board (compatible V40, R40)
PWM signal is work well observe from oscilloscope.

>
> Cheers,
> Andre.
>
>> + pwm->chip.of_xlate = of_pwm_xlate_with_flags;
>> + pwm->chip.of_pwm_n_cells = 3;
>> +
>> + spin_lock_init(&pwm->ctrl_lock);
>> +
>> + ret = pwmchip_add(&pwm->chip);
>> + if (ret < 0) {
>> + dev_err(&pdev->dev, "Failed to add PWM chip: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + platform_set_drvdata(pdev, pwm);
>> +
>> + return 0;
>> +}
>> +
>> +static int sun8i_pwm_remove(struct platform_device *pdev)
>> +{
>> + struct sun8i_pwm_chip *pwm = platform_get_drvdata(pdev);
>> +
>> + return pwmchip_remove(&pwm->chip);
>> +}
>> +
>> +static struct platform_driver sun8i_pwm_driver = {
>> + .driver = {
>> + .name = "sun8i-pwm",
>> + .of_match_table = sun8i_pwm_dt_ids,
>> + },
>> + .probe = sun8i_pwm_probe,
>> + .remove = sun8i_pwm_remove,
>> +};
>> +module_platform_driver(sun8i_pwm_driver);
>> +
>> +MODULE_ALIAS("platform: sun8i-pwm");
>> +MODULE_AUTHOR("Hao Zhang ");
>> +MODULE_DESCRIPTION("Allwinner sun8i PWM driver");
>> +MODULE_LICENSE("GPL v2");
>>
>

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[linux-sunxi] Re: [PATCH v2 4/4] ARM: PWM: add allwinner sun8i pwm support.

2018-05-14 Thread Hao Zhang 
2018-02-26 17:00 GMT+08:00 Maxime Ripard :
> Hi,
>
> Thanks for respinning this serie. It looks mostly good, but you still
> have a quite significant number of checkpatch (--strict) warnings that
> you should address.

Thanks for reviews :) ,i'm sorry for that, it will be fixed next time.
and, besides, in what situation were the checkpatch warning can be ignore？

>
> On Sun, Feb 25, 2018 at 09:53:08PM +0800, hao_zhang wrote:
>> +#define CAPTURE_IRQ_ENABLE_REG   0x0010
>> +#define CFIE(ch) BIT(ch << 1 + 1)
>> +#define CRIE(ch) BIT(ch << 1)
>
> You should also put your argument between parentheses here (and in all
> your other macros).

Do you mean like this ?
#define CFIE(ch) BIT((ch) << 1 + 1)
#define CRIE(ch) BIT((ch) << 1)

>
>> +static const u16 div_m_table[] = {
>> + 1,
>> + 2,
>> + 4,
>> + 8,
>> + 16,
>> + 32,
>> + 64,
>> + 128,
>> + 256
>> +};
>
> If this is just a power of two, you can use either the power of two /
> ilog2 to switch back and forth, instead of using that table.

I think using table is more explicit and extended...

>
>> +static int sun8i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
>> + struct pwm_state *state)
>> +{
>> + int ret;
>> + struct sun8i_pwm_chip *sun8i_pwm = to_sun8i_pwm_chip(chip);
>> + struct pwm_state cstate;
>> +
>> + pwm_get_state(pwm, &cstate);
>> + if (!cstate.enabled) {
>> + ret = clk_prepare_enable(sun8i_pwm->clk);
>> + if (ret) {
>> + dev_err(chip->dev, "Failed to enable PWM clock\n");
>> + return ret;
>> + }
>> + }
>> +
>> + spin_lock(&sun8i_pwm->ctrl_lock);
>
> What do you need that spinlock for? Can you use a mutex instead?
It should be remove.
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Bootlin (formerly Free Electrons)
> Embedded Linux and Kernel engineering
> https://bootlin.com

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Re: [linux-sunxi] Re: Some problem about develop the audio codec driver for A64

2016-09-10 Thread Hao Zhang 
hi,
thanks for the reply, and i'll try to test it and feedback the status.

2016-09-10 0:12 GMT+08:00 jonsm...@gmail.com :
> On Fri, Sep 9, 2016 at 11:36 AM, Chen-Yu Tsai  wrote:
>> Hi,
>>
>> On Fri, Sep 9, 2016 at 11:28 PM, Hao Zhang  wrote:
>>> hello,
>>> I want to pick up some tasks list in this web page
>>> (http://linux-sunxi.org/Linux_mainlining_effort)which is base on A64
>>> and i has some problem on it. if i develop the audio codec driver for
>>> A64, which respository should i use ? I test the function on my pine64
>>> board(about pine64 : https://linux-sunxi.org/Pine64), just review and
>>> looking for some support in the respository which is belong to linus
>>> or linux-sunxi-next, it seem it doesn't support the board ,such as
>>> device tree and so on right ? :) So how to deal with it befor the
>>> task?
>>
>> Pine64 or A64 in general doesn't have a lot of support at the moment.
>> Hopefully we'll start to get the basics in for the next release.
>>
>> Until then you'll have to pick whatever patches you can find to have
>> something working. As for the codec, it looks similar to what we have
>> on the A33, which is an I2S/PCM interface coupled with a codec inside
>> the SoC. It might even be exactly the same. Someone previously expressed
>> interest for the A33 codec. I suggest you pop in to our IRC channel
>> and ask around.
>
> There is an Allwinner written A64 I2S driver in their kernel. It is
> just named daudio instead of I2S. It is device tree enabled.
>
> Follow the lichee part of the instructions here,
> https://gitlab.com/pine64-android/manifest/wikis/home
>
> Source is here, the daudio stuff.
> https://gitlab.com/pine64-android/linux-3.10/tree/master/sound/soc/sunxi
>
>
>>
>> Regards
>> ChenYu
>>
>>>
>>> regards :)
>>> Zhang Hao
>>
>> --
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>
>
>
> --
> Jon Smirl
> jonsm...@gmail.com

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[linux-sunxi] Some problem about develop the audio codec driver for A64

2016-09-09 Thread Hao Zhang 
hello,
I want to pick up some tasks list in this web page
(http://linux-sunxi.org/Linux_mainlining_effort)which is base on A64
and i has some problem on it. if i develop the audio codec driver for
A64, which respository should i use ? I test the function on my pine64
board(about pine64 : https://linux-sunxi.org/Pine64), just review and
looking for some support in the respository which is belong to linus
or linux-sunxi-next, it seem it doesn't support the board ,such as
device tree and so on right ? :) So how to deal with it befor the
task?

regards :)
Zhang Hao

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[linux-sunxi] Re: [PATCH] clk: sunxi: Add CSI (camera's Sensors Interface) module clock driver for sun[457]i

2016-07-10 Thread Hao Zhang 
Hi all
I am developing a media codec driver(using bt656) for cubieboard
one(allwinner a10 processor), i want to use DT to banding csi. after i get
some reference on
Documentation/devicetree/bindings/media/video-interfaces.txt, i have some
question about whether the csi driver for cubieboard one support to parse
the DT node just like in the reference document? if not, whether someone
is developing it or should i necessary to complete it together (What's the
progress of it) ?

Best regards :)
Hao Zhang

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[linux-sunxi] Developing Linux Kernel Driver for media Codec Driver

2016-07-07 Thread Hao Zhang 
hi all

i am developing a linux kernel driver for a 4-CH AHD2.0 RX and 9-CH
Audio Codec which is named nvp6124 .

wedsite : http://www.nextchip.com/ch/products/product.asp?hGubun=AHD.

below are few of its characteristics:

video codec:
it digitizes and decodes ntsc/pal/comet/AHD1.0/AHD2.O video signal into digital
video components which represents 8bit bt656/1120 4:2:2 byte interleave fotmat.

audio codec:
output pcm digital signal converted from analog audio input signals and analog
audio signals converted from pcm digital audio.

control interface:
control and configure through i2c interface.

video interface:
4ch analog video input and output 2ch digital signal, each channal has
8 data ports and a clk clock port
which can connect to the embedded processer.


audio interface(two i2s interface):
audio data convert to PCM data,and outputed via i2s interface .
PCM data can also input via i2s interface, the input audio data is
outputed via internal DAC.


i want to submit the driver, but i have some problem on the below points:

1.must i submit the driver through device tree binding? Does the
kernel tree accept the driver without device tree binding?
just see the video interface ,i know i2c port can binding below the
i2c node, but, how can i bind other data port and clock signal port
with device trees?

2.how to use device tree to bind device and how does the kernel uses
it to match device? can i obtain some document about this?

3.i creat the driver for Cubieboard one(allwinner a10 processer) and
Banana PI BPI-M1(allwinner a20 processer) ,if i submit patch
,which  kernel version shoudle i use ? must i use the lastest kernel
(download in www.kernel.org isn't the sdk of the board)in that boards
?

4.does someone know which lastest kernel version does Cubieboard one
and Banana PI BPI-M1 supports?

5.the maintainer doesn't has the device, how do they know the driver
is work well on my board? just buit without error or warning ?



Best regards :)

Hao Zhang

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[linux-sunxi] Re: Some csi problem in hardware connect

2016-07-05 Thread Hao Zhang 
Sorry ,i was wrong .Maybe the PCLK mean pixel clock, used for MCU camera 
sensor controller to capture each pixel.
and MCLK mean master clock for sensor logical chip. 

在 2016年7月5日星期二 UTC+8下午8:30:54，Hao Zhang写道：
>
>
> Hi all
>
> I have a device with bt656 interface (8 data ports, and a clk port show in 
> the picture), i want to connect it with cubieboard one (allwinner A10 
> processer) or banana pi one(allwinner A20 processer).
> unfortunately, i find out that  A10/A20 uses differential signal CSI0_PCLK 
> and CSI0_MLCK to connect the device but my device only support the normal 
> signal clk.
>  Am I need some other hardware circuit to transform the clk signal to 
> differential signal? or whether  the processer support the normal signal 
> clk that i can connect the device to processer directly?
> If anyone can help me, I'll be most grateful.
>
> <https://lh3.googleusercontent.com/-XxicSjDBK_0/V3ulT41tS6I/BS0/QOFPef1TlfIDvDXd4SC5ekPLK5LjNmidQCLcB/s1600/%25E6%258D%2595%25E8%258E%25B7.PNG>
>  
> <https://lh3.googleusercontent.com/-W4gpNSDVx3M/V3umU1T9mMI/BS8/o9j3MDkoDQ84Vx8L345a6AcGE69am8OAgCLcB/s1600/1.PNG>
>
>   
> <https://lh3.googleusercontent.com/-o7uZxgGNVdE/V3ukazn-bwI/BSs/iVsU-gTXJlofqbqmV2FFYBQ76GGLvuqZACLcB/s1600/6124b.PNG>
>
>
> <https://lh3.googleusercontent.com/-o7uZxgGNVdE/V3ukazn-bwI/BSs/iVsU-gTXJlofqbqmV2FFYBQ76GGLvuqZACLcB/s1600/6124b.PNG>
>
>

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[linux-sunxi] Some csi problem in hardware connect

2016-07-05 Thread Hao Zhang 



Hi all

I have a device with bt656 interface (8 data ports, and a clk port show in 
the picture), i want to connect it with cubieboard one (allwinner A10 
processer) or banana pi one(allwinner A20 processer).
unfortunately, i find out that  A10/A20 uses differential signal CSI0_PCLK 
and CSI0_MLCK to connect the device but my device only support the normal 
signal clk.
 Am I need some other hardware circuit to transform the clk signal to 
differential signal? or whether  the processer support the normal signal 
clk that i can connect the device to processer directly?
If anyone can help me, I'll be most grateful.

 


  


   


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