Re: [linux-sunxi] [PATCH] sunxi: remove magic numbers from clock_get_pll{5,6}

2014-04-18 Thread Ian Campbell 
On Fri, 2014-04-18 at 12:13 +0800, Chen-Yu Tsai wrote:
 You should remove the declaration for clock_get_pll5 from
 
   arch/arm/include/asm/arch-sunxi/clock.h

Oops, yes, indeed.

  +#define CCM_PLL6_CTRL_N_SHIFT  8
  +#define CCM_PLL6_CTRL_N_MASK   (0x1fCCM_PLL6_CTRL_N_SHIFT)
 
 Maybe a space separation between the operands for readability?
 Same for the other places.

It's not my preference but I see it is the prevailing style in this file
so I will adjust to match.

 Looks good otherwise.

Thanks.

Hans has already pulled in the original so I'll fix both of the above in
a follow on patch.

Ian.

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Re: [linux-sunxi] [PATCH] sunxi: remove magic numbers from clock_get_pll{5,6}

2014-04-17 Thread Chen-Yu Tsai 
Hi,

On Tue, Apr 15, 2014 at 3:46 AM, Ian Campbell i...@hellion.org.uk wrote:
 For clock_get_pll5 just remove it since it is unused.

 For clock_get_pll6 introduce the necessary #defines.

 Signed-off-by: Ian Campbell i...@hellion.org.uk
 ---
  arch/arm/cpu/armv7/sunxi/clock.c  | 18 ++
  arch/arm/include/asm/arch-sunxi/clock_sun4i.h |  5 +
  arch/arm/include/asm/arch-sunxi/clock_sun6i.h |  5 +
  3 files changed, 12 insertions(+), 16 deletions(-)

 diff --git a/arch/arm/cpu/armv7/sunxi/clock.c 
 b/arch/arm/cpu/armv7/sunxi/clock.c
 index c07a975..94ba6e0 100644
 --- a/arch/arm/cpu/armv7/sunxi/clock.c
 +++ b/arch/arm/cpu/armv7/sunxi/clock.c
 @@ -24,26 +24,12 @@ int clock_init(void)
 return 0;
  }

 -/* Return PLL5 frequency in Hz
 - * Note: Assumes PLL5 reference is 24MHz clock
 - */
 -unsigned int clock_get_pll5(void)
 -{
 -   struct sunxi_ccm_reg *const ccm =
 -   (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 -   uint32_t rval = readl(ccm-pll5_cfg);
 -   int n = (rval  8)  0x1f;
 -   int k = ((rval  4)  3) + 1;
 -   int p = 1  ((rval  16)  3);
 -   return 2400 * n * k / p;
 -}
 -

You should remove the declaration for clock_get_pll5 from

  arch/arm/include/asm/arch-sunxi/clock.h

as well, to be complete.

  unsigned int clock_get_pll6(void)
  {
 struct sunxi_ccm_reg *const ccm =
 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 uint32_t rval = readl(ccm-pll6_cfg);
 -   int n = (rval  8)  0x1f;
 -   int k = ((rval  4)  3) + 1;
 +   int n = (rval  CCM_PLL6_CTRL_N_MASK)  CCM_PLL6_CTRL_N_SHIFT;
 +   int k = ((rval   CCM_PLL6_CTRL_K_MASK)  CCM_PLL6_CTRL_K_SHIFT) + 1;
 return 2400 * n * k / 2;
  }
 diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h 
 b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
 index 85ae8d7..8e37075 100644
 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
 +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
 @@ -209,6 +209,11 @@ struct sunxi_ccm_reg {
  #define CCM_PLL5_CTRL_BYPASS (0x1  30)
  #define CCM_PLL5_CTRL_EN (0x1  31)

 +#define CCM_PLL6_CTRL_N_SHIFT  8
 +#define CCM_PLL6_CTRL_N_MASK   (0x1fCCM_PLL6_CTRL_N_SHIFT)

Maybe a space separation between the operands for readability?
Same for the other places.

 +#define CCM_PLL6_CTRL_K_SHIFT  4
 +#define CCM_PLL6_CTRL_K_MASK   (0x3CCM_PLL6_CTRL_K_SHIFT)
 +
  #define CCM_GPS_CTRL_RESET (0x1  0)
  #define CCM_GPS_CTRL_GATE (0x1  1)

 diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 
 b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
 index d4ddd1f..382f296 100644
 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
 +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
 @@ -174,6 +174,11 @@ struct sunxi_ccm_reg {

  #define PLL6_CFG_DEFAULT   0x90041911

 +#define CCM_PLL6_CTRL_N_SHIFT  8
 +#define CCM_PLL6_CTRL_N_MASK   (0x1fCCM_PLL6_CTRL_N_SHIFT)
 +#define CCM_PLL6_CTRL_K_SHIFT  4
 +#define CCM_PLL6_CTRL_K_MASK   (0x3CCM_PLL6_CTRL_K_SHIFT)
 +
  #define AHB_GATE_OFFSET_MMC3   11
  #define AHB_GATE_OFFSET_MMC2   10
  #define AHB_GATE_OFFSET_MMC1   9

Looks good otherwise.


Cheers
ChenYu

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[linux-sunxi] [PATCH] sunxi: remove magic numbers from clock_get_pll{5,6}

2014-04-14 Thread Ian Campbell 
For clock_get_pll5 just remove it since it is unused.

For clock_get_pll6 introduce the necessary #defines.

Signed-off-by: Ian Campbell i...@hellion.org.uk
---
 arch/arm/cpu/armv7/sunxi/clock.c  | 18 ++
 arch/arm/include/asm/arch-sunxi/clock_sun4i.h |  5 +
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h |  5 +
 3 files changed, 12 insertions(+), 16 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index c07a975..94ba6e0 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -24,26 +24,12 @@ int clock_init(void)
return 0;
 }
 
-/* Return PLL5 frequency in Hz
- * Note: Assumes PLL5 reference is 24MHz clock
- */
-unsigned int clock_get_pll5(void)
-{
-   struct sunxi_ccm_reg *const ccm =
-   (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-   uint32_t rval = readl(ccm-pll5_cfg);
-   int n = (rval  8)  0x1f;
-   int k = ((rval  4)  3) + 1;
-   int p = 1  ((rval  16)  3);
-   return 2400 * n * k / p;
-}
-
 unsigned int clock_get_pll6(void)
 {
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
uint32_t rval = readl(ccm-pll6_cfg);
-   int n = (rval  8)  0x1f;
-   int k = ((rval  4)  3) + 1;
+   int n = (rval  CCM_PLL6_CTRL_N_MASK)  CCM_PLL6_CTRL_N_SHIFT;
+   int k = ((rval   CCM_PLL6_CTRL_K_MASK)  CCM_PLL6_CTRL_K_SHIFT) + 1;
return 2400 * n * k / 2;
 }
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 85ae8d7..8e37075 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -209,6 +209,11 @@ struct sunxi_ccm_reg {
 #define CCM_PLL5_CTRL_BYPASS (0x1  30)
 #define CCM_PLL5_CTRL_EN (0x1  31)
 
+#define CCM_PLL6_CTRL_N_SHIFT  8
+#define CCM_PLL6_CTRL_N_MASK   (0x1fCCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_K_SHIFT  4
+#define CCM_PLL6_CTRL_K_MASK   (0x3CCM_PLL6_CTRL_K_SHIFT)
+
 #define CCM_GPS_CTRL_RESET (0x1  0)
 #define CCM_GPS_CTRL_GATE (0x1  1)
 
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d4ddd1f..382f296 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -174,6 +174,11 @@ struct sunxi_ccm_reg {
 
 #define PLL6_CFG_DEFAULT   0x90041911
 
+#define CCM_PLL6_CTRL_N_SHIFT  8
+#define CCM_PLL6_CTRL_N_MASK   (0x1fCCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_K_SHIFT  4
+#define CCM_PLL6_CTRL_K_MASK   (0x3CCM_PLL6_CTRL_K_SHIFT)
+
 #define AHB_GATE_OFFSET_MMC3   11
 #define AHB_GATE_OFFSET_MMC2   10
 #define AHB_GATE_OFFSET_MMC1   9
-- 
1.9.0

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