Re: [linux-sunxi] [PATCH 2/9] sunxi: define bit shifts for CPU_AHB_APB0_CFG_REG
On 03/16/2014 06:34 PM, Ian Campbell wrote:
Signed-off-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7/sunxi/clock.c| 31 +++
arch/arm/include/asm/arch-sunxi/clock.h | 8 ++--
2 files changed, 29 insertions(+), 10 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index f7eb37b..54d801c 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -21,12 +21,18 @@ static void clock_init_safe(void)
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* Set safe defaults until PMU is configured */
- writel(AXI_DIV_1 0 | AHB_DIV_2 4 | APB0_DIV_1 8 |
- CPU_CLK_SRC_OSC24M 16, ccm-cpu_ahb_apb0_cfg);
+ writel(AXI_DIV_1 AXI_DIV_SHIFT |
+ AHB_DIV_2 AHB_DIV_SHIFT |
+ APB0_DIV_1 APB0_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M CPU_CLK_SRC_SHIFT,
+ ccm-cpu_ahb_apb0_cfg);
Is this a pre-patch and should more be done here? I don't think this is
making anything more clear/removing magic values is it?
I probably would have done something like (ignore any stupid mistakes,
i'm a little rusty atm :p) (p.s. I didn't think define names completly
through either, so forgive me there too :)
#define CPU_AXI_CLK_DIV_RATIO(n) n) - 1) 0x3) 0)
#define CPU_ATB_APB_CLK_DIV_RATIO(n) n) - 1) 0x3) 2)
/* note to self, isn't there some mathematical way to make this better*/
#define CPU_AHB_CLK_DIV_RATIO(n) (((n) 0x3) 4)
#define __CPU_AHB_CLK_DIV_RATIO_1 0x0
#define __CPU_AHB_CLK_DIV_RATIO_2 0x1
#define __CPU_AHB_CLK_DIV_RATIO_4 0x2
#define __CPU_AHB_CLK_DIV_RATIO_8 0x3
#define CPU_AHB_CLK_DIV_RATIO_1 \
CPU_AHB_CLK_DIV_RATIO(__CPU_AHB_CLK_DIV_RATIO_1)
#define CPU_AHB_CLK_DIV_RATIO_2 \
CPU_AHB_CLK_DIV_RATIO(__CPU_AHB_CLK_DIV_RATIO_2)
#define CPU_AHB_CLK_DIV_RATIO_4 \
CPU_AHB_CLK_DIV_RATIO(__CPU_AHB_CLK_DIV_RATIO_4)
#define CPU_AHB_CLK_DIV_RATIO_8 \
CPU_AHB_CLK_DIV_RATIO(__CPU_AHB_CLK_DIV_RATIO_8)
#define CPU_AHB_CLK_SRC(n) ((n)
actually, I stop right here, because below this comment, I see more that
can be fixed :)
I'll pull your tree and send a patch in a little bit! (If you think my
method is compeltly wrong, hit me up fast!)
Olliver
writel(0xa1005000, ccm-pll1_cfg);
sdelay(200);
- writel(AXI_DIV_1 0 | AHB_DIV_2 4 | APB0_DIV_1 8 |
- CPU_CLK_SRC_PLL1 16, ccm-cpu_ahb_apb0_cfg);
+ writel(AXI_DIV_1 AXI_DIV_SHIFT |
+ AHB_DIV_2 AHB_DIV_SHIFT |
+ APB0_DIV_1 APB0_DIV_SHIFT |
+ CPU_CLK_SRC_PLL1 CPU_CLK_SRC_SHIFT,
+ ccm-cpu_ahb_apb0_cfg);
#ifdef CONFIG_SUN5I
/* Power on reset default for PLL6 is 2400 MHz, which is faster then
* it can reliable do :| Set it to a 600 MHz instead. */
@@ -158,12 +164,18 @@ void clock_set_pll1(int hz)
apb0 = apb0 - 1;
/* Switch to 24MHz clock while changing PLL1 */
- writel(AXI_DIV_1 0 | AHB_DIV_2 4 | APB0_DIV_1 8 |
- CPU_CLK_SRC_OSC24M 16, ccm-cpu_ahb_apb0_cfg);
+ writel(AXI_DIV_1 AXI_DIV_SHIFT |
+ AHB_DIV_2 AHB_DIV_SHIFT |
+ APB0_DIV_1 APB0_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M CPU_CLK_SRC_SHIFT,
+ ccm-cpu_ahb_apb0_cfg);
sdelay(20);
/* Configure sys clock divisors */
- writel(axi 0 | ahb 4 | apb0 8 | CPU_CLK_SRC_OSC24M 16,
+ writel(axi AXI_DIV_SHIFT |
+ ahb AHB_DIV_SHIFT |
+ apb0 APB0_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M CPU_CLK_SRC_SHIFT,
ccm-cpu_ahb_apb0_cfg);
/* Configure PLL1 at the desired frequency */
@@ -171,7 +183,10 @@ void clock_set_pll1(int hz)
sdelay(200);
/* Switch CPU to PLL1 */
- writel(axi 0 | ahb 4 | apb0 8 | CPU_CLK_SRC_PLL1 16,
+ writel(axi AXI_DIV_SHIFT |
+ ahb AHB_DIV_SHIFT |
+ apb0 APB0_DIV_SHIFT |
+ CPU_CLK_SRC_PLL1 CPU_CLK_SRC_SHIFT,
ccm-cpu_ahb_apb0_cfg);
sdelay(20);
}
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h
b/arch/arm/include/asm/arch-sunxi/clock.h
index 8ca2066..533f9b5 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -98,20 +98,24 @@ struct sunxi_ccm_reg {
#define APB1_FACTOR_N 0
/* clock divide */
-#define CPU_CLK_SRC_OSC24M 1
-#define CPU_CLK_SRC_PLL1 2
+#define AXI_DIV_SHIFT (0)
#define AXI_DIV_1 0
#define AXI_DIV_2 1
#define AXI_DIV_3 2
#define AXI_DIV_4 3
+#define AHB_DIV_SHIFT (4)
#define AHB_DIV_1 0
#define AHB_DIV_2 1
#define AHB_DIV_4 2
#define AHB_DIV_8 3
+#define APB0_DIV_SHIFT (8)
#define APB0_DIV_1
Re: [linux-sunxi] [PATCH 2/9] sunxi: define bit shifts for CPU_AHB_APB0_CFG_REG
On Fri, 2014-03-21 at 22:01 +0100, Olliver Schinagl wrote: On 03/16/2014 06:34 PM, Ian Campbell wrote: Signed-off-by: Ian Campbell i...@hellion.org.uk --- arch/arm/cpu/armv7/sunxi/clock.c| 31 +++ arch/arm/include/asm/arch-sunxi/clock.h | 8 ++-- 2 files changed, 29 insertions(+), 10 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c index f7eb37b..54d801c 100644 --- a/arch/arm/cpu/armv7/sunxi/clock.c +++ b/arch/arm/cpu/armv7/sunxi/clock.c @@ -21,12 +21,18 @@ static void clock_init_safe(void) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; /* Set safe defaults until PMU is configured */ - writel(AXI_DIV_1 0 | AHB_DIV_2 4 | APB0_DIV_1 8 | - CPU_CLK_SRC_OSC24M 16, ccm-cpu_ahb_apb0_cfg); + writel(AXI_DIV_1 AXI_DIV_SHIFT | + AHB_DIV_2 AHB_DIV_SHIFT | + APB0_DIV_1 APB0_DIV_SHIFT | + CPU_CLK_SRC_OSC24M CPU_CLK_SRC_SHIFT, + ccm-cpu_ahb_apb0_cfg); Is this a pre-patch and should more be done here? I don't think this is making anything more clear/removing magic values is it? It is removing the 0, 4, 8 and 16 magic shifts and replacing them with descriptive named fields, which is what was asked for. This is a pretty common idiom in this sort of code. I don't think any more *needs* to be done (maybe you want to, that's up to you). I probably would have done something like (ignore any stupid mistakes, i'm a little rusty atm :p) (p.s. I didn't think define names completly through either, so forgive me there too :) #define CPU_AXI_CLK_DIV_RATIO(n) n) - 1) 0x3) 0) #define CPU_ATB_APB_CLK_DIV_RATIO(n) n) - 1) 0x3) 2) /* note to self, isn't there some mathematical way to make this better*/ #define CPU_AHB_CLK_DIV_RATIO(n) (((n) 0x3) 4) #define __CPU_AHB_CLK_DIV_RATIO_1 0x0 #define __CPU_AHB_CLK_DIV_RATIO_2 0x1 #define __CPU_AHB_CLK_DIV_RATIO_4 0x2 #define __CPU_AHB_CLK_DIV_RATIO_8 0x3 #define CPU_AHB_CLK_DIV_RATIO_1 \ CPU_AHB_CLK_DIV_RATIO(__CPU_AHB_CLK_DIV_RATIO_1) #define CPU_AHB_CLK_DIV_RATIO_2 \ CPU_AHB_CLK_DIV_RATIO(__CPU_AHB_CLK_DIV_RATIO_2) #define CPU_AHB_CLK_DIV_RATIO_4 \ CPU_AHB_CLK_DIV_RATIO(__CPU_AHB_CLK_DIV_RATIO_4) #define CPU_AHB_CLK_DIV_RATIO_8 \ CPU_AHB_CLK_DIV_RATIO(__CPU_AHB_CLK_DIV_RATIO_8) #define CPU_AHB_CLK_SRC(n) ((n) Personally I don't think that is making an improvement. The VALUE SHIFT pattern is well known. Ian. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 2/9] sunxi: define bit shifts for CPU_AHB_APB0_CFG_REG
Signed-off-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7/sunxi/clock.c| 31 +++
arch/arm/include/asm/arch-sunxi/clock.h | 8 ++--
2 files changed, 29 insertions(+), 10 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index f7eb37b..54d801c 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -21,12 +21,18 @@ static void clock_init_safe(void)
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* Set safe defaults until PMU is configured */
- writel(AXI_DIV_1 0 | AHB_DIV_2 4 | APB0_DIV_1 8 |
- CPU_CLK_SRC_OSC24M 16, ccm-cpu_ahb_apb0_cfg);
+ writel(AXI_DIV_1 AXI_DIV_SHIFT |
+ AHB_DIV_2 AHB_DIV_SHIFT |
+ APB0_DIV_1 APB0_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M CPU_CLK_SRC_SHIFT,
+ ccm-cpu_ahb_apb0_cfg);
writel(0xa1005000, ccm-pll1_cfg);
sdelay(200);
- writel(AXI_DIV_1 0 | AHB_DIV_2 4 | APB0_DIV_1 8 |
- CPU_CLK_SRC_PLL1 16, ccm-cpu_ahb_apb0_cfg);
+ writel(AXI_DIV_1 AXI_DIV_SHIFT |
+ AHB_DIV_2 AHB_DIV_SHIFT |
+ APB0_DIV_1 APB0_DIV_SHIFT |
+ CPU_CLK_SRC_PLL1 CPU_CLK_SRC_SHIFT,
+ ccm-cpu_ahb_apb0_cfg);
#ifdef CONFIG_SUN5I
/* Power on reset default for PLL6 is 2400 MHz, which is faster then
* it can reliable do :| Set it to a 600 MHz instead. */
@@ -158,12 +164,18 @@ void clock_set_pll1(int hz)
apb0 = apb0 - 1;
/* Switch to 24MHz clock while changing PLL1 */
- writel(AXI_DIV_1 0 | AHB_DIV_2 4 | APB0_DIV_1 8 |
- CPU_CLK_SRC_OSC24M 16, ccm-cpu_ahb_apb0_cfg);
+ writel(AXI_DIV_1 AXI_DIV_SHIFT |
+ AHB_DIV_2 AHB_DIV_SHIFT |
+ APB0_DIV_1 APB0_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M CPU_CLK_SRC_SHIFT,
+ ccm-cpu_ahb_apb0_cfg);
sdelay(20);
/* Configure sys clock divisors */
- writel(axi 0 | ahb 4 | apb0 8 | CPU_CLK_SRC_OSC24M 16,
+ writel(axi AXI_DIV_SHIFT |
+ ahb AHB_DIV_SHIFT |
+ apb0 APB0_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M CPU_CLK_SRC_SHIFT,
ccm-cpu_ahb_apb0_cfg);
/* Configure PLL1 at the desired frequency */
@@ -171,7 +183,10 @@ void clock_set_pll1(int hz)
sdelay(200);
/* Switch CPU to PLL1 */
- writel(axi 0 | ahb 4 | apb0 8 | CPU_CLK_SRC_PLL1 16,
+ writel(axi AXI_DIV_SHIFT |
+ ahb AHB_DIV_SHIFT |
+ apb0 APB0_DIV_SHIFT |
+ CPU_CLK_SRC_PLL1 CPU_CLK_SRC_SHIFT,
ccm-cpu_ahb_apb0_cfg);
sdelay(20);
}
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h
b/arch/arm/include/asm/arch-sunxi/clock.h
index 8ca2066..533f9b5 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -98,20 +98,24 @@ struct sunxi_ccm_reg {
#define APB1_FACTOR_N 0
/* clock divide */
-#define CPU_CLK_SRC_OSC24M 1
-#define CPU_CLK_SRC_PLL1 2
+#define AXI_DIV_SHIFT (0)
#define AXI_DIV_1 0
#define AXI_DIV_2 1
#define AXI_DIV_3 2
#define AXI_DIV_4 3
+#define AHB_DIV_SHIFT (4)
#define AHB_DIV_1 0
#define AHB_DIV_2 1
#define AHB_DIV_4 2
#define AHB_DIV_8 3
+#define APB0_DIV_SHIFT (8)
#define APB0_DIV_1 0
#define APB0_DIV_2 1
#define APB0_DIV_4 2
#define APB0_DIV_8 3
+#define CPU_CLK_SRC_SHIFT (16)
+#define CPU_CLK_SRC_OSC24M 1
+#define CPU_CLK_SRC_PLL1 2
#ifdef CONFIG_SUN5I
#define AHB_CLK_SRC_AXI0
--
1.8.5.3
--
You received this message because you are subscribed to the Google Groups
linux-sunxi group.
To unsubscribe from this group and stop receiving emails from it, send an email
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.
