On Mon, Sep 01, 2014 at 12:18:43PM +0300, Siarhei Siamashka wrote:
On Mon, 1 Sep 2014 12:40:06 +0800
Chen-Yu Tsai w...@csie.org wrote:
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
I want to get some input before i push this.
Is the dram_zq parameter suppose to be filled?
or just the lower 8 bits? It seems all the other
sun4/5/7i boards only have the lower 8 bits set.
Appears that we need a separate documentation for the dram_para struct
in addition to the hardware registers. But the 'dram_zq' parameter is
basically the same as
http://linux-sunxi.org/A10_DRAM_Controller_Register_Guide#SDR_ZQCR0
with just the order of ZPROG and ZDATA changed (ZPROG is configured in
the lower 8 bits of 'dram_zq').
ChenYu
---
sys_config/a13/hsg_h702.fex | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/sys_config/a13/hsg_h702.fex b/sys_config/a13/hsg_h702.fex
index 0748b6b..b691df4 100644
--- a/sys_config/a13/hsg_h702.fex
+++ b/sys_config/a13/hsg_h702.fex
@@ -59,11 +59,11 @@ dram_baseaddr = 0x4000
dram_clk = 432
dram_type = 3
dram_rank_num = 1
-dram_chip_density = 2048
-dram_io_width = 8
+dram_chip_density = 4096
+dram_io_width = 16
This appears to be a change from two ddr3 chips with density 2048 and 8
data lines to a single ddr3 chip with density 4096 and 16 data lines.
They are mostly equivalent. And I don't think that it is even possible
to distinguish these two configurations in any way from the software.
Except that higher density chips require more time for refresh. So
using the configuration with density 2048 is not quite a safe choice
if there is in fact only one chip with density 4096.
dram_bus_width = 16
dram_cas = 9
-dram_zq = 0x7b
+dram_zq = 0x56b9697b
It looks like this sets ZDATA to 0x6b969 and also sets the ZDEN bit.
Which means that ZQ calibration is bypassed and the ZPROG value (0x7b)
is not used.
And it additionally sets the 'NOICAL' bit:
https://github.com/omegamoon/Rockchip-GPL-Kernel/blob/master/arch/arm/mach-rk29/ddr.c#L218
Which still needs to be tested and documented in the wiki.
Was this dram configuration originally set by boot0?
dram_odt_en = 0
Maybe I need to run more tests to be completely sure, but when I checked
this stuff, I could not observe any measurable effects of setting ZQ
configuration unless ODT is also enabled.
dram_size = 512
dram_tpr0 = 0x42d899b7
Siarhei, since you are the expert on this, could you throw some of this
in the wiki, and document the current dram_para more completely?
Also, do you have a31 and a23 hw?
When Olimex starts shipping a31 we really should put you front in line,
so we can get that memory controller up and running properly. For a23,
try to find one of the cheap tablets (second hand ones should be
popping up), its memory controller seems significantly different from
a31.
Luc Verhaegen.
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