[linux-sunxi] Re: [PATCH v4 2/6] clk: sunxi: Add H3 clocks support

2015-10-30 Thread Arnd Bergmann
On Tuesday 27 October 2015 17:50:22 Jens Kuske wrote:
> +   of_property_read_string_index(node, "clock-output-names",
> + i, &clk_name);
> +
> +   if (index == 17 || (index >= 29 && index <= 31))
> +   clk_parent = AHB2;
> +   else if (index <= 63 || index >= 128)
> +   clk_parent = AHB1;
> +   else if (index >= 64 && index <= 95)
> +   clk_parent = APB1;
> +   else if (index >= 96 && index <= 127)
> +   clk_parent = APB2;
> +
> +   clk_reg = reg + 4 * (index / 32);
> 

Same as for the reset driver, this probably means you should have one
cell to indicate which bus it is for, and another cell for the
index.

Arnd

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[linux-sunxi] Re: [PATCH v4 2/6] clk: sunxi: Add H3 clocks support

2015-11-01 Thread Jens Kuske
Hi,

On 30/10/15 09:28, Arnd Bergmann wrote:
> On Tuesday 27 October 2015 17:50:22 Jens Kuske wrote:
>> +   of_property_read_string_index(node, "clock-output-names",
>> + i, &clk_name);
>> +
>> +   if (index == 17 || (index >= 29 && index <= 31))
>> +   clk_parent = AHB2;
>> +   else if (index <= 63 || index >= 128)
>> +   clk_parent = AHB1;
>> +   else if (index >= 64 && index <= 95)
>> +   clk_parent = APB1;
>> +   else if (index >= 96 && index <= 127)
>> +   clk_parent = APB2;
>> +
>> +   clk_reg = reg + 4 * (index / 32);
>>
> 
> Same as for the reset driver, this probably means you should have one
> cell to indicate which bus it is for, and another cell for the
> index.
> 

This is what Maxime suggested in an earlier version:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/344213.html

In between I had another version with the parents in DT, but he
didn't like that too.

Jens

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[linux-sunxi] Re: [PATCH v4 2/6] clk: sunxi: Add H3 clocks support

2015-11-04 Thread Maxime Ripard
Hi Arnd,

On Fri, Oct 30, 2015 at 09:28:55AM +0100, Arnd Bergmann wrote:
> On Tuesday 27 October 2015 17:50:22 Jens Kuske wrote:
> > +   of_property_read_string_index(node, "clock-output-names",
> > + i, &clk_name);
> > +
> > +   if (index == 17 || (index >= 29 && index <= 31))
> > +   clk_parent = AHB2;
> > +   else if (index <= 63 || index >= 128)
> > +   clk_parent = AHB1;
> > +   else if (index >= 64 && index <= 95)
> > +   clk_parent = APB1;
> > +   else if (index >= 96 && index <= 127)
> > +   clk_parent = APB2;
> > +
> > +   clk_reg = reg + 4 * (index / 32);
> > 
> 
> Same as for the reset driver, this probably means you should have one
> cell to indicate which bus it is for, and another cell for the
> index.

It's not really comparable to the reset driver.

What's happening here is that we have a single set of (contiguous)
registers, controlling gates from different parents.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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