[linux-sunxi] [PATCH v4 2/6] mfd: axp20x: Split the driver into core and i2c bits

[Chen-Yu Tsai]

The axp20x driver assumes the device is i2c based. This is not the
case with later chips, which use a proprietary 2 wire serial bus
by Allwinner called "Reduced Serial Bus".

This patch follows the example of mfd/wm831x and splits it into
an interface independent core, and an i2c specific glue layer.
MFD_AXP20X and the new MFD_AXP20X_I2C are changed to tristate
symbols, allowing the driver to be built as modules.

Included but unused header files are removed as well.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/mfd/Kconfig|  14 +++--
 drivers/mfd/Makefile   |   1 +
 drivers/mfd/axp20x-i2c.c   | 127 +
 drivers/mfd/axp20x.c   | 108 +-
 include/linux/mfd/axp20x.h |  33 +++-
 5 files changed, 183 insertions(+), 100 deletions(-)
 create mode 100644 drivers/mfd/axp20x-i2c.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 4d92df6ef9fe..804cd3dcce32 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -91,14 +91,18 @@ config MFD_BCM590XX
  Support for the BCM590xx PMUs from Broadcom
 
 config MFD_AXP20X
-   bool "X-Powers AXP20X"
+   tristate
select MFD_CORE
-   select REGMAP_I2C
select REGMAP_IRQ
-   depends on I2C=y
+
+config MFD_AXP20X_I2C
+   tristate "X-Powers AXP series PMICs with I2C"
+   select MFD_AXP20X
+   select REGMAP_I2C
+   depends on I2C
help
- If you say Y here you get support for the X-Powers AXP202, AXP209 and
- AXP288 power management IC (PMIC).
+ If you say Y here you get support for the X-Powers AXP series power
+ management ICs (PMICs) controlled with I2C.
  This driver include only the core APIs. You have to select individual
  components like regulators or the PEK (Power Enable Key) under the
  corresponding menus.
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index a8b76b81b467..a6913007d667 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -107,6 +107,7 @@ obj-$(CONFIG_PMIC_DA9052)   += da9052-core.o
 obj-$(CONFIG_MFD_DA9052_SPI)   += da9052-spi.o
 obj-$(CONFIG_MFD_DA9052_I2C)   += da9052-i2c.o
 obj-$(CONFIG_MFD_AXP20X)   += axp20x.o
+obj-$(CONFIG_MFD_AXP20X_I2C)   += axp20x-i2c.o
 
 obj-$(CONFIG_MFD_LP3943)   += lp3943.o
 obj-$(CONFIG_MFD_LP8788)   += lp8788.o lp8788-irq.o
diff --git a/drivers/mfd/axp20x-i2c.c b/drivers/mfd/axp20x-i2c.c
new file mode 100644
index ..75b247af2514
--- /dev/null
+++ b/drivers/mfd/axp20x-i2c.c
@@ -0,0 +1,127 @@
+/*
+ * axp20x-i2c.c - I2C driver for the X-Powers' Power Management ICs
+ *
+ * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK 
DC-DC
+ * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
+ * as well as configurable GPIOs.
+ *
+ * This driver supports the I2C variants.
+ *
+ * Author: Carlo Caione <ca...@caione.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static const struct of_device_id axp20x_i2c_of_match[] = {
+   { .compatible = "x-powers,axp152", .data = (void *) AXP152_ID },
+   { .compatible = "x-powers,axp202", .data = (void *) AXP202_ID },
+   { .compatible = "x-powers,axp209", .data = (void *) AXP209_ID },
+   { .compatible = "x-powers,axp221", .data = (void *) AXP221_ID },
+   { },
+};
+MODULE_DEVICE_TABLE(of, axp20x_i2c_of_match);
+
+/*
+ * This is useless for OF-enabled devices, but it is needed by I2C subsystem
+ */
+static const struct i2c_device_id axp20x_i2c_id[] = {
+   { },
+};
+MODULE_DEVICE_TABLE(i2c, axp20x_i2c_id);
+
+static const struct acpi_device_id axp20x_i2c_acpi_match[] = {
+   {
+   .id = "INT33F4",
+   .driver_data = AXP288_ID,
+   },
+   { },
+};
+MODULE_DEVICE_TABLE(acpi, axp20x_i2c_acpi_match);
+
+static int axp20x_i2c_match_device(struct axp20x_dev *axp20x,
+  struct device *dev)
+{
+   const struct acpi_device_id *acpi_id;
+   const struct of_device_id *of_id;
+
+   if (dev->of_node) {
+   of_id = of_match_device(axp20x_i2c_of_match, dev);
+   if (!of_id) {
+   dev_err(dev, "Unable to match OF ID\n");
+   return -ENODEV;
+   }
+   axp20x->variant = (long) of_id->data;
+   } else {
+   acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
+   if (!acpi_id || !acpi_id->driver_data) {
+   dev_err(dev, "Unable to match ACPI ID and data

Re: [linux-sunxi] Re: [PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

[Chen-Yu Tsai]

On Mon, Nov 23, 2015 at 6:50 PM, Hans de Goede  wrote:
> HI,
>
>
> On 23-11-15 09:57, Maxime Ripard wrote:
>>
>> Hi,
>>
>> On Sun, Nov 01, 2015 at 02:33:23PM +0100, Jens Kuske wrote:
>
> +   bus_gates: clk@01c20060 {
> +   #clock-cells = <1>;
> +   compatible =
> "allwinner,sun8i-h3-bus-gates-clk";
> +   reg = <0x01c20060 0x14>;
> +   clocks = <>, <>, <>, <>;
> +   clock-names = "ahb1", "ahb2", "apb1", "apb2";
> +   clock-indices = <5>, <6>, <8>,
> +   <9>, <10>, <13>,
> +   <14>, <17>, <18>,
> +   <19>, <20>,
> +   <21>, <23>,
> +   <24>, <25>,
> +   <26>, <27>,
> +   <28>, <29>,
> +   <30>, <31>, <32>,
> +   <35>, <36>, <37>,
> +   <40>, <41>, <43>,
> +   <44>, <52>, <53>,
> +   <54>, <64>,
> +   <65>, <69>, <72>,
> +   <76>, <77>, <78>,
> +   <96>, <97>, <98>,
> +   <112>, <113>,
> +   <114>, <115>, <116>,
> +   <128>, <135>;
> +   clock-output-names = "ahb1_ce", "ahb1_dma",
> "ahb1_mmc0",
> +   "ahb1_mmc1", "ahb1_mmc2",
> "ahb1_nand",
> +   "ahb1_sdram", "ahb2_gmac",
> "ahb1_ts",
> +   "ahb1_hstimer", "ahb1_spi0",
> +   "ahb1_spi1", "ahb1_otg",
> +   "ahb1_otg_ehci0", "ahb1_ehic1",


 ahb1_ehci1? Same for the following 3 lines.
>>>
>>> I'll fix them...


> +   "ahb1_ehic2", "ahb1_ehic3",
> +   "ahb1_otg_ohci0", "ahb2_ohic1",
> +   "ahb2_ohic2", "ahb2_ohic3",
> "ahb1_ve",
> +   "ahb1_lcd0", "ahb1_lcd1",
> "ahb1_deint",
> +   "ahb1_csi", "ahb1_tve",
> "ahb1_hdmi",
> +   "ahb1_de", "ahb1_gpu",
> "ahb1_msgbox",
> +   "ahb1_spinlock", "apb1_codec",
> +   "apb1_spdif", "apb1_pio",
> "apb1_ths",
> +   "apb1_i2s0", "apb1_i2s1",
> "apb1_i2s2",
> +   "apb2_i2c0", "apb2_i2c1",
> "apb2_i2c2",
> +   "apb2_uart0", "apb2_uart1",
> +   "apb2_uart2", "apb2_uart3",
> "apb2_scr",
> +   "ahb1_ephy", "ahb1_dbg";


 If it weren't for the last 2 clocks, we could cleanly split out apb1 and
 apb2
 gates. Having a separate AHB clock gate taking 2 addresses seems messy
 as well. :(
>>>
>>>
>>> Well, maybe we still should do that, if we split the resets too at least
>>> apb[12]  would line up again.
>>>
>>> I don't know what to do with these bus things any more, all variants I
>>> sent had issues somewhere...
>>
>>
>> AFAIK, Arnd had some objections, but he never got back to us when we
>> explained how the hardware was laid out, so I don't know if they still
>> apply.
>>
> +   };
> +
> +   mmc0_clk: clk@01c20088 {
> +   #clock-cells = <1>;
> +   compatible = "allwinner,sun4i-a10-mmc-clk";
> +   reg = <0x01c20088 0x4>;
> +   clocks = <>, < 0>, < 0>;
> +   clock-output-names = "mmc0",
> +"mmc0_output",
> +"mmc0_sample";
> +   };
> +
> +   mmc1_clk: clk@01c2008c {
> +   #clock-cells = <1>;
> +   compatible = "allwinner,sun4i-a10-mmc-clk";
> +   reg = <0x01c2008c 0x4>;
> +   clocks = <>, < 0>, < 0>;
> +   clock-output-names = "mmc1",
> +"mmc1_output",
> + 

[linux-sunxi] [PATCH v3 3/5] clk: sunxi: Add sun9i A80 cpus (cpu special) clock support

[Chen-Yu Tsai]

The "cpus" clock is the clock for the embedded processor in the A80.
It is also part of the PRCM clock tree. This clock includes a pre-
divider on one of its inputs. For now we are using a custom clock
driver for it. In the future we may want to develop a generalized
driver for these types of clocks, which also includes the AHB clock
driver on sun[5678]i.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---

Hi Maxime,

I'll do the factors clock refactoring mentioned during the discussion
around v2 later on.

---
 Documentation/devicetree/bindings/clock/sunxi.txt |   1 +
 drivers/clk/sunxi/Makefile|   1 +
 drivers/clk/sunxi/clk-sun9i-cpus.c| 240 ++
 3 files changed, 242 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-sun9i-cpus.c

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index b6859ed6913f..153ac72869e8 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -27,6 +27,7 @@ Required properties:
"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
+   "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 121333ce34ea..07d914c3f6d1 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -13,6 +13,7 @@ obj-y += clk-simple-gates.o
 obj-y += clk-sun8i-apb0.o
 obj-y += clk-sun8i-mbus.o
 obj-y += clk-sun9i-core.o
+obj-y += clk-sun9i-cpus.o
 obj-y += clk-sun9i-mmc.o
 obj-y += clk-usb.o
 
diff --git a/drivers/clk/sunxi/clk-sun9i-cpus.c 
b/drivers/clk/sunxi/clk-sun9i-cpus.c
new file mode 100644
index ..7626d2194b96
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun9i-cpus.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright (C) 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <w...@csie.org>
+ *
+ * Allwinner A80 CPUS clock driver
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static DEFINE_SPINLOCK(sun9i_a80_cpus_lock);
+
+/**
+ * sun9i_a80_cpus_clk_setup() - Setup function for a80 cpus composite clk
+ */
+
+#define SUN9I_CPUS_MAX_PARENTS 4
+#define SUN9I_CPUS_MUX_PARENT_PLL4 3
+#define SUN9I_CPUS_MUX_SHIFT   16
+#define SUN9I_CPUS_MUX_MASKGENMASK(17, 16)
+#define SUN9I_CPUS_MUX_GET_PARENT(reg) ((reg & SUN9I_CPUS_MUX_MASK) >> \
+   SUN9I_CPUS_MUX_SHIFT)
+
+#define SUN9I_CPUS_DIV_SHIFT   4
+#define SUN9I_CPUS_DIV_MASKGENMASK(5, 4)
+#define SUN9I_CPUS_DIV_GET(reg)((reg & SUN9I_CPUS_DIV_MASK) >> 
\
+   SUN9I_CPUS_DIV_SHIFT)
+#define SUN9I_CPUS_DIV_SET(reg, div)   ((reg & ~SUN9I_CPUS_DIV_MASK) | \
+   (div << SUN9I_CPUS_DIV_SHIFT))
+#define SUN9I_CPUS_PLL4_DIV_SHIFT  8
+#define SUN9I_CPUS_PLL4_DIV_MASK   GENMASK(12, 8)
+#define SUN9I_CPUS_PLL4_DIV_GET(reg)   ((reg & SUN9I_CPUS_PLL4_DIV_MASK) >> \
+   SUN9I_CPUS_PLL4_DIV_SHIFT)
+#define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | 
\
+   (div << 
SUN9I_CPUS_PLL4_DIV_SHIFT))
+
+struct sun9i_a80_cpus_clk {
+   struct clk_hw hw;
+   void __iomem *reg;
+};
+
+#define to_sun9i_a80_cpus_clk(_hw) container_of(_hw, struct 
sun9i_a80_cpus_clk, hw)
+
+static unsigned long sun9i_a80_cpus_clk_recalc_rate(struct clk_hw *hw,
+   unsigned long parent_rate)
+{
+   struct sun9i_a80_cpus_clk *cpus = to_sun9i_a80_cpus_clk(hw);
+   unsigned long rate;
+   u32 reg;
+
+   /* Fetch the register value */
+   reg = readl(cpus->reg);
+
+   /* apply pre-divider first if parent is pll4 */
+   if (SUN9I_CPUS_MUX_GET_PARENT(reg) == SUN9I_CPUS_MUX_PARENT_PLL4)
+   parent_rate /= SUN9I_CPUS_PLL4_DIV_GET(reg) + 1;
+
+   /* clk divider */
+   rate = parent_rate / (SUN9I_CPUS_DIV_GET(reg) + 1);
+
+   return rate;
+}
+
+static long sun9i_a80_cpus_clk_round(unsigned long rate, u8 *divp, u8 
*pre_divp,
+u8 parent, unsigned long parent_rate)
+{
+   u8 div, pre_div = 1;
+
+   /*
+* clock can only divide, so we will never be able to achieve
+* frequencies higher than the parent frequency
+*/
+   if (p

[linux-sunxi] [PATCH v3 5/5] ARM: dts: sun9i: Add TODO comments for the main and low power clocks

[Chen-Yu Tsai]

The main (24MHz) clock on the A80 is configurable via the PRCM address
space. The low power/speed (32kHz) clock is from an external chip, the
AC100.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index a4ce348c0831..eb69a62f6bc4 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -128,6 +128,17 @@
 */
ranges = <0 0 0 0x2000>;
 
+   /*
+* This clock is actually configurable from the PRCM address
+* space. The external 24M oscillator can be turned off, and
+* the clock switched to an internal 16M RC oscillator. Under
+* normal operation there's no reason to do this, and the
+* default is to use the external good one, so just model this
+* as a fixed clock. Also it is not entirely clear if the
+* osc24M mux in the PRCM affects the entire clock tree, which
+* would also throw all the PLL clock rates off, or just the
+* downstream clocks in the PRCM.
+*/
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -135,6 +146,13 @@
clock-output-names = "osc24M";
};
 
+   /*
+* The 32k clock is from an external source, normally the
+* AC100 codec/RTC chip. This clock is by default enabled
+* and clocked at 32768 Hz, from the oscillator connected
+* to the AC100. It is configurable, but no such driver or
+* bindings exist yet.
+*/
osc32k: osc32k_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
-- 
2.6.2

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[linux-sunxi] [PATCH v3 2/5] clk: sunxi: Add sun9i A80 apbs gates support

[Chen-Yu Tsai]

This patch adds support for the PRCM apbs clock gates found on the
Allwinner A80 SoC.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 drivers/clk/sunxi/clk-simple-gates.c  | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index a94bb56a0e9e..b6859ed6913f 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -55,6 +55,7 @@ Required properties:
"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
+   "allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
diff --git a/drivers/clk/sunxi/clk-simple-gates.c 
b/drivers/clk/sunxi/clk-simple-gates.c
index 0214c6548afd..c8acc0612c15 100644
--- a/drivers/clk/sunxi/clk-simple-gates.c
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -140,6 +140,8 @@ CLK_OF_DECLARE(sun9i_a80_apb0, 
"allwinner,sun9i-a80-apb0-gates-clk",
   sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-gates-clk",
   sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_apbs, "allwinner,sun9i-a80-apbs-gates-clk",
+  sunxi_simple_gates_init);
 
 static const int sun4i_a10_ahb_critical_clocks[] __initconst = {
14, /* ahb_sdram */
-- 
2.6.2

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[linux-sunxi] [PATCH v3 1/5] clk: sunxi: Add CLK_OF_DECLARE support for sun8i-a23-apb0-clk driver

[Chen-Yu Tsai]

The APBS clock on sun9i is the same as the APB0 clock on sun8i. With
sun9i we are supporting the PRCM clocks by using CLK_OF_DECLARE,
instead of through a PRCM mfd device and subdevices for each clock
and reset control. As such we need a CLK_OF_DECLARE version of
the sun8i-a23-apb0-clk driver.

Also, build it for all Allwinner/sunxi platforms, and not just for
configurations with MFD_SUN6I_PRCM enabled.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/clk/sunxi/Makefile |  4 ++--
 drivers/clk/sunxi/clk-sun8i-apb0.c | 43 ++
 2 files changed, 45 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index cb4c299214ce..121333ce34ea 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -10,11 +10,11 @@ obj-y += clk-a10-pll2.o
 obj-y += clk-a20-gmac.o
 obj-y += clk-mod0.o
 obj-y += clk-simple-gates.o
+obj-y += clk-sun8i-apb0.o
 obj-y += clk-sun8i-mbus.o
 obj-y += clk-sun9i-core.o
 obj-y += clk-sun9i-mmc.o
 obj-y += clk-usb.o
 
 obj-$(CONFIG_MFD_SUN6I_PRCM) += \
-   clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
-   clk-sun8i-apb0.o
+   clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o
diff --git a/drivers/clk/sunxi/clk-sun8i-apb0.c 
b/drivers/clk/sunxi/clk-sun8i-apb0.c
index 7ae5d2c2cde1..11b2f2fde245 100644
--- a/drivers/clk/sunxi/clk-sun8i-apb0.c
+++ b/drivers/clk/sunxi/clk-sun8i-apb0.c
@@ -17,8 +17,51 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
+static void sun8i_a23_apb0_setup(struct device_node *node)
+{
+   const char *clk_name = node->name;
+   const char *clk_parent;
+   void __iomem *reg;
+   struct resource res;
+   struct clk *clk;
+   int ret;
+
+   reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+   if (IS_ERR(reg))
+   return;
+
+   clk_parent = of_clk_get_parent_name(node, 0);
+   if (!clk_parent)
+   goto err_unmap;
+
+   of_property_read_string(node, "clock-output-names", _name);
+
+   /* The A23 APB0 clock is a standard 2 bit wide divider clock */
+   clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg,
+  0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
+   if (IS_ERR(clk))
+   goto err_unmap;
+
+   ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+   if (ret)
+   goto err_unregister;
+
+   return;
+
+err_unregister:
+   clk_unregister_divider(clk);
+
+err_unmap:
+   iounmap(reg);
+   of_address_to_resource(node, 0, );
+   release_mem_region(res.start, resource_size());
+}
+CLK_OF_DECLARE(sun8i_a23_apb0, "allwinner,sun8i-a23-apb0-clk",
+  sun8i_a23_apb0_setup);
+
 static int sun8i_a23_apb0_clk_probe(struct platform_device *pdev)
 {
struct device_node *np = pdev->dev.of_node;
-- 
2.6.2

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[linux-sunxi] [PATCH v3 4/5] ARM: dts: sun9i: Add A80 PRCM clocks and reset control nodes

[Chen-Yu Tsai]

This adds the supported PRCM clocks and reset controls to the A80 dtsi.
The DAUDIO module clocks are not supported yet.

Also update clock and reset phandles for r_uart.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 79 +++-
 1 file changed, 78 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 1118bf5cc4fb..a4ce348c0831 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -164,6 +164,14 @@
 "usb_phy2", "usb_hsic_12M";
};
 
+   pll3: clk@0608 {
+   /* placeholder until implemented */
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-rate = <0>;
+   clock-output-names = "pll3";
+   };
+
pll4: clk@060c {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-pll4-clk";
@@ -350,6 +358,68 @@
"apb1_uart2", "apb1_uart3",
"apb1_uart4", "apb1_uart5";
};
+
+   cpus_clk: clk@08001410 {
+   compatible = "allwinner,sun9i-a80-cpus-clk";
+   reg = <0x08001410 0x4>;
+   #clock-cells = <0>;
+   clocks = <>, <>, <>, <>;
+   clock-output-names = "cpus";
+   };
+
+   ahbs: ahbs_clk {
+   compatible = "fixed-factor-clock";
+   #clock-cells = <0>;
+   clock-div = <1>;
+   clock-mult = <1>;
+   clocks = <_clk>;
+   clock-output-names = "ahbs";
+   };
+
+   apbs: clk@0800141c {
+   compatible = "allwinner,sun8i-a23-apb0-clk";
+   reg = <0x0800141c 0x4>;
+   #clock-cells = <0>;
+   clocks = <>;
+   clock-output-names = "apbs";
+   };
+
+   apbs_gates: clk@08001428 {
+   compatible = "allwinner,sun9i-a80-apbs-gates-clk";
+   reg = <0x08001428 0x4>;
+   #clock-cells = <1>;
+   clocks = <>;
+   clock-indices = <0>, <1>,
+   <2>, <3>,
+   <4>, <5>,
+   <6>, <7>,
+   <12>, <13>,
+   <16>, <17>,
+   <18>, <20>;
+   clock-output-names = "apbs_pio", "apbs_ir",
+   "apbs_timer", "apbs_rsb",
+   "apbs_uart", "apbs_1wire",
+   "apbs_i2c0", "apbs_i2c1",
+   "apbs_ps2_0", "apbs_ps2_1",
+   "apbs_dma", "apbs_i2s0",
+   "apbs_i2s1", "apbs_twd";
+   };
+
+   r_1wire_clk: clk@08001450 {
+   reg = <0x08001450 0x4>;
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-mod0-clk";
+   clocks = <>, <>;
+   clock-output-names = "r_1wire";
+   };
+
+   r_ir_clk: clk@08001454 {
+   reg = <0x08001454 0x4>;
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-mod0-clk";
+   clocks = <>, <>;
+   clock-output-names = "r_ir";
+   };
};
 
soc {
@@ -764,13 +834,20 @@
interrupts = ;
};
 
+   apbs_rst: reset@080014b0 {
+   reg = <0x080014b0 0x4>;
+   compatible = "allwinner,sun6i-a31-clock-reset";
+   #reset-cells = <1>;
+   };
+
r_uart: serial@08002800 {
   

[linux-sunxi] Re: [PATCH v4 2/6] mfd: axp20x: Split the driver into core and i2c bits

[Chen-Yu Tsai]

On Tue, Nov 24, 2015 at 8:35 PM, Andy Shevchenko
<andy.shevche...@gmail.com> wrote:
> On Tue, Nov 24, 2015 at 1:28 PM, Chen-Yu Tsai <w...@csie.org> wrote:
>> Hi,
>>
>> On Tue, Nov 24, 2015 at 5:37 PM, Andy Shevchenko
>> <andy.shevche...@gmail.com> wrote:
>>> On Tue, Nov 24, 2015 at 5:48 AM, Chen-Yu Tsai <w...@csie.org> wrote:
>>>> The axp20x driver assumes the device is i2c based. This is not the
>>>> case with later chips, which use a proprietary 2 wire serial bus
>>>> by Allwinner called "Reduced Serial Bus".
>>>>
>>>> This patch follows the example of mfd/wm831x and splits it into
>>>> an interface independent core, and an i2c specific glue layer.
>>>> MFD_AXP20X and the new MFD_AXP20X_I2C are changed to tristate
>>>> symbols, allowing the driver to be built as modules.
>>>>
>>>> Included but unused header files are removed as well.
>
> So…
>
>>>> +   if (dev->of_node) {
>>>
>>> What about
>>>
>>> if (…of_node) {
>>>   const struct of_device_id *id;
>>> …
>>> } else if ACPI_COMPANION(…) {
>
> This should be has_acpi_companion().

I don't think the "else if" is necessary. There's only 2 possible ways
the device gets probed, either device tree or ACPI.

>>>   const struct acpi_device_id *id;
>>> …
>>> } else {
>>>  return -ENODEV;
>>> }
>>
>> I really don't want to change code that I'm just moving around.
>> Same goes for the other comments about this patch. I can do another
>> patch on top of this to fix the style issues if it really bothers
>> people.
>
> Fair enough.
> My comments mostly about unnecessity of second parameter in the functions.
>
> So,  you already did some clean up in this patch (above), what about
> to do another? I also prefer separate patch *before* you do a split.

Sure. I'll do a patch or 2 before the split. Would you mind if I add your
Suggested-by tag?


Regards
ChenYu

>>>> +   axp20x = devm_kzalloc(>dev, sizeof(*axp20x), GFP_KERNEL);
>>>> +   if (!axp20x)
>>>> +   return -ENOMEM;
>>>> +
>>>> +   ret = axp20x_i2c_match_device(axp20x, >dev);
>>>> +   if (ret)
>>>> +   return ret;
>>>> +
>>>> +   axp20x->dev = >dev;
>>>> +   axp20x->irq = i2c->irq;
>>>
>>> If you move _match_device() here you will be able to drop away struct
>>> device * parameter.
>
> --
> With Best Regards,
> Andy Shevchenko

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[linux-sunxi] Re: [PATCH v4 2/6] mfd: axp20x: Split the driver into core and i2c bits

[Chen-Yu Tsai]

Hi,

On Tue, Nov 24, 2015 at 5:37 PM, Andy Shevchenko
<andy.shevche...@gmail.com> wrote:
> On Tue, Nov 24, 2015 at 5:48 AM, Chen-Yu Tsai <w...@csie.org> wrote:
>> The axp20x driver assumes the device is i2c based. This is not the
>> case with later chips, which use a proprietary 2 wire serial bus
>> by Allwinner called "Reduced Serial Bus".
>>
>> This patch follows the example of mfd/wm831x and splits it into
>> an interface independent core, and an i2c specific glue layer.
>> MFD_AXP20X and the new MFD_AXP20X_I2C are changed to tristate
>> symbols, allowing the driver to be built as modules.
>>
>> Included but unused header files are removed as well.
>>
>> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
>> ---
>>  drivers/mfd/Kconfig|  14 +++--
>>  drivers/mfd/Makefile   |   1 +
>>  drivers/mfd/axp20x-i2c.c   | 127 
>> +
>>  drivers/mfd/axp20x.c   | 108 +-
>>  include/linux/mfd/axp20x.h |  33 +++-
>>  5 files changed, 183 insertions(+), 100 deletions(-)
>>  create mode 100644 drivers/mfd/axp20x-i2c.c
>>
>> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
>> index 4d92df6ef9fe..804cd3dcce32 100644
>> --- a/drivers/mfd/Kconfig
>> +++ b/drivers/mfd/Kconfig
>> @@ -91,14 +91,18 @@ config MFD_BCM590XX
>>   Support for the BCM590xx PMUs from Broadcom
>>
>>  config MFD_AXP20X
>> -   bool "X-Powers AXP20X"
>> +   tristate
>> select MFD_CORE
>> -   select REGMAP_I2C
>> select REGMAP_IRQ
>> -   depends on I2C=y
>> +
>> +config MFD_AXP20X_I2C
>> +   tristate "X-Powers AXP series PMICs with I2C"
>> +   select MFD_AXP20X
>> +   select REGMAP_I2C
>> +   depends on I2C
>> help
>> - If you say Y here you get support for the X-Powers AXP202, AXP209 
>> and
>> - AXP288 power management IC (PMIC).
>> + If you say Y here you get support for the X-Powers AXP series power
>> + management ICs (PMICs) controlled with I2C.
>>   This driver include only the core APIs. You have to select 
>> individual
>>   components like regulators or the PEK (Power Enable Key) under the
>>   corresponding menus.
>> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
>> index a8b76b81b467..a6913007d667 100644
>> --- a/drivers/mfd/Makefile
>> +++ b/drivers/mfd/Makefile
>> @@ -107,6 +107,7 @@ obj-$(CONFIG_PMIC_DA9052)   += da9052-core.o
>>  obj-$(CONFIG_MFD_DA9052_SPI)   += da9052-spi.o
>>  obj-$(CONFIG_MFD_DA9052_I2C)   += da9052-i2c.o
>>  obj-$(CONFIG_MFD_AXP20X)   += axp20x.o
>> +obj-$(CONFIG_MFD_AXP20X_I2C)   += axp20x-i2c.o
>>
>>  obj-$(CONFIG_MFD_LP3943)   += lp3943.o
>>  obj-$(CONFIG_MFD_LP8788)   += lp8788.o lp8788-irq.o
>> diff --git a/drivers/mfd/axp20x-i2c.c b/drivers/mfd/axp20x-i2c.c
>> new file mode 100644
>> index ..75b247af2514
>> --- /dev/null
>> +++ b/drivers/mfd/axp20x-i2c.c
>> @@ -0,0 +1,127 @@
>> +/*
>> + * axp20x-i2c.c - I2C driver for the X-Powers' Power Management ICs
>> + *
>> + * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK 
>> DC-DC
>> + * converters, LDOs, multiple 12-bit ADCs of voltage, current and 
>> temperature
>> + * as well as configurable GPIOs.
>> + *
>> + * This driver supports the I2C variants.
>> + *
>> + * Author: Carlo Caione <ca...@caione.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +static const struct of_device_id axp20x_i2c_of_match[] = {
>> +   { .compatible = "x-powers,axp152", .data = (void *) AXP152_ID },
>> +   { .compatible = "x-powers,axp202", .data = (void *) AXP202_ID },
>> +   { .compatible = "x-powers,axp209", .data = (void *) AXP209_ID },
>> +   { .compatible = "x-powers,axp221", .data = (void *) AXP221_ID },
>> +   { },
>> +};
>> +MODULE_DEVICE_TABLE(of, axp20x_i2c_of_match);
>> +
>> +/*
>> + * This is useless for OF-enabled devices, but it is needed by I2C subsyst

[linux-sunxi] [PATCH v7 00/10] mfd: axp20x: Add support for RSB based AXP223

[Chen-Yu Tsai]

Hi everyone,

This is v7 of the AXP223 PMIC series. v7 fixes the address of the AXP223
in the DT. 

Lee, please merge the first 8 patches. Once they're in, Maxime can take
the DTS patches.

Changes since v6:

  - Add copyright notice to axp20x-rsb.c

  - Correct order of header files in axp20x-rsb.c

  - Use generic dev_set_drvdata() instead of sunxi_rsb_device_set_drvdata()

  - Drop file name from file headers

  - Add patch adding missing copyright notice for original axp20x author

Changes since v5:

  - Correct AXP223 address to 0x3a3.

Changes since v4:

  - Get rid of second parameter of axp20x_match_device() (new patch 2)

  - Match against dev->driver->of_match_table, so the entirety of
axp20x_match_device() can be kept in the core. (new patch 3)

  - Move *_device_id tables to bottom of the driver, right above driver
declaration. (patch 4 & 6)

  - Remove extra whitespaces while moving i2c specific code (patch 4)

  - Remove leftover whitespace and code style issues in axp20x core
(new patch 5)

  - Remove extra whitespaces in rsb specific code (patch 6)

Changes since v3:

  - Removed settings for axp223 reg_rtc_ldo from board dts files that
are already in axp22x.dtsi. The name is kept.

  - Dropped simplefb label and defconfig patches, as they are merged.

Changes since v2:

  - s/It's/Its/ for the commit messages of patches 5 and 7

  - Add Rob's Acked-by for patch 1

Changes since v1:

  - Dropped NMI interrupt controller dts patch (Merged)

  - Change MFD_AXP20X to represent the axp20x core, and drop MFD_AXP20X_CORE
  
  - Keep the axp20x core bits named axp20x.c

  - Add patch 7 to add AXP223 to sun8i-q8-common.dtsi

  - Add patch 8 & 9 to update defconfigs

  - Make axp20x drivers tristate and buildable as modules

  - Drop "_sunxi" substring from identifiers in axp20x-rsb driver


This series adds support for the Reduced Serial Bus based AXP223 PMIC.
The AXP223 is functionally identical to the AXP221, which we already
support. Only some default values for the regulators are different.
The defaults fit their recommended application, paired with different
SoCs.

Patch 1 adds AXP223 to the list of supported chips in the DT binding.

Patch 2 gets rid of the extra "struct device *" parameter from
axp20x_match_device().

Patch 3 makes axp20x_match_device() use dev->driver->of_match_table,
so the function can be library-ized without modification.

Patch 4 adds the missing copyright notice for axp20x's original author.

Patch 5 splits the axp20x mfd driver into 2 parts, a core library, and
an I2C driver.

Patch 6 cleans up some leftover whitespace issues in axp20x core.

Patch 7 adds an RSB based driver for the AXP223.

Patch 8 adds support for the AXP223 regulators

Patch 9 enables the AXP223 PMIC and its regulators for the Sinlinx
SinA33.

Patch 10 enables the AXP223 PMIC and its regulators for A23/A33 based
Q8 tablet devices.


Regards
ChenYu



Chen-Yu Tsai (10):
  mfd: axp20x: Add AXP223 to list of supported PMICs in DT bindings
  mfd: axp20x: Remove second struct device * parameter for
axp20x_match_device()
  mfd: axp20x: use dev->driver->of_match_table in axp20x_match_device()
  mfd: axp20x: Add missing copyright notice
  mfd: axp20x: Split the driver into core and i2c bits
  mfd: axp20x: Whitespace, open parenthesis alignment code style fixes
  mfd: axp20x: Add support for RSB based AXP223 PMIC
  regulator: axp20x: Support new AXP223 PMIC
  ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator
nodes
  ARM: dts: sun8i: q8-common: Add AXP223 PMIC device and regulator nodes

 Documentation/devicetree/bindings/mfd/axp20x.txt |   7 +-
 arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts   |  76 +++-
 arch/arm/boot/dts/sun8i-q8-common.dtsi   |  83 +-
 drivers/mfd/Kconfig  |  25 --
 drivers/mfd/Makefile |   2 +
 drivers/mfd/axp20x-i2c.c | 104 ++
 drivers/mfd/axp20x-rsb.c |  80 +
 drivers/mfd/axp20x.c | 105 ++-
 drivers/regulator/axp20x-regulator.c |   3 +
 include/linux/mfd/axp20x.h   |  34 +++-
 10 files changed, 425 insertions(+), 94 deletions(-)
 create mode 100644 drivers/mfd/axp20x-i2c.c
 create mode 100644 drivers/mfd/axp20x-rsb.c

-- 
2.6.4

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[linux-sunxi] [PATCH v7 03/10] mfd: axp20x: use dev->driver->of_match_table in axp20x_match_device()

[Chen-Yu Tsai]

In axp20x_match_device(), match the of_device_id table bound to the
device driver instead of pointing to axp20x_of_match directly. This
will allow us to keep axp20x_match_device() unmodified when we expand
the axp20x driver into multiple ones covering different interface
types.

of_device_get_match_data() cannot be used here as we need to know if
it failed to get a match, or if the match data value just happened to
be 0, as it is for the AXP152.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
 drivers/mfd/axp20x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 685a78614f83..3e186f2dcac3 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -613,7 +613,7 @@ static int axp20x_match_device(struct axp20x_dev *axp20x)
const struct of_device_id *of_id;
 
if (dev->of_node) {
-   of_id = of_match_device(axp20x_of_match, dev);
+   of_id = of_match_device(dev->driver->of_match_table, dev);
if (!of_id) {
dev_err(dev, "Unable to match OF ID\n");
return -ENODEV;
-- 
2.6.4

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[linux-sunxi] [PATCH v7 02/10] mfd: axp20x: Remove second struct device * parameter for axp20x_match_device()

[Chen-Yu Tsai]

The first argument passed to axp20x_match_device(), struct axp20x_dev *,
already contains a pointer to the device. By rearranging some code,
moving the assignment of the pointer before axp20x_match_device() is
called, we can eliminate the second parameter.

Suggested-by: Andy Shevchenko <andy.shevche...@gmail.com>
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
 drivers/mfd/axp20x.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 9842199e2e6c..685a78614f83 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -606,8 +606,9 @@ static void axp20x_power_off(void)
 AXP20X_OFF);
 }
 
-static int axp20x_match_device(struct axp20x_dev *axp20x, struct device *dev)
+static int axp20x_match_device(struct axp20x_dev *axp20x)
 {
+   struct device *dev = axp20x->dev;
const struct acpi_device_id *acpi_id;
const struct of_device_id *of_id;
 
@@ -673,14 +674,14 @@ static int axp20x_i2c_probe(struct i2c_client *i2c,
if (!axp20x)
return -ENOMEM;
 
-   ret = axp20x_match_device(axp20x, >dev);
-   if (ret)
-   return ret;
-
axp20x->i2c_client = i2c;
axp20x->dev = >dev;
dev_set_drvdata(axp20x->dev, axp20x);
 
+   ret = axp20x_match_device(axp20x);
+   if (ret)
+   return ret;
+
axp20x->regmap = devm_regmap_init_i2c(i2c, axp20x->regmap_cfg);
if (IS_ERR(axp20x->regmap)) {
ret = PTR_ERR(axp20x->regmap);
-- 
2.6.4

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[linux-sunxi] [PATCH v7 08/10] regulator: axp20x: Support new AXP223 PMIC

[Chen-Yu Tsai]

The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Reviewed-by: Mark Brown <broo...@kernel.org>
---
 drivers/regulator/axp20x-regulator.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/regulator/axp20x-regulator.c 
b/drivers/regulator/axp20x-regulator.c
index 35de22fdb7a0..55cce8125716 100644
--- a/drivers/regulator/axp20x-regulator.c
+++ b/drivers/regulator/axp20x-regulator.c
@@ -244,6 +244,7 @@ static int axp20x_set_dcdc_freq(struct platform_device 
*pdev, u32 dcdcfreq)
step = 75;
break;
case AXP221_ID:
+   case AXP223_ID:
min = 1800;
max = 4050;
def = 3000;
@@ -322,6 +323,7 @@ static int axp20x_set_dcdc_workmode(struct regulator_dev 
*rdev, int id, u32 work
break;
 
case AXP221_ID:
+   case AXP223_ID:
if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
return -EINVAL;
 
@@ -360,6 +362,7 @@ static int axp20x_regulator_probe(struct platform_device 
*pdev)
nregulators = AXP20X_REG_ID_MAX;
break;
case AXP221_ID:
+   case AXP223_ID:
regulators = axp22x_regulators;
nregulators = AXP22X_REG_ID_MAX;
break;
-- 
2.6.4

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[linux-sunxi] [PATCH v7 07/10] mfd: axp20x: Add support for RSB based AXP223 PMIC

[Chen-Yu Tsai]

The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---

Changes since v6:

  - Drop filename from file header
  - Use generic dev_set_drvdata()
  - Properly sort #include statements
  - Add copyright notice

---
 drivers/mfd/Kconfig| 11 +++
 drivers/mfd/Makefile   |  1 +
 drivers/mfd/axp20x-rsb.c   | 80 ++
 drivers/mfd/axp20x.c   |  2 ++
 include/linux/mfd/axp20x.h |  1 +
 5 files changed, 95 insertions(+)
 create mode 100644 drivers/mfd/axp20x-rsb.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 804cd3dcce32..13c565103e96 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -107,6 +107,17 @@ config MFD_AXP20X_I2C
  components like regulators or the PEK (Power Enable Key) under the
  corresponding menus.
 
+config MFD_AXP20X_RSB
+   tristate "X-Powers AXP series PMICs with RSB"
+   select MFD_AXP20X
+   depends on SUNXI_RSB
+   help
+ If you say Y here you get support for the X-Powers AXP series power
+ management ICs (PMICs) controlled with RSB.
+ This driver include only the core APIs. You have to select individual
+ components like regulators or the PEK (Power Enable Key) under the
+ corresponding menus.
+
 config MFD_CROS_EC
tristate "ChromeOS Embedded Controller"
select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index a6913007d667..caea6637d5e8 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -108,6 +108,7 @@ obj-$(CONFIG_MFD_DA9052_SPI)+= da9052-spi.o
 obj-$(CONFIG_MFD_DA9052_I2C)   += da9052-i2c.o
 obj-$(CONFIG_MFD_AXP20X)   += axp20x.o
 obj-$(CONFIG_MFD_AXP20X_I2C)   += axp20x-i2c.o
+obj-$(CONFIG_MFD_AXP20X_RSB)   += axp20x-rsb.o
 
 obj-$(CONFIG_MFD_LP3943)   += lp3943.o
 obj-$(CONFIG_MFD_LP8788)   += lp8788.o lp8788-irq.o
diff --git a/drivers/mfd/axp20x-rsb.c b/drivers/mfd/axp20x-rsb.c
new file mode 100644
index ..28c20247c112
--- /dev/null
+++ b/drivers/mfd/axp20x-rsb.c
@@ -0,0 +1,80 @@
+/*
+ * RSB driver for the X-Powers' Power Management ICs
+ *
+ * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK 
DC-DC
+ * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
+ * as well as configurable GPIOs.
+ *
+ * This driver supports the RSB variants.
+ *
+ * Copyright (C) 2015 Chen-Yu Tsai
+ *
+ * Author: Chen-Yu Tsai <w...@csie.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static int axp20x_rsb_probe(struct sunxi_rsb_device *rdev)
+{
+   struct axp20x_dev *axp20x;
+   int ret;
+
+   axp20x = devm_kzalloc(>dev, sizeof(*axp20x), GFP_KERNEL);
+   if (!axp20x)
+   return -ENOMEM;
+
+   axp20x->dev = >dev;
+   axp20x->irq = rdev->irq;
+   dev_set_drvdata(>dev, axp20x);
+
+   ret = axp20x_match_device(axp20x);
+   if (ret)
+   return ret;
+
+   axp20x->regmap = devm_regmap_init_sunxi_rsb(rdev, axp20x->regmap_cfg);
+   if (IS_ERR(axp20x->regmap)) {
+   ret = PTR_ERR(axp20x->regmap);
+   dev_err(>dev, "regmap init failed: %d\n", ret);
+   return ret;
+   }
+
+   return axp20x_device_probe(axp20x);
+}
+
+static int axp20x_rsb_remove(struct sunxi_rsb_device *rdev)
+{
+   struct axp20x_dev *axp20x = sunxi_rsb_device_get_drvdata(rdev);
+
+   return axp20x_device_remove(axp20x);
+}
+
+static const struct of_device_id axp20x_rsb_of_match[] = {
+   { .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },
+   { },
+};
+MODULE_DEVICE_TABLE(of, axp20x_rsb_of_match);
+
+static struct sunxi_rsb_driver axp20x_rsb_driver = {
+   .driver = {
+   .name   = "axp20x-rsb",
+   .of_match_table = of_match_ptr(axp20x_rsb_of_match),
+   },
+   .probe  = axp20x_rsb_probe,
+   .remove = axp20x_rsb_remove,
+};
+module_sunxi_rsb_driver(axp20x_rsb_driver);
+
+MODULE_DESCRIPTION("PMIC MFD sunXi RSB driver for AXP20X");
+MODULE_AUTHOR("Chen-Yu Tsai <w...@csie.org>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 3054ea4b95e8..a57d6e940610 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -35,6 +35,7 @@ static const char * const axp20x_model_names[] = {
"AXP202",
"AXP209",
"AXP221",
+   &q

[linux-sunxi] [PATCH v7 06/10] mfd: axp20x: Whitespace, open parenthesis alignment code style fixes

[Chen-Yu Tsai]

This fixes some leftover code style issues in the axp20x core.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
 drivers/mfd/axp20x.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 8e569bcfe3bc..3054ea4b95e8 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -593,14 +593,14 @@ int axp20x_match_device(struct axp20x_dev *axp20x)
dev_err(dev, "Unable to match OF ID\n");
return -ENODEV;
}
-   axp20x->variant = (long) of_id->data;
+   axp20x->variant = (long)of_id->data;
} else {
acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
if (!acpi_id || !acpi_id->driver_data) {
dev_err(dev, "Unable to match ACPI ID and data\n");
return -ENODEV;
}
-   axp20x->variant = (long) acpi_id->driver_data;
+   axp20x->variant = (long)acpi_id->driver_data;
}
 
switch (axp20x->variant) {
@@ -634,7 +634,7 @@ int axp20x_match_device(struct axp20x_dev *axp20x)
return -EINVAL;
}
dev_info(dev, "AXP20x variant %s found\n",
-   axp20x_model_names[axp20x->variant]);
+axp20x_model_names[axp20x->variant]);
 
return 0;
 }
@@ -654,7 +654,7 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
}
 
ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
-   axp20x->nr_cells, NULL, 0, NULL);
+ axp20x->nr_cells, NULL, 0, NULL);
 
if (ret) {
dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret);
-- 
2.6.4

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[linux-sunxi] [PATCH v7 09/10] ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator nodes

[Chen-Yu Tsai]

This board has a X-Powers AXP223 PMIC connected via RSB. Its regulators
provide power to various parts of the SoC and the board.

Also update the regulator supply phandles.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 76 +-
 1 file changed, 73 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts 
b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
index 13ce68f06dd6..8af38a9719ca 100644
--- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
@@ -68,7 +68,7 @@
 };
 
  {
-   vref-supply = <_vcc3v0>;
+   vref-supply = <_dcdc1>;
status = "okay";
 
button@200 {
@@ -96,7 +96,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin_sina33>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <4>;
cd-gpios = < 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
cd-inverted;
@@ -106,7 +106,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_8bit_pins>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <8>;
non-removable;
status = "okay";
@@ -132,6 +132,76 @@
 
 _rsb {
status = "okay";
+
+   axp22x: pmic@3a3 {
+   compatible = "x-powers,axp223";
+   reg = <0x3a3>;
+   interrupt-parent = <_intc>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   eldoin-supply = <_dcdc1>;
+   };
+};
+
+#include "axp22x.dtsi"
+
+_aldo1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-io";
+};
+
+_aldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <235>;
+   regulator-max-microvolt = <265>;
+   regulator-name = "vdd-dll";
+};
+
+_aldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <270>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pll-avcc";
+};
+
+_dc5ldo {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpus";
+};
+
+_dcdc1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-3v0";
+};
+
+_dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-sys";
+};
+
+_dcdc3 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpu";
+};
+
+_dcdc5 {
+   regulator-always-on;
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <150>;
+   regulator-name = "vcc-dram";
+};
+
+_rtc_ldo {
+   regulator-name = "vcc-rtc";
 };
 
  {
-- 
2.6.4

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[linux-sunxi] [PATCH v7 10/10] ARM: dts: sun8i: q8-common: Add AXP223 PMIC device and regulator nodes

[Chen-Yu Tsai]

A23/A33 Q8 tablets have an X-Powers AXP223 PMIC connected via RSB. Its
regulators provide power to various parts of the SoC and the board.

Also add lcd regulator supply for simplefb and update the existing
vmmc-supply for mmc0.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-q8-common.dtsi | 83 +-
 1 file changed, 81 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi 
b/arch/arm/boot/dts/sun8i-q8-common.dtsi
index 1a69231d2da5..9d2b7e2f5975 100644
--- a/arch/arm/boot/dts/sun8i-q8-common.dtsi
+++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi
@@ -56,7 +56,6 @@
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
enable-gpios = < 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
-   /* backlight is powered by AXP223 DC1SW */
};
 
chosen {
@@ -67,7 +66,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin_q8>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <4>;
cd-gpios = < 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
cd-inverted;
@@ -92,6 +91,82 @@
 
 _rsb {
status = "okay";
+
+   axp22x: pmic@3a3 {
+   compatible = "x-powers,axp223";
+   reg = <0x3a3>;
+   interrupt-parent = <_intc>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   eldoin-supply = <_dcdc1>;
+   };
+};
+
+#include "axp22x.dtsi"
+
+_aldo1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-io";
+};
+
+_aldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <235>;
+   regulator-max-microvolt = <265>;
+   regulator-name = "vdd-dll";
+};
+
+_aldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <270>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pll-avcc";
+};
+
+_dc1sw {
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-lcd";
+};
+
+_dc5ldo {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpus";
+};
+
+_dcdc1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-3v0";
+};
+
+_dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-sys";
+};
+
+_dcdc3 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpu";
+};
+
+_dcdc5 {
+   regulator-always-on;
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <150>;
+   regulator-name = "vcc-dram";
+};
+
+_rtc_ldo {
+   regulator-name = "vcc-rtc";
 };
 
 _uart {
@@ -99,3 +174,7 @@
pinctrl-0 = <_uart_pins_a>;
status = "okay";
 };
+
+_lcd {
+   vcc-lcd-supply = <_dc1sw>;
+};
-- 
2.6.4

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[linux-sunxi] [PATCH 5/5] sunxi: power: axp818: Enable support for ALDOs

[Chen-Yu Tsai]

Previously, AXP818 ALDO support was partially added to Kconfig, but
never enabled in the board file, nor properly set or configured in
Kconfig. The boards continue to work because the AXP818 is designed
to pair with the A83T/H8, and the default voltages match the reference
design's requirements.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 board/sunxi/board.c|  8 +++-
 drivers/power/Kconfig  | 13 ++---
 drivers/power/axp818.c | 37 +
 3 files changed, 50 insertions(+), 8 deletions(-)

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 85f01fd..e0ff650 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -446,20 +446,18 @@ void sunxi_board_init(void)
power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
 #endif
 
-#ifdef CONFIG_AXP221_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
 #endif
-#ifndef CONFIG_AXP818_POWER
power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
-#endif
-#if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP818_POWER)
+#if !defined(CONFIG_AXP152_POWER)
power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
 #endif
 #ifdef CONFIG_AXP209_POWER
power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
 #endif
 
-#ifdef CONFIG_AXP221_POWER
+#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP818_POWER)
power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 6f61763..e91a5c0 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -118,20 +118,24 @@ config AXP_DCDC5_VOLT
 
 config AXP_ALDO1_VOLT
int "axp pmic (a)ldo1 voltage"
-   depends on AXP221_POWER
+   depends on AXP221_POWER || AXP818_POWER
default 0 if MACH_SUN6I
+   default 1800 if MACH_SUN8I_A83T
default 3000 if MACH_SUN8I
---help---
Set the voltage (mV) to program the axp pmic aldo1 at, set to 0 to
disable aldo1.
On A31 boards aldo1 is often used to power the wifi module.
On A23 / A33 boards aldo1 is used for VCC-IO and should be 3.0V.
+   On A83T / H8 boards aldo1 is used for MIPI CSI, DSI, HDMI, EFUSE, and
+   should be 1.8V.
 
 config AXP_ALDO2_VOLT
int "axp pmic (a)ldo2 voltage"
depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER
default 3000 if AXP152_POWER || AXP209_POWER
default 0 if MACH_SUN6I
+   default 1800 if MACH_SUN8I_A83T
default 2500 if MACH_SUN8I
---help---
Set the voltage (mV) to program the axp pmic aldo2 at, set to 0 to
@@ -140,18 +144,21 @@ config AXP_ALDO2_VOLT
On A31 boards aldo2 is typically unused and should be disabled.
On A31 boards aldo2 may be used for LPDDR2 then it should be 1.8V.
On A23 / A33 boards aldo2 is used for VDD-DLL and should be 2.5V.
+   On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC,
+   LPDDR2, and the codec. It should be 1.8V.
 
 config AXP_ALDO3_VOLT
int "axp pmic (a)ldo3 voltage"
depends on AXP209_POWER || AXP221_POWER || AXP818_POWER
-   default 0 if AXP209_POWER || AXP818_POWER
+   default 0 if AXP209_POWER
default 3000 if MACH_SUN6I || MACH_SUN8I
---help---
Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to
disable aldo3.
On A10(s) / A13 / A20 boards aldo3 should be 2.8V.
On A23 / A31 / A33 boards aldo3 is VCC-PLL and AVCC and should be 3.0V.
-   On A83T aldo3 is used for LVDS, DSI, MIPI, HDMI, etc.
+   On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be
+   3.0V.
 
 config AXP_ALDO4_VOLT
int "axp pmic (a)ldo4 voltage"
diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c
index 3119b64..e885d02 100644
--- a/drivers/power/axp818.c
+++ b/drivers/power/axp818.c
@@ -110,6 +110,43 @@ int axp_set_dcdc5(unsigned int mvolt)
AXP818_OUTPUT_CTRL1_DCDC5_EN);
 }
 
+int axp_set_aldo(int aldo_num, unsigned int mvolt)
+{
+   int ret;
+   u8 cfg;
+
+   if (aldo_num < 1 || aldo_num > 3)
+   return -EINVAL;
+
+   if (mvolt == 0)
+   return pmic_bus_clrbits(AXP818_OUTPUT_CTRL3,
+   AXP818_OUTPUT_CTRL3_ALDO1_EN << (aldo_num - 1));
+
+   cfg = axp818_mvolt_to_cfg(mvolt, 700, 3300, 100);
+   ret = pmic_bus_write(AXP818_ALDO1_CTRL + (aldo_num - 1), cfg);
+   if (ret)
+   return ret;
+
+   return pmic_bus_setbits(AXP818_OUTPUT_CTRL3,
+   AXP818_OUTPUT_CTRL3_ALDO1_EN << (aldo_num - 1));
+}
+
+/* TODO: re-work other AXP drivers

[linux-sunxi] [PATCH 3/5] power: axp818: Add support for DLDO and ELDO regulators

[Chen-Yu Tsai]

AXP818 provides an array of LDOs to provide power to various peripherals.
None of these regulators are critical.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/power/Kconfig  | 12 ++--
 drivers/power/axp818.c | 44 
 2 files changed, 50 insertions(+), 6 deletions(-)

diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index e86dd72..6f61763 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -164,7 +164,7 @@ config AXP_ALDO4_VOLT
 
 config AXP_DLDO1_VOLT
int "axp pmic dldo1 voltage"
-   depends on AXP221_POWER
+   depends on AXP221_POWER || AXP818_POWER
default 0
---help---
Set the voltage (mV) to program the axp pmic dldo1 at, set to 0 to
@@ -174,7 +174,7 @@ config AXP_DLDO1_VOLT
 
 config AXP_DLDO2_VOLT
int "axp pmic dldo2 voltage"
-   depends on AXP221_POWER
+   depends on AXP221_POWER || AXP818_POWER
default 0
---help---
Set the voltage (mV) to program the axp pmic dldo2 at, set to 0 to
@@ -182,7 +182,7 @@ config AXP_DLDO2_VOLT
 
 config AXP_DLDO3_VOLT
int "axp pmic dldo3 voltage"
-   depends on AXP221_POWER
+   depends on AXP221_POWER || AXP818_POWER
default 0
---help---
Set the voltage (mV) to program the axp pmic dldo3 at, set to 0 to
@@ -198,7 +198,7 @@ config AXP_DLDO4_VOLT
 
 config AXP_ELDO1_VOLT
int "axp pmic eldo1 voltage"
-   depends on AXP221_POWER
+   depends on AXP221_POWER || AXP818_POWER
default 0
---help---
Set the voltage (mV) to program the axp pmic eldo1 at, set to 0 to
@@ -206,7 +206,7 @@ config AXP_ELDO1_VOLT
 
 config AXP_ELDO2_VOLT
int "axp pmic eldo2 voltage"
-   depends on AXP221_POWER
+   depends on AXP221_POWER || AXP818_POWER
default 0
---help---
Set the voltage (mV) to program the axp pmic eldo2 at, set to 0 to
@@ -214,7 +214,7 @@ config AXP_ELDO2_VOLT
 
 config AXP_ELDO3_VOLT
int "axp pmic eldo3 voltage"
-   depends on AXP221_POWER
+   depends on AXP221_POWER || AXP818_POWER
default 0
---help---
Set the voltage (mV) to program the axp pmic eldo3 at, set to 0 to
diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c
index 4b21a83..3119b64 100644
--- a/drivers/power/axp818.c
+++ b/drivers/power/axp818.c
@@ -110,6 +110,50 @@ int axp_set_dcdc5(unsigned int mvolt)
AXP818_OUTPUT_CTRL1_DCDC5_EN);
 }
 
+int axp_set_dldo(int dldo_num, unsigned int mvolt)
+{
+   int ret;
+   u8 cfg;
+
+   if (dldo_num < 1 || dldo_num > 4)
+   return -EINVAL;
+
+   if (mvolt == 0)
+   return pmic_bus_clrbits(AXP818_OUTPUT_CTRL2,
+   AXP818_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1));
+
+   cfg = axp818_mvolt_to_cfg(mvolt, 700, 3300, 100);
+   if (dldo_num == 2 && mvolt > 3300)
+   cfg += 1 + axp818_mvolt_to_cfg(mvolt, 3400, 4200, 200);
+   ret = pmic_bus_write(AXP818_ELDO1_CTRL + (dldo_num - 1), cfg);
+   if (ret)
+   return ret;
+
+   return pmic_bus_setbits(AXP818_OUTPUT_CTRL2,
+   AXP818_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1));
+}
+
+int axp_set_eldo(int eldo_num, unsigned int mvolt)
+{
+   int ret;
+   u8 cfg;
+
+   if (eldo_num < 1 || eldo_num > 3)
+   return -EINVAL;
+
+   if (mvolt == 0)
+   return pmic_bus_clrbits(AXP818_OUTPUT_CTRL2,
+   AXP818_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
+
+   cfg = axp818_mvolt_to_cfg(mvolt, 700, 1900, 50);
+   ret = pmic_bus_write(AXP818_ELDO1_CTRL + (eldo_num - 1), cfg);
+   if (ret)
+   return ret;
+
+   return pmic_bus_setbits(AXP818_OUTPUT_CTRL2,
+   AXP818_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
+}
+
 int axp_init(void)
 {
u8 axp_chip_id;
-- 
2.6.4

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[linux-sunxi] [PATCH 1/5] power: axp818: Remove duplicate register definition macros

[Chen-Yu Tsai]

Some of the register definitions are duplicated. Drop them.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 include/axp818.h | 8 
 1 file changed, 8 deletions(-)

diff --git a/include/axp818.h b/include/axp818.h
index 1dc6456..46d05ad 100644
--- a/include/axp818.h
+++ b/include/axp818.h
@@ -32,13 +32,6 @@
 #define AXP818_OUTPUT_CTRL3_ALDO2_EN   (1 << 6)
 #define AXP818_OUTPUT_CTRL3_ALDO3_EN   (1 << 7)
 
-#define AXP818_DCDC1_CTRL  0x20
-#define AXP818_DCDC2_CTRL  0x21
-#define AXP818_DCDC3_CTRL  0x22
-#define AXP818_DCDC4_CTRL  0x23
-#define AXP818_DCDC5_CTRL  0x24
-#define AXP818_DCDC6_CTRL  0x25
-
 #define AXP818_DLDO1_CTRL  0x15
 #define AXP818_DLDO2_CTRL  0x16
 #define AXP818_DLDO3_CTRL  0x17
@@ -46,7 +39,6 @@
 #define AXP818_ELDO1_CTRL  0x19
 #define AXP818_ELDO2_CTRL  0x1a
 #define AXP818_ELDO3_CTRL  0x1b
-#define AXP818_ELDO3_CTRL  0x1b
 #define AXP818_FLDO1_CTRL  0x1c
 #define AXP818_FLDO2_3_CTRL0x1d
 #define AXP818_DCDC1_CTRL  0x20
-- 
2.6.4

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[linux-sunxi] Re: [PATCH v6 4/9] mfd: axp20x: Split the driver into core and i2c bits

[Chen-Yu Tsai]

Hi,

On Mon, Jan 11, 2016 at 5:25 PM, Lee Jones <lee.jo...@linaro.org> wrote:
> On Thu, 17 Dec 2015, Chen-Yu Tsai wrote:
>
>> The axp20x driver assumes the device is i2c based. This is not the
>> case with later chips, which use a proprietary 2 wire serial bus
>> by Allwinner called "Reduced Serial Bus".
>>
>> This patch follows the example of mfd/wm831x and splits it into
>> an interface independent core, and an i2c specific glue layer.
>> MFD_AXP20X and the new MFD_AXP20X_I2C are changed to tristate
>> symbols, allowing the driver to be built as modules.
>>
>> Whitespace and other style errors in the moved i2c specific code
>> have been fixed. Included but unused header files are removed as
>> well.
>>
>> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
>> ---
>>  drivers/mfd/Kconfig|  14 ---
>>  drivers/mfd/Makefile   |   1 +
>>  drivers/mfd/axp20x-i2c.c   | 102 
>> +
>>  drivers/mfd/axp20x.c   |  88 +++---
>>  include/linux/mfd/axp20x.h |  33 ++-
>>  5 files changed, 158 insertions(+), 80 deletions(-)
>>  create mode 100644 drivers/mfd/axp20x-i2c.c
>
> Acked-by: Lee Jones <lee.jo...@linaro.org>
>

[..]

>> diff --git a/drivers/mfd/axp20x-i2c.c b/drivers/mfd/axp20x-i2c.c
>> new file mode 100644
>> index ..b54205677bb2
>> --- /dev/null
>> +++ b/drivers/mfd/axp20x-i2c.c
>> @@ -0,0 +1,102 @@
>> +/*
>> + * axp20x-i2c.c - I2C driver for the X-Powers' Power Management ICs

Do you want me to remove the filenames from these 2 files (axp20x.c and
axp20x-i2c.c) as well?

>> + *
>> + * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK 
>> DC-DC
>> + * converters, LDOs, multiple 12-bit ADCs of voltage, current and 
>> temperature
>> + * as well as configurable GPIOs.
>> + *
>> + * This driver supports the I2C variants.
>> + *
>> + * Author: Carlo Caione <ca...@caione.org>

Not sure about the copyright, since it's not mine.

>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +

[..]

Regards
ChenYu

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Re: [linux-sunxi] Re: Sunxi boards for KernelCI?

[Chen-Yu Tsai]

On Tue, Jan 12, 2016 at 10:08 PM, Benjamin Henrion  wrote:
> On Tue, Jan 12, 2016 at 3:05 PM, Benjamin Henrion  wrote:
>> Looking at fosdem talks, I found this project:
>>
>> https://fosdem.org/2016/schedule/event/kernelci/
>> http://kernelci.org/soc/sunxi/
>>
>> If you have spare boards...
>
> They seem to use TFTP to load their kernels:
>
> http://storage.kernelci.org/next/next-20160112/arm-multi_v7_defconfig/lab-tbaker/boot-sun7i-a20-bananapi.html
>
> Which might be problematic for boards that do not have ethernet...

At least for the A80 they use android fastboot.

ChenYu

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[linux-sunxi] Re: [PATCH] mmc: sunxi: Add support to the Allwinner A83T

[Chen-Yu Tsai]

Hi,

On Sat, Jun 4, 2016 at 6:01 PM, Jean-Francois Moine  wrote:
> The A83T has different clock delays.
> The values have been adapted from the Banana Pi M3 driver.
>
> Signed-off-by: Jean-Francois Moine 
> ---
>  Documentation/devicetree/bindings/mmc/sunxi-mmc.txt |  3 ++-
>  drivers/mmc/host/sunxi-mmc.c| 12 +++-
>  2 files changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt 
> b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> index 4bf41d8..45b8520 100644
> --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> +++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> @@ -8,7 +8,8 @@ as the speed of SD standard 3.0.
>  Absolute maximum transfer rate is 200MB/s
>
>  Required properties:
> - - compatible : "allwinner,sun4i-a10-mmc" or "allwinner,sun5i-a13-mmc"
> + - compatible : "allwinner,sun4i-a10-mmc", "allwinner,sun5i-a13-mmc",
> +   "allwinner,sun8i-a83t-mmc" or "allwinner,sun9i-a80-mmc"
>   - reg : mmc controller base registers
>   - clocks : a list with 4 phandle + clock specifier pairs
>   - clock-names : must contain "ahb", "mmc", "output" and "sample"
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index 7fc8b7a..707e705 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -941,6 +941,7 @@ static int sunxi_mmc_card_busy(struct mmc_host *mmc)
>  static const struct of_device_id sunxi_mmc_of_match[] = {
> { .compatible = "allwinner,sun4i-a10-mmc", },
> { .compatible = "allwinner,sun5i-a13-mmc", },
> +   { .compatible = "allwinner,sun8i-a83t-mmc", },
> { .compatible = "allwinner,sun9i-a80-mmc", },
> { /* sentinel */ }
>  };
> @@ -962,10 +963,17 @@ static const struct sunxi_mmc_clk_delay 
> sunxi_mmc_clk_delays[] = {
> [SDXC_CLK_25M]  = { .output = 180, .sample =  75 },
> [SDXC_CLK_50M]  = { .output =  90, .sample = 120 },
> [SDXC_CLK_50M_DDR]  = { .output =  60, .sample = 120 },
> -   /* Value from A83T "new timing mode". Works but might not be right. */

Please don't remove this. It was how I found a working value. Until we figure
out an actual correct value, the warning should stay there.

> [SDXC_CLK_50M_DDR_8BIT] = { .output =  90, .sample = 180 },
>  };
>
> +static const struct sunxi_mmc_clk_delay sun8i_a83t_mmc_clk_delays[] = {
> +   [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
> +   [SDXC_CLK_25M]  = { .output = 180, .sample =  50 },
> +   [SDXC_CLK_50M]  = { .output =  60, .sample =  50 },

These 2 don't look right.

> +   [SDXC_CLK_50M_DDR]  = { .output =  180, .sample = 90 },
> +   [SDXC_CLK_50M_DDR_8BIT] = { .output =  180, .sample = 90 },

Nor does this one. As explained in the comment from the clock driver:

We can only outphase the clocks by multiple of the PLL's period.

Since the MMC clock in only a divider, and the formula to get the
outphasing in degrees is deg = 360 * delta / period

Now, for the fishy ones I mentioned, MMC clock = card clock (or card * 2
for DDR 8 bit), and parent clock is PLL6 @ 600 MHz. A step would be 15,
30 or 60 degrees. Thus you cannot get an outphasing of 50 degrees, or 90
degrees for 50M DDR 8bit.

Could you provide a link to the original driver? Or perhaps just the
original delay values?

The values do work better on my Cubietruck plus, giving a throughput
of 36 MB/s read, instead of 17 MB/s with the original values. However
that is still only half of what it should be capable of. I will test
my BPI M3 tomorrow.


Regards
ChenYu

> +};
> +
>  static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
> [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
> [SDXC_CLK_25M]  = { .output = 180, .sample =  75 },
> @@ -987,6 +995,8 @@ static int sunxi_mmc_resource_request(struct 
> sunxi_mmc_host *host,
>
> if (of_device_is_compatible(np, "allwinner,sun9i-a80-mmc"))
> host->clk_delays = sun9i_mmc_clk_delays;
> +   else if (of_device_is_compatible(np, "allwinner,sun8i-a83t-mmc"))
> +   host->clk_delays = sun8i_a83t_mmc_clk_delays;
> else
> host->clk_delays = sunxi_mmc_clk_delays;
>
> --
> 2.8.3
>

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Re: [linux-sunxi] Re: [PATCH RFC 1/2] clk: sunxi-ng: Add the A83T and A80 PLL clocks

[Chen-Yu Tsai]

Hi,

On Fri, Jun 3, 2016 at 7:16 PM, Jean-Francois Moine <moin...@free.fr> wrote:
> Hi Wens,
>
> Thanks for the review.
>
> On Fri, 3 Jun 2016 14:53:24 +0800
> Chen-Yu Tsai <w...@csie.org> wrote:
>
>> On Tue, May 31, 2016 at 3:26 PM, Jean-Francois Moine <moin...@free.fr> wrote:
>> > The A83T and A80 SoCs have unique settings of their PLL clocks.
>> >
>> > Signed-off-by: Jean-Francois Moine <moin...@free.fr>
>> > ---
>> >  drivers/clk/sunxi-ng/ccu_ndmp.c | 247 
>> > 
>> >  drivers/clk/sunxi-ng/ccu_ndmp.h |  45 
>> >  2 files changed, 292 insertions(+)
>> >  create mode 100644 drivers/clk/sunxi-ng/ccu_ndmp.c
>> >  create mode 100644 drivers/clk/sunxi-ng/ccu_ndmp.h
>> >
>> > diff --git a/drivers/clk/sunxi-ng/ccu_ndmp.c 
>> > b/drivers/clk/sunxi-ng/ccu_ndmp.c
>> > new file mode 100644
>> > index 000..079b155
>> > --- /dev/null
>> > +++ b/drivers/clk/sunxi-ng/ccu_ndmp.c
>> > @@ -0,0 +1,247 @@
>> > +/*
>> > + * PLL clocks of sun8iw6 (A83T) and sun9iw1 (A80)
>> > + *
>> > + * Copyright (c) 2016 Jean-Francois Moine <moin...@free.fr>
>> > + *
>> > + * This program is free software; you can redistribute it and/or
>> > + * modify it under the terms of the GNU General Public License as
>> > + * published by the Free Software Foundation; either version 2 of
>> > + * the License, or (at your option) any later version.
>> > + *
>> > + * The clock rates are computed as:
>> > + * rate = parent_rate / d1 * n / d2 / m >> p
>> > + */
>> > +
>> > +#include 
>> > +#include 
>> > +#include 
>> > +
>> > +#include "ccu_gate.h"
>> > +#include "ccu_ndmp.h"
> [snip]
>> > +/* d1 and d2 may be only 1 or 2 */
>> > +static int ccu_ndmp_get_fact(struct ccu_ndmp *ndmp,
>> > +   unsigned long rate, unsigned long prate,
>> > +   int *p_n, int *p_d1, int *p_d2, int *p_m, int *p_p)
>> > +{
>> > +   int n, d1, d2, m, p, d;
>> > +   unsigned long t;
>> > +
>> > +   /* m implies only n, d1, d2 and m (pll-audio) */
>> > +   /* Setting d1=1 and d2=2 keeps n and m small enough
>> > +*  with error < 5/1 */
>> > +   /* As only 2 rates are used, this could be simplified:
>>
>> Best not simplify generic code to specific use cases.
>
> Well, the Allwinner's audio PLL clocks always ask for these 2 rates only.
> Anyway, this is just a comment.
>
>> > +*  22579200Hz => n = 32, m = 17
>> > +*  24576000Hz => n = 43, m = 21
>> > +*/
>> > +   if (ndmp->m.shift) {
>>
>> shift could be 0. Testing against width is better.
>> Same for the other functions.
>
> Yes. I fixed this already, with some other bugs.
>
>> > +   long unsigned int lun, lum;
>>
>>   unsigned long, to match other places.
>>
>> > +
>> > +   d1 = 0 + 1;
>> > +   d2 = 1 + 1;
>> > +   t = prate / 2;
>> > +   rational_best_approximation(rate, t,
>> > +   1 << ndmp->n.width,
>> > +   1 << ndmp->m.width,
>> > +   , );
>> > +   if (lum == 0)
>> > +   return -EINVAL;
>> > +   n = lun;
>> > +   m = lum;
>> > +   p = 0;
>> > +
>> > +   /* no d1 implies n alone (pll-cxcpux) */
>>
>> Pretending these don't have a p factor does not make it disappear.
>>
>> > +   } else if (!ndmp->d1.shift) {
>> > +   d1 = d2 = 0 + 1;
>>
>> If you say they aren't there, why do you still need to set them.
>>
>> > +   n = rate / prate;
>> > +   m = 1;
>> > +   p = 0;
>>
>> A note about why p isn't used would be nice. Like:
>>
>> P should only be used for rates under 288 MHz.
>>
>> from the manual.
>
> Yes.
>
>> > +
>> > +   /* p implies only n, d1 and p (pll-videox) */
>> > +   } else if (ndmp->m.shift) {
>>
>>^ p?
>
> Yes. Already fixed.
&g

[linux-sunxi] Re: [PATCH RFC 1/2] clk: sunxi-ng: Add the A83T and A80 PLL clocks

[Chen-Yu Tsai]

Hi,

On Tue, May 31, 2016 at 3:26 PM, Jean-Francois Moine  wrote:
> The A83T and A80 SoCs have unique settings of their PLL clocks.
>
> Signed-off-by: Jean-Francois Moine 
> ---
>  drivers/clk/sunxi-ng/ccu_ndmp.c | 247 
> 
>  drivers/clk/sunxi-ng/ccu_ndmp.h |  45 
>  2 files changed, 292 insertions(+)
>  create mode 100644 drivers/clk/sunxi-ng/ccu_ndmp.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu_ndmp.h
>
> diff --git a/drivers/clk/sunxi-ng/ccu_ndmp.c b/drivers/clk/sunxi-ng/ccu_ndmp.c
> new file mode 100644
> index 000..079b155
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu_ndmp.c
> @@ -0,0 +1,247 @@
> +/*
> + * PLL clocks of sun8iw6 (A83T) and sun9iw1 (A80)
> + *
> + * Copyright (c) 2016 Jean-Francois Moine 
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * The clock rates are computed as:
> + * rate = parent_rate / d1 * n / d2 / m >> p
> + */
> +
> +#include 
> +#include 
> +#include 
> +
> +#include "ccu_gate.h"
> +#include "ccu_ndmp.h"
> +
> +static void ccu_ndmp_disable(struct clk_hw *hw)
> +{
> +   struct ccu_ndmp *ndmp = hw_to_ccu_ndmp(hw);
> +
> +   return ccu_gate_helper_disable(>common, ndmp->enable);
> +}
> +
> +static int ccu_ndmp_enable(struct clk_hw *hw)
> +{
> +   struct ccu_ndmp *ndmp = hw_to_ccu_ndmp(hw);
> +
> +   return ccu_gate_helper_enable(>common, ndmp->enable);
> +}
> +
> +static int ccu_ndmp_is_enabled(struct clk_hw *hw)
> +{
> +   struct ccu_ndmp *ndmp = hw_to_ccu_ndmp(hw);
> +
> +   return ccu_gate_helper_is_enabled(>common, ndmp->enable);
> +}
> +
> +static unsigned long ccu_ndmp_recalc_rate(struct clk_hw *hw,
> +   unsigned long parent_rate)
> +{
> +   struct ccu_ndmp *ndmp = hw_to_ccu_ndmp(hw);
> +   int n, d1, d2, m, p;
> +   unsigned long rate;
> +   u32 reg;
> +
> +   reg = readl(ndmp->common.base + ndmp->common.reg);
> +
> +   rate = parent_rate;
> +
> +   if (ndmp->d1.shift) {
> +   d1 = reg >> ndmp->d1.shift;
> +   d1 &= (1 << ndmp->d1.width) - 1;
> +   rate /= (d1 + 1);
> +   }
> +
> +   n = reg >> ndmp->n.shift;
> +   n &= (1 << ndmp->n.width) - 1;
> +   if (!(ndmp->common.features & CCU_FEATURE_N0))
> +   n++;
> +   rate *= n;
> +
> +   if (ndmp->d2.shift) {
> +   d2 = reg >> ndmp->d2.shift;
> +   d2 &= (1 << ndmp->d2.width) - 1;
> +   rate /= (d2 + 1);
> +   }
> +
> +   if (ndmp->m.shift) {
> +   m = reg >> ndmp->m.shift;
> +   m &= (1 << ndmp->m.width) - 1;
> +   rate /= (m + 1);
> +   }
> +
> +   if (ndmp->p.shift) {
> +   p = reg >> ndmp->p.shift;
> +   p &= (1 << ndmp->p.width) - 1;
> +   rate >>= p;
> +   }
> +
> +   return rate;
> +}
> +
> +/* d1 and d2 may be only 1 or 2 */
> +static int ccu_ndmp_get_fact(struct ccu_ndmp *ndmp,
> +   unsigned long rate, unsigned long prate,
> +   int *p_n, int *p_d1, int *p_d2, int *p_m, int *p_p)
> +{
> +   int n, d1, d2, m, p, d;
> +   unsigned long t;
> +
> +   /* m implies only n, d1, d2 and m (pll-audio) */
> +   /* Setting d1=1 and d2=2 keeps n and m small enough
> +*  with error < 5/1 */
> +   /* As only 2 rates are used, this could be simplified:

Best not simplify generic code to specific use cases.

> +*  22579200Hz => n = 32, m = 17
> +*  24576000Hz => n = 43, m = 21
> +*/
> +   if (ndmp->m.shift) {

shift could be 0. Testing against width is better.
Same for the other functions.

> +   long unsigned int lun, lum;

  unsigned long, to match other places.

> +
> +   d1 = 0 + 1;
> +   d2 = 1 + 1;
> +   t = prate / 2;
> +   rational_best_approximation(rate, t,
> +   1 << ndmp->n.width,
> +   1 << ndmp->m.width,
> +   , );
> +   if (lum == 0)
> +   return -EINVAL;
> +   n = lun;
> +   m = lum;
> +   p = 0;
> +
> +   /* no d1 implies n alone (pll-cxcpux) */

Pretending these don't have a p factor does not make it disappear.

> +   } else if (!ndmp->d1.shift) {
> +   d1 = d2 = 0 + 1;

If you say they aren't there, why do you still need to set them.

> +   n = rate / prate;
> +   m = 1;
> +   p = 0;

A note about why p isn't used would be nice. Like:

P should only be used for 

[linux-sunxi] Re: [PATCH 3/5] ARM: sun8i: dt: Add DT bindings documentation for Allwinner sun8i-emac

[Chen-Yu Tsai]

Hi Rob,

On Thu, Jun 9, 2016 at 3:11 AM, Rob Herring  wrote:
> On Mon, Jun 06, 2016 at 08:10:54PM +0200, Corentin LABBE wrote:
>> Le 06/06/2016 16:14, Rob Herring a écrit :
>> > On Fri, Jun 03, 2016 at 11:56:28AM +0200, LABBE Corentin wrote:
>> >> This patch adds documentation for Device-Tree bindings for the
>> >> Allwinner sun8i-emac driver.
>> >>
>> >> Signed-off-by: LABBE Corentin 
>> >> ---
>> >>  .../bindings/net/allwinner,sun8i-emac.txt  | 64 
>> >> ++
>> >>  1 file changed, 64 insertions(+)
>> >>  create mode 100644 
>> >> Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt
>> >>
>> >> diff --git 
>> >> a/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt 
>> >> b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt
>> >> new file mode 100644
>> >> index 000..cf71a71
>> >> --- /dev/null
>> >> +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt
>> >> @@ -0,0 +1,64 @@
>> >> +* Allwinner sun8i EMAC ethernet controller
>> >> +
>> >> +Required properties:
>> >> +- compatible: "allwinner,sun8i-a83t-emac", "allwinner,sun8i-h3-emac",
>> >> +  or "allwinner,sun50i-a64-emac"
>> >> +- reg: address and length of the register sets for the device.
>> >> +- reg-names: should be "emac" and "syscon", matching the register sets
>> >
>> > Is syscon shared with other devices? Your example only has 1 reg
>> > address.
>> >
>>
>> The example is bad, emac and syscon are two distinct regspaces.
>> I will correct the example.
>
> And the syscon registers are not shared with anything else? Typically,
> syscon registers would be a separate node not part of this blocks
> registers. The main thing is make sure you are not creating overlapping
> register addresses.

These syscon registers are in a separate address range, like a glue layer
over the underlying EMAC hardware. There are only 2 registers defined in
that address range, and this particular one is used only for EMAC related
controls.

The other register is not used anywhere in the kernel. It's a readonly
register that gives the SoC revision. IIRC there was some work to add
per-platform functions to support this, but we haven't the need to use
it yet.

Hope this clears things up.

Regards
ChenYu

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[linux-sunxi] Re: [PATCH] ARM: dts: sun7i: Add dts file for Bananapi M1 Plus board

[Chen-Yu Tsai]

Hi,

On Tue, May 31, 2016 at 3:43 AM, Maxime Ripard
 wrote:
> Hi,
>
> On Mon, May 30, 2016 at 08:30:13PM +0800, luoyi...@gmail.com wrote:
>> From: luoyi 
>>
>> Add support for the Bananapi M1 Plus A20 development board from 
>> sinovoip.com.cn .
>> This board features 1G RAM, 2 USB A receptacles, 1 micro USB receptacle for
>> OTG, 1 micro USB receptacle for power, HDMI, sata, Gbit ethernet, ir 
>> receiver,
>> 3.5 mm jack for stero sound out, on board microphone, 40 gpio pins and sdio 
>> wifi.
>
> What is the difference between the M1+ and the M1?
>
>>
>> Signed-off-by: Luo Yi 
>> ---
>>  arch/arm/boot/dts/Makefile   |   1 +
>>  arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 270 
>> +++
>>  2 files changed, 271 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index e06a5ab..fde407f 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -685,6 +685,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
>>   sun6i-a31s-yones-toptech-bs1078-v2.dtb
>>  dtb-$(CONFIG_MACH_SUN7I) += \
>>   sun7i-a20-bananapi.dtb \
>> + sun7i-a20-bananapi-m1-plus.dtb \
>>   sun7i-a20-bananapro.dtb \
>>   sun7i-a20-cubieboard2.dtb \
>>   sun7i-a20-cubietruck.dtb \
>> diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts 
>> b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
>> new file mode 100644
>> index 000..b62fc1d
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
>> @@ -0,0 +1,270 @@
>> +/*
>> + * Copyright 2016 Luo Yi 
>> + *
>> + * Thanks to the original work by Hans de Goede 
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +/dts-v1/;
>> +#include "sun7i-a20.dtsi"
>> +#include "sunxi-common-regulators.dtsi"
>> +#include 
>> +#include 
>> +
>> +/ {
>> + model = "Banana Pi BPI-M1-Plus";
>> + compatible = "sinovoip,bpi-m1-plus", "allwinner,sun7i-a20";
>> +
>> + aliases {
>> + serial0 = 
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + leds {
>> + compatible = "gpio-leds";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <_pins_bananapi>;
>> +
>> + red {
>> + label = "bananapi:red:usr";
>
> The first part the label is the board name, in that case that would be
> bananapi-m1-plus.
>
>> + gpios = < 7 25 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "default-on";
>
> So that's the power led?
>
>> + };
>> +
>> + green {
>> + label = "bananapi:green:usr";
>> + gpios = < 7 24 GPIO_ACTIVE_HIGH>;
>> + 

[linux-sunxi] [PATCH 0/3] ARM: dts: sun8i-h3: Add dts file for Sinovoip BPI-M2+

[Chen-Yu Tsai]

Hi everyone,

This series adds support for Sinovoip's BPI-M2+, an Allwinner H3 SoC based
development board. It is a smaller form factor than the original BPI-M2,
which was based on a different SoC.

The patches are pretty self-explaining.

Regards
ChenYu


Chen-Yu Tsai (3):
  ARM: dts: sun8i-h3: move uart0 pins to sort pinmux list in proper
order
  ARM: dts: sun8i-h3: Add uart1 pinmux setting
  ARM: dts: sun8i-h3: Add dts file for Sinovoip BPI-M2+

 arch/arm/boot/dts/Makefile |   3 +-
 .../arm/boot/dts/sun8i-h3-sinovoip-bpi-m2-plus.dts | 196 +
 arch/arm/boot/dts/sun8i-h3.dtsi|  21 ++-
 3 files changed, 212 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/boot/dts/sun8i-h3-sinovoip-bpi-m2-plus.dts

-- 
2.8.1

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[linux-sunxi] [PATCH 2/3] ARM: dts: sun8i-h3: Add uart1 pinmux setting

[Chen-Yu Tsai]

Add uart1 pins for 4 pin (RX/TX/RTS/CTS) mode.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 52558046dbaf..3c37f7e2b079 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -540,6 +540,13 @@
allwinner,drive = ;
allwinner,pull = ;
};
+
+   uart1_pins_a: uart1@0 {
+   allwinner,pins = "PG6", "PG7", "PG8", "PG9";
+   allwinner,function = "uart1";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
};
 
ahb_rst: reset@01c202c0 {
-- 
2.8.1

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[linux-sunxi] [PATCH 3/3] ARM: dts: sun8i-h3: Add dts file for Sinovoip BPI-M2+

[Chen-Yu Tsai]

The BPI-M2+ is an H3 development board. It is a smaller form factor than
the original BPI-M2, with the new H3 SoC.

It has 1GB DRAM, 8GB eMMC, a micro SD card slot, HDMI output, 2 USB
host connector and 1 USB OTG connector, an IR receiver, WiFi+BT based
on Ampak AP6212.

The board also has a 3 pin header for (debug) UART, a 40 pin GPIO header
based on the Raspberry Pi B+, but the peripheral signals are not the
same, and an FPC connector for connecting BPI's camera.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/Makefile |   3 +-
 .../arm/boot/dts/sun8i-h3-sinovoip-bpi-m2-plus.dts | 196 +
 2 files changed, 198 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun8i-h3-sinovoip-bpi-m2-plus.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 06b6c2d695bf..970e9064f56d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -765,7 +765,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-orangepi-2.dtb \
sun8i-h3-orangepi-one.dtb \
sun8i-h3-orangepi-pc.dtb \
-   sun8i-h3-orangepi-plus.dtb
+   sun8i-h3-orangepi-plus.dtb \
+   sun8i-h3-sinovoip-bpi-m2-plus.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/boot/dts/sun8i-h3-sinovoip-bpi-m2-plus.dts 
b/arch/arm/boot/dts/sun8i-h3-sinovoip-bpi-m2-plus.dts
new file mode 100644
index ..8a19b4b44f1f
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-sinovoip-bpi-m2-plus.dts
@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <w...@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include 
+#include 
+#include 
+
+/ {
+   model = "Sinovoip BPI-M2+";
+   compatible = "sinovoip,bpi-m2+", "allwinner,sun8i-h3";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <_led_bpi_m2p>;
+
+   pwr_led {
+   label = "orangepi:green:pwr";
+   gpios = <_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+   default-state = "on";
+   };
+   };
+
+   gpio_keys {
+   compatible = "gpio-keys";
+   pinctrl-names = "default";
+   pinctrl-0 = <_r_bpi_m2p>;
+
+   sw4 {
+   label = "sw4";
+   linux,code = ;
+   gpios = <_pio 0 3 GPIO_ACTIVE_LOW>;
+   };
+   };
+
+   wifi_pwrseq: wifi_pwrseq {
+   compatible = "mmc-pwrseq-simple&

[linux-sunxi] [PATCH 1/3] ARM: dts: sun8i-h3: move uart0 pins to sort pinmux list in proper order

[Chen-Yu Tsai]

Move uart0 pins to sort the list of pin settings in alphabetical order.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 4a4926b0b0ed..52558046dbaf 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -501,13 +501,6 @@
interrupt-controller;
#interrupt-cells = <3>;
 
-   uart0_pins_a: uart0@0 {
-   allwinner,pins = "PA4", "PA5";
-   allwinner,function = "uart0";
-   allwinner,drive = ;
-   allwinner,pull = ;
-   };
-
mmc0_pins_a: mmc0@0 {
allwinner,pins = "PF0", "PF1", "PF2", "PF3",
 "PF4", "PF5";
@@ -540,6 +533,13 @@
allwinner,drive = ;
allwinner,pull = ;
};
+
+   uart0_pins_a: uart0@0 {
+   allwinner,pins = "PA4", "PA5";
+   allwinner,function = "uart0";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
};
 
ahb_rst: reset@01c202c0 {
-- 
2.8.1

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Re: [linux-sunxi] sunxi-next branch

[Chen-Yu Tsai]

Hi,

On Wed, Jun 22, 2016 at 1:02 AM,   wrote:
>  Hi All,
>
> I couldn't find sunxi-next branch that include hypervisor support in current
> git repo ( git://github.com/jwrdegoede/u-boot-sunxi.git). Please let me know
> if what is correct branch i need to use for creating uboot for cubieboards
> A20 with hypervisor mode.

Mainline U-boot is hosted in a custodian repository over at Denx.

See https://linux-sunxi.org/Mainline_U-boot

ChenYu

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Re: [linux-sunxi] Re: Reliability of A20 boards

[Chen-Yu Tsai]

On Sun, Jun 19, 2016 at 4:14 AM, Stefan Monnier
 wrote:
>> My cubietruck with battery and Samsung HDD has been up for 79 days using
>> this power supply:
>
> BTW, by "reliability" I don't mean "time between reboots" but "time
> before hardware failure".  So far my experience with sunxi hardware
> running 24/7 (mostly used as NAS) has been rather mixed:
> - Cubietruck: dead after a bit less than a year (DRAM not recognized by
>   U-Boot any more).
> - BananaPi: it took me a week to find a micro-USB cable that would be
>   able to provide enough power.  And after about a year, the power
>   supply weakened, so it wasn't booting any more (and it seems to have
>   caused HDD corruption).  I'm in the process of getting another power
>   supply and it seems the board is actually not faulty.
> - OrangePi-mini: not yet up to a year, but working OK so far (fewer
>   power problems largely thanks to the experience gained earlier with
>   the BananaPi I guess).
> - Mele-A2000: this one actually still works, with the original power
>   supply, tho it's having some non-deterministic boot failures which
>   could be explained by power supply issues.
>
> I really love these little buggers because they consume very little power
> but offer all the resources I need.  I just wished I could feel more
> confident that it won't die on me when I'm away for a few weeks.

My Cubieboard2 and Cubietruck have been online for almost as long
as I've been doing sunxi work, which is a bit more than 2 years IIRC.

I've switched power supplies in between though. The PSU that came with
the Cubieboard2 is probably a better one, as it outputs right around 5V.
Others I've had either only give 4.8 ~ 4.9V, or way higher than 5V. This
causes problems with SATA on the Cubies. The step-up converter on the
Cubietruck doesn't like higher voltages, giving off weird noises.

The PSU I currently use is the Anker 60W 10-port USB charger:


https://www.amazon.com/Anker-10-Port-Charger-Multi-Port-PowerPort/dp/B00YRYS4T4/

Last time I checked the output is around 5.1V but it works well for all
my boards.

ChenYu

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[linux-sunxi] Re: [PATCH v2] ARM: dts: sun8i: Add dts file for Olimex A33-OLinuXino

[Chen-Yu Tsai]

On Mon, Jun 20, 2016 at 2:42 PM, Stefan Mavrodiev
 wrote:
> A33-OLinuXino is A33 development board designed by Olimex LTD.
>
> It has AXP233 PMU, 1GB DRAM, a micro SD card, one USB-OTG connector,
> headphone and mic jacks, connector for LiPo battery and optional
> 4GB NAND Flash.
>
> It has two 40-pin headers. One for LCD panel, and one for
> additional modules. Also there is CSI/DSI connector.
>
> Signed-off-by: Stefan Mavrodiev 
> ---
> Changes for v2:
> - Removed unused power nodes
> - Removed default-trigger for green led
> - Removed "always-on" option for LCD power
>
>  arch/arm/boot/dts/Makefile|   1 +
>  arch/arm/boot/dts/sun8i-a33-olinuxino.dts | 207 
> ++
>  2 files changed, 208 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sun8i-a33-olinuxino.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 970e906..b78f363 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -760,6 +760,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
> sun8i-a33-ippo-q8h-v1.2.dtb \
> sun8i-a33-q8-tablet.dtb \
> sun8i-a33-sinlinx-sina33.dtb \
> +   sun8i-a33-olinuxino.dtb \
> sun8i-a83t-allwinner-h8homlet-v2.dtb \
> sun8i-a83t-cubietruck-plus.dtb \
> sun8i-h3-orangepi-2.dtb \
> diff --git a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts 
> b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts
> new file mode 100644
> index 000..14fa801
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts
> @@ -0,0 +1,207 @@
> +/*
> + * Copyright 2016 - Stefan Mavrodiev 
> + *  Olimex LTD. 
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun8i-a33.dtsi"
> +#include "sunxi-common-regulators.dtsi"
> +
> +#include 
> +#include 
> +#include 
> +
> +/ {
> +   model = "A33-OLinuXino";
> +   compatible = "allwinner,sun8i-a33";
> +
> +   aliases {
> +   serial0 = 
> +   };
> +
> +   chosen {
> +   stdout-path = "serial0:115200n8";
> +   };
> +
> +   leds {
> +   compatible = "gpio-leds";
> +   pinctrl-names = "default";
> +   pinctrl-0 = <_pin_olinuxino>;
> +
> +   green {
> +   label = "olinuxino:green:usr";
> +   gpios = < 1 7 GPIO_ACTIVE_HIGH>; /* LED2 */
> +   };
> +   };
> +};
> +
> + {
> +   status = "okay";
> +};
> +
> + {
> +   status = "okay";
> +};

Please sort the nodes alphabetically.

> +
> + {
> +   pinctrl-names = "default";
> +   pinctrl-0 = <_pins_a>, <_cd_pin_olinuxino>;
> +   vmmc-supply = <_dcdc1>;
> +   bus-width = <4>;
> +   cd-gpios = < 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
> +   cd-inverted;
> +   status = "okay";
> +};
> +
> + {
> +   

[linux-sunxi] Re: sun4i drm driver not working on q8 a13 tablet ?

[Chen-Yu Tsai]

Hi,

On Mon, Jun 13, 2016 at 3:40 PM, Maxime Ripard
 wrote:
> On Thu, Jun 09, 2016 at 10:34:40AM +0200, Hans de Goede wrote:
>> Hi,
>>
>> On 09-06-16 09:53, Maxime Ripard wrote:
>> >Hi Hans,
>> >
>> >On Sat, Jun 04, 2016 at 08:10:54PM +0200, Hans de Goede wrote:
>> >>Hi All,
>> >>
>> >>As part of testing that my "ARM: dts: sun5i: Move display blocks to 
>> >>sun5i.dtsi"
>> >>patch did not break anything I've been trying to get the sun4i-drm kms
>> >>driver to work on a q8 a13 tablet.
>> >>
>> >>I've build the drm / panel bits as modules after doing :
>> >>
>> >>[root@localhost ~]# insmod syscopyarea.ko
>> >>[root@localhost ~]# insmod sysfillrect.ko
>> >>[root@localhost ~]# insmod sysimgblt.ko
>> >>[root@localhost ~]# insmod fb_sys_fops.ko
>> >>[root@localhost ~]# insmod drm.ko
>> >>[root@localhost ~]# insmod drm_kms_helper.ko
>> >>[root@localhost ~]# insmod sun4i-tcon.ko
>> >>[root@localhost ~]# insmod sun4i_backend.ko
>> >>[root@localhost ~]# insmod panel-simple.ko
>> >>[root@localhost ~]# insmod sun4i-drm.ko
>> >>
>> >>I get the following in dmesg:
>> >>
>> >>[   87.791338] [drm] Initialized drm 1.1.0 20060810
>> >>[  113.883947] panel supply power not found, using dummy regulator
>> >>[  119.199189] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>> >>[  119.210695] [drm] No driver support for vblank timestamp query.
>> >>[  119.238295] sun4i-drm display-engine: bound 1e6.display-backend 
>> >>(ops __mod_of__sun4i_backend_of_table_device_table [sun4i_backend])
>> >>[  119.261666] sun4i-drm display-engine: bound 1c0c000.lcd-controller (ops 
>> >>__mod_of__sun4i_tcon_of_table_device_table [sun4i_tcon])
>> >>[  119.287566] checking generic (5fe89000 177000) vs hw (0 )
>> >>[  119.287599] fb: switching to sun4i-drm-fb from simple
>> >>[  119.304752] Console: switching to colour dummy device 80x30
>> >>[  119.319700] sun4i-drm display-engine: No connectors reported connected 
>> >>with modes
>> >>[  119.343392] [drm] Cannot find any crtc or sizes - going 1024x768
>> >>[  119.374591] Console: switching to colour frame buffer device 128x48
>> >>[  119.433258] sun4i-drm display-engine: fb0:  frame buffer device
>> >>
>> >>Esp. notice the "sun4i-drm display-engine: No connectors reported 
>> >>connected with modes"
>> >>and "[drm] Cannot find any crtc or sizes - going 1024x768"
>> >>
>> >>Which clearly is wrong, after this the lcd-panel display becomes
>> >>a mess, as if it is not getting any video data, which indeed
>> >>seems to be what is happening.
>> >
>> >Which panel is it using? Have you added the panel timings to the
>> >simple-panel driver?
>>
>> This is using the dts patches from Chen-Yu which you've recent merged into 
>> next.
>
> Could you set drm.debug=0xff in the kernel command line, and paste the
> dmesg output?

I tried that, but it didn't give any more information.

On the side, I got some warnings about axp IRQs:

[1.169696] axp20x-i2c 0-0034: AXP20x variant AXP209 found
[1.192074] input: axp20x-pek as
/devices/platform/soc@01c0/1c2ac00.i2c/i2c-0/0-0034/axp20x-pek/input/input1
[1.782501] random: nonblocking pool is initialized
[   80.327487] irq 63: nobody cared (try booting with the "irqpoll" option)
[   80.337724] CPU: 0 PID: 77 Comm: irq/63-axp20x_i Not tainted
4.7.0-rc4-00110-g4eb35c76ed74-dirty #34
[   80.353741] Hardware name: Allwinner sun4i/sun5i Families
[   80.362723] [] (unwind_backtrace) from []
(show_stack+0xb/0xc)
[   80.373969] [] (show_stack) from []
(dump_stack+0x6f/0x7c)
[   80.384887] [] (dump_stack) from []
(__report_bad_irq+0x1d/0x8c)
[   80.396336] [] (__report_bad_irq) from []
(note_interrupt+0x1d7/0x214)
[   80.408405] [] (note_interrupt) from []
(handle_irq_event_percpu+0x79/0xc8)
[   80.420959] [] (handle_irq_event_percpu) from
[] (handle_irq_event+0x27/0x3c)
[   80.433840] [] (handle_irq_event) from []
(handle_fasteoi_irq+0x71/0xf4)
[   80.446381] [] (handle_fasteoi_irq) from []
(generic_handle_irq+0x17/0x20)
[   80.459202] [] (generic_handle_irq) from []
(__handle_domain_irq+0x3b/0x7c)
[   80.472202] [] (__handle_domain_irq) from []
(sun4i_handle_irq+0x2f/0x3c)
[   80.485171] [] (sun4i_handle_irq) from []
(__irq_svc+0x4d/0x74)
[   80.497280] Exception stack(0xdf747e98 to 0xdf747ee0)
[   80.506776] 7e80:
df6f2360 df60ac00
[   80.519489] 7ea0:  df747ee8 df6f2300 df6f2360 df700300
df6f2310 df700300 c0153109
[   80.532221] 7ec0: c01532be   df747ee8 c05a4723
c05a4726 0033 
[   80.544996] [] (__irq_svc) from []
(_raw_spin_unlock_irq+0xa/0x1c)
[   80.557638] [] (_raw_spin_unlock_irq) from []
(irq_finalize_oneshot.part.1+0x41/0x80)
[   80.576873] [] (irq_finalize_oneshot.part.1) from
[] (irq_thread_fn+0x2d/0x30)
[   80.595664] [] (irq_thread_fn) from []
(irq_thread+0x109/0x198)
[   80.608310] [] (irq_thread) from [] (kthread+0xa5/0xbc)
[   80.620267] [] (kthread) from []
(ret_from_fork+0x11/0x20)
[   80.632419] handlers:
[   80.639429] [] 

[linux-sunxi] Re: [PATCH 10/14] ARM: dts: sun8i: Add sy8106a regulator to Orange Pi PC

[Chen-Yu Tsai]

On Fri, Jun 24, 2016 at 3:21 AM,   wrote:
> From: Ondrej Jirman 
>
> Add sy8106a regulator to r_twi bus on Orange Pi PC. This
> regulator controls the CPUX voltage.
>
> Signed-off-by: Ondrej Jirman 
> ---
>  arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 10 ++
>  1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts 
> b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
> index e5991da..7e04017 100644
> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
> @@ -92,6 +92,16 @@
>
>  _twi {
> status = "okay";
> +
> +   vdd_cpu: regulator@65 {
> +   compatible = "sy8106a";
> +   reg = <0x65>;
> +   regulator-min-microvolt = <100>;
> +   regulator-max-microvolt = <140>;
> +   regulator-ramp-delay = <200>;
> +   regulator-boot-on;
> +   regulator-always-on;
> +   };

This should be merged with the previous "enable r_twi" patch.

ChenYu

>  };
>
>   {
> --
> 2.9.0
>

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[linux-sunxi] Re: [PATCH 01/14] ARM: dts: sun8i: Add SID node

[Chen-Yu Tsai]

On Fri, Jun 24, 2016 at 3:20 AM,   wrote:
> From: Josef Gajdusek 
>
> Add a node describing the Security ID memory to the Allwinner H3 .dtsi file.
>
> Signed-off-by: Josef Gajdusek 
> ---
>  arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
>  1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index 4a4926b..172576d 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -389,6 +389,13 @@
> #size-cells = <0>;
> };
>
> +   sid: eeprom@01c14000 {
> +   compatible = "allwinner,sun4i-a10-sid";

This has been discussed before. The hardware is not compatible.
The write control registers are at different offsets.

ChenYu

> +   reg = <0x01c14000 0x400>;
> +   #address-cells = <1>;
> +   #size-cells = <1>;
> +   };
> +
> usbphy: phy@01c19400 {
> compatible = "allwinner,sun8i-h3-usb-phy";
> reg = <0x01c19400 0x2c>,
> --
> 2.9.0
>

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[linux-sunxi] Re: [PATCH 04/14] dt-bindings: document sun8i_ths

[Chen-Yu Tsai]

On Fri, Jun 24, 2016 at 3:20 AM,   wrote:
> From: Ondrej Jirman 
>
> This patch adds the binding documentation for the sun8i_ths driver
>
> Signed-off-by: Ondřej Jirman 
> ---
>  .../devicetree/bindings/thermal/sun8i-ths.txt  | 31 
> ++
>  1 file changed, 31 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt
>
> diff --git a/Documentation/devicetree/bindings/thermal/sun8i-ths.txt 
> b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt
> new file mode 100644
> index 000..826cd57
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt
> @@ -0,0 +1,31 @@
> +* sun8i THS

An explanation of the acronym would be nice, both in the docs,
and in the commit message.

> +
> +Required properties:
> +- compatible : "allwinner,sun8i-h3-ths"
> +- reg : Address range of the thermal registers and location of the 
> calibration

*sensor*

Also you only specify one address range in the example. The "location
of the calibration value" is handled by the nvram-* properties. Please
remove the description.

> +value
> +- resets : Must contain an entry for each entry in reset-names.

This, and clocks below, should probably read "must contain phandles
to reset/clock controls matching the entries of the names".

Regards
ChenYu

> +   see ../reset/reset.txt for details
> +- reset-names : Must include the name "ahb"
> +- clocks : Must contain an entry for each entry in clock-names.
> +- clock-names : Must contain "ahb" for the bus gate and "ths" for the THS
> +  clock
> +
> +Optional properties:
> +- nvmem-cells : Must contain an entry for each entry in nvmem-cell-names
> +- nvmem-cell-names : Must contain "calibration" for the cell containing the
> +  temperature calibration cell, if available
> +
> +Example:
> +ths: ths@01c25000 {
> +   #thermal-sensor-cells = <0>;
> +   compatible = "allwinner,sun8i-h3-ths";
> +   reg = <0x01c25000 0x400>;
> +   interrupts = ;
> +   resets = <_rst 136>;
> +   reset-names = "ahb";
> +   clocks = <_gates 72>, <_clk>;
> +   clock-names = "ahb", "ths";
> +   nvmem-cells = <_calibration>;
> +   nvmem-cell-names = "calibration";
> +};
> --
> 2.9.0
>

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[linux-sunxi] Re: [PATCH 03/14] thermal: Add support for sun8i THS on Allwinner H3

[Chen-Yu Tsai]

Hi,

On Fri, Jun 24, 2016 at 3:20 AM,   wrote:
> From: Ondrej Jirman 
>

The subject could read:

  thermal: sun8i_ths: Add support for the thermal sensor on Allwinner H3

> This patch adds support for the sun8i thermal sensor on
> Allwinner H3 SoC.
>
> Signed-off-by: Ondřej Jirman 
> ---
>  drivers/thermal/Kconfig |   7 ++
>  drivers/thermal/Makefile|   1 +
>  drivers/thermal/sun8i_ths.c | 295 
> 
>  3 files changed, 303 insertions(+)
>  create mode 100644 drivers/thermal/sun8i_ths.c
>
> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
> index 2d702ca..3de0f8d 100644
> --- a/drivers/thermal/Kconfig
> +++ b/drivers/thermal/Kconfig
> @@ -351,6 +351,13 @@ config MTK_THERMAL
>   Enable this option if you want to have support for thermal 
> management
>   controller present in Mediatek SoCs
>
> +config SUN8I_THS
> +   tristate "sun8i THS driver"

Explain THS.

> +   depends on MACH_SUN8I
> +   depends on OF
> +   help
> + Enable this to support thermal reporting on some newer Allwinner 
> SoCs.
> +
>  menu "Texas Instruments thermal drivers"
>  depends on ARCH_HAS_BANDGAP || COMPILE_TEST
>  depends on HAS_IOMEM
> diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
> index 10b07c1..7261ee8 100644
> --- a/drivers/thermal/Makefile
> +++ b/drivers/thermal/Makefile
> @@ -51,3 +51,4 @@ obj-$(CONFIG_TEGRA_SOCTHERM)  += tegra/
>  obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o
>  obj-$(CONFIG_MTK_THERMAL)  += mtk_thermal.o
>  obj-$(CONFIG_GENERIC_ADC_THERMAL)  += thermal-generic-adc.o
> +obj-$(CONFIG_SUN8I_THS)+= sun8i_ths.o
> diff --git a/drivers/thermal/sun8i_ths.c b/drivers/thermal/sun8i_ths.c
> new file mode 100644
> index 000..618ccc3
> --- /dev/null
> +++ b/drivers/thermal/sun8i_ths.c
> @@ -0,0 +1,295 @@
> +/*
> + * sun8i THS driver

Explain THS.

> + *
> + * Copyright (C) 2016 Ondřej Jirman
> + * Based on the work of Josef Gajdusek 
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define THS_H3_CTRL0   0x00
> +#define THS_H3_CTRL2   0x40
> +#define THS_H3_INT_CTRL0x44
> +#define THS_H3_STAT0x48
> +#define THS_H3_FILTER  0x70
> +#define THS_H3_CDATA   0x74
> +#define THS_H3_DATA0x80
> +
> +#define THS_H3_CTRL0_SENSOR_ACQ0_OFFS   0
> +#define THS_H3_CTRL0_SENSOR_ACQ0(x) \
> +((x) << THS_H3_CTRL0_SENSOR_ACQ0_OFFS)
> +#define THS_H3_CTRL2_SENSE_EN_OFFS  0
> +#define THS_H3_CTRL2_SENSE_EN \
> +BIT(THS_H3_CTRL2_SENSE_EN_OFFS)
> +#define THS_H3_CTRL2_SENSOR_ACQ1_OFFS   16
> +#define THS_H3_CTRL2_SENSOR_ACQ1(x) \
> +((x) << THS_H3_CTRL2_SENSOR_ACQ1_OFFS)
> +
> +#define THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS8
> +#define THS_H3_INT_CTRL_DATA_IRQ_EN \
> +   BIT(THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS)
> +#define THS_H3_INT_CTRL_THERMAL_PER_OFFS12
> +#define THS_H3_INT_CTRL_THERMAL_PER(x) \
> +   ((x) << THS_H3_INT_CTRL_THERMAL_PER_OFFS)
> +
> +#define THS_H3_STAT_DATA_IRQ_STS_OFFS   8
> +#define THS_H3_STAT_DATA_IRQ_STS \
> +BIT(THS_H3_STAT_DATA_IRQ_STS_OFFS)
> +
> +#define THS_H3_FILTER_TYPE_OFFS 0
> +#define THS_H3_FILTER_TYPE(x) \
> +((x) << THS_H3_FILTER_TYPE_OFFS)
> +#define THS_H3_FILTER_EN_OFFS   2
> +#define THS_H3_FILTER_EN \
> +BIT(THS_H3_FILTER_EN_OFFS)

Is it really necessary to split the lines of all the macros?
It makes it harder to find and read stuff.

You're also not using any of the *_OFFS macros in the actual code,
so just drop them.

> +
> +#define THS_H3_CLK_IN 4000  /* Hz */
> +#define THS_H3_DATA_PERIOD 330  /* ms */
> +
> +#define THS_H3_FILTER_TYPE_VALUE   2  /* average over 2^(n+1) 
> samples */
> +#define THS_H3_FILTER_DIV  (1 << 
> (THS_H3_FILTER_TYPE_VALUE + 1))
> +#define THS_H3_INT_CTRL_THERMAL_PER_VALUE \
> +   (THS_H3_DATA_PERIOD * (THS_H3_CLK_IN / 1000) / THS_H3_FILTER_DIV / 
> 4096 - 1)
> +#define THS_H3_CTRL0_SENSOR_ACQ0_VALUE 0x3f /* 16us */
> +#define THS_H3_CTRL2_SENSOR_ACQ1_VALUE 0x3f
> +
> +struct sun8i_ths_data {
> +   struct reset_control *reset;
> +   struct clk *clk;
> +   struct clk *busclk;
> +   void __iomem *regs;
> +   struct nvmem_cell 

[linux-sunxi] Re: [PATCH 07/14] regulator: SY8106A regulator driver

[Chen-Yu Tsai]

On Fri, Jun 24, 2016 at 3:20 AM,   wrote:
> From: Ondrej Jirman 
>
> SY8106A is I2C attached single output voltage regulator
> made by Silergy.
>
> Signed-off-by: Ondrej Jirman 
> ---
>  drivers/regulator/Kconfig |   8 +-
>  drivers/regulator/Makefile|   2 +-
>  drivers/regulator/sy8106a-regulator.c | 153 
> ++
>  3 files changed, 161 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/regulator/sy8106a-regulator.c
>
> diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
> index 144cbf5..fc3fae2 100644
> --- a/drivers/regulator/Kconfig
> +++ b/drivers/regulator/Kconfig
> @@ -860,5 +860,11 @@ config REGULATOR_WM8994
>   This driver provides support for the voltage regulators on the
>   WM8994 CODEC.
>
> -endif
> +config REGULATOR_SY8106A
> +   tristate "Silergy SY8106A"
> +   depends on I2C

Maybe you should also depend on OF since the driver is going to crippled
without any constraints set, or (OF || COMPILE_TEST) if you want some
compile test coverage.

> +   select REGMAP_I2C
> +   help
> + This driver provides support for the voltage regulator SY8106A.
>
> +endif
> diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
> index 85a1d44..f382095 100644
> --- a/drivers/regulator/Makefile
> +++ b/drivers/regulator/Makefile
> @@ -110,6 +110,6 @@ obj-$(CONFIG_REGULATOR_WM831X) += wm831x-ldo.o
>  obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
>  obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
>  obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o
> -
> +obj-$(CONFIG_REGULATOR_SY8106A) += sy8106a-regulator.o

Follow the existing ordering in the Makefile.

>
>  ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
> diff --git a/drivers/regulator/sy8106a-regulator.c 
> b/drivers/regulator/sy8106a-regulator.c
> new file mode 100644
> index 000..34bd69c
> --- /dev/null
> +++ b/drivers/regulator/sy8106a-regulator.c
> @@ -0,0 +1,153 @@
> +/*
> + * sy8106a-regulator.c - Regulator device driver for SY8106A
> + *
> + * Copyright (C) 2016  Ondřej Jirman 
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Library General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Library General Public License for more details.
> + *
> + * You should have received a copy of the GNU Library General Public
> + * License along with this library; if not, write to the
> + * Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
> + * Boston, MA  02110-1301, USA.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 

Do you need this one?

> +#include 
> +#include 

And this one?

> +#include 
> +#include 

Sort alphabetically please.

> +
> +#define SY8106A_REG_VOUT1_SEL  0x01
> +#define SY8106A_REG_VOUT_COM   0x02
> +#define SY8106A_REG_VOUT1_SEL_MASK 0x7f
> +#define SY8106A_DISABLE_REG0x01

BIT(0) would be clearer.

> +
> +struct sy8106a {
> +   struct regulator_dev *rdev;
> +   struct regmap *regmap;
> +};
> +
> +static const struct regmap_config sy8106a_regmap_config = {
> +   .reg_bits = 8,
> +   .val_bits = 8,
> +};
> +
> +static int sy8106a_set_voltage_sel(struct regulator_dev *rdev, unsigned sel)
> +{
> +   return regmap_update_bits(rdev->regmap, rdev->desc->vsel_reg,
> + 0xff, sel | 0x80);

Can you use .apply_bit / .apply_reg with regulator_set_voltage_sel_regmap?

> +}
> +
> +static const struct regulator_ops sy8106a_ops = {
> +   .is_enabled = regulator_is_enabled_regmap,
> +   .set_voltage_sel = sy8106a_set_voltage_sel,
> +   .set_voltage_time_sel = regulator_set_voltage_time_sel,
> +   .get_voltage_sel = regulator_get_voltage_sel_regmap,
> +   .list_voltage = regulator_list_voltage_linear,
> +};
> +
> +/* Default limits measured in millivolts and milliamps */
> +#define SY8106A_MIN_MV 680
> +#define SY8106A_MAX_MV 1950
> +#define SY8106A_STEP_MV10
> +
> +static const struct regulator_desc sy8106a_reg = {
> +   .name = "SY8106A",
> +   .id = 0,
> +   .ops = _ops,
> +   .type = REGULATOR_VOLTAGE,
> +   .n_voltages = ((SY8106A_MAX_MV - SY8106A_MIN_MV) / SY8106A_STEP_MV) + 
> 1,
> +   .min_uV = (SY8106A_MIN_MV * 1000),
> +   .uV_step = (SY8106A_STEP_MV * 1000),
> +   .vsel_reg = SY8106A_REG_VOUT1_SEL,
> +   .vsel_mask = SY8106A_REG_VOUT1_SEL_MASK,
> +   .enable_reg = SY8106A_REG_VOUT_COM,
> +   .enable_mask = SY8106A_DISABLE_REG,
> +   

[linux-sunxi] Re: [PATCH 06/14] ARM: dts: sun8i: Add cpu0 label to sun8i-h3.dtsi

[Chen-Yu Tsai]

On Fri, Jun 24, 2016 at 3:20 AM,   wrote:
> From: Ondrej Jirman 
>
> Add label to the first cpu so that it can be referenced
> from derived dts files.
>
> Signed-off-by: Ondrej Jirman 
> ---
>  arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index 9938972..82faefc 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -52,7 +52,7 @@
> #address-cells = <1>;
> #size-cells = <0>;
>
> -   cpu@0 {
> +   cpu0: cpu@0 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> reg = <0>;

Can you also set the cpu clock here? It is part of the SoC
and does not belong in the board DTS files.

Otherwise this one looks good.

ChenYu

> --
> 2.9.0
>

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[linux-sunxi] Re: [PATCH v6 6/9] mfd: axp20x: Add support for RSB based AXP223 PMIC

[Chen-Yu Tsai]

On Mon, Jan 11, 2016 at 8:09 PM, Lee Jones <lee.jo...@linaro.org> wrote:
> On Mon, 11 Jan 2016, Chen-Yu Tsai wrote:
>> On Mon, Jan 11, 2016 at 5:24 PM, Lee Jones <lee.jo...@linaro.org> wrote:
>> > On Thu, 17 Dec 2015, Chen-Yu Tsai wrote:
>> >
>> >> The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
>> >> It is functionally identical to AXP221; only the regulator default
>> >> voltage/status and the external host interface are different.
>> >>
>> >> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
>> >> ---
>> >>  drivers/mfd/Kconfig| 11 +++
>> >>  drivers/mfd/Makefile   |  1 +
>> >>  drivers/mfd/axp20x-rsb.c   | 78 
>> >> ++
>> >>  drivers/mfd/axp20x.c   |  2 ++
>> >>  include/linux/mfd/axp20x.h |  1 +
>> >>  5 files changed, 93 insertions(+)
>> >>  create mode 100644 drivers/mfd/axp20x-rsb.c
>
> [...]
>
>> >> +static int axp20x_rsb_probe(struct sunxi_rsb_device *rdev)
>> >> +{
>> >> + struct axp20x_dev *axp20x;
>> >> + int ret;
>> >> +
>> >> + axp20x = devm_kzalloc(>dev, sizeof(*axp20x), GFP_KERNEL);
>> >> + if (!axp20x)
>> >> + return -ENOMEM;
>> >> +
>> >> + axp20x->dev = >dev;
>> >> + axp20x->irq = rdev->irq;
>> >> + sunxi_rsb_device_set_drvdata(rdev, axp20x);
>> >
>> > What's the point of this call?  Why do you need a sunxi_ variant?
>>
>> This is an inline call defined in include/linux/sunxi-rsb.h,
>> which is equivalent to dev_set_drvdata(>dev, data).
>>
>> It seems many subsystems or bus drivers have this pattern.
>>
>> git grep void.*_set_drvdata include/linux/ | wc -l
>>
>> yields 34, not including dev_set_drvdata itself and this sunxi_rsb
>> variant.
>
> That doesn't answer my question.  Why is it required?
>
> Looks like superfluous churn to me.  Aggregation for the sake of it.

I assumed it better to use functions matching the specific bus, and also
matching sunxi_rsb_device_get_drvdata() in the remove function.

But since we already get "struct device" two lines above, it's already
leaking the implementation, which beats the purpose of the wrapper. I'll
replace it with dev_set_drvdata() in the next version.


Regards
ChenYu

>> >> + ret = axp20x_match_device(axp20x);
>> >> + if (ret)
>> >> + return ret;
>> >> +
>> >> + axp20x->regmap = devm_regmap_init_sunxi_rsb(rdev, 
>> >> axp20x->regmap_cfg);
>> >> + if (IS_ERR(axp20x->regmap)) {
>> >> + ret = PTR_ERR(axp20x->regmap);
>> >> + dev_err(>dev, "regmap init failed: %d\n", ret);
>> >> + return ret;
>> >> + }
>> >> +
>> >> + return axp20x_device_probe(axp20x);
>> >> +}
>> >> +
>> >> +static int axp20x_rsb_remove(struct sunxi_rsb_device *rdev)
>> >> +{
>> >> + struct axp20x_dev *axp20x = sunxi_rsb_device_get_drvdata(rdev);
>> >> +
>> >> +     return axp20x_device_remove(axp20x);
>> >> +}
>> >> +
>> >> +static const struct of_device_id axp20x_rsb_of_match[] = {
>> >> + { .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },
>> >> + { },
>> >> +};
>> >> +MODULE_DEVICE_TABLE(of, axp20x_rsb_of_match);
>> >> +
>> >> +static struct sunxi_rsb_driver axp20x_rsb_driver = {
>> >> + .driver = {
>> >> + .name   = "axp20x-rsb",
>> >> + .of_match_table = of_match_ptr(axp20x_rsb_of_match),
>> >> + },
>> >> + .probe  = axp20x_rsb_probe,
>> >> + .remove = axp20x_rsb_remove,
>> >> +};
>> >> +module_sunxi_rsb_driver(axp20x_rsb_driver);
>> >> +
>> >> +MODULE_DESCRIPTION("PMIC MFD sunXi RSB driver for AXP20X");
>> >> +MODULE_AUTHOR("Chen-Yu Tsai <w...@csie.org>");
>> >> +MODULE_LICENSE("GPL v2");
>> >> diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
>> >> index 54a00168da26..968d77fb95d8 100644
>> >> --- a/drivers/mfd/axp20x.c
>> >> +++ b/drivers/mfd/axp20x.c
>> >> @@ -33,6 +33,7 @@ static const char * co

Re: [linux-sunxi] Looking for help with Building Modules

[Chen-Yu Tsai]

On Mon, Jan 18, 2016 at 3:48 AM, David Keaney  wrote:
> I have built a basic kernel following the Mailine Kernel Howto and have it
> working on my board but now I'm trying to compile a kernel
> with 'Enable loadable module support' enabled and this is where I'm running
> into problems.
>
> The kernel compiles ok but when it gets to building the modules I get the
> following output with no modules in the output folder
>
>
> ~/linux$ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- INSTALL_MOD_PATH=output
> make modules modules_install
>  CHK include/config/kernel.release
>CHK include/generated/uapi/linux/version.h
>CHK include/generated/utsrelease.h
>  make[1]: `include/generated/mach-types.h' is up to date.
>CC  kernel/bounds.s
>CHK include/generated/bounds.h
>CC  arch/arm/kernel/asm-offsets.s
>CHK include/generated/asm-offsets.h
>CALLscripts/checksyscalls.sh
>CHK include/generated/compile.h
>CHK kernel/config_data.h
>Building modules, stage 2.
>MODPOST 0 modules
>DEPMOD  4.1.0-rc7-00061-g2bfc60d
>  ~/linux$
>
>
> Host Machine: Ubuntu 14.04
> gcc version: 4.8.4
>
> Is there anything else I need to do other then just enabling loadable module
> support

You have to specify which drivers you want to build as modules.
In menuconfig, things that can be built as modules (known as tri-state in
Kconfig) have their option in <> angle brackets, while non-module ones are
in [] square brackets. If a driver is to be built as a module, the option
would say .

This is basic kernel compiling. There should be a ton of guides on the
Internet.

ChenYu

> Any help would be greatly appreciated
>
> --
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[linux-sunxi] Re: [PATCH v2 05/26] clk: sunxi: Add display and TCON0 clocks driver

[Chen-Yu Tsai]

Hi,

On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
 wrote:
> The A10 SoCs and its relatives has a special clock controller to drive the
> display engines (both frontend and backend), that have a lot in common with
> the clock to drive the first TCON channel.
>
> Add a driver to support both.
>
> Signed-off-by: Maxime Ripard 
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |   2 +
>  drivers/clk/sunxi/Makefile|   1 +
>  drivers/clk/sunxi/clk-sun4i-display.c | 241 
> ++
>  3 files changed, 244 insertions(+)
>  create mode 100644 drivers/clk/sunxi/clk-sun4i-display.c
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
> b/Documentation/devicetree/bindings/clock/sunxi.txt
> index 8a47b77abfca..5360554a7d3f 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -55,6 +55,7 @@ Required properties:
> "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
> "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
> "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
> +   "allwinner,sun4i-a10-display-clk" - for the display clocks on the A10
> "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
> "allwinner,sun4i-a10-mmc-clk" - for the MMC clock
> "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
> @@ -64,6 +65,7 @@ Required properties:
> "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
> "allwinner,sun7i-a20-out-clk" - for the external output clocks
> "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
> +   "allwinner,sun4i-a10-tcon-ch0-clk" - for the TCON channel 0 clock on 
> the A10
> "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
> "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
> "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index cb4c299214ce..a991cd8ca509 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -10,6 +10,7 @@ obj-y += clk-a10-pll2.o
>  obj-y += clk-a20-gmac.o
>  obj-y += clk-mod0.o
>  obj-y += clk-simple-gates.o
> +obj-y += clk-sun4i-display.o
>  obj-y += clk-sun8i-mbus.o
>  obj-y += clk-sun9i-core.o
>  obj-y += clk-sun9i-mmc.o
> diff --git a/drivers/clk/sunxi/clk-sun4i-display.c 
> b/drivers/clk/sunxi/clk-sun4i-display.c
> new file mode 100644
> index ..9dc6894f0934
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-sun4i-display.c
> @@ -0,0 +1,241 @@
> +/*
> + * Copyright 2015 Maxime Ripard
> + *
> + * Maxime Ripard 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +struct sun4i_a10_display_clk_data {
> +   boolhas_div;
> +   boolhas_rst;
> +   u8  parents;
> +
> +   u8  offset_en;
> +   u8  offset_div;
> +   u8  offset_mux;
> +   u8  offset_rst;
> +
> +   u8  width_div;
> +   u8  width_mux;
> +};
> +
> +struct reset_data {
> +   void __iomem*reg;
> +   spinlock_t  *lock;
> +   struct reset_controller_dev rcdev;
> +   u8  offset;
> +};
> +
> +static DEFINE_SPINLOCK(sun4i_a10_display_lock);
> +
> +static inline struct reset_data *rcdev_to_reset_data(struct 
> reset_controller_dev *rcdev)
> +{
> +   return container_of(rcdev, struct reset_data, rcdev);
> +};
> +
> +static int sun4i_a10_display_assert(struct reset_controller_dev *rcdev,
> +   unsigned long id)
> +{
> +   struct reset_data *data = rcdev_to_reset_data(rcdev);
> +   unsigned long flags;
> +   u32 reg;
> +
> +   spin_lock_irqsave(data->lock, flags);
> +
> +   reg = readl(data->reg);
> +   writel(reg & ~BIT(data->offset), data->reg);
> +
> +   spin_unlock_irqrestore(data->lock, flags);
> +
> +   return 0;
> +}
> +
> +static int sun4i_a10_display_deassert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> +   struct reset_data *data = rcdev_to_reset_data(rcdev);
> +   unsigned long flags;
> +   

[linux-sunxi] Re: [PATCH v2 07/26] clk: sunxi: Add TCON channel1 clock

[Chen-Yu Tsai]

Hi,

On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
 wrote:
> The TCON is a controller generating the timings to output videos signals,
> acting like both a CRTC and an encoder.
>
> It has two channels depending on the output, each channel being driven by
> its own clock (and own clock controller).
>
> Add a driver for the channel 1 clock.
>
> Signed-off-by: Maxime Ripard 
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |   1 +
>  drivers/clk/sunxi/Makefile|   1 +
>  drivers/clk/sunxi/clk-sun4i-tcon-ch1.c| 154 
> ++
>  3 files changed, 156 insertions(+)
>  create mode 100644 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
> b/Documentation/devicetree/bindings/clock/sunxi.txt
> index bb9fb78dcff8..fe34fc56e803 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -67,6 +67,7 @@ Required properties:
> "allwinner,sun7i-a20-out-clk" - for the external output clocks
> "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
> "allwinner,sun4i-a10-tcon-ch0-clk" - for the TCON channel 0 clock on 
> the A10
> +   "allwinner,sun4i-a10-tcon-ch1-clk" - for the TCON channel 1 clock on 
> the A10
> "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
> "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
> "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index 40c32ffd912c..0a20873cd103 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -12,6 +12,7 @@ obj-y += clk-mod0.o
>  obj-y += clk-simple-gates.o
>  obj-y += clk-sun4i-display.o
>  obj-y += clk-sun4i-pll3.o
> +obj-y += clk-sun4i-tcon-ch1.o
>  obj-y += clk-sun8i-mbus.o
>  obj-y += clk-sun9i-core.o
>  obj-y += clk-sun9i-mmc.o
> diff --git a/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c 
> b/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
> new file mode 100644
> index ..51ddc38821f7
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
> @@ -0,0 +1,154 @@
> +/*
> + * Copyright 2015 Maxime Ripard
> + *
> + * Maxime Ripard 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define SUN4I_TCON_CH1_SCLK_NAME_LEN   32
> +
> +#define SUN4I_A10_TCON_CH1_SCLK2_PARENTS   4
> +
> +#define SUN4I_A10_TCON_CH1_SCLK2_GATE_BIT  31
> +#define SUN4I_A10_TCON_CH1_SCLK2_MUX_MASK  3
> +#define SUN4I_A10_TCON_CH1_SCLK2_MUX_SHIFT 24
> +#define SUN4I_A10_TCON_CH1_SCLK2_DIV_WIDTH 4
> +#define SUN4I_A10_TCON_CH1_SCLK2_DIV_SHIFT 0
> +
> +#define SUN4I_A10_TCON_CH1_SCLK1_GATE_BIT  15
> +#define SUN4I_A10_TCON_CH1_SCLK1_DIV_WIDTH 1
> +#define SUN4I_A10_TCON_CH1_SCLK1_DIV_SHIFT 11
> +
> +static DEFINE_SPINLOCK(sun4i_a10_tcon_ch1_lock);
> +
> +static void __init sun4i_a10_tcon_ch1_setup(struct device_node *node)
> +{
> +   const char *sclk2_parents[SUN4I_A10_TCON_CH1_SCLK2_PARENTS];
> +   const char *sclk1_name = node->name;
> +   const char *sclk2_name;
> +   struct clk_divider *sclk1_div, *sclk2_div;
> +   struct clk_gate *sclk1_gate, *sclk2_gate;
> +   struct clk_mux *sclk2_mux;
> +   struct clk *sclk1, *sclk2;
> +   void __iomem *reg;
> +   int i, ret;
> +
> +   of_property_read_string(node, "clock-output-names",
> +   _name);
> +
> +   sclk2_name = kasprintf(GFP_KERNEL, "%s2", sclk1_name);
> +   if (!sclk2_name)
> +   return;
> +
> +   reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> +   if (IS_ERR(reg)) {
> +   pr_err("%s: Could not map the clock registers\n", sclk2_name);
> +   return;
> +   }
> +
> +   for (i = 0; i < SUN4I_A10_TCON_CH1_SCLK2_PARENTS; i++)
> +   sclk2_parents[i] = of_clk_get_parent_name(node, i);

of_clk_parent_fill?

> +
> +   sclk2_mux = kzalloc(sizeof(*sclk2_mux), GFP_KERNEL);
> +   if (!sclk2_mux)
> +   return;
> +
> +   sclk2_mux->reg = reg;
> +   sclk2_mux->shift = SUN4I_A10_TCON_CH1_SCLK2_MUX_SHIFT;
> +   sclk2_mux->mask = SUN4I_A10_TCON_CH1_SCLK2_MUX_MASK;
> +   sclk2_mux->lock = 

[linux-sunxi] Re: [PATCH v2 11/26] ARM: sun5i: Add DRAM gates

[Chen-Yu Tsai]

On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
 wrote:
> The DRAM gates control whether the image / display devices on the SoC have
> access to the DRAM clock or not.
>
> Enable it.
>
> Signed-off-by: Maxime Ripard 
> ---
>  arch/arm/boot/dts/sun5i-a10s.dtsi |  7 ---
>  arch/arm/boot/dts/sun5i-a13.dtsi  |  2 +-
>  arch/arm/boot/dts/sun5i-r8.dtsi   |  2 +-
>  arch/arm/boot/dts/sun5i.dtsi  | 19 +++
>  4 files changed, 25 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi 
> b/arch/arm/boot/dts/sun5i-a10s.dtsi
> index bddd0de88af6..52d2c79cb37b 100644
> --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
> +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
> @@ -66,7 +66,7 @@
>  "simple-framebuffer";
> allwinner,pipeline = "de_be0-lcd0-hdmi";
> clocks = < 1>, <_gates 36>, <_gates 43>,
> -<_gates 44>;
> +<_gates 44>, <_gates 26>;
> status = "disabled";
> };
>
> @@ -74,7 +74,8 @@
> compatible = "allwinner,simple-framebuffer",
>  "simple-framebuffer";
> allwinner,pipeline = "de_be0-lcd0";
> -   clocks = < 1>, <_gates 36>, <_gates 44>;
> +   clocks = < 1>, <_gates 36>, <_gates 44>,
> +<_gates 26>;
> status = "disabled";
> };
>
> @@ -83,7 +84,7 @@
>  "simple-framebuffer";
> allwinner,pipeline = "de_be0-lcd0-tve0";
> clocks = < 1>, <_gates 34>, <_gates 36>,
> -<_gates 44>;
> +<_gates 44>, <_gates 26>;
> status = "disabled";
> };
> };
> diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi 
> b/arch/arm/boot/dts/sun5i-a13.dtsi
> index 9669b03f20f3..f29163650ca8 100644
> --- a/arch/arm/boot/dts/sun5i-a13.dtsi
> +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
> @@ -62,7 +62,7 @@
>  "simple-framebuffer";
> allwinner,pipeline = "de_be0-lcd0";
> clocks = <_gates 36>, <_gates 44>, 
> <_be_clk>,
> -<_ch0_clk>;
> +<_ch0_clk>, <_gates 26>;
> status = "disabled";
> };
> };
> diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
> index b1e4e0170d51..691d3de75b35 100644
> --- a/arch/arm/boot/dts/sun5i-r8.dtsi
> +++ b/arch/arm/boot/dts/sun5i-r8.dtsi
> @@ -53,7 +53,7 @@
> allwinner,pipeline = "de_be0-lcd0-tve0";
> clocks = <_gates 34>, <_gates 36>,
>  <_gates 44>, <_be_clk>,
> -<_ch1_clk>;
> +<_ch1_clk>, <_gates 26>;
> status = "disabled";
> };
> };
> diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
> index 0840612b5ed6..c72d94228915 100644
> --- a/arch/arm/boot/dts/sun5i.dtsi
> +++ b/arch/arm/boot/dts/sun5i.dtsi
> @@ -338,6 +338,25 @@
> clock-output-names = "usb_ohci0", "usb_phy";
> };
>
> +   dram_gates: clk@01c20100 {
> +   #clock-cells = <1>;
> +   compatible = "allwinner,sun5i-a13-dram-gates-clk";
> +   reg = <0x01c20100 0x4>;
> +   clocks = < 0>;
> +   clock-indices = <0>,
> +   <1>,

According to A10s manual, bit 3 is DRAM clock for TS (transport stream
decoder), while bit 5 is for the TV encoder.

The others look good.

ChenYu

> +   <25>,
> +   <26>,
> +   <29>,
> +   <31>;
> +   clock-output-names = "dram_ve",
> +"dram_csi",
> +"dram_de_fe",
> +"dram_de_be",
> +"dram_ace",
> +"dram_iep";
> +   };
> +
> codec_clk: clk@01c20140 {
> #clock-cells = <0>;
> compatible = "allwinner,sun4i-a10-codec-clk";
> --
> 2.6.4
>

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[linux-sunxi] Re: [PATCH v2 10/26] ARM: sun5i: a13: Add display and TCON clocks

[Chen-Yu Tsai]

Hi,

On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
 wrote:
> Enable the display and TCON (channel 0 and channel 1) clocks that are going
> to be needed to drive the display engine, tcon and TV encoders.
>
> Signed-off-by: Maxime Ripard 
> ---
>  arch/arm/boot/dts/sun5i-a13.dtsi | 38 +-
>  arch/arm/boot/dts/sun5i-r8.dtsi  |  5 +++--
>  2 files changed, 40 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi 
> b/arch/arm/boot/dts/sun5i-a13.dtsi
> index d910d3a6c41c..9669b03f20f3 100644
> --- a/arch/arm/boot/dts/sun5i-a13.dtsi
> +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
> @@ -61,7 +61,8 @@
> compatible = "allwinner,simple-framebuffer",
>  "simple-framebuffer";
> allwinner,pipeline = "de_be0-lcd0";
> -   clocks = < 1>, <_gates 36>, <_gates 44>;
> +   clocks = <_gates 36>, <_gates 44>, 
> <_be_clk>,
> +<_ch0_clk>;
> status = "disabled";
> };
> };
> @@ -149,6 +150,41 @@
>  "apb1_i2c2", "apb1_uart1",
>  "apb1_uart3";
> };
> +
> +   de_be_clk: clk@01c20104 {
> +   #clock-cells = <0>;
> +   #reset-cells = <0>;
> +   compatible = "allwinner,sun4i-a10-display-clk";
> +   reg = <0x01c20104 0x4>;
> +   clocks = <>, <>, < 1>;
> +   clock-output-names = "de-be";
> +   };
> +
> +   de_fe_clk: clk@01c2010c {
> +   #clock-cells = <0>;
> +   #reset-cells = <0>;
> +   compatible = "allwinner,sun4i-a10-display-clk";
> +   reg = <0x01c2010c 0x4>;
> +   clocks = <>, <>, < 1>;
> +   clock-output-names = "de-fe";
> +   };
> +
> +   tcon_ch0_clk: clk@01c20118 {
> +   #clock-cells = <0>;
> +   #reset-cells = <1>;

You got it right here...

> +   compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
> +   reg = <0x01c20118 0x4>;
> +   clocks = <>, <>, <>, <>;
> +   clock-output-names = "tcon-ch0-sclk";
> +   };
> +
> +   tcon_ch1_clk: clk@01c2012c {
> +   #clock-cells = <0>;
> +   compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
> +   reg = <0x01c2012c 0x4>;
> +   clocks = <>, <>, <>, <>;
> +   clock-output-names = "tcon-ch1-sclk";
> +   };

I suggest moving these to sun5i.dtsi, as they are shared amongst them.

ChenYu

> };
>
> soc@01c0 {
> diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
> index 0ef865601ac9..b1e4e0170d51 100644
> --- a/arch/arm/boot/dts/sun5i-r8.dtsi
> +++ b/arch/arm/boot/dts/sun5i-r8.dtsi
> @@ -51,8 +51,9 @@
> compatible = "allwinner,simple-framebuffer",
>  "simple-framebuffer";
> allwinner,pipeline = "de_be0-lcd0-tve0";
> -   clocks = < 1>, <_gates 34>, <_gates 36>,
> -<_gates 44>;
> +   clocks = <_gates 34>, <_gates 36>,
> +<_gates 44>, <_be_clk>,
> +<_ch1_clk>;
> status = "disabled";
> };
> };
> --
> 2.6.4
>

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[linux-sunxi] Re: [PATCH v2 06/26] clk: sunxi: Add PLL3 clock

[Chen-Yu Tsai]

   if (IS_ERR(clk)) {
> +   pr_err("%s: Couldn't register the clock\n", clk_name);
> +   goto err_free_mult;
> +   }
> +
> +   ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
> +   if (WARN_ON(ret))

Any particular reason for WARN_ON instead of pr_err like above?

> +   goto err_clk_unregister;
> +
> +   return;
> +
> +err_clk_unregister:
> +   clk_unregister_composite(clk);
> +err_free_mult:
> +   kfree(mult);
> +err_free_gate:
> +   kfree(gate);

Clean up after of_io_request_and_map(), otherwise

Acked-by: Chen-Yu Tsai <w...@csie.org>

Thanks!

> +}
> +
> +CLK_OF_DECLARE(sun4i_a10_pll3, "allwinner,sun4i-a10-pll3-clk",
> +  sun4i_a10_pll3_setup);
> --
> 2.6.4
>

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[linux-sunxi] [PATCH 3/3] ARM: dts: sun8i: Add device tree for Cubietruck Plus

[Chen-Yu Tsai]

Cubietruck Plus is a A83T/H8 based development board. The board has
standard DDR3 SDRAM, AXP818 PMIC/codec, SD/MMC, eMMC, USB 2.0 host
via HSIC USB Hub, USB OTG, SATA via USB bridge, gigabit ethernet,
WiFi, headphone out / mic in, and various GPIO headers.

The board also has an EEPROM on i2c0 which holds the MAC address.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/Makefile   |  1 +
 arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 65 
 2 files changed, 66 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5dbb67b26318..de9b2f1fd272 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -664,6 +664,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
+   sun8i-a83t-cubietruck-plus.dtb \
sun8i-h3-orangepi-plus.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts 
b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
new file mode 100644
index ..88b1e0970b8d
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <w...@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+
+/ {
+   model = "Cubietech Cubietruck Plus";
+   compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_b>;
+   status = "okay";
+};
-- 
2.7.0.rc3

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[linux-sunxi] [PATCH 2/3] ARM: dts: sun8i: Add watchdog device node for A83T

[Chen-Yu Tsai]

The A83T, like previous Allwinner SoCs, has a watchdog as part of its
timer block. Add a device node for it.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 08df5598df9c..8d27b6381257 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -182,6 +182,13 @@
clocks = <>;
};
 
+   watchdog@01c20ca0 {
+   compatible = "allwinner,sun6i-a31-wdt";
+   reg = <0x01c20ca0 0x20>;
+   interrupts = ;
+   clocks = <>;
+   };
+
uart0: serial@01c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
-- 
2.7.0.rc3

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[linux-sunxi] [PATCH 0/3] ARM: dts: sun8i: Add timer/watchdog for A83T and Cubietruck Plus

[Chen-Yu Tsai]

Hi Maxime,

This small series adds the timer/watchdog block for A83T, and also a new
board, the A83T/H8 based Cubietruck Plus from Cubietech.

Patch 1 from Vishnu adds the timer device node. This was picked from his
github branch sunxi-a83-wip.

Patch 2 adds the watchdog device node. We get watchdog and reboot support
on the A83T.

Patch 3 adds a basic DTS file for the Cubieteuck Plus.

Chen-Yu Tsai (2):
  ARM: dts: sun8i: Add watchdog device node for A83T
  ARM: dts: sun8i: Add device tree for Cubietruck Plus

Vishnu Patekar (1):
  ARM: dts: sun8i: Enable timer node for A83T

 arch/arm/boot/dts/Makefile   |  1 +
 arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 65 
 arch/arm/boot/dts/sun8i-a83t.dtsi| 15 ++
 3 files changed, 81 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts

-- 
2.7.0.rc3

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[linux-sunxi] [PATCH 1/3] ARM: dts: sun8i: Enable timer node for A83T

[Chen-Yu Tsai]

From: Vishnu Patekar <vishnupatekar0...@gmail.com>

A83T timer is compatible with that of earlier SOCs.
Just add timer node to enable and re-use it.

Signed-off-by: Vishnu Patekar <vishnupatekar0...@gmail.com>
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index bad5df7175b4..08df5598df9c 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -174,6 +174,14 @@
};
};
 
+   timer@01c20c00 {
+   compatible = "allwinner,sun4i-a10-timer";
+   reg = <0x01c20c00 0xa0>;
+   interrupts = ,
+;
+   clocks = <>;
+   };
+
uart0: serial@01c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
-- 
2.7.0.rc3

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[linux-sunxi] Re: [PATCH v2 12/26] ARM: sun5i: Add TV encoder gate to the DTSI

[Chen-Yu Tsai]

On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> It turns out that the A13 / R8 also have a tve encoder block, and a gate
> for it.
>
> Add it to the DT.
>
> Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>

Acked-by: Chen-Yu Tsai <w...@csie.org>

> ---
>  arch/arm/boot/dts/sun5i-a13.dtsi | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)

[...]

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[linux-sunxi] Re: [PATCH 07/14] regulator: SY8106A regulator driver

[Chen-Yu Tsai]

On Sat, Jun 25, 2016 at 8:11 AM, Ondřej Jirman <meg...@megous.com> wrote:
> Hi,
>
> thank you for the review. I've resolved most of the issues. Some more
> comments below.
>
> On 24.6.2016 05:41, Chen-Yu Tsai wrote:
>> On Fri, Jun 24, 2016 at 3:20 AM,  <meg...@megous.com> wrote:
>>> From: Ondrej Jirman <meg...@megous.com>
>>>
>>> SY8106A is I2C attached single output voltage regulator
>>> made by Silergy.
>>>
>>> Signed-off-by: Ondrej Jirman <meg...@megous.com>
>>> ---
>>>  drivers/regulator/Kconfig |   8 +-
>>>  drivers/regulator/Makefile|   2 +-
>>>  drivers/regulator/sy8106a-regulator.c | 153 
>>> ++
>>>  3 files changed, 161 insertions(+), 2 deletions(-)
>>>  create mode 100644 drivers/regulator/sy8106a-regulator.c
>>>
>>> diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
>>> index 144cbf5..fc3fae2 100644
>>> --- a/drivers/regulator/Kconfig
>>> +++ b/drivers/regulator/Kconfig
>>> @@ -860,5 +860,11 @@ config REGULATOR_WM8994
>>>   This driver provides support for the voltage regulators on the
>>>   WM8994 CODEC.
>>>
>>> -endif
>>> +config REGULATOR_SY8106A
>>> +   tristate "Silergy SY8106A"
>>> +   depends on I2C
>>
>> Maybe you should also depend on OF since the driver is going to crippled
>> without any constraints set, or (OF || COMPILE_TEST) if you want some
>> compile test coverage.
>>
>>> +   select REGMAP_I2C
>>> +   help
>>> + This driver provides support for the voltage regulator SY8106A.
>>>
>>> +endif
>>> diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
>>> index 85a1d44..f382095 100644
>>> --- a/drivers/regulator/Makefile
>>> +++ b/drivers/regulator/Makefile
>>> @@ -110,6 +110,6 @@ obj-$(CONFIG_REGULATOR_WM831X) += wm831x-ldo.o
>>>  obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
>>>  obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
>>>  obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o
>>> -
>>> +obj-$(CONFIG_REGULATOR_SY8106A) += sy8106a-regulator.o
>>
>> Follow the existing ordering in the Makefile.
>>
>>>
>>>  ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
>>> diff --git a/drivers/regulator/sy8106a-regulator.c 
>>> b/drivers/regulator/sy8106a-regulator.c
>>> new file mode 100644
>>> index 000..34bd69c
>>> --- /dev/null
>>> +++ b/drivers/regulator/sy8106a-regulator.c
>>> @@ -0,0 +1,153 @@
>>> +/*
>>> + * sy8106a-regulator.c - Regulator device driver for SY8106A
>>> + *
>>> + * Copyright (C) 2016  Ondřej Jirman <meg...@megous.com>
>>> + *
>>> + * This library is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU Library General Public
>>> + * License as published by the Free Software Foundation; either
>>> + * version 2 of the License, or (at your option) any later version.
>>> + *
>>> + * This library is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
>>> + * Library General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU Library General Public
>>> + * License along with this library; if not, write to the
>>> + * Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
>>> + * Boston, MA  02110-1301, USA.
>>> + */
>>> +
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>
>> Do you need this one?
>>
>>> +#include 
>>> +#include 
>>
>> And this one?
>>
>>> +#include 
>>> +#include 
>>
>> Sort alphabetically please.
>>
>>> +
>>> +#define SY8106A_REG_VOUT1_SEL  0x01
>>> +#define SY8106A_REG_VOUT_COM   0x02
>>> +#define SY8106A_REG_VOUT1_SEL_MASK 0x7f
>>> +#define SY8106A_DISABLE_REG0x01
>>
>> BIT(0) would be clearer.
>>
>>> +
>>> +struct sy8106a {
>>> +   struct regulator_dev *rdev;
>>> +   struct regmap *regmap;
>>> +};
>>> +
>>> +static const struct regmap_config sy81

[linux-sunxi] Re: [PATCH 06/14] ARM: dts: sun8i: Add cpu0 label to sun8i-h3.dtsi

[Chen-Yu Tsai]

On Sat, Jun 25, 2016 at 6:51 AM, Ondřej Jirman <meg...@megous.com> wrote:
> Hello,
>
> comments below.
>
> On 24.6.2016 05:48, Chen-Yu Tsai wrote:
>> On Fri, Jun 24, 2016 at 3:20 AM,  <meg...@megous.com> wrote:
>>> From: Ondrej Jirman <meg...@megous.com>
>>>
>>> Add label to the first cpu so that it can be referenced
>>> from derived dts files.
>>>
>>> Signed-off-by: Ondrej Jirman <meg...@megous.com>
>>> ---
>>>  arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi 
>>> b/arch/arm/boot/dts/sun8i-h3.dtsi
>>> index 9938972..82faefc 100644
>>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>>> @@ -52,7 +52,7 @@
>>> #address-cells = <1>;
>>> #size-cells = <0>;
>>>
>>> -   cpu@0 {
>>> +   cpu0: cpu@0 {
>>> compatible = "arm,cortex-a7";
>>> device_type = "cpu";
>>> reg = <0>;
>>
>> Can you also set the cpu clock here? It is part of the SoC
>> and does not belong in the board DTS files.
>
> Do you mean operating-points, or something else? Different SBCs will
> probably require different combinations of operating points just for
> safety's sake, because they have different regulators and [some have
> botched] thermal designs, so it might make sense to customize it for
> differnt boards, and I don't feel adventurous enough setting it for all
> H3 boards out there.

I meant clocks = <...> and clock-latency = <...>.

These 2 are part of the SoC.

The OPP can stay in the board files. It's a pity there's no standard
OPP table for H3 though. :(

ChenYu

>
> Or is this comment related to the missing cpu clock rate message I see
> on every boot?
>
> [0.058912] /cpus/cpu@0 missing clock-frequency property
>
> regards,
>   Ondrej
>
>> Otherwise this one looks good.
>>
>> ChenYu
>>
>>> --
>>> 2.9.0
>>>
>

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Re: [linux-sunxi] Re: [PATCH 01/14] ARM: dts: sun8i: Add SID node

[Chen-Yu Tsai]

Hi,

On Sat, Jun 25, 2016 at 3:58 AM, Ondřej Jirman <meg...@megous.com> wrote:
> Hello,
>
> thank you for the review.
>
> On 24.6.2016 04:41, Chen-Yu Tsai wrote:
>> On Fri, Jun 24, 2016 at 3:20 AM,  <meg...@megous.com> wrote:
>>> From: Josef Gajdusek <a...@atx.name>
>>>
>>> Add a node describing the Security ID memory to the Allwinner H3 .dtsi file.
>>>
>>> Signed-off-by: Josef Gajdusek <a...@atx.name>
>>> ---
>>>  arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
>>>  1 file changed, 7 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi 
>>> b/arch/arm/boot/dts/sun8i-h3.dtsi
>>> index 4a4926b..172576d 100644
>>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>>> @@ -389,6 +389,13 @@
>>> #size-cells = <0>;
>>> };
>>>
>>> +   sid: eeprom@01c14000 {
>>> +   compatible = "allwinner,sun4i-a10-sid";
>>
>> This has been discussed before. The hardware is not compatible.
>> The write control registers are at different offsets.
>
> I'm not sure what you mean by write control registers. Code in
> sunxi_sid.c implements only read access to the nvram. Can you pelase
> elaborate?

See 
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-November/388022.html

Also, different compatibles are used for different hardware, regardless
of how close the drivers may be. The driver might only be compatible when
implementing a subset of the possible features. If one were to fully
implement it, they would become incompatible.

To put it another way, the compatible string designates the hardware,
and the driver implements support for that compatible string.

ChenYu

>   Ondrej
>
>>
>> ChenYu
>>
>>> +   reg = <0x01c14000 0x400>;
>>> +   #address-cells = <1>;
>>> +   #size-cells = <1>;
>>> +   };
>>> +
>>> usbphy: phy@01c19400 {
>>> compatible = "allwinner,sun8i-h3-usb-phy";
>>> reg = <0x01c19400 0x2c>,
>>> --
>>> 2.9.0
>>>
>
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Re: [linux-sunxi] [PATCH] [V2] ARM: dts: sun7i: Add dts file for Bananapi M1 Plus board

[Chen-Yu Tsai]

On Thu, Jun 16, 2016 at 4:52 AM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi Chen-Yu,
>
> On Mon, Jun 13, 2016 at 11:01:53AM +0800, Chen-Yu Tsai wrote:
>> On Fri, Jun 10, 2016 at 5:38 PM, Maxime Ripard
>> <maxime.rip...@free-electrons.com> wrote:
>> > On Thu, Jun 02, 2016 at 11:15:55AM +0200, Bernhard Nortmann wrote:
>> >> Am 02.06.2016 um 10:16 schrieb Maxime Ripard:
>> >> >[...]
>> >> >Yes, everything that is shared with the banana-pro (which, judging
>> >> >from Bernhard, is pretty much everything but a GPIO) should be merged
>> >> >in the banapro DT.
>> >> >
>> >> >Maxime
>> >> >
>> >>
>> >> Don't take my word for granted, as I do not own this hardware or know it
>> >> particularly well. There is no doubt that "BPi-M1+" and "Banana Pro" are
>> >> very similar, but if in doubt the information form the wiki should be
>> >> verified.
>> >
>> > H, ok. Chen-Yu, any input on this? You know the banana-pis much
>> > more than I do.
>>
>> I did a comparison of the "Banana Pro" vs the "BPi-M1+".
>>
>> The differences are similar to what we have with any other development
>> board, say the Cubietruck:
>>
>>   - A different WiFi chip is used, and the BT part is not hooked up.
>>   - Different GPIOs for external power regulator/switches
>>   - Different GPIOs for LEDs
>>   - Different peripherals exposed on the headers.
>>
>> IMO There's no need to merge or have a common .dtsi for the two boards.
>
> Ok.
>
>> They (and all the other development boards) look similar because
>> everyone is following the basic set by Allwinner's reference design,
>> like which MMC controller and pins are used for SD/MMC, which ones
>> are used for SDIO-based WiFi, and so on.
>>
>> I did a version completely from scratch using just the schematics:
>>
>>   https://github.com/wens/linux/commits/bpi-m1-plus
>
> So, what do you mean by that? Do you have some comments on that patch,
> or should I merge it, and you'll post your additions on top of it?

I'd like Luo to send a new version, based on what was his updated v1.

I'll reply to that one with some comments.


ChenYu

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Re: [linux-sunxi] Re: [PATCH] ARM: dts: sun7i: Add dts file for Bananapi M1 Plus board

[Chen-Yu Tsai]

Hi,

On Wed, Jun 1, 2016 at 10:40 AM, luoyi  wrote:
> This is the new version of the patch.  and I think maybe every board
> should have their own dtb files. and we can you some cpp  macro tricks
> to merge their coressponding dts file.
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index e06a5ab..fde407f 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -685,6 +685,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
>  sun6i-a31s-yones-toptech-bs1078-v2.dtb
>  dtb-$(CONFIG_MACH_SUN7I) += \
>  sun7i-a20-bananapi.dtb \
> +sun7i-a20-bananapi-m1-plus.dtb \
>  sun7i-a20-bananapro.dtb \
>  sun7i-a20-cubieboard2.dtb \
>  sun7i-a20-cubietruck.dtb \
> diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
> b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
> new file mode 100644
> index 000..548ed31
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
> @@ -0,0 +1,266 @@
> +/*
> + * Copyright 2016 Luo Yi 
> + *
> + * Thanks to the original work by Hans de Goede 
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun7i-a20.dtsi"
> +#include "sunxi-common-regulators.dtsi"
> +#include 
> +#include 
> +
> +/ {
> +model = "Banana Pi BPI-M1-Plus";
> +compatible = "sinovoip,bpi-m1-plus", "allwinner,sun7i-a20";
> +
> +aliases {
> +serial0 = 
> +};
> +
> +chosen {
> +stdout-path = "serial0:115200n8";
> +};
> +
> +leds {

Extra space at end of line.

> +compatible = "gpio-leds";
> +pinctrl-names = "default";
> +pinctrl-0 = <_pins_bananapi>;
> +
> +green {
> +label = "bananapi:green:usr";

The led labels should use the board name.

> +gpios = < 7 24 GPIO_ACTIVE_HIGH>;
> +};
> +
> +red {
> +label = "bananapi:red:usr";
> +gpios = < 7 25 GPIO_ACTIVE_HIGH>;
> +linux,default-trigger = "default-on";
> +};
> +
> +};
> +
> +mmc3_pwrseq: mmc3_pwrseq {
> +compatible = "mmc-pwrseq-simple";
> +pinctrl-names = "default";
> +pinctrl-0 = <_pwrseq_pin_bananapim1plus>;
> +reset-gpios = < 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */
> +};
> +
> +reg_gmac_3v3: gmac-3v3 {
> +compatible = "regulator-fixed";
> +pinctrl-names = "default";
> +pinctrl-0 = <_power_pin_bananapi>;
> +regulator-name = "gmac-3v3";
> +regulator-min-microvolt = <330>;
> +regulator-max-microvolt = <330>;
> +startup-delay-us = <10>;
> +enable-active-high;
> +gpio = < 7 23 GPIO_ACTIVE_HIGH>;
> +};
> +
> +};
> +
> + {
> +status = "okay";
> +};
> +
> + {
> +status = "okay";
> +};
> +
> + {
> +status = "okay";
> +};
> +
> + {
> +status = "okay";
> +};
> +
> + {
> +pinctrl-names = "default";
> +pinctrl-0 = 

[linux-sunxi] [PATCH 4/6] ARM: sunxi_defconfig: Enable INPUT_EVDEV so axp20x-pek can be used

[Chen-Yu Tsai]

sunxi_defconfig already enables INPUT_AXP20X_PEK, but the device is not
exposed to userspace. Enable INPUT_EVDEV so it is.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/configs/sunxi_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index e29b81694184..a3a27e830ef9 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -58,6 +58,7 @@ CONFIG_STMMAC_ETH=y
 # CONFIG_NET_VENDOR_WIZNET is not set
 # CONFIG_WLAN is not set
 # CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_SUN4I_LRADC=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
-- 
2.7.0

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[linux-sunxi] [PATCH 1/6] ARM: sunxi_defconfig: Enable sunxi IR driver

[Chen-Yu Tsai]

A consumer IR receiver is commonly found on Allwinner SoC based
development boards and set top boxes. The driver has been available
for some time. Enable it by default.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/configs/sunxi_defconfig | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index a9a81a714be4..7d2e7bf81a47 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -92,6 +92,10 @@ CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_AXP20X=y
 CONFIG_REGULATOR_GPIO=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_RC_SUPPORT=y
+CONFIG_RC_DEVICES=y
+CONFIG_IR_SUNXI=y
 CONFIG_FB=y
 CONFIG_FB_SIMPLE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
-- 
2.7.0

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[linux-sunxi] [PATCH 0/6] ARM: defconfig: Enable recently merged drivers for sunxi

[Chen-Yu Tsai]

Hi everyone,

This series enables drivers for devices that are likely to be used on sunxi.
This includes the IR receiver, audio codec, USB OTG, and also enabling input
device interface in userspace so the power button works.

The patches are self-explanatory.

MUSB for USB OTG is enabled only now because it used to require USB gadget
drivers as modules to work reliably. It was an issue of probe ordering. This
has since been fixed (or worked around) in 4.5-rc1.

The IR receiver driver isn't enabled for multi_v7_defconfig, as I didn't see
any others enabled. On the other hand, MUSB is enabled, because for tablets
this is likely the only option for external USB peripherals.

Regards
ChenYu


Chen-Yu Tsai (6):
  ARM: sunxi_defconfig: Enable sunxi IR driver
  ARM: sunxi_defconfig: Enable A10 audio codec driver
  ARM: sunxi_defconfig: Enable MUSB HDRC driver with Allwinner glue
  ARM: sunxi_defconfig: Enable INPUT_EVDEV so axp20x-pek can be used
  ARM: multi_v7_defconfig: Enable A10 audio codec driver as module
  ARM: multi_v7_defconfig: Enable MUSB HDRC driver with Allwinner glue

 arch/arm/configs/multi_v7_defconfig |  3 +++
 arch/arm/configs/sunxi_defconfig| 14 ++
 2 files changed, 17 insertions(+)

-- 
2.7.0

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[linux-sunxi] [PATCH 3/6] ARM: sunxi_defconfig: Enable MUSB HDRC driver with Allwinner glue

[Chen-Yu Tsai]

Allwinner SoCs typically have a Mentor Graphics Inventra MUSB dual role
controller for USB OTG.

Now that the issue with MUSB and USB gadget registration order has been
resolved, we can enable this driver in dual role mode. This requires the
NOP USB transceiver driver, which is also enabled.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/configs/sunxi_defconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index efa12c88fe1c..e29b81694184 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -109,6 +109,11 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_HCD_PLATFORM=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_CDC_COMPOSITE=y
 CONFIG_MMC=y
 CONFIG_MMC_SUNXI=y
 CONFIG_NEW_LEDS=y
-- 
2.7.0

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[linux-sunxi] [PATCH 5/6] ARM: multi_v7_defconfig: Enable A10 audio codec driver as module

[Chen-Yu Tsai]

The A10 audio codec driver supports the on-chip audio codec found on
Allwinner A10, A10s, A13, A20 SoCs.

Build it as a module, since it is not critical.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig 
b/arch/arm/configs/multi_v7_defconfig
index 314f6be2dca2..03703b7ea530 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -559,6 +559,7 @@ CONFIG_SND_SOC_ROCKCHIP_RT5645=m
 CONFIG_SND_SOC_SH4_FSI=m
 CONFIG_SND_SOC_RCAR=m
 CONFIG_SND_SOC_RSRC_CARD=m
+CONFIG_SND_SUN4I_CODEC=m
 CONFIG_SND_SOC_SAMSUNG=m
 CONFIG_SND_SOC_SNOW=m
 CONFIG_SND_SOC_ODROIDX2=m
-- 
2.7.0

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[linux-sunxi] [PATCH 6/6] ARM: multi_v7_defconfig: Enable MUSB HDRC driver with Allwinner glue

[Chen-Yu Tsai]

Allwinner SoCs typically have a Mentor Graphics Inventra MUSB high speed
dual role controller for USB OTG.

Now that the issue with MUSB and USB gadget registration order has been
resolved, we can enable this driver in dual role mode.

This patch only enables the driver core and Allwinner platform support.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/configs/multi_v7_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/multi_v7_defconfig 
b/arch/arm/configs/multi_v7_defconfig
index 03703b7ea530..b500f18d0c35 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -592,6 +592,8 @@ CONFIG_USB_OHCI_EXYNOS=m
 CONFIG_USB_R8A66597_HCD=m
 CONFIG_USB_RENESAS_USBHS=m
 CONFIG_USB_STORAGE=y
+CONFIG_USB_MUSB_HDRC=m
+CONFIG_USB_MUSB_SUNXI=m
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC2=m
 CONFIG_USB_CHIPIDEA=y
-- 
2.7.0

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[linux-sunxi] [PATCH 2/6] ARM: sunxi_defconfig: Enable A10 audio codec driver

[Chen-Yu Tsai]

The A10 audio codec driver supports the on-chip audio codec found on
Allwinner A10, A10s, A13, A20 SoCs.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/configs/sunxi_defconfig | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 7d2e7bf81a47..efa12c88fe1c 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -100,6 +100,10 @@ CONFIG_FB=y
 CONFIG_FB_SIMPLE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SUN4I_CODEC=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_HCD_PLATFORM=y
-- 
2.7.0

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[linux-sunxi] Re: [PATCH 07/11] ARM: dts: sunxi: Add dtsi file for AXP809 PMIC

[Chen-Yu Tsai]

On Tue, Feb 2, 2016 at 8:17 PM, Mark Brown <broo...@kernel.org> wrote:
> On Tue, Feb 02, 2016 at 06:27:40PM +0800, Chen-Yu Tsai wrote:
>
>> + reg_dcdc1: dcdc1 {
>> + regulator-name = "dcdc1";
>> + };
>
> Why is this generic DTS include specifying regulator names?

My intent is to provide better looking names by default.
I just realized I could do this in the driver by replacing
a few fields.

But I still might need to do this for the AXP806, which
is a slave PMIC also used with A80 SoCs. The names overlap
with the AXP809. Allwinner gets around this by adding a
"s_" prefix to them. I suppose that works too.

Mark, may I assume you are OK with this DTS include listing
the regulators, even if their sections are empty?

>
>> + reg_rtc_ldo: rtc_ldo {
>> + /* RTC_LDO is a fixed, always-on regulator */
>> + regulator-always-on;
>> + regulator-min-microvolt = <180>;
>> + regulator-max-microvolt = <180>;
>
> If the regulator itself is limited in this way there is no need to
> specify this in the DTS.

Will remove.

Thanks
ChenYu

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[linux-sunxi] Re: [PATCH 07/11] ARM: dts: sunxi: Add dtsi file for AXP809 PMIC

[Chen-Yu Tsai]

On Tue, Feb 9, 2016 at 12:22 AM, Mark Brown <broo...@kernel.org> wrote:
> On Mon, Feb 08, 2016 at 10:56:05PM +0800, Chen-Yu Tsai wrote:
>> On Mon, Feb 8, 2016 at 10:53 PM, Mark Brown <broo...@kernel.org> wrote:
>> > On Sat, Feb 06, 2016 at 08:42:24PM +0800, Chen-Yu Tsai wrote:
>
>> >> Mark, may I assume you are OK with this DTS include listing
>> >> the regulators, even if their sections are empty?
>
>> > If it has no content why have it?
>
>> I'd like the regulator core to disable any unused ones. The core
>> considers regulators that don't have nodes as not having constraints,
>> and won't touch them.
>
>> Any other ways to do this? Or am I going about this the wrong way?
>
> The whole point with constraints is that they describe what is safe on a
> given board.  This includes powering off unused regulators - it should
> be something that the system integrator configures, not something that
> they get as default.

OK. So how should one describe a regulator as unused? Just leave it out
since it's not wired to anything? Or have an empty node at the board
level? One of the regulators involved on my board is by (hardware)
default on.

Thanks
ChenYu

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[linux-sunxi] Re: [PATCH 07/11] ARM: dts: sunxi: Add dtsi file for AXP809 PMIC

[Chen-Yu Tsai]

On Mon, Feb 8, 2016 at 10:53 PM, Mark Brown <broo...@kernel.org> wrote:
> On Sat, Feb 06, 2016 at 08:42:24PM +0800, Chen-Yu Tsai wrote:
>
>> Mark, may I assume you are OK with this DTS include listing
>> the regulators, even if their sections are empty?
>
> If it has no content why have it?

I'd like the regulator core to disable any unused ones. The core
considers regulators that don't have nodes as not having constraints,
and won't touch them.

Any other ways to do this? Or am I going about this the wrong way?

Thanks
ChenYu

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[linux-sunxi] Re: [PATCH 3/6] ARM: sunxi_defconfig: Enable MUSB HDRC driver with Allwinner glue

[Chen-Yu Tsai]

On Tue, Feb 9, 2016 at 4:15 PM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi,
>
> On Sat, Feb 06, 2016 at 11:53:46PM +0800, Chen-Yu Tsai wrote:
>> Allwinner SoCs typically have a Mentor Graphics Inventra MUSB dual role
>> controller for USB OTG.
>>
>> Now that the issue with MUSB and USB gadget registration order has been
>> resolved, we can enable this driver in dual role mode. This requires the
>> NOP USB transceiver driver, which is also enabled.
>>
>> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
>> ---
>>  arch/arm/configs/sunxi_defconfig | 5 +
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/configs/sunxi_defconfig 
>> b/arch/arm/configs/sunxi_defconfig
>> index efa12c88fe1c..e29b81694184 100644
>> --- a/arch/arm/configs/sunxi_defconfig
>> +++ b/arch/arm/configs/sunxi_defconfig
>> @@ -109,6 +109,11 @@ CONFIG_USB_EHCI_HCD=y
>>  CONFIG_USB_EHCI_HCD_PLATFORM=y
>>  CONFIG_USB_OHCI_HCD=y
>>  CONFIG_USB_OHCI_HCD_PLATFORM=y
>> +CONFIG_USB_MUSB_HDRC=y
>> +CONFIG_USB_MUSB_SUNXI=y
>> +CONFIG_NOP_USB_XCEIV=y
>> +CONFIG_USB_GADGET=y
>> +CONFIG_USB_CDC_COMPOSITE=y
>
> I'd prefer not to have any default gadget here, just like you did on
> multi_v7.

FYI the default here (in Kconfig) would be CONFIG_USB_ETH
"Ethernet Gadget (with CDC Ethernet support)".

CDC_COMPOSITE (CDC Ethernet + serial) is somewhat more useful.
But I'll change it.

ChenYu

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[linux-sunxi] Re: [PATCH v3 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set

[Chen-Yu Tsai]

On Thu, Feb 4, 2016 at 7:33 AM, Krzysztof Adamski <k...@japko.eu> wrote:
> sunxi_pmx_set accepts pin number and then calculates offset by
> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
> gets offset so we have to convert it to pin number so we won't get
> negative value in sunxi_pmx_set.
>
> This was only used on A10 so far, where there is only one GPIO chip with
> pin_base set to 0 so it didn't matter. However H3 also requires this
> workaround but have two pinmux sections, triggering problem for PL port.
>
> Signed-off-by: Krzysztof Adamski <k...@japko.eu>

Acked-by: Chen-Yu Tsai <w...@csie.org>

(resent as my mail setup failed to deliver)

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[linux-sunxi] Re: [PATCH v2 10/26] ARM: sun5i: a13: Add display and TCON clocks

[Chen-Yu Tsai]

On Thu, Feb 4, 2016 at 4:31 AM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi,
>
> On Sun, Jan 17, 2016 at 01:06:07AM +0800, Chen-Yu Tsai wrote:
>> > +   compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
>> > +   reg = <0x01c20118 0x4>;
>> > +   clocks = <>, <>, <>, <>;
>> > +   clock-output-names = "tcon-ch0-sclk";
>> > +   };
>> > +
>> > +   tcon_ch1_clk: clk@01c2012c {
>> > +   #clock-cells = <0>;
>> > +   compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
>> > +   reg = <0x01c2012c 0x4>;
>> > +   clocks = <>, <>, <>, <>;
>> > +   clock-output-names = "tcon-ch1-sclk";
>> > +   };
>>
>> I suggest moving these to sun5i.dtsi, as they are shared amongst them.
>
> Eventually, yes, but I don't have an a10s board handy, and I couldn't
> test the clocks that needs to be taken by simplefb.
>
> Once properly tested, they can definitely be moved to sun5i.dtsi.

Acked-by: Chen-Yu Tsai <w...@csie.org>

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[linux-sunxi] [PATCH v2 0/2] clk: sunxi: Fix APBS clock for Allwinner A80

[Chen-Yu Tsai]

Hi everyone,

This is v2 of the A80 APBS clock fixes series.

When I did the A80 PRCM support, I failed to notice the A80's APBS clock
was not the same as the A23's APB0 clock. The former is a zero-based
divider, while the latter is a power-of-two divider. But the lowest 2
dividers are the same.

The hardware defaults to the lowest setting, or a /1 divider. Since the
child gates do not propagate clk_set_rate up, and no consumers here do
clk_set_rate, this actually works.

I realized my mistake while reviewing the A83T's PRCM patches. The A83T
shares the same PRCM clocks as the A80.

Maxime, since this was introduced in 4.5-rc1, please apply this series
for 4.5 so we fix it before the release.


Changes since v1:

  - Replace the CLK_OF_DECLARE version of sun8i-a23-apb0-clk with the
A80 APBS version, instead of writing a new driver.

Regards
ChenYu


Chen-Yu Tsai (2):
  clk: sunxi: Add support for A80 APBS clock
  ARM: dts: sun9i: Fix apbs clock compatible

 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 arch/arm/boot/dts/sun9i-a80.dtsi  |  2 +-
 drivers/clk/sunxi/clk-sun8i-apb0.c| 23 ---
 3 files changed, 10 insertions(+), 16 deletions(-)

-- 
2.7.0

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[linux-sunxi] [PATCH v2 1/2] clk: sunxi: Add support for A80 APBS clock

[Chen-Yu Tsai]

A80's APBS clock is not the same as the APB0 clock on A23. The A80's
is a zero-based divider, while the A23's is a power-of-two divider.

Replace the CLK_OF_DECLARE version of sun8i-a23-apb0. This also extends
the common setup function to take div clk flags.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/clk-sun8i-apb0.c| 23 ---
 2 files changed, 9 insertions(+), 15 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 966dcaffcb9c..5206e48694d6 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -60,6 +60,7 @@ Required properties:
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
"allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T
"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
+   "allwinner,sun9i-a80-apbs-clk" - for the APBS clock on A80
"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
diff --git a/drivers/clk/sunxi/clk-sun8i-apb0.c 
b/drivers/clk/sunxi/clk-sun8i-apb0.c
index 7ba61103a6f5..cfe9c19a831b 100644
--- a/drivers/clk/sunxi/clk-sun8i-apb0.c
+++ b/drivers/clk/sunxi/clk-sun8i-apb0.c
@@ -21,7 +21,7 @@
 #include 
 
 static struct clk *sun8i_a23_apb0_register(struct device_node *node,
-  void __iomem *reg)
+  void __iomem *reg, u8 div_flags)
 {
const char *clk_name = node->name;
const char *clk_parent;
@@ -36,7 +36,7 @@ static struct clk *sun8i_a23_apb0_register(struct device_node 
*node,
 
/* The A23 APB0 clock is a standard 2 bit wide divider clock */
clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg,
-  0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
+  0, 2, div_flags, NULL);
if (IS_ERR(clk))
return clk;
 
@@ -52,7 +52,7 @@ err_unregister:
return ERR_PTR(ret);
 }
 
-static void sun8i_a23_apb0_setup(struct device_node *node)
+static void sun9i_a80_apbs_setup(struct device_node *node)
 {
void __iomem *reg;
struct resource res;
@@ -60,18 +60,11 @@ static void sun8i_a23_apb0_setup(struct device_node *node)
 
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
-   /*
-* This happens with clk nodes instantiated through mfd,
-* as those do not have their resources assigned in the
-* device tree. Do not print an error in this case.
-*/
-   if (PTR_ERR(reg) != -EINVAL)
-   pr_err("Could not get registers for a23-apb0-clk\n");
-
+   pr_err("Could not get registers for a80-apbs-clk\n");
return;
}
 
-   clk = sun8i_a23_apb0_register(node, reg);
+   clk = sun8i_a23_apb0_register(node, reg, 0);
if (IS_ERR(clk))
goto err_unmap;
 
@@ -82,8 +75,8 @@ err_unmap:
of_address_to_resource(node, 0, );
release_mem_region(res.start, resource_size());
 }
-CLK_OF_DECLARE(sun8i_a23_apb0, "allwinner,sun8i-a23-apb0-clk",
-  sun8i_a23_apb0_setup);
+CLK_OF_DECLARE(sun9i_a80_apbs, "allwinner,sun9i-a80-apbs-clk",
+  sun9i_a80_apbs_setup);
 
 static int sun8i_a23_apb0_clk_probe(struct platform_device *pdev)
 {
@@ -97,7 +90,7 @@ static int sun8i_a23_apb0_clk_probe(struct platform_device 
*pdev)
if (IS_ERR(reg))
return PTR_ERR(reg);
 
-   clk = sun8i_a23_apb0_register(np, reg);
+   clk = sun8i_a23_apb0_register(np, reg, CLK_DIVIDER_POWER_OF_TWO);
if (IS_ERR(clk))
return PTR_ERR(clk);
 
-- 
2.7.0

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[linux-sunxi] [PATCH v2 2/2] ARM: dts: sun9i: Fix apbs clock compatible

[Chen-Yu Tsai]

The APBS clock on A80 is not compatible with A23's APB0 clock. The only
reason it works is becase the lowest and default divider is the same.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index f68b3242b33a..2b4ce813b0ad 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -395,7 +395,7 @@
};
 
apbs: clk@0800141c {
-   compatible = "allwinner,sun8i-a23-apb0-clk";
+   compatible = "allwinner,sun9i-a80-apbs-clk";
reg = <0x0800141c 0x4>;
#clock-cells = <0>;
clocks = <>;
-- 
2.7.0

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[linux-sunxi] Re: [PATCH 10/14] ARM: dts: sun8i-a83t: Add PRCM related clocks and resets

[Chen-Yu Tsai]

On Sat, Feb 13, 2016 at 12:06 AM, Vishnu Patekar
<vishnupatekar0...@gmail.com> wrote:
> Hello Wens,
>
>
> On Tue, Feb 2, 2016 at 2:44 PM, Chen-Yu Tsai <w...@csie.org> wrote:
>> On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
>> <vishnupatekar0...@gmail.com> wrote:
>>> This adds A83T PRCM related clocks, clock resets.
>>>
>>> As a83t apb0 gates clock support is added earlier, this enables it.
>>> Apart from apb0 gates, other added clocks are compatible with
>>> earlier sun8i socs.
>>>
>>> Signed-off-by: Vishnu Patekar <vishnupatekar0...@gmail.com>
>>> ---
>>>  arch/arm/boot/dts/sun8i-a83t.dtsi | 44 
>>> +++
>>>  1 file changed, 44 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
>>> b/arch/arm/boot/dts/sun8i-a83t.dtsi
>>> index ac96aa1..5ea20ff 100644
>>> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
>>> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
>>> @@ -268,6 +268,44 @@
>>>  "mmc2_output",
>>>  "mmc2_sample";
>>> };
>>> +
>>> +   cpus_clk: clk@01f01400 {
>>> +   compatible = "allwinner,sun9i-a80-cpus-clk";
>>> +   reg = <0x01f01400 0x4>;
>>> +   #clock-cells = <0>;
>>> +   clocks = <>, <>, <>, 
>>> <>;
>>> +   clock-output-names = "cpus";
>>> +   };
>>> +
>>> +   ahb0: ahb0_clk {
>>> +   compatible = "fixed-factor-clock";
>>> +   #clock-cells = <0>;
>>> +   clock-div = <1>;
>>> +   clock-mult = <1>;
>>> +   clocks = <_clk>;
>>> +   clock-output-names = "ahb0";
>>> +   };
>>> +
>>> +   apb0: clk@01f0140c {
>>> +   compatible = "allwinner,sun8i-a23-apb0-clk";
>>
>> This is actually wrong, as it is wrong in sun9i-a80.dtsi.
>> I've sent a patch series for it.
> A83T apb0 is different from A80, and it's same as A23, so this should
> be correct.
> Please correct me in case I'm missing something.

My user manual (v1.5.1) says A83T apb0 dividers (page. 246) are
/1, /2, /3, /4, while the A23 is /1, /2, /4, /8.

ChenYu

>> Also the drivers for "allwinner,sun9i-a80-cpus-clk" and
>> "allwinner,sun9i-a80-apbs-clk"
>> are only compiled for CONFIG_MACH_SUN9I. Please add a patch to address this.
> Okie.
>>
>> Regards
>> ChenYu
>>
>>> +   reg = <0x01f0140c 0x4>;
>>> +   #clock-cells = <0>;
>>> +   clocks = <>;
>>> +   clock-output-names = "apb0";
>>> +   };
>>> +
>>> +   apb0_gates: clk@01f01428 {
>>> +   compatible = "allwinner,sun8i-a83t-apb0-gates-clk";
>>> +   reg = <0x01f01428 0x4>;
>>> +   #clock-cells = <1>;
>>> +   clocks = <>;
>>> +   clock-indices = <0>, <1>,
>>> +   <2>, <3>,
>>> +   <4>, <6>, <7>;
>>> +   clock-output-names = "apb0_pio", "apb0_ir",
>>> +   "apb0_timer", "apb0_rsb",
>>> +   "apb0_uart", "apb0_i2c0", 
>>> "apb0_twd";
>>> +   };
>>> };
>>>
>>> soc {
>>> @@ -434,5 +472,11 @@
>>> #interrupt-cells = <3>;
>>> interrupts = >> IRQ_TYPE_LEVEL_HIGH)>;
>>> };
>>> +
>>> +   apb0_reset: reset@01f014b0 {
>>> +   reg = <0x01f014b0 0x4>;
>>> +   compatible = "allwinner,sun6i-a31-clock-reset";
>>> +   #reset-cells = <1>;
>>> +   };
>>> };
>>>  };
>>> --
>>> 1.9.1
>>>

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[linux-sunxi] Re: [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set

[Chen-Yu Tsai]

Hi,

On Thu, Feb 11, 2016 at 9:17 PM, Linus Walleij  wrote:
> On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski  wrote:
>
>> sunxi_pmx_set accepts pin number and then calculates offset by
>> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
>> gets offset so we have to convert it to pin number so we won't get
>> negative value in sunxi_pmx_set.
>>
>> This was only used on A10 so far, where there is only one GPIO chip with
>> pin_base set to 0 so it didn't matter. However H3 also requires this
>> workaround but have two pinmux sections, triggering problem for PL port.
>>
>> Signed-off-by: Krzysztof Adamski 
>
> Waiting for Maxime to review this. I guess this patch can be merged
> independently of the other patches?

FYI there's a v4 of this patch that both Maxime and I acked.

ChenYu

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[linux-sunxi] [PATCH v8 01/10] mfd: axp20x: Add AXP223 to list of supported PMICs in DT bindings

[Chen-Yu Tsai]

The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Acked-by: Rob Herring <r...@kernel.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
 Documentation/devicetree/bindings/mfd/axp20x.txt | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt 
b/Documentation/devicetree/bindings/mfd/axp20x.txt
index a474359dd206..fd39fa54571b 100644
--- a/Documentation/devicetree/bindings/mfd/axp20x.txt
+++ b/Documentation/devicetree/bindings/mfd/axp20x.txt
@@ -5,11 +5,12 @@ axp152 (X-Powers)
 axp202 (X-Powers)
 axp209 (X-Powers)
 axp221 (X-Powers)
+axp223 (X-Powers)
 
 Required properties:
 - compatible: "x-powers,axp152", "x-powers,axp202", "x-powers,axp209",
- "x-powers,axp221"
-- reg: The I2C slave address for the AXP chip
+ "x-powers,axp221", "x-powers,axp223"
+- reg: The I2C slave address or RSB hardware address for the AXP chip
 - interrupt-parent: The parent interrupt controller
 - interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin
 - interrupt-controller: The PMIC has its own internal IRQs
@@ -51,7 +52,7 @@ LDO3  : LDO   : ldo3in-supply
 LDO4   : LDO   : ldo24in-supply: shared supply
 LDO5   : LDO   : ldo5in-supply
 
-AXP221 regulators, type, and corresponding input supply names:
+AXP221/AXP223 regulators, type, and corresponding input supply names:
 
 RegulatorTypeSupply Name Notes
 ---- -
-- 
2.7.0

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[linux-sunxi] [PATCH v8 10/10] ARM: dts: sun8i: q8-common: Add AXP223 PMIC device and regulator nodes

[Chen-Yu Tsai]

A23/A33 Q8 tablets have an X-Powers AXP223 PMIC connected via RSB. Its
regulators provide power to various parts of the SoC and the board.

Also add lcd regulator supply for simplefb and update the existing
vmmc-supply for mmc0.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-q8-common.dtsi | 83 +-
 1 file changed, 81 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi 
b/arch/arm/boot/dts/sun8i-q8-common.dtsi
index 1a69231d2da5..9d2b7e2f5975 100644
--- a/arch/arm/boot/dts/sun8i-q8-common.dtsi
+++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi
@@ -56,7 +56,6 @@
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
enable-gpios = < 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
-   /* backlight is powered by AXP223 DC1SW */
};
 
chosen {
@@ -67,7 +66,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin_q8>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <4>;
cd-gpios = < 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
cd-inverted;
@@ -92,6 +91,82 @@
 
 _rsb {
status = "okay";
+
+   axp22x: pmic@3a3 {
+   compatible = "x-powers,axp223";
+   reg = <0x3a3>;
+   interrupt-parent = <_intc>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   eldoin-supply = <_dcdc1>;
+   };
+};
+
+#include "axp22x.dtsi"
+
+_aldo1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-io";
+};
+
+_aldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <235>;
+   regulator-max-microvolt = <265>;
+   regulator-name = "vdd-dll";
+};
+
+_aldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <270>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pll-avcc";
+};
+
+_dc1sw {
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-lcd";
+};
+
+_dc5ldo {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpus";
+};
+
+_dcdc1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-3v0";
+};
+
+_dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-sys";
+};
+
+_dcdc3 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpu";
+};
+
+_dcdc5 {
+   regulator-always-on;
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <150>;
+   regulator-name = "vcc-dram";
+};
+
+_rtc_ldo {
+   regulator-name = "vcc-rtc";
 };
 
 _uart {
@@ -99,3 +174,7 @@
pinctrl-0 = <_uart_pins_a>;
status = "okay";
 };
+
+_lcd {
+   vcc-lcd-supply = <_dc1sw>;
+};
-- 
2.7.0

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[linux-sunxi] [PATCH v8 05/10] mfd: axp20x: Split the driver into core and i2c bits

[Chen-Yu Tsai]

The axp20x driver assumes the device is i2c based. This is not the
case with later chips, which use a proprietary 2 wire serial bus
by Allwinner called "Reduced Serial Bus".

This patch follows the example of mfd/wm831x and splits it into
an interface independent core, and an i2c specific glue layer.
MFD_AXP20X and the new MFD_AXP20X_I2C are changed to tristate
symbols, allowing the driver to be built as modules.

Whitespace and other style errors in the moved i2c specific code
have been fixed. Included but unused header files are removed as
well.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
 drivers/mfd/Kconfig|  14 +++---
 drivers/mfd/Makefile   |   1 +
 drivers/mfd/axp20x-i2c.c   | 104 +
 drivers/mfd/axp20x.c   |  90 +++
 include/linux/mfd/axp20x.h |  33 +-
 5 files changed, 161 insertions(+), 81 deletions(-)
 create mode 100644 drivers/mfd/axp20x-i2c.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 9ca66de0c1c1..0037b9c933d9 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -91,14 +91,18 @@ config MFD_BCM590XX
  Support for the BCM590xx PMUs from Broadcom
 
 config MFD_AXP20X
-   bool "X-Powers AXP20X"
+   tristate
select MFD_CORE
-   select REGMAP_I2C
select REGMAP_IRQ
-   depends on I2C=y
+
+config MFD_AXP20X_I2C
+   tristate "X-Powers AXP series PMICs with I2C"
+   select MFD_AXP20X
+   select REGMAP_I2C
+   depends on I2C
help
- If you say Y here you get support for the X-Powers AXP202, AXP209 and
- AXP288 power management IC (PMIC).
+ If you say Y here you get support for the X-Powers AXP series power
+ management ICs (PMICs) controlled with I2C.
  This driver include only the core APIs. You have to select individual
  components like regulators or the PEK (Power Enable Key) under the
  corresponding menus.
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 0f230a6103f8..dba4f99d9044 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -111,6 +111,7 @@ obj-$(CONFIG_PMIC_DA9052)   += da9052-core.o
 obj-$(CONFIG_MFD_DA9052_SPI)   += da9052-spi.o
 obj-$(CONFIG_MFD_DA9052_I2C)   += da9052-i2c.o
 obj-$(CONFIG_MFD_AXP20X)   += axp20x.o
+obj-$(CONFIG_MFD_AXP20X_I2C)   += axp20x-i2c.o
 
 obj-$(CONFIG_MFD_LP3943)   += lp3943.o
 obj-$(CONFIG_MFD_LP8788)   += lp8788.o lp8788-irq.o
diff --git a/drivers/mfd/axp20x-i2c.c b/drivers/mfd/axp20x-i2c.c
new file mode 100644
index ..b1b865822c07
--- /dev/null
+++ b/drivers/mfd/axp20x-i2c.c
@@ -0,0 +1,104 @@
+/*
+ * I2C driver for the X-Powers' Power Management ICs
+ *
+ * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK 
DC-DC
+ * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
+ * as well as configurable GPIOs.
+ *
+ * This driver supports the I2C variants.
+ *
+ * Copyright (C) 2014 Carlo Caione
+ *
+ * Author: Carlo Caione <ca...@caione.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static int axp20x_i2c_probe(struct i2c_client *i2c,
+   const struct i2c_device_id *id)
+{
+   struct axp20x_dev *axp20x;
+   int ret;
+
+   axp20x = devm_kzalloc(>dev, sizeof(*axp20x), GFP_KERNEL);
+   if (!axp20x)
+   return -ENOMEM;
+
+   axp20x->dev = >dev;
+   axp20x->irq = i2c->irq;
+   dev_set_drvdata(axp20x->dev, axp20x);
+
+   ret = axp20x_match_device(axp20x);
+   if (ret)
+   return ret;
+
+   axp20x->regmap = devm_regmap_init_i2c(i2c, axp20x->regmap_cfg);
+   if (IS_ERR(axp20x->regmap)) {
+   ret = PTR_ERR(axp20x->regmap);
+   dev_err(>dev, "regmap init failed: %d\n", ret);
+   return ret;
+   }
+
+   return axp20x_device_probe(axp20x);
+}
+
+static int axp20x_i2c_remove(struct i2c_client *i2c)
+{
+   struct axp20x_dev *axp20x = i2c_get_clientdata(i2c);
+
+   return axp20x_device_remove(axp20x);
+}
+
+static const struct of_device_id axp20x_i2c_of_match[] = {
+   { .compatible = "x-powers,axp152", .data = (void *)AXP152_ID },
+   { .compatible = "x-powers,axp202", .data = (void *)AXP202_ID },
+   { .compatible = "x-powers,axp209", .data = (void *)AXP209_ID },
+   { .compatible = "x-powers,axp221", .data = (void *)AXP221_ID },
+   { },
+};
+MODULE_DEVICE_TABLE(of, axp20x_i2c_of_match);
+
+/*
+ * This is useless for OF-enabled devices, but 

[linux-sunxi] [PATCH v8 02/10] mfd: axp20x: Remove second struct device * parameter for axp20x_match_device()

[Chen-Yu Tsai]

The first argument passed to axp20x_match_device(), struct axp20x_dev *,
already contains a pointer to the device. By rearranging some code,
moving the assignment of the pointer before axp20x_match_device() is
called, we can eliminate the second parameter.

Suggested-by: Andy Shevchenko <andy.shevche...@gmail.com>
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
 drivers/mfd/axp20x.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 9842199e2e6c..685a78614f83 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -606,8 +606,9 @@ static void axp20x_power_off(void)
 AXP20X_OFF);
 }
 
-static int axp20x_match_device(struct axp20x_dev *axp20x, struct device *dev)
+static int axp20x_match_device(struct axp20x_dev *axp20x)
 {
+   struct device *dev = axp20x->dev;
const struct acpi_device_id *acpi_id;
const struct of_device_id *of_id;
 
@@ -673,14 +674,14 @@ static int axp20x_i2c_probe(struct i2c_client *i2c,
if (!axp20x)
return -ENOMEM;
 
-   ret = axp20x_match_device(axp20x, >dev);
-   if (ret)
-   return ret;
-
axp20x->i2c_client = i2c;
axp20x->dev = >dev;
dev_set_drvdata(axp20x->dev, axp20x);
 
+   ret = axp20x_match_device(axp20x);
+   if (ret)
+   return ret;
+
axp20x->regmap = devm_regmap_init_i2c(i2c, axp20x->regmap_cfg);
if (IS_ERR(axp20x->regmap)) {
ret = PTR_ERR(axp20x->regmap);
-- 
2.7.0

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[linux-sunxi] [PATCH v8 04/10] mfd: axp20x: Add missing copyright notice

[Chen-Yu Tsai]

Supply a backdated copyright notice.

Cc: Carlo Caione <ca...@caione.org>
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Carlo Caione <ca...@caione.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
 drivers/mfd/axp20x.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 3e186f2dcac3..cec51e689d1d 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -5,6 +5,8 @@
  * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
  * as well as configurable GPIOs.
  *
+ * Copyright (C) 2014 Carlo Caione
+ *
  * Author: Carlo Caione <ca...@caione.org>
  *
  * This program is free software; you can redistribute it and/or modify
-- 
2.7.0

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[linux-sunxi] [PATCH v8 06/10] mfd: axp20x: Whitespace, open parenthesis alignment code style fixes

[Chen-Yu Tsai]

This fixes some leftover code style issues in the axp20x core.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
 drivers/mfd/axp20x.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 8e569bcfe3bc..3054ea4b95e8 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -593,14 +593,14 @@ int axp20x_match_device(struct axp20x_dev *axp20x)
dev_err(dev, "Unable to match OF ID\n");
return -ENODEV;
}
-   axp20x->variant = (long) of_id->data;
+   axp20x->variant = (long)of_id->data;
} else {
acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
if (!acpi_id || !acpi_id->driver_data) {
dev_err(dev, "Unable to match ACPI ID and data\n");
return -ENODEV;
}
-   axp20x->variant = (long) acpi_id->driver_data;
+   axp20x->variant = (long)acpi_id->driver_data;
}
 
switch (axp20x->variant) {
@@ -634,7 +634,7 @@ int axp20x_match_device(struct axp20x_dev *axp20x)
return -EINVAL;
}
dev_info(dev, "AXP20x variant %s found\n",
-   axp20x_model_names[axp20x->variant]);
+axp20x_model_names[axp20x->variant]);
 
return 0;
 }
@@ -654,7 +654,7 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
}
 
ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
-   axp20x->nr_cells, NULL, 0, NULL);
+ axp20x->nr_cells, NULL, 0, NULL);
 
if (ret) {
dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret);
-- 
2.7.0

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[linux-sunxi] [PATCH v8 07/10] mfd: axp20x: Add support for RSB based AXP223 PMIC

[Chen-Yu Tsai]

The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
 drivers/mfd/Kconfig| 11 +++
 drivers/mfd/Makefile   |  1 +
 drivers/mfd/axp20x-rsb.c   | 80 ++
 drivers/mfd/axp20x.c   |  2 ++
 include/linux/mfd/axp20x.h |  1 +
 5 files changed, 95 insertions(+)
 create mode 100644 drivers/mfd/axp20x-rsb.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 0037b9c933d9..ae3990b5a2bf 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -107,6 +107,17 @@ config MFD_AXP20X_I2C
  components like regulators or the PEK (Power Enable Key) under the
  corresponding menus.
 
+config MFD_AXP20X_RSB
+   tristate "X-Powers AXP series PMICs with RSB"
+   select MFD_AXP20X
+   depends on SUNXI_RSB
+   help
+ If you say Y here you get support for the X-Powers AXP series power
+ management ICs (PMICs) controlled with RSB.
+ This driver include only the core APIs. You have to select individual
+ components like regulators or the PEK (Power Enable Key) under the
+ corresponding menus.
+
 config MFD_CROS_EC
tristate "ChromeOS Embedded Controller"
select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index dba4f99d9044..c69ea744fd1a 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -112,6 +112,7 @@ obj-$(CONFIG_MFD_DA9052_SPI)+= da9052-spi.o
 obj-$(CONFIG_MFD_DA9052_I2C)   += da9052-i2c.o
 obj-$(CONFIG_MFD_AXP20X)   += axp20x.o
 obj-$(CONFIG_MFD_AXP20X_I2C)   += axp20x-i2c.o
+obj-$(CONFIG_MFD_AXP20X_RSB)   += axp20x-rsb.o
 
 obj-$(CONFIG_MFD_LP3943)   += lp3943.o
 obj-$(CONFIG_MFD_LP8788)   += lp8788.o lp8788-irq.o
diff --git a/drivers/mfd/axp20x-rsb.c b/drivers/mfd/axp20x-rsb.c
new file mode 100644
index ..28c20247c112
--- /dev/null
+++ b/drivers/mfd/axp20x-rsb.c
@@ -0,0 +1,80 @@
+/*
+ * RSB driver for the X-Powers' Power Management ICs
+ *
+ * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK 
DC-DC
+ * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
+ * as well as configurable GPIOs.
+ *
+ * This driver supports the RSB variants.
+ *
+ * Copyright (C) 2015 Chen-Yu Tsai
+ *
+ * Author: Chen-Yu Tsai <w...@csie.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static int axp20x_rsb_probe(struct sunxi_rsb_device *rdev)
+{
+   struct axp20x_dev *axp20x;
+   int ret;
+
+   axp20x = devm_kzalloc(>dev, sizeof(*axp20x), GFP_KERNEL);
+   if (!axp20x)
+   return -ENOMEM;
+
+   axp20x->dev = >dev;
+   axp20x->irq = rdev->irq;
+   dev_set_drvdata(>dev, axp20x);
+
+   ret = axp20x_match_device(axp20x);
+   if (ret)
+   return ret;
+
+   axp20x->regmap = devm_regmap_init_sunxi_rsb(rdev, axp20x->regmap_cfg);
+   if (IS_ERR(axp20x->regmap)) {
+   ret = PTR_ERR(axp20x->regmap);
+   dev_err(>dev, "regmap init failed: %d\n", ret);
+   return ret;
+   }
+
+   return axp20x_device_probe(axp20x);
+}
+
+static int axp20x_rsb_remove(struct sunxi_rsb_device *rdev)
+{
+   struct axp20x_dev *axp20x = sunxi_rsb_device_get_drvdata(rdev);
+
+   return axp20x_device_remove(axp20x);
+}
+
+static const struct of_device_id axp20x_rsb_of_match[] = {
+   { .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },
+   { },
+};
+MODULE_DEVICE_TABLE(of, axp20x_rsb_of_match);
+
+static struct sunxi_rsb_driver axp20x_rsb_driver = {
+   .driver = {
+   .name   = "axp20x-rsb",
+   .of_match_table = of_match_ptr(axp20x_rsb_of_match),
+   },
+   .probe  = axp20x_rsb_probe,
+   .remove = axp20x_rsb_remove,
+};
+module_sunxi_rsb_driver(axp20x_rsb_driver);
+
+MODULE_DESCRIPTION("PMIC MFD sunXi RSB driver for AXP20X");
+MODULE_AUTHOR("Chen-Yu Tsai <w...@csie.org>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 3054ea4b95e8..a57d6e940610 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -35,6 +35,7 @@ static const char * const axp20x_model_names[] = {
"AXP202",
"AXP209",
"AXP221",
+   "AXP223",
"AXP288",
 };
 
@@ -618,6 +619,7 @@ int axp20x_match_device(struct axp20x_dev *axp20x)
  

[linux-sunxi] [PATCH v8 00/10] mfd: axp20x: Add support for RSB based AXP223

[Chen-Yu Tsai]

Hi everyone,

This is v8 of the AXP223 PMIC series. All the driver bits are acked.
Lee, please merge the first 8 patches. Once they're in, Maxime can take
the DTS patches.

Changes since v7:

  - Shortened commit message of "mfd: axp20x: Add missing copyright notice"

Changes since v6:

  - Add copyright notice to axp20x-rsb.c

  - Correct order of header files in axp20x-rsb.c

  - Use generic dev_set_drvdata() instead of sunxi_rsb_device_set_drvdata()

  - Drop file name from file headers

  - Add patch adding missing copyright notice for original axp20x author

Changes since v5:

  - Correct AXP223 address to 0x3a3.

Changes since v4:

  - Get rid of second parameter of axp20x_match_device() (new patch 2)

  - Match against dev->driver->of_match_table, so the entirety of
axp20x_match_device() can be kept in the core. (new patch 3)

  - Move *_device_id tables to bottom of the driver, right above driver
declaration. (patch 4 & 6)

  - Remove extra whitespaces while moving i2c specific code (patch 4)

  - Remove leftover whitespace and code style issues in axp20x core
(new patch 5)

  - Remove extra whitespaces in rsb specific code (patch 6)

Changes since v3:

  - Removed settings for axp223 reg_rtc_ldo from board dts files that
are already in axp22x.dtsi. The name is kept.

  - Dropped simplefb label and defconfig patches, as they are merged.

Changes since v2:

  - s/It's/Its/ for the commit messages of patches 5 and 7

  - Add Rob's Acked-by for patch 1

Changes since v1:

  - Dropped NMI interrupt controller dts patch (Merged)

  - Change MFD_AXP20X to represent the axp20x core, and drop MFD_AXP20X_CORE
  
  - Keep the axp20x core bits named axp20x.c

  - Add patch 7 to add AXP223 to sun8i-q8-common.dtsi

  - Add patch 8 & 9 to update defconfigs

  - Make axp20x drivers tristate and buildable as modules

  - Drop "_sunxi" substring from identifiers in axp20x-rsb driver


This series adds support for the Reduced Serial Bus based AXP223 PMIC.
The AXP223 is functionally identical to the AXP221, which we already
support. Only some default values for the regulators are different.
The defaults fit their recommended application, paired with different
SoCs.

Patch 1 adds AXP223 to the list of supported chips in the DT binding.

Patch 2 gets rid of the extra "struct device *" parameter from
axp20x_match_device().

Patch 3 makes axp20x_match_device() use dev->driver->of_match_table,
so the function can be library-ized without modification.

Patch 4 adds the missing copyright notice for axp20x's original author.

Patch 5 splits the axp20x mfd driver into 2 parts, a core library, and
an I2C driver.

Patch 6 cleans up some leftover whitespace issues in axp20x core.

Patch 7 adds an RSB based driver for the AXP223.

Patch 8 adds support for the AXP223 regulators

Patch 9 enables the AXP223 PMIC and its regulators for the Sinlinx
SinA33.

Patch 10 enables the AXP223 PMIC and its regulators for A23/A33 based
Q8 tablet devices.


Regards
ChenYu


Chen-Yu Tsai (10):
  mfd: axp20x: Add AXP223 to list of supported PMICs in DT bindings
  mfd: axp20x: Remove second struct device * parameter for
axp20x_match_device()
  mfd: axp20x: use dev->driver->of_match_table in axp20x_match_device()
  mfd: axp20x: Add missing copyright notice
  mfd: axp20x: Split the driver into core and i2c bits
  mfd: axp20x: Whitespace, open parenthesis alignment code style fixes
  mfd: axp20x: Add support for RSB based AXP223 PMIC
  regulator: axp20x: Support new AXP223 PMIC
  ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator
nodes
  ARM: dts: sun8i: q8-common: Add AXP223 PMIC device and regulator nodes

 Documentation/devicetree/bindings/mfd/axp20x.txt |   7 +-
 arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts   |  76 +++-
 arch/arm/boot/dts/sun8i-q8-common.dtsi   |  83 +-
 drivers/mfd/Kconfig  |  25 --
 drivers/mfd/Makefile |   2 +
 drivers/mfd/axp20x-i2c.c | 104 ++
 drivers/mfd/axp20x-rsb.c |  80 +
 drivers/mfd/axp20x.c | 105 ++-
 drivers/regulator/axp20x-regulator.c |   3 +
 include/linux/mfd/axp20x.h   |  34 +++-
 10 files changed, 425 insertions(+), 94 deletions(-)
 create mode 100644 drivers/mfd/axp20x-i2c.c
 create mode 100644 drivers/mfd/axp20x-rsb.c

-- 
2.7.0

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[linux-sunxi] [PATCH v8 03/10] mfd: axp20x: use dev->driver->of_match_table in axp20x_match_device()

[Chen-Yu Tsai]

In axp20x_match_device(), match the of_device_id table bound to the
device driver instead of pointing to axp20x_of_match directly. This
will allow us to keep axp20x_match_device() unmodified when we expand
the axp20x driver into multiple ones covering different interface
types.

of_device_get_match_data() cannot be used here as we need to know if
it failed to get a match, or if the match data value just happened to
be 0, as it is for the AXP152.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
 drivers/mfd/axp20x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 685a78614f83..3e186f2dcac3 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -613,7 +613,7 @@ static int axp20x_match_device(struct axp20x_dev *axp20x)
const struct of_device_id *of_id;
 
if (dev->of_node) {
-   of_id = of_match_device(axp20x_of_match, dev);
+   of_id = of_match_device(dev->driver->of_match_table, dev);
if (!of_id) {
dev_err(dev, "Unable to match OF ID\n");
return -ENODEV;
-- 
2.7.0

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[linux-sunxi] [PATCH v8 08/10] regulator: axp20x: Support new AXP223 PMIC

[Chen-Yu Tsai]

The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Reviewed-by: Mark Brown <broo...@kernel.org>
---
 drivers/regulator/axp20x-regulator.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/regulator/axp20x-regulator.c 
b/drivers/regulator/axp20x-regulator.c
index f2e1a39ce0f3..e86d1fc2d80b 100644
--- a/drivers/regulator/axp20x-regulator.c
+++ b/drivers/regulator/axp20x-regulator.c
@@ -244,6 +244,7 @@ static int axp20x_set_dcdc_freq(struct platform_device 
*pdev, u32 dcdcfreq)
step = 75;
break;
case AXP221_ID:
+   case AXP223_ID:
min = 1800;
max = 4050;
def = 3000;
@@ -322,6 +323,7 @@ static int axp20x_set_dcdc_workmode(struct regulator_dev 
*rdev, int id, u32 work
break;
 
case AXP221_ID:
+   case AXP223_ID:
if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
return -EINVAL;
 
@@ -360,6 +362,7 @@ static int axp20x_regulator_probe(struct platform_device 
*pdev)
nregulators = AXP20X_REG_ID_MAX;
break;
case AXP221_ID:
+   case AXP223_ID:
regulators = axp22x_regulators;
nregulators = AXP22X_REG_ID_MAX;
break;
-- 
2.7.0

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[linux-sunxi] [PATCH v8 09/10] ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator nodes

[Chen-Yu Tsai]

This board has a X-Powers AXP223 PMIC connected via RSB. Its regulators
provide power to various parts of the SoC and the board.

Also update the regulator supply phandles.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 76 +-
 1 file changed, 73 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts 
b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
index bd2a3beb4629..fef6abc0a703 100644
--- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
@@ -68,7 +68,7 @@
 };
 
  {
-   vref-supply = <_vcc3v0>;
+   vref-supply = <_dcdc1>;
status = "okay";
 
button@200 {
@@ -96,7 +96,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin_sina33>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <4>;
cd-gpios = < 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
cd-inverted;
@@ -106,7 +106,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_8bit_pins>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
@@ -135,6 +135,76 @@
 
 _rsb {
status = "okay";
+
+   axp22x: pmic@3a3 {
+   compatible = "x-powers,axp223";
+   reg = <0x3a3>;
+   interrupt-parent = <_intc>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   eldoin-supply = <_dcdc1>;
+   };
+};
+
+#include "axp22x.dtsi"
+
+_aldo1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-io";
+};
+
+_aldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <235>;
+   regulator-max-microvolt = <265>;
+   regulator-name = "vdd-dll";
+};
+
+_aldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <270>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pll-avcc";
+};
+
+_dc5ldo {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpus";
+};
+
+_dcdc1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-3v0";
+};
+
+_dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-sys";
+};
+
+_dcdc3 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpu";
+};
+
+_dcdc5 {
+   regulator-always-on;
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <150>;
+   regulator-name = "vcc-dram";
+};
+
+_rtc_ldo {
+   regulator-name = "vcc-rtc";
 };
 
  {
-- 
2.7.0

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Re: [linux-sunxi] Re: [PATCH v7 04/10] mfd: axp20x: Add missing copyright notice

[Chen-Yu Tsai]

On Thu, Feb 11, 2016 at 11:24 PM, Lee Jones <lee.jo...@linaro.org> wrote:
> On Mon, 25 Jan 2016, Lee Jones wrote:
>
>> On Wed, 13 Jan 2016, Chen-Yu Tsai wrote:
>>
>> > When the driver was merged, the original author did not include a proper
>> > copyright notice. This patch adds the notice, backdated to when the
>> > driver was merged.
>>
>> This is very wordy.
>>
>> "Supply a backdated copyright notice."
>
> Can you re-submit this set with this fixed and the Acks you collected?

Just did. Hopefully you'll see it in your inbox, and not your spam folder.

Thanks
ChenYu

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[linux-sunxi] Re: [PATCH RFC 10/11] clk: sunxi: rewrite sun6i-ar100 using factors clk

[Chen-Yu Tsai]

On Mon, Feb 1, 2016 at 12:59 AM, Paul Gortmaker
<paul.gortma...@windriver.com> wrote:
> On Mon, Jan 25, 2016 at 8:15 AM, Chen-Yu Tsai <w...@csie.org> wrote:
>> sun6i's AR100 clock is a classic factors clk case:
>>
>> AR100 = ((parent mux) >> p) / (m + 1)
>>
>> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
>
> This patch adds a ".remove" function to a driver that is controlled by
> a bool Kconfig, and hence the remove code can't be called unless
> one explicitly goes into sysfs and muddles with the unbind as root
> (which normally has no sane use case for builtin, non-modular code).
>
> Since I'm trying to cut back on the amount of dead code we have
> in .remove functions for built in drivers, is there a valid use case
> for this one here, or can I just stage a delete commit for it too?

It's just there to balance the probe code. I thought it was missing.
But what you said makes sense. Go ahead.

> Normally I've set the set the disallow-unbind flag when deleting
> a .remove function to make it clear there is no sane use case
> for wandering into sysfs and unhooking the builtin driver.

Cool.

Thanks
ChenYu

>
> Thanks,
> Paul.
> --
>
>> ---
>>  drivers/clk/sunxi/clk-sun6i-ar100.c | 235 
>> ++--
>>  1 file changed, 61 insertions(+), 174 deletions(-)
>>
>> diff --git a/drivers/clk/sunxi/clk-sun6i-ar100.c 
>> b/drivers/clk/sunxi/clk-sun6i-ar100.c
>> index 20887686bdbe..a7f5777834eb 100644
>> --- a/drivers/clk/sunxi/clk-sun6i-ar100.c
>> +++ b/drivers/clk/sunxi/clk-sun6i-ar100.c
>> @@ -8,211 +8,97 @@
>>   *
>>   */
>>
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>
>> -#define SUN6I_AR100_MAX_PARENTS4
>> -#define SUN6I_AR100_SHIFT_MASK 0x3
>> -#define SUN6I_AR100_SHIFT_MAX  SUN6I_AR100_SHIFT_MASK
>> -#define SUN6I_AR100_SHIFT_SHIFT4
>> -#define SUN6I_AR100_DIV_MASK   0x1f
>> -#define SUN6I_AR100_DIV_MAX(SUN6I_AR100_DIV_MASK + 1)
>> -#define SUN6I_AR100_DIV_SHIFT  8
>> -#define SUN6I_AR100_MUX_MASK   0x3
>> -#define SUN6I_AR100_MUX_SHIFT  16
>> -
>> -struct ar100_clk {
>> -   struct clk_hw hw;
>> -   void __iomem *reg;
>> -};
>> -
>> -static inline struct ar100_clk *to_ar100_clk(struct clk_hw *hw)
>> -{
>> -   return container_of(hw, struct ar100_clk, hw);
>> -}
>> -
>> -static unsigned long ar100_recalc_rate(struct clk_hw *hw,
>> -  unsigned long parent_rate)
>> -{
>> -   struct ar100_clk *clk = to_ar100_clk(hw);
>> -   u32 val = readl(clk->reg);
>> -   int shift = (val >> SUN6I_AR100_SHIFT_SHIFT) & 
>> SUN6I_AR100_SHIFT_MASK;
>> -   int div = (val >> SUN6I_AR100_DIV_SHIFT) & SUN6I_AR100_DIV_MASK;
>> -
>> -   return (parent_rate >> shift) / (div + 1);
>> -}
>> -
>> -static int ar100_determine_rate(struct clk_hw *hw,
>> -   struct clk_rate_request *req)
>> -{
>> -   int nparents = clk_hw_get_num_parents(hw);
>> -   long best_rate = -EINVAL;
>> -   int i;
>> -
>> -   req->best_parent_hw = NULL;
>> -
>> -   for (i = 0; i < nparents; i++) {
>> -   unsigned long parent_rate;
>> -   unsigned long tmp_rate;
>> -   struct clk_hw *parent;
>> -   unsigned long div;
>> -   int shift;
>> -
>> -   parent = clk_hw_get_parent_by_index(hw, i);
>> -   parent_rate = clk_hw_get_rate(parent);
>> -   div = DIV_ROUND_UP(parent_rate, req->rate);
>> -
>> -   /*
>> -* The AR100 clk contains 2 divisors:
>> -* - one power of 2 divisor
>> -* - one regular divisor
>> -*
>> -* First check if we can safely shift (or divide by a power
>> -* of 2) without losing precision on the requested rate.
>> -*/
>> -   shift = ffs(div) - 1;
>> -   if (shift > SUN6I_AR100_SHIFT_MAX)
>> -   shift = SUN6I_AR100_SHIFT_MAX;
>> -
>> -   div >>= shift;
>> -
>> -   /*
>> -* Then if the divisor is still bigger than what the HW
>> -* actually supports, use a bigger shift (or power of 

[linux-sunxi] Re: [PATCH v3 4/5] ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi

[Chen-Yu Tsai]

On Thu, Feb 4, 2016 at 7:33 AM, Krzysztof Adamski  wrote:
> Add the corresponding device node for R_PIO on H3 to the dtsi. Support
> for the controller was added in earlier commit.
>
> Signed-off-by: Krzysztof Adamski 
> ---
>  arch/arm/boot/dts/sun8i-h3.dtsi | 12 
>  1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index bb37f52..f618a95 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -517,5 +517,17 @@
> compatible = "allwinner,sun6i-a31-clock-reset";
> #reset-cells = <1>;
> };
> +
> +   r_pio: pinctrl@01f02c00 {
> +   compatible = "allwinner,sun8i-h3-r-pinctrl";
> +   reg = <0x01f02c00 0x400>;
> +   interrupts = ;
> +   clocks = <_gates 0>;
> +   resets = <_reset 0>;
> +   gpio-controller;
> +   #gpio-cells = <3>;
> +   interrupt-controller;
> +   #interrupt-cells = <2>;

This should be 3: bank number + pin number + flags.
The rest looks good.

(resent as my mail setup failed to deliver)

> +   };
> };
>  };
> --
> 2.1.4
>

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[linux-sunxi] Re: [PATCH v2] pinctrl: sunxi: H3 requires irq_read_needs_mux

[Chen-Yu Tsai]

On Fri, Feb 5, 2016 at 9:39 PM, Linus Walleij <linus.wall...@linaro.org> wrote:
> On Wed, Feb 3, 2016 at 8:57 AM, Krzysztof Adamski <k...@japko.eu> wrote:
>
>> It seems that on H3, just like on A10, when GPIOs are configured as
>> external interrupt data registers does not contain their value.  When
>> value is read, GPIO function must be temporary switched to input for
>> reads.
>>
>> Signed-off-by: Krzysztof Adamski <k...@japko.eu>
>
> 1. Waiting for Maxime's ACK on this patch.

Maxime already acked v1.

Acked-by: Chen-Yu Tsai <w...@csie.org>

> 2. Is this a regression that need to go in to fixes?

This driver was introduced in 4.5-rc1. It'd be nice if this fix could make
it in 4.5. :)


Thanks
ChenYu

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[linux-sunxi] Re: [PATCH RFC 03/15] mmc: sunxi: Block signal voltage switching (CMD11)

[Chen-Yu Tsai]

On Fri, Jan 29, 2016 at 6:42 PM, Ulf Hansson <ulf.hans...@linaro.org> wrote:
> On 21 January 2016 at 06:26, Chen-Yu Tsai <w...@csie.org> wrote:
>> Allwinner's mmc controller supports signal voltage switching. This is
>> supported in code in Allwinner's kernel. However, publicly available
>> boards all tie it to a fixed 3.0/3.3V regulator, with options to tie
>> it to 1.8V for eMMC on some.
>>
>> Since Allwinner's kernel is an ancient 3.4, it is hard to say whether
>> adapting it's code to a modern mainline kernel would work. Block signal
>> voltage switching until someone has proper hardware to implement and
>> test this.
>>
>> This only affects SD UHS-1 modes, as eMMC switches the voltage directly
>> without any signaling.
>>
>> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
>> ---
>>  drivers/mmc/host/sunxi-mmc.c | 14 ++
>>  1 file changed, 14 insertions(+)
>>
>> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
>> index 790f01662b4e..0495ae7da6d6 100644
>> --- a/drivers/mmc/host/sunxi-mmc.c
>> +++ b/drivers/mmc/host/sunxi-mmc.c
>> @@ -816,6 +816,20 @@ static void sunxi_mmc_request(struct mmc_host *mmc, 
>> struct mmc_request *mrq)
>> }
>> }
>>
>> +   /*
>> +* TODO Support signal voltage switching
>> +*
>> +* Compared to Allwinner's kernel, recent updates in the mmc core
>> +* mean this should be as easy as setting the flags in cmd_val and
>> +* imask, and waiting for it to finish. However no boards support
>> +* this so this cannot be tested. Block it for now.
>> +*/
>> +   if (cmd->opcode == SD_SWITCH_VOLTAGE) {
>> +   mrq->cmd->error = -EPERM;
>> +   mmc_request_done(mmc, mrq);
>> +   return;
>> +   }
>
> Unless some of the MMC_CAP_UHS* mode is set, this command shouldn't be sent.
>
> So, if you *really* want to protect from this, I think it's better to
> clear these caps in the ->probe() function, after mmc_of_parse() has
> been called.

OK. If we need to block these, then we need to block all the other
unsupported caps, which seems excessive and unnecessary. I'll drop
this patch.

Thanks
ChenYu

>
>> +
>> if (cmd->opcode == MMC_GO_IDLE_STATE) {
>> cmd_val |= SDXC_SEND_INIT_SEQUENCE;
>> imask |= SDXC_COMMAND_DONE;
>> --
>> 2.7.0.rc3
>>
>
> Kind regards
> Uffe

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Re: [linux-sunxi] Problem with Allwinner H3 clocks

[Chen-Yu Tsai]

On Fri, Jan 29, 2016 at 2:25 PM, Hans de Goede  wrote:
> Hi,
>
> On 01/28/2016 08:29 PM, Maxime Ripard wrote:
>>
>> On Thu, Jan 28, 2016 at 05:59:18PM +0100, Jean-Francois Moine wrote:
>
>
> 
>
>>> The A23/A33/H3 (and surely some other SoCs) documentations about
>>> the peripheral/periph/periph0/periph1 PLLs say:
>>>
>>> Note: The PLL Output should be fixed to 600MHz, it is not
>>> recommended to vary this value arbitrarily.
>>
>>
>> I don't know if it's worth it at this point. The pll6 seems to work
>> fine at other rates. Have you experienced any breakage when running at
>> another frequency?
>
>
> Hmm, are we actually changing the freq of pll6 on any SoCs? I know we've
> the code to it, but given that it is shared between many pheripherals,
> I assume we end up never changing it. I assume / hope that the clock
> framework protects against reclocking a clock with multiple users ...

No we're not. And none of the children of pll6 have CLK_SET_RATE_PARENT
set, so they won't change pll6. I think the point is pll6 itself _can_
be changed, but that would screw up all the peripherals depending on it.

There's also SATA and USB that might be driven by it.

ChenYu

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[linux-sunxi] [PATCH 0/3] mmc: sunxi: Support eMMC DDR modes

[Chen-Yu Tsai]

Hi everyone,

This was "mmc: sunxi: Support vqmmc regulator and eMMC DDR modes". vqmmc
support and DT patches were merged even though it was an RFC series, to
my suprise.

These are the remaining patches that add eMMC HS-DDR support to sunxi.

Patch 1 adds timing delays for MMC_DDR52 mode.

Patch 2 adds support for 8 bit eMMC DDR52 mode. Under this mode, the
controller must run at twice the card clock, and different timing delays
are needed.

Patch 3 enables eMMC HS-DDR for sunxi-mmc.


Changes since RFC:

  - Dropped patches that are merged

  - Dropped "mmc: sunxi: Block signal voltage switching (CMD11)".
According to Ulf, the mmc core won't send this command unless the UHS
capabilities are set. We don't.

  - Increased f_max to 52 MHz. Clock rate range for 50 MHz timing delay
also increased to match. See patch 1.


Regards
ChenYu


Chen-Yu Tsai (3):
  mmc: sunxi: Support MMC_DDR52 timing modes
  mmc: sunxi: Support 8 bit eMMC DDR transfer modes
  mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support

 drivers/mmc/host/sunxi-mmc.c | 42 --
 1 file changed, 32 insertions(+), 10 deletions(-)

-- 
2.7.0

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[linux-sunxi] [PATCH 3/3] mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support

[Chen-Yu Tsai]

Now that clock delay settings for 8 bit DDR are correct, and vqmmc
support is available, we can enable MMC_CAP_1_8V_DDR support. This
enables MMC HS-DDR at up to 52 MHz, even if signal voltage switching
is not available.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---

There was discussion about an alternative: setting this capability
in the DT to preserve DT backwards compatibility. However just setting
it in the DT without the driver updates also breaks it. Furthermore,
Maxime's latest "clk: sunxi: Refactor A31 PLL6 so that it can be reused"
patch will break DT compatility. Given the above, I see no reason to
try and maintain compatibility only to fail.

---
 drivers/mmc/host/sunxi-mmc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index bb4592696046..2aee17cd85ae 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -1131,6 +1131,7 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
mmc->f_min  =   40;
mmc->f_max  = 5200;
mmc->caps  |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+ MMC_CAP_1_8V_DDR |
  MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
 
ret = mmc_of_parse(mmc);
-- 
2.7.0

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[linux-sunxi] [PATCH 2/3] mmc: sunxi: Support 8 bit eMMC DDR transfer modes

[Chen-Yu Tsai]

Allwinner's MMC controller needs to run at double the card clock rate
for 8 bit DDR transfer modes. Interestingly, this is not needed for
4 bit DDR transfers.

Different clock delays are needed for 8 bit eMMC DDR, due to the
increased module clock rate. For the A80 though, the same values for
4 bit and 8 bit are shared. The new values for the other SoCs were from
A83T user manual's "new timing mode" default values, which describes
them in clock phase, rather than delay periods. These values were used
without any modification. They may not be correct, but they work.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/mmc/host/sunxi-mmc.c | 33 ++---
 1 file changed, 26 insertions(+), 7 deletions(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index fe6c171fd135..bb4592696046 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -215,6 +215,7 @@
 #define SDXC_CLK_25M   1
 #define SDXC_CLK_50M   2
 #define SDXC_CLK_50M_DDR   3
+#define SDXC_CLK_50M_DDR_8BIT  4
 
 struct sunxi_mmc_clk_delay {
u32 output;
@@ -656,11 +657,17 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
*host,
  struct mmc_ios *ios)
 {
u32 rate, oclk_dly, rval, sclk_dly;
+   u32 clock = ios->clock;
int ret;
 
-   rate = clk_round_rate(host->clk_mmc, ios->clock);
+   /* 8 bit DDR requires a higher module clock */
+   if (ios->timing == MMC_TIMING_MMC_DDR52 &&
+   ios->bus_width == MMC_BUS_WIDTH_8)
+   clock <<= 1;
+
+   rate = clk_round_rate(host->clk_mmc, clock);
dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n",
-   ios->clock, rate);
+   clock, rate);
 
/* setting clock rate */
ret = clk_set_rate(host->clk_mmc, rate);
@@ -677,6 +684,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
*host,
/* clear internal divider */
rval = mmc_readl(host, REG_CLKCR);
rval &= ~0xff;
+   /* set internal divider for 8 bit eMMC DDR, so card clock is right */
+   if (ios->timing == MMC_TIMING_MMC_DDR52 &&
+   ios->bus_width == MMC_BUS_WIDTH_8) {
+   rval |= 1;
+   rate >>= 1;
+   }
mmc_writel(host, REG_CLKCR, rval);
 
/* determine delays */
@@ -687,13 +700,16 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
*host,
oclk_dly = host->clk_delays[SDXC_CLK_25M].output;
sclk_dly = host->clk_delays[SDXC_CLK_25M].sample;
} else if (rate <= 5200) {
-   if (ios->timing == MMC_TIMING_UHS_DDR50 ||
-   ios->timing == MMC_TIMING_MMC_DDR52) {
-   oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output;
-   sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample;
-   } else {
+   if (ios->timing != MMC_TIMING_UHS_DDR50 &&
+   ios->timing != MMC_TIMING_MMC_DDR52) {
oclk_dly = host->clk_delays[SDXC_CLK_50M].output;
sclk_dly = host->clk_delays[SDXC_CLK_50M].sample;
+   } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
+   oclk_dly = 
host->clk_delays[SDXC_CLK_50M_DDR_8BIT].output;
+   sclk_dly = 
host->clk_delays[SDXC_CLK_50M_DDR_8BIT].sample;
+   } else {
+   oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output;
+   sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample;
}
} else {
return -EINVAL;
@@ -951,6 +967,8 @@ static const struct sunxi_mmc_clk_delay 
sunxi_mmc_clk_delays[] = {
[SDXC_CLK_25M]  = { .output = 180, .sample =  75 },
[SDXC_CLK_50M]  = { .output =  90, .sample = 120 },
[SDXC_CLK_50M_DDR]  = { .output =  60, .sample = 120 },
+   /* Value from A83T "new timing mode". Works but might not be right. */
+   [SDXC_CLK_50M_DDR_8BIT] = { .output =  90, .sample = 180 },
 };
 
 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
@@ -958,6 +976,7 @@ static const struct sunxi_mmc_clk_delay 
sun9i_mmc_clk_delays[] = {
[SDXC_CLK_25M]  = { .output = 180, .sample =  75 },
[SDXC_CLK_50M]  = { .output = 150, .sample = 120 },
[SDXC_CLK_50M_DDR]  = { .output =  90, .sample = 120 },
+   [SDXC_CLK_50M_DDR_8BIT] = { .output =  90, .sample = 120 },
 };
 
 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
-- 
2.7.0

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[linux-sunxi] [PATCH 1/3] mmc: sunxi: Support MMC_DDR52 timing modes

[Chen-Yu Tsai]

DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52).
Consider MMC_DDR52 when setting clock delays.

Since MMC high speed mode goes up to 52 MHz instead of 50 MHz for SD,
and this number is visible in the capability macro, increase the
clock rate upper limit to 52 MHz.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/mmc/host/sunxi-mmc.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 765dfb9f77ec..fe6c171fd135 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -686,8 +686,9 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
*host,
} else if (rate <= 2500) {
oclk_dly = host->clk_delays[SDXC_CLK_25M].output;
sclk_dly = host->clk_delays[SDXC_CLK_25M].sample;
-   } else if (rate <= 5000) {
-   if (ios->timing == MMC_TIMING_UHS_DDR50) {
+   } else if (rate <= 5200) {
+   if (ios->timing == MMC_TIMING_UHS_DDR50 ||
+   ios->timing == MMC_TIMING_MMC_DDR52) {
oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output;
sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample;
} else {
@@ -762,7 +763,8 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct 
mmc_ios *ios)
 
/* set ddr mode */
rval = mmc_readl(host, REG_GCTRL);
-   if (ios->timing == MMC_TIMING_UHS_DDR50)
+   if (ios->timing == MMC_TIMING_UHS_DDR50 ||
+   ios->timing == MMC_TIMING_MMC_DDR52)
rval |= SDXC_DDR_MODE;
else
rval &= ~SDXC_DDR_MODE;
@@ -1106,9 +1108,9 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
mmc->max_segs   = PAGE_SIZE / sizeof(struct sunxi_idma_des);
mmc->max_seg_size   = (1 << host->idma_des_size_bits);
mmc->max_req_size   = mmc->max_seg_size * mmc->max_segs;
-   /* 400kHz ~ 50MHz */
+   /* 400kHz ~ 52MHz */
mmc->f_min  =   40;
-   mmc->f_max  = 5000;
+   mmc->f_max  = 5200;
mmc->caps  |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
  MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
 
-- 
2.7.0

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[linux-sunxi] Re: [PATCH RFC 11/11] clk: sunxi: rewrite sun8i-a23-mbus-clk using the simpler composite clk

[Chen-Yu Tsai]

Hi,

On Thu, Jan 28, 2016 at 1:49 AM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> On Mon, Jan 25, 2016 at 09:15:47PM +0800, Chen-Yu Tsai wrote:
>> sun8i-a23-mbus-clk used sunxi's factors clk, which is nice for very
>> complicated clocks, but is not really needed here.
>>
>> Convert sun8i-a23-mbus-clk to use clk_composite, as it is a gate + mux
>> + divider. This makes the code easier to understand.
>>
>> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
>
> Applied, thanks!
> Maxime

Given your suggestion for extending and generalizing factors clk
clock rate calculations, maybe we just leave this one out and use
the new stuff later?

Thanks
ChenYu

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Re: [linux-sunxi] Problem with Allwinner H3 clocks

[Chen-Yu Tsai]

Hi,

On Wed, Jan 27, 2016 at 3:46 PM, Jean-Francois Moine  wrote:
> Hi Jens,
>
> My H3 machine (OPI2) cannot boot with the PLL6 (periph0) as defined
> in the kernel 4.5-rc1. As there is no UART, I don't know what is wrong.
>
> But, applying your old patch
>
> [PATCH v4 1/6] clk: sunxi: Let divs clocks read the base factor clock name 
> from devicetree
> (https://lkml.org/lkml/2015/10/27/532)
>
> makes everything work correctly again (thanks to other patches, I have
> 4 CPUs, USB, thermal sensor and video).
>
> Any idea?

What kernel and DTS are you using? What other patches have you applied?

Patches for H3 USB, thermal sensor and video have not been merged, so it's
likely to have some integration problems. FYI you should always check the
result after self-applying or rebasing DT patches, as there isn't enough
context for git to know if a patch has been applied or not.

4.5-rc1 + sunxi-next boots fine on my Orange PI PC, using the Orange PI Plus
DTS for now.


Regards
ChenYu

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[linux-sunxi] Re: [PATCH 01/14] pinctrl: sunxi: Add A83T R_PIO controller support

[Chen-Yu Tsai]

Hi,

On Sun, Jan 31, 2016 at 9:20 AM, Vishnu Patekar
<vishnupatekar0...@gmail.com> wrote:
> The A83T has R_PIO pin controller, it's same as A23, execpt A83T
> interrupt bit is 6th and A83T has one extra pin PL12.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0...@gmail.com>
> ---
>  .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
>  drivers/pinctrl/sunxi/Kconfig  |   5 +
>  drivers/pinctrl/sunxi/Makefile |   1 +
>  drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c   | 119 
> +
>  4 files changed, 126 insertions(+)
>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
>
> diff --git 
> a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt 
> b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> index 9213b27..f9ff10b 100644
> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> @@ -20,6 +20,7 @@ Required properties:
>"allwinner,sun9i-a80-pinctrl"
>"allwinner,sun9i-a80-r-pinctrl"
>"allwinner,sun8i-a83t-pinctrl"
> +  "allwinner,sun8i-a83t-r-pinctrl"
>"allwinner,sun8i-h3-pinctrl"
>
>  - reg: Should contain the register physical address and length for the
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index f8dbc8b..c0e4a8b 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -46,6 +46,11 @@ config PINCTRL_SUN8I_A83T
> def_bool MACH_SUN8I
> select PINCTRL_SUNXI_COMMON
>
> +config PINCTRL_SUN8I_A83T_R
> +   def_bool MACH_SUN8I
> +   depends on RESET_CONTROLLER
> +   select PINCTRL_SUNXI_COMMON
> +

Keep them sorted please.

Otherwise,

Acked-by: Chen-Yu Tsai <w...@csie.org>

>  config PINCTRL_SUN8I_A23_R
> def_bool MACH_SUN8I
> depends on RESET_CONTROLLER
> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> index ef82f22..bfd4fa0 100644
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> @@ -13,6 +13,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)   += 
> pinctrl-sun8i-a23.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A23_R)  += pinctrl-sun8i-a23-r.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A83T)   += pinctrl-sun8i-a83t.o
> +obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o
>  obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
>  obj-$(CONFIG_PINCTRL_SUN9I_A80)+= pinctrl-sun9i-a80.o
>  obj-$(CONFIG_PINCTRL_SUN9I_A80_R)  += pinctrl-sun9i-a80-r.o
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c 
> b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
> new file mode 100644
> index 000..11787894
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
> @@ -0,0 +1,119 @@
> +/*
> + * Allwinner A83T SoCs special pins pinctrl driver.
> + *
> + * Copyright (C) 2016 Vishnu Patekar
> + * Vishnu Patekar <vishnupatekar0...@gmail.com>
> + *
> + * Based on pinctrl-sun8i-a23.c, which is:
> + * Copyright (C) 2014 Chen-Yu Tsai <w...@csie.org>
> + * Copyright (C) 2014 Maxime Ripard <maxime.rip...@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "pinctrl-sunxi.h"
> +
> +static const struct sunxi_desc_pin sun8i_a83t_r_pins[] = {
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
> + SUNXI_FUNCTION(0x3, "s_twi"), /* SCK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PL_EINT0 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
> + SUNXI_FUNCTION(0x3, "s_twi"), /* SDA */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PL_EINT1 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),