Re: [linux-sunxi] [PATCH v4 8/8] arm64: allwinner: h5: enable USB OTG on Orange Pi PC 2 board
On Mon, Mar 20, 2017 at 12:31 AM, Icenowy Zheng wrote: > Orange Pi PC 2 board features a OTG port like the one on older H3 Orange > Pi's, with PG12 pin being the id det pin and PL2 being the vbus driver > pin. > > Add support for it. > > Signed-off-by: Icenowy Zheng Acked-by: Chen-Yu Tsai -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [PATCH v4 3/8] phy: sun4i-usb: add PHYCTL offset for H3 SoC
On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng wrote:
> The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
> register offset missing.
>
> Add it. Because it's a SoC after A33, its PHYCTL offset should be 0x10.
You are implying that all SoCs after A33 have PHYCTL at 0x10.
This is not true. As the A83T, which was released after the A33, has
PHYCTL at the old offset.
Just state that H3 has PHYCTL at 0x10.
ChenYu
> Signed-off-by: Icenowy Zheng
> ---
> New patch in v4.
>
> drivers/phy/phy-sun4i-usb.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
> index 62b4d25448c6..a650f283f6ff 100644
> --- a/drivers/phy/phy-sun4i-usb.c
> +++ b/drivers/phy/phy-sun4i-usb.c
> @@ -821,6 +821,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
> .num_phys = 4,
> .type = sun8i_h3_phy,
> .disc_thresh = 3,
> + .phyctl_offset = REG_PHYCTL_A33,
> .dedicated_clocks = true,
> .enable_pmu_unk1 = true,
> };
> --
> 2.12.0
>
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Re: [linux-sunxi] [PATCH v4 2/8] phy: sun4i-usb: change PHYCTL register clearing code
On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng wrote:
> It seems that all SoCs after A33 (including A33) need the PHYCTL
> register to be cleared before writing to it. These SoCs all have another
> feature: PHYCTL register is at 0x10, not 0x04.
As mentioned in the other patch, the basis for this description is
wrong. Just state that, among all the currently supported SoCs, when
PHYCTL is at 0x10, the register must be cleared before writing to it.
This would match what the logic in your patch means. Please also
update the comment.
ChenYu
>
> Change PHYCTL register clearing code to judge whether clearing is needed
> based on the PHYCTL offset.
>
> Signed-off-by: Icenowy Zheng
> ---
> New patch in v4.
>
> drivers/phy/phy-sun4i-usb.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
> index a21b5f24a340..62b4d25448c6 100644
> --- a/drivers/phy/phy-sun4i-usb.c
> +++ b/drivers/phy/phy-sun4i-usb.c
> @@ -188,10 +188,8 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy
> *phy, u32 addr, u32 data,
>
> spin_lock_irqsave(&phy_data->reg_lock, flags);
>
> - if (phy_data->cfg->type == sun8i_a33_phy ||
> - phy_data->cfg->type == sun50i_a64_phy ||
> - phy_data->cfg->type == sun8i_v3s_phy) {
> - /* A33 or A64 needs us to set phyctl to 0 explicitly */
> + if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
> + /* SoCs newer than A33 need us to set phyctl to 0 explicitly
> */
> writel(0, phyctl);
> }
>
> --
> 2.12.0
>
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Re: [linux-sunxi] [PATCH v4 3/8] phy: sun4i-usb: add PHYCTL offset for H3 SoC
On Fri, Mar 24, 2017 at 2:27 PM, Icenowy Zheng wrote:
>
>
> 24.03.2017, 11:05, "Chen-Yu Tsai" :
>> On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng wrote:
>>> The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
>>> register offset missing.
>>>
>>> Add it. Because it's a SoC after A33, its PHYCTL offset should be 0x10.
>>
>> You are implying that all SoCs after A33 have PHYCTL at 0x10.
>>
>> This is not true. As the A83T, which was released after the A33, has
>> PHYCTL at the old offset.
>
> No, in Allwinner's BSP A83T is using also PHYCTL at 0x10.
>
> The code in linux-3.4/drivers/usb/sunxi_usb/include/sunxi_usb_bsp.c is
> ```
> #if defined (CONFIG_ARCH_SUN8IW5) || defined (CONFIG_ARCH_SUN8IW6) || defined
> (CONFIG_ARCH_SUN8IW9) || defined (CONFIG_ARCH_SUN8IW8) || defined
> (CONFIG_ARCH_SUN8IW7)
> #define USBPHYC_REG_o_PHYCTL 0x0410
> #else
> #define USBPHYC_REG_o_PHYCTL 0x0404
> #endif
> ```
>
> In linux-3.10/drivers/usb/sunxi_usb/include/sunxi_usb_bsp.c is
> ```
> #if defined (CONFIG_ARCH_SUN50I) || defined (CONFIG_ARCH_SUN8IW10) || defined
> (CONFIG_ARCH_SUN8IW11)
> #define USBPHYC_REG_o_PHYCTL 0x0410
> #else
> #define USBPHYC_REG_o_PHYCTL 0x0404
> #endif
> ```
>
> So sun50i* and sun50iw5~w11 all use PHYCTL at 0x10.
>
Seems you are right. However I think it's best to not assume or infer
anything. Who knows, Allwinner might re-release some old SoC under a
different under a different name again.
Just state the facts: H3 has its PHYCTL at 0x10.
ChenYu
>>
>> Just state that H3 has PHYCTL at 0x10.
>>
>> ChenYu
>>
>>> Signed-off-by: Icenowy Zheng
>>> ---
>>> New patch in v4.
>>>
>>> drivers/phy/phy-sun4i-usb.c | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
>>> index 62b4d25448c6..a650f283f6ff 100644
>>> --- a/drivers/phy/phy-sun4i-usb.c
>>> +++ b/drivers/phy/phy-sun4i-usb.c
>>> @@ -821,6 +821,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
>>> .num_phys = 4,
>>> .type = sun8i_h3_phy,
>>> .disc_thresh = 3,
>>> + .phyctl_offset = REG_PHYCTL_A33,
>>> .dedicated_clocks = true,
>>> .enable_pmu_unk1 = true,
>>> };
>>> --
>>> 2.12.0
>>>
>>> --
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Re: [linux-sunxi] Re: [RESEND PATCH v4 2/9] iio: adc: add support for X-Powers AXP20X and AXP22X PMICs ADCs
On Fri, Mar 24, 2017 at 3:55 PM, Quentin Schulz wrote: > Hi, > > On 23/03/2017 10:52, Chen-Yu Tsai wrote: >> On Thu, Mar 23, 2017 at 5:35 PM, Sebastian Reichel wrote: >>> Hi, >>> >>> On Wed, Mar 22, 2017 at 12:34:45PM +0800, Chen-Yu Tsai wrote: >>>> P.S. I'm thinking about having MFD_AXP20X imply its various sub-drivers. >>>> Not sure if that was the intended usage of the new imply syntax though. >>> >>> I think adding "default MFD_AXP20X" to the sub-drivers is cleaner, >>> as you will not end up with a long list. >> >> I'd still need to add imply statements for the various subsystems though, >> like regulators, power supplies, extcon, etc.. >> But I suppose that's cleaner, and fits the original intent of the syntax. >> > > Hum. I don't really understand what you are saying.. Am I supposed to > modify something or, is it okay and we're waiting for Lee to apply on > his tree? > > Thanks in advance for clearing it up, > > Quentin I'm just mentioning some follow up tasks I want to do. The patch is fine and we're waiting for Lee to take it. ChenYu -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 0/3] clk: sunxi-ng: minimum multiplier and comment fixes
Hi Maxime, Here's a few fixes I came up with while thinking more about how to implement some of the tricky clocks on the A83T. Please have a look. The first 2 might need to go in stable, but I'll leave the decision to you. Regards ChenYu Chen-Yu Tsai (3): clk: sunxi-ng: use 1 as fallback for minimum multiplier clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatch clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 3 +-- drivers/clk/sunxi-ng/ccu_nk.c| 8 drivers/clk/sunxi-ng/ccu_nkm.c | 8 drivers/clk/sunxi-ng/ccu_nkmp.c | 8 drivers/clk/sunxi-ng/ccu_nm.c| 4 ++-- 5 files changed, 15 insertions(+), 16 deletions(-) -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 3/3] clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code
We ignore the d1 and d2 dividers in the audio PLL, and force them to
1 (register value 0) at probe time. However the comment preceding the
audio PLL definition says we enforce the default value, which is not
the same.
Fix the preceding comment to match what we do in code.
Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU")
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
index e13e313ce4f5..a031beefa5b5 100644
--- a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
+++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
@@ -70,8 +70,7 @@ static struct ccu_nm pll_c1cpux_clk = {
/*
* The Audio PLL has d1, d2 dividers in addition to the usual N, M
* factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz
- * and 24.576 MHz, ignore them for now. Enforce the default for them,
- * which is d1 = 0, d2 = 1.
+ * and 24.576 MHz, ignore them for now. Enforce d1 = 0 and d2 = 0.
*/
#define SUN9I_A80_PLL_AUDIO_REG0x008
--
2.11.0
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[linux-sunxi] [PATCH 1/3] clk: sunxi-ng: use 1 as fallback for minimum multiplier
A zero multiplier does not make sense for clocks.
Use 1 as the minimum when a multiplier minimum isn't specified.
Fixes: 2beaa601c849 ("clk: sunxi-ng: Implement minimum for multipliers")
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu_nk.c | 8
drivers/clk/sunxi-ng/ccu_nkm.c | 8
drivers/clk/sunxi-ng/ccu_nkmp.c | 4 ++--
drivers/clk/sunxi-ng/ccu_nm.c | 2 +-
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c
index b9e9b8a9d1b4..2485bda87a9a 100644
--- a/drivers/clk/sunxi-ng/ccu_nk.c
+++ b/drivers/clk/sunxi-ng/ccu_nk.c
@@ -102,9 +102,9 @@ static long ccu_nk_round_rate(struct clk_hw *hw, unsigned
long rate,
if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= nk->fixed_post_div;
- _nk.min_n = nk->n.min;
+ _nk.min_n = nk->n.min ?: 1;
_nk.max_n = nk->n.max ?: 1 << nk->n.width;
- _nk.min_k = nk->k.min;
+ _nk.min_k = nk->k.min ?: 1;
_nk.max_k = nk->k.max ?: 1 << nk->k.width;
ccu_nk_find_best(*parent_rate, rate, &_nk);
@@ -127,9 +127,9 @@ static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long
rate,
if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate = rate * nk->fixed_post_div;
- _nk.min_n = nk->n.min;
+ _nk.min_n = nk->n.min ?: 1;
_nk.max_n = nk->n.max ?: 1 << nk->n.width;
- _nk.min_k = nk->k.min;
+ _nk.min_k = nk->k.min ?: 1;
_nk.max_k = nk->k.max ?: 1 << nk->k.width;
ccu_nk_find_best(parent_rate, rate, &_nk);
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
index 71f81e95a061..cba84afe1cf1 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.c
+++ b/drivers/clk/sunxi-ng/ccu_nkm.c
@@ -109,9 +109,9 @@ static unsigned long ccu_nkm_round_rate(struct
ccu_mux_internal *mux,
struct ccu_nkm *nkm = data;
struct _ccu_nkm _nkm;
- _nkm.min_n = nkm->n.min;
+ _nkm.min_n = nkm->n.min ?: 1;
_nkm.max_n = nkm->n.max ?: 1 << nkm->n.width;
- _nkm.min_k = nkm->k.min;
+ _nkm.min_k = nkm->k.min ?: 1;
_nkm.max_k = nkm->k.max ?: 1 << nkm->k.width;
_nkm.min_m = 1;
_nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
@@ -138,9 +138,9 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned
long rate,
unsigned long flags;
u32 reg;
- _nkm.min_n = nkm->n.min;
+ _nkm.min_n = nkm->n.min ?: 1;
_nkm.max_n = nkm->n.max ?: 1 << nkm->n.width;
- _nkm.min_k = nkm->k.min;
+ _nkm.min_k = nkm->k.min ?: 1;
_nkm.max_k = nkm->k.max ?: 1 << nkm->k.width;
_nkm.min_m = 1;
_nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
index 488055ed944f..162ff2664f64 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
@@ -116,9 +116,9 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned
long rate,
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
struct _ccu_nkmp _nkmp;
- _nkmp.min_n = nkmp->n.min;
+ _nkmp.min_n = nkmp->n.min ?: 1;
_nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width;
- _nkmp.min_k = nkmp->k.min;
+ _nkmp.min_k = nkmp->k.min ?: 1;
_nkmp.max_k = nkmp->k.max ?: 1 << nkmp->k.width;
_nkmp.min_m = 1;
_nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
index af71b1909cd9..f312c92f2a21 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -99,7 +99,7 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned
long rate,
struct ccu_nm *nm = hw_to_ccu_nm(hw);
struct _ccu_nm _nm;
- _nm.min_n = nm->n.min;
+ _nm.min_n = nm->n.min ?: 1;
_nm.max_n = nm->n.max ?: 1 << nm->n.width;
_nm.min_m = 1;
_nm.max_m = nm->m.max ?: 1 << nm->m.width;
--
2.11.0
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[linux-sunxi] [PATCH 2/3] clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatch
In commit 2beaa601c849 ("clk: sunxi-ng: Implement minimum for
multipliers"), the multiplier minimums in the set_rate callback
for NM and NKMP style clocks were not updated.
This patch fixes them to match their round_rate callbacks.
Fixes: 2beaa601c849 ("clk: sunxi-ng: Implement minimum for multipliers")
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu_nkmp.c | 4 ++--
drivers/clk/sunxi-ng/ccu_nm.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
index 162ff2664f64..e58c95787f94 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
@@ -138,9 +138,9 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned
long rate,
unsigned long flags;
u32 reg;
- _nkmp.min_n = 1;
+ _nkmp.min_n = nkmp->n.min ?: 1;
_nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width;
- _nkmp.min_k = 1;
+ _nkmp.min_k = nkmp->k.min ?: 1;
_nkmp.max_k = nkmp->k.max ?: 1 << nkmp->k.width;
_nkmp.min_m = 1;
_nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
index f312c92f2a21..5e5e90a4a50c 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -122,7 +122,7 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long
rate,
else
ccu_frac_helper_disable(&nm->common, &nm->frac);
- _nm.min_n = 1;
+ _nm.min_n = nm->n.min ?: 1;
_nm.max_n = nm->n.max ?: 1 << nm->n.width;
_nm.min_m = 1;
_nm.max_m = nm->m.max ?: 1 << nm->m.width;
--
2.11.0
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Re: [linux-sunxi] Re: Mainline kernel doesn't suspend due to mmc1
On Sun, Mar 26, 2017 at 3:21 AM, Eyad Majali wrote: > UPDATE > I disabled mmc1 in the dtsi which also disabled RTL8723BS , now the kernel > hangs when doing suspend with console cursor not blinking We don't support suspend. ChenYu > > > On Saturday, March 25, 2017 at 7:50:07 PM UTC+2, Eyad Majali wrote: >> >> Hi, >> when suspending the kernel it wakes up automatically shortly after , here >> is the log >> >> [ 251.210392] RTL8723BS: rtw_cmd_thread(wlan0) stop_req:1, break >> [ 251.211070] RTL8723BS: rtw_dev_unload: driver not in IPS >> [ 251.218241] RTL8723BS: rtw suspend success in 10 ms >> [ 251.218272] dpm_run_callback(): pm_generic_suspend+0x0/0x30 returns -38 >> [ 251.218291] PM: Device mmc1:0001:1 failed to suspend async: error -38 >> [ 251.228102] PM: Some devices failed to suspend, or early wake event >> detected >> [ 251.318924] PM: resume of devices complete after 90.759 msecs >> [ 251.320466] Restarting tasks ... >> [ 251.322310] done. >> >> the mmc1 is used for SDIO wifi , any idea how can I fix this ?? > > -- > You received this message because you are subscribed to the Google Groups > "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to linux-sunxi+unsubscr...@googlegroups.com. > For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 0/2] drm/sun4i: Add display backend interrupt to dt binding
Hi Maxime, As promised, here is the patch adding the interrupt line for the display backend to the sun5i shared dtsi, and another one adding it to the device tree bindings. The display backend has an undocumented (in the user manual) interrupt that, according to vendor code, is raised when the current scanout is completed. This might be a better fit for DRM/KMS vblank signalling, rather than the TCON's vblank interrupt. If true, it would allow us to cut out the TCON from the crtc in the driver, instead keeping it solely as an encoder, simplifying some of the inter-component code. Regardless, the interrupt line exists and should be added to the device tree. Regards ChenYu Chen-Yu Tsai (2): drm/sun4i: Add display backend interrupt to device tree binding ARM: dts: sun5i: Add interrupt for display backend Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 2 ++ arch/arm/boot/dts/sun5i.dtsi | 1 + 2 files changed, 3 insertions(+) -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 1/2] drm/sun4i: Add display backend interrupt to device tree binding
The display backend has an interrupt line. Add it to the device tree
binding.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index b82c00449468..57a8d0610062 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -94,6 +94,7 @@ Required properties:
* allwinner,sun6i-a31-display-backend
* allwinner,sun8i-a33-display-backend
- reg: base address and size of the memory-mapped region.
+ - interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the frontend and backend
* ahb: the backend interface clock
* mod: the backend module clock
@@ -265,6 +266,7 @@ fe0: display-frontend@1e0 {
be0: display-backend@1e6 {
compatible = "allwinner,sun5i-a13-display-backend";
reg = <0x01e6 0x1>;
+ interrupts = <47>;
clocks = <&ahb_gates 44>, <&de_be_clk>,
<&dram_gates 26>;
clock-names = "ahb", "mod",
--
2.11.0
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[linux-sunxi] [PATCH 2/2] ARM: dts: sun5i: Add interrupt for display backend
The display backend on sun5i shares the same interrupt line as the
display frontend. Add it.
Signed-off-by: Chen-Yu Tsai
---
This won't directly apply to old releases. We may want to backport
them though?
---
arch/arm/boot/dts/sun5i.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index fc338ce7af79..5175f9cc9bed 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -689,6 +689,7 @@
be0: display-backend@01e6 {
compatible = "allwinner,sun5i-a13-display-backend";
reg = <0x01e6 0x1>;
+ interrupts = <47>;
clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
<&ccu CLK_DRAM_DE_BE>;
clock-names = "ahb", "mod",
--
2.11.0
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[linux-sunxi] Re: [PATCH v2 00/13] sunxi: Add support for R40 SoC
Hi, On Mon, Mar 6, 2017 at 4:05 PM, Chen-Yu Tsai wrote: > Hi everyone, > > This is v2 of my Allwinner R40 SoC support series. > > Changes since v1: > > - Add Maxime's ack for all but the first patch. > > - Add a patch to split up very long Kconfig lines. > > This series adds support for the new R40 SoC. The R40 is marketed as the > successor to the A20. It is mostly pin compatible (in software) with the > A20. It has a somewhat similar memory layout, a hybrid of A20 and newer > sun6i gen.. Like the A20, it does not have a PRCM block. What's the status on this? The series has been sitting for some time, with all patches acked. AFAIK there are 3 patch series in flight that will conflict with each other on the DRAM stuff. Can we at least start by merging one so we can do conflict resolution? Thanks ChenYu -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH 2/2] ARM: dts: sun5i: Add interrupt for display backend
On Wed, Mar 29, 2017 at 3:13 PM, Maxime Ripard wrote: > On Mon, Mar 27, 2017 at 10:38:47PM +0800, Chen-Yu Tsai wrote: >> The display backend on sun5i shares the same interrupt line as the >> display frontend. Add it. >> >> Signed-off-by: Chen-Yu Tsai > > And ideally, patches prefix shouldn't have dts here too. I've dropped > it and applied, thanks! Seems like this was a recent policy change? Or almost everyone was getting it wrong in the past. >> This won't directly apply to old releases. We may want to backport >> them though? > > Yep, probably. Do you want to send it to stable? It won't apply, due to the recent sun5i merger. We could wait until it lands in Linus' tree, then send a backport patch to stable, to keep the noise to a minimum. ChenYu -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v3 04/11] drm/sun4i: abstract the layer type
On Mon, Apr 3, 2017 at 4:14 PM, Maxime Ripard
wrote:
> Hi,
>
> On Thu, Mar 30, 2017 at 03:46:06AM +0800, Icenowy Zheng wrote:
>> As we are going to add support for the Allwinner DE2 Mixer in sun4i-drm
>> driver, we will finally have two types of layer.
>>
>> Abstract the layer type to void * and a ops struct, which contains the
>> only function used by crtc -- get the drm_plane struct of the layer.
>>
>> Signed-off-by: Icenowy Zheng
>> ---
>> Refactored patch in v3.
>>
>> drivers/gpu/drm/sun4i/sun4i_crtc.c | 19 +++
>> drivers/gpu/drm/sun4i/sun4i_crtc.h | 3 ++-
>> drivers/gpu/drm/sun4i/sun4i_layer.c | 19 ++-
>> drivers/gpu/drm/sun4i/sun4i_layer.h | 2 +-
>> drivers/gpu/drm/sun4i/sunxi_layer.h | 17 +
>> 5 files changed, 49 insertions(+), 11 deletions(-)
>> create mode 100644 drivers/gpu/drm/sun4i/sunxi_layer.h
>>
>> diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c
>> b/drivers/gpu/drm/sun4i/sun4i_crtc.c
>> index 3c876c3a356a..33854ee7f636 100644
>> --- a/drivers/gpu/drm/sun4i/sun4i_crtc.c
>> +++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c
>> @@ -29,6 +29,7 @@
>> #include "sun4i_crtc.h"
>> #include "sun4i_drv.h"
>> #include "sun4i_layer.h"
>> +#include "sunxi_layer.h"
>> #include "sun4i_tcon.h"
>>
>> static void sun4i_crtc_atomic_begin(struct drm_crtc *crtc,
>> @@ -149,7 +150,7 @@ struct sun4i_crtc *sun4i_crtc_init(struct drm_device
>> *drm,
>> scrtc->tcon = tcon;
>>
>> /* Create our layers */
>> - scrtc->layers = sun4i_layers_init(drm, scrtc->backend);
>> + scrtc->layers = (void **)sun4i_layers_init(drm, scrtc);
>> if (IS_ERR(scrtc->layers)) {
>> dev_err(drm->dev, "Couldn't create the planes\n");
>> return NULL;
>> @@ -157,14 +158,15 @@ struct sun4i_crtc *sun4i_crtc_init(struct drm_device
>> *drm,
>>
>> /* find primary and cursor planes for drm_crtc_init_with_planes */
>> for (i = 0; scrtc->layers[i]; i++) {
>> - struct sun4i_layer *layer = scrtc->layers[i];
>> + void *layer = scrtc->layers[i];
>> + struct drm_plane *plane = scrtc->layer_ops->get_plane(layer);
>>
>> - switch (layer->plane.type) {
>> + switch (plane->type) {
>> case DRM_PLANE_TYPE_PRIMARY:
>> - primary = &layer->plane;
>> + primary = plane;
>> break;
>> case DRM_PLANE_TYPE_CURSOR:
>> - cursor = &layer->plane;
>> + cursor = plane;
>> break;
>> default:
>> break;
>> @@ -190,10 +192,11 @@ struct sun4i_crtc *sun4i_crtc_init(struct drm_device
>> *drm,
>> /* Set possible_crtcs to this crtc for overlay planes */
>> for (i = 0; scrtc->layers[i]; i++) {
>> uint32_t possible_crtcs = BIT(drm_crtc_index(&scrtc->crtc));
>> - struct sun4i_layer *layer = scrtc->layers[i];
>> + void *layer = scrtc->layers[i];
>> + struct drm_plane *plane = scrtc->layer_ops->get_plane(layer);
>>
>> - if (layer->plane.type == DRM_PLANE_TYPE_OVERLAY)
>> - layer->plane.possible_crtcs = possible_crtcs;
>> + if (plane->type == DRM_PLANE_TYPE_OVERLAY)
>> + plane->possible_crtcs = possible_crtcs;
>
> I think the logic should be reversed here, the CRTC shouldn't care
> (much) about the layers at all.
Correct. It shouldn't. However since the layers are tied to a specific
crtc, they get created as part of the crtc init sequence.
> We should modify sun4i_crtc_init to get the argument it needs (primary
> and cursor planes for example) through its parameters, and have the
> caller (which iirc is sun4i_drv) call it with the right parameters
The caller is (now) sun4i_crtc_init.
> depending on whether you're using DE or DE2.
Ack.
>
> If we're doing that, I don't think we even need the pointer to the
> array of layers in struct sun4i_crtc, which will make it easier to
> deal with.
Ack.
ChenYu
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Re: [linux-sunxi] Re: [PATCH v3 04/11] drm/sun4i: abstract the layer type
On Wed, Apr 5, 2017 at 3:53 AM, Icenowy Zheng wrote:
>
>
> 在 2017年04月05日 03:28, Sean Paul 写道:
>>
>> On Thu, Mar 30, 2017 at 03:46:06AM +0800, Icenowy Zheng wrote:
>>>
>>> As we are going to add support for the Allwinner DE2 Mixer in sun4i-drm
>>> driver, we will finally have two types of layer.
>>>
>>> Abstract the layer type to void * and a ops struct, which contains the
>>> only function used by crtc -- get the drm_plane struct of the layer.
>>>
>>> Signed-off-by: Icenowy Zheng
>>> ---
>>> Refactored patch in v3.
>>>
>>> drivers/gpu/drm/sun4i/sun4i_crtc.c | 19 +++
>>> drivers/gpu/drm/sun4i/sun4i_crtc.h | 3 ++-
>>> drivers/gpu/drm/sun4i/sun4i_layer.c | 19 ++-
>>> drivers/gpu/drm/sun4i/sun4i_layer.h | 2 +-
>>> drivers/gpu/drm/sun4i/sunxi_layer.h | 17 +
>>> 5 files changed, 49 insertions(+), 11 deletions(-)
>>> create mode 100644 drivers/gpu/drm/sun4i/sunxi_layer.h
>>>
>>> diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c
>>> b/drivers/gpu/drm/sun4i/sun4i_crtc.c
>>> index 3c876c3a356a..33854ee7f636 100644
>>> --- a/drivers/gpu/drm/sun4i/sun4i_crtc.c
>>> +++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c
>>> @@ -29,6 +29,7 @@
>>> #include "sun4i_crtc.h"
>>> #include "sun4i_drv.h"
>>> #include "sun4i_layer.h"
>>> +#include "sunxi_layer.h"
>>> #include "sun4i_tcon.h"
>>>
>>> static void sun4i_crtc_atomic_begin(struct drm_crtc *crtc,
>>> @@ -149,7 +150,7 @@ struct sun4i_crtc *sun4i_crtc_init(struct drm_device
>>> *drm,
>>> scrtc->tcon = tcon;
>>>
>>> /* Create our layers */
>>> - scrtc->layers = sun4i_layers_init(drm, scrtc->backend);
>>> + scrtc->layers = (void **)sun4i_layers_init(drm, scrtc);
>>> if (IS_ERR(scrtc->layers)) {
>>> dev_err(drm->dev, "Couldn't create the planes\n");
>>> return NULL;
>>> @@ -157,14 +158,15 @@ struct sun4i_crtc *sun4i_crtc_init(struct
>>> drm_device *drm,
>>>
>>> /* find primary and cursor planes for drm_crtc_init_with_planes
>>> */
>>> for (i = 0; scrtc->layers[i]; i++) {
>>> - struct sun4i_layer *layer = scrtc->layers[i];
>>> + void *layer = scrtc->layers[i];
>>> + struct drm_plane *plane =
>>> scrtc->layer_ops->get_plane(layer);
>>>
>>> - switch (layer->plane.type) {
>>> + switch (plane->type) {
>>> case DRM_PLANE_TYPE_PRIMARY:
>>> - primary = &layer->plane;
>>> + primary = plane;
>>> break;
>>> case DRM_PLANE_TYPE_CURSOR:
>>> - cursor = &layer->plane;
>>> + cursor = plane;
>>> break;
>>> default:
>>> break;
>>> @@ -190,10 +192,11 @@ struct sun4i_crtc *sun4i_crtc_init(struct
>>> drm_device *drm,
>>> /* Set possible_crtcs to this crtc for overlay planes */
>>> for (i = 0; scrtc->layers[i]; i++) {
>>> uint32_t possible_crtcs =
>>> BIT(drm_crtc_index(&scrtc->crtc));
>>> - struct sun4i_layer *layer = scrtc->layers[i];
>>> + void *layer = scrtc->layers[i];
>>> + struct drm_plane *plane =
>>> scrtc->layer_ops->get_plane(layer);
>>>
>>> - if (layer->plane.type == DRM_PLANE_TYPE_OVERLAY)
>>> - layer->plane.possible_crtcs = possible_crtcs;
>>> + if (plane->type == DRM_PLANE_TYPE_OVERLAY)
>>> + plane->possible_crtcs = possible_crtcs;
>>> }
>>>
>>> return scrtc;
>>> diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.h
>>> b/drivers/gpu/drm/sun4i/sun4i_crtc.h
>>> index 230cb8f0d601..a4036ee44cf8 100644
>>> --- a/drivers/gpu/drm/sun4i/sun4i_crtc.h
>>> +++ b/drivers/gpu/drm/sun4i/sun4i_crtc.h
>>> @@ -19,7 +19,8 @@ struct sun4i_crtc {
>>>
>>> struct sun4i_backend*backend;
>>> struct sun4i_tcon *tcon;
>>> - struct sun4i_layer **layers;
>>> + void**layers;
>>> + const struct sunxi_layer_ops*layer_ops;
>>
>>
>> I think you should probably take a different approach to abstract the
>> layer
>> type. How about creating
>>
>> struct sunxi_layer {
>> struct drm_plane plane;
>> }
>>
>> base and then subclassing that for sun4i and sun8i? By doing this you can
>> avoid
>> the nasty casting and you can also get rid of the get_plane() hook and
>> layer_ops.
>
>
> For the situation that using ** things are easily to get weird.
That code could be reworked, by initializing the layers directly within
the crtc init code. If you look at rockchip's drm driver, you'll see
they do this. There is a good reason to do it this way, as you need
to first create the primary and cursor layers, pass them in when you
create the crtc, then initialize any additional layers with the
possible_crtcs bitmap.
In our driver we are currently initializing all
Re: [linux-sunxi] [PATCH 01/11] arm64: allwinner: a64: enable RSB on A64
On Wed, Apr 5, 2017 at 2:01 AM, Icenowy Zheng wrote:
> Allwinner A64 have a RSB controller like the one on A23/A33 SoCs.
>
> Add it and its pinmux.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 21 +
> 1 file changed, 21 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 6bc606b4d74d..9a75b1c7c91a 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -420,6 +420,27 @@
> #gpio-cells = <3>;
> interrupt-controller;
> #interrupt-cells = <3>;
> +
> + r_rsb_pins: rsb@0 {
> + pins = "PL0", "PL1";
> + function = "s_rsb";
> + drive-strength = <20>;
We don't need this. The hardware default should be enough.
> + bias-pull-up;
Boards should have external pull-ups for these pins, as the PMICs
start up in I2C mode. If any board actually doesn't have them and
needs the internal pull-ups, they should be set at the board level.
Otherwise,
Acked-by: Chen-Yu Tsai
> + };
> + };
> +
> + r_rsb: rsb@1f03400 {
> + compatible = "allwinner,sun8i-a23-rsb";
> + reg = <0x01f03400 0x400>;
> + interrupts = ;
> + clocks = <&r_ccu 6>;
> + clock-frequency = <300>;
> + resets = <&r_ccu 2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&r_rsb_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> };
> };
> };
> --
> 2.12.2
>
> --
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Re: [linux-sunxi] [PATCH 02/11] arm64: allwinner: a64: add NMI controller on A64
On Wed, Apr 5, 2017 at 2:01 AM, Icenowy Zheng wrote: > Allwinner A64 SoC features a NMI controller, which is usually connected > to the AXP PMIC. > > Add support for it. > > Signed-off-by: Icenowy Zheng This might not be the best representation of the R_INTC block. Though we'd need to change it for all SoCs if we want to be accurate. For now, Acked-by: Chen-Yu Tsai -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [PATCH 03/11] dt-bindings: add device tree binding for X-Powers AXP803 PMIC
On Wed, Apr 5, 2017 at 2:01 AM, Icenowy Zheng wrote: > AXP803 is a PMIC produced by Shenzhen X-Powers, with either I2C or RSB > bus. > > Add a compatible for it. > > Signed-off-by: Icenowy Zheng > --- > Documentation/devicetree/bindings/mfd/axp20x.txt | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt > b/Documentation/devicetree/bindings/mfd/axp20x.txt > index b41d2601c6ba..31607631b0d8 100644 > --- a/Documentation/devicetree/bindings/mfd/axp20x.txt > +++ b/Documentation/devicetree/bindings/mfd/axp20x.txt > @@ -7,11 +7,12 @@ axp209 (X-Powers) > axp221 (X-Powers) > axp223 (X-Powers) > axp809 (X-Powers) > +axp803 (X-Powers) > > Required properties: > - compatible: "x-powers,axp152", "x-powers,axp202", "x-powers,axp209", > "x-powers,axp221", "x-powers,axp223", "x-powers,axp806", > - "x-powers,axp809" > + "x-powers,axp809", "x-powers,axp803" Please sort them in ascending order. Otherwise, Acked-by: Chen-Yu Tsai > - reg: The I2C slave address or RSB hardware address for the AXP chip > - interrupt-parent: The parent interrupt controller > - interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin > -- > 2.12.2 > > -- > You received this message because you are subscribed to the Google Groups > "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to linux-sunxi+unsubscr...@googlegroups.com. > For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [PATCH 02/11] arm64: allwinner: a64: add NMI controller on A64
On Wed, Apr 5, 2017 at 2:11 PM, Maxime Ripard wrote: > On Wed, Apr 05, 2017 at 11:51:45AM +0800, Chen-Yu Tsai wrote: >> On Wed, Apr 5, 2017 at 2:01 AM, Icenowy Zheng wrote: >> > Allwinner A64 SoC features a NMI controller, which is usually connected >> > to the AXP PMIC. >> > >> > Add support for it. >> > >> > Signed-off-by: Icenowy Zheng >> >> This might not be the best representation of the R_INTC block. Though >> we'd need to change it for all SoCs if we want to be accurate. For now, > > What do you think would be a good representation? My gut feeling is that this is the old INTC from sun4/5i. It's supposed to be the interrupt controller for the embedded low power core. I've not done a thorough comparison though. ChenYu -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 3/3] clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor
The DDR1 PLL on the A33 is an oddball amongst the A33 CCU clocks.
It is a clock multiplier, with the effective multiplier in the
range of 12 ~ 255 and no offset between the multiplier value and
the value programmed into the register.
Implement the zero offset and minimum value of 12 for this clock.
Fixes: d05c748bd730 ("clk: sunxi-ng: Add A33 CCU support")
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index a7b3c08ed0e2..56370c2c7f98 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -159,13 +159,17 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk,
"pll-de",
BIT(28),/* lock */
CLK_SET_RATE_UNGATE);
-/* TODO: Fix N */
-static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
- "osc24M", 0x04c,
- 8, 6, /* N */
- BIT(31), /* gate */
- BIT(28), /* lock */
- CLK_SET_RATE_UNGATE);
+static struct ccu_mult pll_ddr1_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 6, 0, 12, 0),
+ .common = {
+ .reg= 0x04c,
+ .hw.init= CLK_HW_INIT("pll-ddr1", "osc24M",
+ &ccu_mult_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
static const char * const cpux_parents[] = { "osc32k", "osc24M",
"pll-cpux" , "pll-cpux" };
--
2.11.0
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[linux-sunxi] [PATCH 0/3] clk: sunxi-ng: more misc fixes
Hi Maxime, Here are 3 more clk fixes. The first one is needed for the second. The third is a TODO I spotted while doing the first two. ChenYu Chen-Yu Tsai (3): clk: sunxi-ng: mult: Support PLL lock detection clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 18 ++ drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 70 ++-- drivers/clk/sunxi-ng/ccu_mult.c | 2 ++ drivers/clk/sunxi-ng/ccu_mult.h | 2 ++ 4 files changed, 67 insertions(+), 25 deletions(-) -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 1/3] clk: sunxi-ng: mult: Support PLL lock detection
Some PLL clocks are N (multiplier) type clocks, or can be simplified
as such. An example of the former is the DDR1 PLL clock on the A33.
An example of the latter is the CPU PLL clock on the A80, in which
the P divider is only used for low frequencies that are of little
use. Both clocks support PLL lock detection.
The mult clock macro implies support for this, but that is not true.
The field is simply discarded. This patch adds proper support for it.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu_mult.c | 2 ++
drivers/clk/sunxi-ng/ccu_mult.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
index 8724c01171b1..671141359895 100644
--- a/drivers/clk/sunxi-ng/ccu_mult.c
+++ b/drivers/clk/sunxi-ng/ccu_mult.c
@@ -137,6 +137,8 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned
long rate,
spin_unlock_irqrestore(cm->common.lock, flags);
+ ccu_helper_wait_for_lock(&cm->common, cm->lock);
+
return 0;
}
diff --git a/drivers/clk/sunxi-ng/ccu_mult.h b/drivers/clk/sunxi-ng/ccu_mult.h
index 524acddfcb2e..f9c37b987d72 100644
--- a/drivers/clk/sunxi-ng/ccu_mult.h
+++ b/drivers/clk/sunxi-ng/ccu_mult.h
@@ -33,6 +33,7 @@ struct ccu_mult_internal {
struct ccu_mult {
u32 enable;
+ u32 lock;
struct ccu_frac_internalfrac;
struct ccu_mult_internalmult;
@@ -45,6 +46,7 @@ struct ccu_mult {
_flags) \
struct ccu_mult _struct = { \
.enable = _gate,\
+ .lock = _lock,\
.mult = _SUNXI_CCU_MULT(_mshift, _mwidth),\
.common = { \
.reg= _reg, \
--
2.11.0
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[linux-sunxi] [PATCH 2/3] clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks
The CPU cluster PLLs on the A80 are NP clocks that are atypical in two ways:
- The P factor is 1 bit wide, and translates to a /1 or /4 divider.
- The P factor should only be used for output frequencies lower than
288 MHz. The N factor has a lower limit of 12, which likely contributed
to this extra divider.
According to the user manual, the clocks can only go as low as 200 MHz.
The vendor BSP kernel does not even define operating points below 360
MHz for these clocks. The lower end for cpufreq in the vendor kernel is
even higher. The mainline Linux kernel doesn't support cpufreq for the
A80 at the moment. This means the lower frequencies are untested, and
will likely remain unused.
The new sunxi-ng style clocks don't support the quirks listed above.
Instead of trying to work the quirks in for something of little usage,
we re-model the clocks into N-type multipler clocks, with P fixed at 1.
At probe time we check if P is set to 4, and fix it up if needed. This
is highly unlikely though.
Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU")
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 70 ++--
1 file changed, 52 insertions(+), 18 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
index a031beefa5b5..8936ef87652c 100644
--- a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
+++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
@@ -29,41 +29,41 @@
#define CCU_SUN9I_LOCK_REG 0x09c
-static struct clk_div_table pll_cpux_p_div_table[] = {
- { .val = 0, .div = 1 },
- { .val = 1, .div = 4 },
- { /* Sentinel */ },
-};
-
/*
- * The CPU PLLs are actually NP clocks, but P is /1 or /4, so here we
- * use the NM clocks with a divider table for M.
+ * The CPU PLLs are actually NP clocks, with P being /1 or /4. However
+ * P should only be used for output frequencies lower than 228 MHz.
+ * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
+ *
+ * For now we can just model it as a multiplier clock, and force P to /1.
*/
-static struct ccu_nm pll_c0cpux_clk = {
+#define SUN9I_A80_PLL_C0CPUX_REG 0x000
+#define SUN9I_A80_PLL_C1CPUX_REG 0x004
+
+static struct ccu_mult pll_c0cpux_clk = {
.enable = BIT(31),
.lock = BIT(0),
- .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
- .m = _SUNXI_CCU_DIV_TABLE(16, 1, pll_cpux_p_div_table),
+ .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.common = {
- .reg= 0x000,
+ .reg= SUN9I_A80_PLL_C0CPUX_REG,
.lock_reg = CCU_SUN9I_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init= CLK_HW_INIT("pll-c0cpux", "osc24M",
- &ccu_nm_ops, CLK_SET_RATE_UNGATE),
+ &ccu_mult_ops,
+ CLK_SET_RATE_UNGATE),
},
};
-static struct ccu_nm pll_c1cpux_clk = {
+static struct ccu_mult pll_c1cpux_clk = {
.enable = BIT(31),
.lock = BIT(1),
- .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
- .m = _SUNXI_CCU_DIV_TABLE(16, 1, pll_cpux_p_div_table),
+ .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.common = {
- .reg= 0x004,
+ .reg= SUN9I_A80_PLL_C1CPUX_REG,
.lock_reg = CCU_SUN9I_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init= CLK_HW_INIT("pll-c1cpux", "osc24M",
- &ccu_nm_ops, CLK_SET_RATE_UNGATE),
+ &ccu_mult_ops,
+ CLK_SET_RATE_UNGATE),
},
};
@@ -1188,6 +1188,36 @@ static const struct sunxi_ccu_desc sun9i_a80_ccu_desc = {
.num_resets = ARRAY_SIZE(sun9i_a80_ccu_resets),
};
+#define SUN9I_A80_PLL_P_SHIFT 16
+#define SUN9I_A80_PLL_N_SHIFT 8
+#define SUN9I_A80_PLL_N_WIDTH 8
+
+static void sun9i_a80_cpu_pll_fixup(void __iomem *reg)
+{
+ u32 val = readl(reg);
+
+ /* bail out if P divider is not used */
+ if (!(val & BIT(SUN9I_A80_PLL_P_SHIFT)))
+ return;
+
+ /*
+* If P is used, output should be less than 288 MHz. When we
+* set P to 1, we should also decrease the multiplier so the
+* output doesn't go out of range, but not too much such that
+* the multiplier stays above 12, the minimal operation value.
+*
+* To keep it simple, set the multiplier to 17, the reset value.
+*/
+ val &= ~GENMASK(SUN9I_A80_PLL_N_SHIFT + SUN
Re: [linux-sunxi] [PATCH 02/11] arm64: allwinner: a64: add NMI controller on A64
On Wed, Apr 5, 2017 at 3:28 PM, Maxime Ripard wrote: > On Wed, Apr 05, 2017 at 02:20:31PM +0800, Chen-Yu Tsai wrote: >> On Wed, Apr 5, 2017 at 2:11 PM, Maxime Ripard >> wrote: >> > On Wed, Apr 05, 2017 at 11:51:45AM +0800, Chen-Yu Tsai wrote: >> >> On Wed, Apr 5, 2017 at 2:01 AM, Icenowy Zheng wrote: >> >> > Allwinner A64 SoC features a NMI controller, which is usually connected >> >> > to the AXP PMIC. >> >> > >> >> > Add support for it. >> >> > >> >> > Signed-off-by: Icenowy Zheng >> >> >> >> This might not be the best representation of the R_INTC block. Though >> >> we'd need to change it for all SoCs if we want to be accurate. For now, >> > >> > What do you think would be a good representation? >> >> My gut feeling is that this is the old INTC from sun4/5i. > > Ah, that would make sense. > >> It's supposed to be the interrupt controller for the embedded low >> power core. I've not done a thorough comparison though. > > Do we have some documentation / code for this one? I can't remember where or if I saw any. If Allwinner ever released any source code for the OpenRISC core we could actually verify it. However the base address of this block, in addition to the register offsets found in the driver for "allwinner,sun6i-a31-sc-nmi" do match up with the sun4i irqchip. The question is if any of the other interrupt lines are hooked up, and if yes, to what. A possibility would be that it has all the interrupt lines in the SoC also hooked up, at the same numbers as the GIC (minus 32). It would feed both the GIC and CPUS. This is just an educated guess though. Regards ChenYu -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [PATCH 04/11] mfd: axp20x: support AXP803 variant
On Wed, Apr 5, 2017 at 2:01 AM, Icenowy Zheng wrote:
> AXP803 is a new PMIC chip produced by X-Powers, usually paired with A64
> via RSB bus. The PMIC itself is like AXP288, but with RSB support and
> dedicated VBUS and ACIN.
>
> Add support for it in the axp20x mfd driver.
>
> Currently only power key function is supported.
>
> Signed-off-by: Icenowy Zheng
> ---
> drivers/mfd/axp20x-rsb.c | 1 +
> drivers/mfd/axp20x.c | 113
> +
> include/linux/mfd/axp20x.h | 40 +++-
> 3 files changed, 153 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mfd/axp20x-rsb.c b/drivers/mfd/axp20x-rsb.c
> index a732cb50bcff..3ff8a7d1ce88 100644
> --- a/drivers/mfd/axp20x-rsb.c
> +++ b/drivers/mfd/axp20x-rsb.c
> @@ -63,6 +63,7 @@ static const struct of_device_id axp20x_rsb_of_match[] = {
> { .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },
> { .compatible = "x-powers,axp806", .data = (void *)AXP806_ID },
> { .compatible = "x-powers,axp809", .data = (void *)AXP809_ID },
> + { .compatible = "x-powers,axp803", .data = (void *)AXP803_ID },
As mentioned in the previous patches, please sort them in ascending order.
> { },
> };
> MODULE_DEVICE_TABLE(of, axp20x_rsb_of_match);
> diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
> index 5ba3b04cc9b1..e468e08d84db 100644
> --- a/drivers/mfd/axp20x.c
> +++ b/drivers/mfd/axp20x.c
> @@ -43,6 +43,7 @@ static const char * const axp20x_model_names[] = {
> "AXP288",
> "AXP806",
> "AXP809",
> + "AXP803",
Same here.
> };
>
> static const struct regmap_range axp152_writeable_ranges[] = {
> @@ -165,6 +166,32 @@ static const struct regmap_access_table
> axp806_volatile_table = {
> .n_yes_ranges = ARRAY_SIZE(axp806_volatile_ranges),
> };
>
> +static const struct regmap_range axp803_writeable_ranges[] = {
> + regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
> + regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
> +};
> +
> +static const struct regmap_range axp803_volatile_ranges[] = {
> + regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP288_POWER_REASON),
> + regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL),
> + regmap_reg_range(AXP288_BC_DET_STAT, AXP288_BC_DET_STAT),
> + regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
> + regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
> + regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
> + regmap_reg_range(AXP288_RT_BATT_V_H, AXP288_RT_BATT_V_L),
> + regmap_reg_range(AXP20X_FG_RES, AXP288_FG_CC_CAP_REG),
> +};
> +
> +static const struct regmap_access_table axp803_writeable_table = {
> + .yes_ranges = axp803_writeable_ranges,
> + .n_yes_ranges = ARRAY_SIZE(axp803_writeable_ranges),
> +};
> +
> +static const struct regmap_access_table axp803_volatile_table = {
> + .yes_ranges = axp803_volatile_ranges,
> + .n_yes_ranges = ARRAY_SIZE(axp803_volatile_ranges),
> +};
> +
If they are the same as the AXP288, please just use that set,
instead of duplicating it. You can add a note, like what I did
for the AXP22x/AXP809.
> static struct resource axp152_pek_resources[] = {
> DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
> DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
> @@ -278,6 +305,20 @@ static struct resource axp809_pek_resources[] = {
> },
> };
>
> +static struct resource axp803_pek_resources[] = {
> + {
> + .name = "PEK_DBR",
> + .start = AXP803_IRQ_PEK_RIS_EDGE,
> + .end= AXP803_IRQ_PEK_RIS_EDGE,
> + .flags = IORESOURCE_IRQ,
> + }, {
> + .name = "PEK_DBF",
> + .start = AXP803_IRQ_PEK_FAL_EDGE,
> + .end= AXP803_IRQ_PEK_FAL_EDGE,
> + .flags = IORESOURCE_IRQ,
> + },
> +};
> +
You can use axp288_power_button_resources directly. See below
about the interrupts and symbol names.
> static const struct regmap_config axp152_regmap_config = {
> .reg_bits = 8,
> .val_bits = 8,
> @@ -323,6 +364,15 @@ static const struct regmap_config axp806_regmap_config =
> {
> .cache_type = REGCACHE_RBTREE,
> };
>
> +static const struct regmap_config axp803_regmap_config = {
> + .reg_bits = 8,
> + .val_bits = 8,
> + .wr_table = &axp803_writeable_table,
> + .volatile_table = &axp803_volatile_table,
> + .max_register = AXP288_FG_TUNE5,
> + .cache_type = REGCACHE_RBTREE,
> +};
> +
Drop this and use axp288_regmap_config.
> #define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \
> [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
>
> @@ -507,6 +557,43 @@ static const struct regmap_irq axp809_regmap_irqs[] = {
> INIT_REGMAP_IRQ(AXP809, GPIO0_
Re: [linux-sunxi] [PATCH 07/11] regulator: axp20x-regulator: add support for AXP803
Hi,
On Wed, Apr 5, 2017 at 2:01 AM, Icenowy Zheng wrote:
> AXP803 PMIC also have a series of regulators (DCDCs and LDOs)
> controllable via I2C/RSB bus.
>
> Add support for them.
>
> Signed-off-by: Icenowy Zheng
> ---
> drivers/regulator/axp20x-regulator.c | 135
> +++
> include/linux/mfd/axp20x.h | 37 ++
> 2 files changed, 158 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/regulator/axp20x-regulator.c
> b/drivers/regulator/axp20x-regulator.c
> index 0b9d4e3e52c7..219a731df392 100644
> --- a/drivers/regulator/axp20x-regulator.c
> +++ b/drivers/regulator/axp20x-regulator.c
> @@ -355,6 +355,81 @@ static const struct regulator_desc axp809_regulators[] =
> {
> AXP_DESC_SW(AXP809, SW, "sw", "swin", AXP22X_PWR_OUT_CTRL2, BIT(6)),
> };
>
> +static const struct regulator_linear_range axp803_dcdc234_ranges[] = {
> + REGULATOR_LINEAR_RANGE(50, 0x0, 0x46, 1),
> + REGULATOR_LINEAR_RANGE(120, 0x47, 0x4b, 2),
> +};
Can you keep the ranges the datasheet uses? It makes it easier to compare.
> +
> +static const struct regulator_linear_range axp803_dcdc5_ranges[] = {
> + REGULATOR_LINEAR_RANGE(80, 0x0, 0x20, 1),
> + REGULATOR_LINEAR_RANGE(114, 0x21, 0x43, 2),
1.14 ~ 1.84 / 0.02 = 36 steps. This would end at 0x44.
> +};
> +
> +static const struct regulator_linear_range axp803_dcdc6_ranges[] = {
> + REGULATOR_LINEAR_RANGE(60, 0x0, 0x32, 1),
> + REGULATOR_LINEAR_RANGE(112, 0x33, 0x47, 2),
> +};
> +
> +static const struct regulator_linear_range axp803_dldo2_ranges[] = {
> + REGULATOR_LINEAR_RANGE(70, 0x0, 0x1a, 10),
> + REGULATOR_LINEAR_RANGE(340, 0x1b, 0x1f, 20),
> +};
This is the same as axp806_cldo2_ranges. To keep the variants sorted
in ascending order, you could keep this version but replace references
to axp806_cldo2_ranges with this one.
> +
> +static const struct regulator_desc axp803_regulators[] = {
> + AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
> +AXP803_DCDC1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(0)),
> + AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2", axp803_dcdc234_ranges,
> + 76, AXP803_DCDC2_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
> + BIT(1)),
> + AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3", axp803_dcdc234_ranges,
> + 76, AXP803_DCDC3_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
> + BIT(2)),
> + AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4", axp803_dcdc234_ranges,
> + 76, AXP803_DCDC4_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
> + BIT(3)),
> + AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5", axp803_dcdc5_ranges,
> + 68, AXP803_DCDC5_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
> + BIT(4)),
> + AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6", axp803_dcdc6_ranges,
> + 72, AXP803_DCDC6_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
> + BIT(5)),
> + /* secondary switchable output of DCDC1 */
> + AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL, AXP22X_PWR_OUT_CTRL2,
> + BIT(7)),
> + AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
> +AXP22X_ALDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(5)),
> + AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
> +AXP22X_ALDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(6)),
> + AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
> +AXP22X_ALDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(7)),
> + AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
> +AXP22X_DLDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(3)),
> + AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin", axp803_dldo2_ranges,
> + 32, AXP22X_DLDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2,
> + BIT(4)),
> + AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
> +AXP22X_DLDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(5)),
> + AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
> +AXP22X_DLDO4_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(6)),
dldo3 and dldo4 are controlled from AXP22X_PWR_OUT_CTRL2.
> + AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
> +AXP22X_ELDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(0)),
> + AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
> +AXP22X_ELDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(1)),
> + AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
> +AXP22X_ELDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(2)),
> + AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
> +AXP803_FLDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(2)),
> + AXP_DES
Re: [linux-sunxi] [PATCH 04/11] mfd: axp20x: support AXP803 variant
On Wed, Apr 5, 2017 at 11:03 PM, Icenowy Zheng wrote:
>
>
> 在 2017年04月05日 22:58, Chen-Yu Tsai 写道:
>>
>> On Wed, Apr 5, 2017 at 2:01 AM, Icenowy Zheng wrote:
>>>
>>> AXP803 is a new PMIC chip produced by X-Powers, usually paired with A64
>>> via RSB bus. The PMIC itself is like AXP288, but with RSB support and
>>> dedicated VBUS and ACIN.
>>>
>>> Add support for it in the axp20x mfd driver.
>>>
>>> Currently only power key function is supported.
>>>
>>> Signed-off-by: Icenowy Zheng
>>> ---
>>> drivers/mfd/axp20x-rsb.c | 1 +
>>> drivers/mfd/axp20x.c | 113
>>> +
>>> include/linux/mfd/axp20x.h | 40 +++-
>>> 3 files changed, 153 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/mfd/axp20x-rsb.c b/drivers/mfd/axp20x-rsb.c
>>> index a732cb50bcff..3ff8a7d1ce88 100644
>>> --- a/drivers/mfd/axp20x-rsb.c
>>> +++ b/drivers/mfd/axp20x-rsb.c
>>> @@ -63,6 +63,7 @@ static const struct of_device_id axp20x_rsb_of_match[]
>>> = {
>>> { .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },
>>> { .compatible = "x-powers,axp806", .data = (void *)AXP806_ID },
>>> { .compatible = "x-powers,axp809", .data = (void *)AXP809_ID },
>>> + { .compatible = "x-powers,axp803", .data = (void *)AXP803_ID },
>>
>>
>> As mentioned in the previous patches, please sort them in ascending order.
>>
>>> { },
>>> };
>>> MODULE_DEVICE_TABLE(of, axp20x_rsb_of_match);
>>> diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
>>> index 5ba3b04cc9b1..e468e08d84db 100644
>>> --- a/drivers/mfd/axp20x.c
>>> +++ b/drivers/mfd/axp20x.c
>>> @@ -43,6 +43,7 @@ static const char * const axp20x_model_names[] = {
>>> "AXP288",
>>> "AXP806",
>>> "AXP809",
>>> + "AXP803",
>>
>>
>> Same here.
>>
>>> };
>>>
>>> static const struct regmap_range axp152_writeable_ranges[] = {
>>> @@ -165,6 +166,32 @@ static const struct regmap_access_table
>>> axp806_volatile_table = {
>>> .n_yes_ranges = ARRAY_SIZE(axp806_volatile_ranges),
>>> };
>>>
>>> +static const struct regmap_range axp803_writeable_ranges[] = {
>>> + regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
>>> + regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
>>> +};
>>> +
>>> +static const struct regmap_range axp803_volatile_ranges[] = {
>>> + regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP288_POWER_REASON),
>>> + regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL),
>>> + regmap_reg_range(AXP288_BC_DET_STAT, AXP288_BC_DET_STAT),
>>> + regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
>>> + regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
>>> + regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
>>> + regmap_reg_range(AXP288_RT_BATT_V_H, AXP288_RT_BATT_V_L),
>>> + regmap_reg_range(AXP20X_FG_RES, AXP288_FG_CC_CAP_REG),
>>> +};
>>> +
>>> +static const struct regmap_access_table axp803_writeable_table = {
>>> + .yes_ranges = axp803_writeable_ranges,
>>> + .n_yes_ranges = ARRAY_SIZE(axp803_writeable_ranges),
>>> +};
>>> +
>>> +static const struct regmap_access_table axp803_volatile_table = {
>>> + .yes_ranges = axp803_volatile_ranges,
>>> + .n_yes_ranges = ARRAY_SIZE(axp803_volatile_ranges),
>>> +};
>>> +
>>
>>
>> If they are the same as the AXP288, please just use that set,
>> instead of duplicating it. You can add a note, like what I did
>> for the AXP22x/AXP809.
>>
>>> static struct resource axp152_pek_resources[] = {
>>> DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
>>> DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
>>> @@ -278,6 +305,20 @@ static struct resource axp809_pek_resources[] = {
>>> },
>>> };
>>>
>>> +static struct resource axp803_pek_resources[] = {
>>> + {
>>> + .name = "PEK_DBR",
>>> + .start = AXP803_IRQ_PEK_RIS_EDGE,
>>> + .end= AXP803_IRQ_
[linux-sunxi] Re: [PATCH 1/3] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
On Wed, Apr 5, 2017 at 8:58 PM, Kishon Vijay Abraham I wrote:
>
>
> On Wednesday 05 April 2017 06:20 PM, Icenowy Zheng wrote:
>> From: Icenowy Zheng
>>
>> Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
>> controllers: one is MUSB and the other is a EHCI/OHCI pair.
>>
>> When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
>> tweak, like other EHCI/OHCI pairs in Allwinner SoCs.
>>
>> Add this to the binding of USB PHYs on Allwinner H3/V3s/A64.
>>
>> Signed-off-by: Icenowy Zheng
>> Acked-by: Chen-Yu Tsai
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>>
>> Kishon, could you push this to 4.11?
>
> Is this for the patch titled "phy: sun4i-usb: add support for V3s USB PHY"
> that
> was added during the last merge window.
Yes. In fact, as the description suggests, this also applies retroactively to
H3 and A64, which were added in the following commits:
4.9 732e35da7b4a ("dt: bindings: add bindings for Allwinner A64 usb phy")
4.5 626a630e003c ("phy-sun4i-usb: Add support for the host usb-phys found
on the H3 SoC")
Though this was missed at the time the binding was added.
ChenYu
> this patch looks simpler enough to be merged in this -rc cycle. However it
> depends on Greg KH.
>
> Thanks
> Kishon
>
>>
>> Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
>> b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
>> index e42334258185..005bc22938ff 100644
>> --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
>> +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
>> @@ -15,6 +15,7 @@ Required properties:
>> - reg : a list of offset + length pairs
>> - reg-names :
>>* "phy_ctrl"
>> + * "pmu0" for H3, V3s and A64
>>* "pmu1"
>>* "pmu2" for sun4i, sun6i or sun7i
>> - #phy-cells : from the generic phy bindings, must be 1
>>
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[linux-sunxi] Re: [PATCH 09/11] drm/sun4i: Support two display pipelines
Hi,
On Thu, Mar 9, 2017 at 10:40 PM, Maxime Ripard
wrote:
> On Thu, Mar 09, 2017 at 07:20:30PM +0800, Chen-Yu Tsai wrote:
>> On Thu, Mar 9, 2017 at 6:36 PM, Maxime Ripard
>> wrote:
>> > Hi,
>> >
>> > On Thu, Mar 09, 2017 at 06:05:32PM +0800, Chen-Yu Tsai wrote:
>> >> Some Allwinner SoCs have two display pipelines (frontend -> backend ->
>> >> tcon).
>> >>
>> >> Previously we only supported one pipeline. This patch extends the
>> >> current driver to support two. It extends the tcon and backend pointers
>> >> in sun4i_drv into arrays, and makes the related bind functions store
>> >> the pointer into said arrays based on the id fetched from the device
>> >> tree. In the case of the tcons, it falls back to a first come order
>> >> if no encoders that can be used for differentiating the tcons are
>> >> defined. The driver's depth-first traversal of the of graph, coupled
>> >> with the increasing address ordering of the of graph endpoints, and
>> >> the fact that tcon0 should always be enabled for the tcon/encoder
>> >> mux to be accessible, means that tcon1 would always come after tcon0.
>> >>
>> >> Assignment of the device structure into sun4i_drv is moved to the end
>> >> of the bind function, when all possible error checks have passed.
>> >>
>> >> This patch also drops a trailing 0 in one of the backend probe messages.
>> >>
>> >> Signed-off-by: Chen-Yu Tsai
>> >> ---
>> >> drivers/gpu/drm/sun4i/sun4i_backend.c | 9 +++--
>> >> drivers/gpu/drm/sun4i/sun4i_drv.c | 2 +-
>> >> drivers/gpu/drm/sun4i/sun4i_drv.h | 6 --
>> >> drivers/gpu/drm/sun4i/sun4i_tcon.c| 25 +
>> >> 4 files changed, 29 insertions(+), 13 deletions(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c
>> >> b/drivers/gpu/drm/sun4i/sun4i_backend.c
>> >> index f3c92d54c8e4..8d22efd5a9cc 100644
>> >> --- a/drivers/gpu/drm/sun4i/sun4i_backend.c
>> >> +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
>> >> @@ -350,12 +350,15 @@ static int sun4i_backend_bind(struct device *dev,
>> >> struct device *master,
>> >> if (!backend)
>> >> return -ENOMEM;
>> >> dev_set_drvdata(dev, backend);
>> >> - drv->backend = backend;
>> >>
>> >> backend->id = sun4i_backend_of_get_id(dev->of_node);
>> >> if (backend->id < 0)
>> >> return backend->id;
>> >>
>> >> + /* We only support SUN4I_DRM_MAX_PIPELINES number of backends */
>> >> + if (backend->id >= SUN4I_DRM_MAX_PIPELINES)
>> >> + return -EINVAL;
>> >> +
>> >> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> >> regs = devm_ioremap_resource(dev, res);
>> >> if (IS_ERR(regs))
>> >> @@ -364,7 +367,7 @@ static int sun4i_backend_bind(struct device *dev,
>> >> struct device *master,
>> >> backend->regs = devm_regmap_init_mmio(dev, regs,
>> >> &sun4i_backend_regmap_config);
>> >> if (IS_ERR(backend->regs)) {
>> >> - dev_err(dev, "Couldn't create the backend0 regmap\n");
>> >> + dev_err(dev, "Couldn't create the backend regmap\n");
>> >> return PTR_ERR(backend->regs);
>> >> }
>> >>
>> >> @@ -413,6 +416,8 @@ static int sun4i_backend_bind(struct device *dev,
>> >> struct device *master,
>> >> }
>> >> }
>> >>
>> >> + drv->backend[backend->id] = backend;
>> >> +
>> >> /* Reset the registers */
>> >> for (i = 0x800; i < 0x1000; i += 4)
>> >> regmap_write(backend->regs, i, 0);
>> >> diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
>> >> b/drivers/gpu/drm/sun4i/sun4i_drv.c
>> >> index 767bbadcc85d..c15ecb8343d7 100644
>> >> --- a/drivers/gpu/drm/sun4i/sun4i_drv.c
>> >> +++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
>> >> @@ -271,7 +271,7 @@ static int sun4i_drv_probe(struct platform_device
>> >> *pdev)
>> >> struct device_node *np = pdev->dev.of_node;
>> >&
Re: [linux-sunxi] [PATCH 2/5] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
Hi,
On Sun, Apr 9, 2017 at 2:50 AM, Icenowy Zheng wrote:
The subject can just say "set CLK_SET_RATE_PARENT for CPUX clock on H3".
> The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
> can be adjusted by changing the frequency of the PLL_CPUX clock.
>
> Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
> clock can be adjusted when adjusting the CPUX clock.
>
This paragraph needs some work, particularly the verbs you chose. In the
clk subsystem "setting parent clock" actually refers to re-parenting.
>From include/linux/clk-provider.h:
#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
So what you want to say is to propagate rate changes to CPUX up one
level, so PLL_CPUX gets changed as well.
The precise wording could be something like:
The CPUX clock is the clock source for the ARM cores on the H3 SoC.
It is a mux clock fed by, amongst other fixed clock sources, the
configurable PLL_CPUX.
Set CLK_SET_RATE_PARENT on the CPUX clock, so rate changes to it
are propagated up one level to the PLL_CPUX clock.
ChenYu
> Signed-off-by: Icenowy Zheng
> ---
> drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> index 4cbc1b701b7c..90b4e26a70bc 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> @@ -135,7 +135,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk,
> "pll-de",
> static const char * const cpux_parents[] = { "osc32k", "osc24M",
> "pll-cpux" , "pll-cpux" };
> static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
> -0x050, 16, 2, CLK_IS_CRITICAL);
> +0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
>
> static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
>
> --
> 2.12.2
>
> --
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Re: [linux-sunxi] Re: [PATCH v2 03/11] dt-bindings: add device tree binding for X-Powers AXP803 PMIC
Hi, On Tue, Apr 11, 2017 at 11:00 PM, Icenowy Zheng wrote: > > > On Tue, 11 Apr 2017, Lee Jones wrote: > >> On Sat, 08 Apr 2017, Icenowy Zheng wrote: >> >>> AXP803 is a PMIC produced by Shenzhen X-Powers, with either I2C or RSB >>> bus. >>> >>> Add a compatible for it. >>> >>> Signed-off-by: Icenowy Zheng >>> Acked-by: Chen-Yu Tsai >>> --- >>> Changes in v2: >>> - Place AXP803 before AXP806/809. >>> - Added Chen-Yu's ACK. >>> >>> Documentation/devicetree/bindings/mfd/axp20x.txt | 5 +++-- >>> 1 file changed, 3 insertions(+), 2 deletions(-) >> >> >> For my own reference: >> Acked-for-MFD-by: Lee Jones > > > Excuse me... Who will apply this patch? > > I think this patch should be applied by you as it's in bindings/mfd > directory, however, if I'm wrong, please point out ;-) We need the DT maintainers to ack it first. :) ChenYu -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 1/3] clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks
In common PLL designs, changes to the dividers take effect almost
immediately, while changes to the multipliers (implemented as
dividers in the feedback loop) take a few cycles to work into
the feedback loop for the PLL to stablize.
Sometimes when the PLL clock rate is changed, the decrease in the
divider is too much for the decrease in the multiplier to catch up.
The PLL clock rate will spike, and in some cases, might lock up
completely. This is especially the case if the divider changed is
the pre-divider, which affects the reference frequency.
This patch introduces a clk notifier callback that will gate and
then ungate a clk after a rate change, effectively resetting it,
so it continues to work, despite any possible lockups. Care must
be taken to reparent any consumers to other temporary clocks during
the rate change, and that this notifier callback must be the first
to be registered.
This is intended to fix occasional lockups with cpufreq on newer
Allwinner SoCs, such as the A33 and the H3. Previously it was
thought that reparenting the cpu clock away from the PLL while
it stabilized was enough, as this worked quite well on the A31.
On the A33, hangs have been observed after cpufreq was recently
introduced. With the H3, a more thorough test [1] showed that
reparenting alone isn't enough. The system still locks up unless
the dividers are limited to 1.
A hunch was if the PLL was stuck in some unknown state, perhaps
gating then ungating it would bring it back to normal. Tests
done by Icenowy Zheng using Ondrej's test firmware shows this
to be a valid solution.
[1] http://www.spinics.net/lists/arm-kernel/msg552501.html
Reported-by: Ondrej Jirman
Signed-off-by: Chen-Yu Tsai
Tested-by: Icenowy Zheng
Tested-by: Quentin Schulz
---
drivers/clk/sunxi-ng/ccu_common.c | 49 +++
drivers/clk/sunxi-ng/ccu_common.h | 12 ++
2 files changed, 61 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu_common.c
b/drivers/clk/sunxi-ng/ccu_common.c
index 188fa50d0380..40aac316128f 100644
--- a/drivers/clk/sunxi-ng/ccu_common.c
+++ b/drivers/clk/sunxi-ng/ccu_common.c
@@ -14,11 +14,13 @@
* GNU General Public License for more details.
*/
+#include
#include
#include
#include
#include "ccu_common.h"
+#include "ccu_gate.h"
#include "ccu_reset.h"
static DEFINE_SPINLOCK(ccu_lock);
@@ -39,6 +41,53 @@ void ccu_helper_wait_for_lock(struct ccu_common *common, u32
lock)
WARN_ON(readl_relaxed_poll_timeout(addr, reg, reg & lock, 100, 7));
}
+/*
+ * This clock notifier is called when the frequency of a PLL clock is
+ * changed. In common PLL designs, changes to the dividers take effect
+ * almost immediately, while changes to the multipliers (implemented
+ * as dividers in the feedback loop) take a few cycles to work into
+ * the feedback loop for the PLL to stablize.
+ *
+ * Sometimes when the PLL clock rate is changed, the decrease in the
+ * divider is too much for the decrease in the multiplier to catch up.
+ * The PLL clock rate will spike, and in some cases, might lock up
+ * completely.
+ *
+ * This notifier callback will gate and then ungate the clock,
+ * effectively resetting it, so it proceeds to work. Care must be
+ * taken to reparent consumers to other temporary clocks during the
+ * rate change, and that this notifier callback must be the first
+ * to be registered.
+ */
+static int ccu_pll_notifier_cb(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct ccu_pll_nb *pll = to_ccu_pll_nb(nb);
+ int ret = 0;
+
+ if (event != POST_RATE_CHANGE)
+ goto out;
+
+ ccu_gate_helper_disable(pll->common, pll->enable);
+
+ ret = ccu_gate_helper_enable(pll->common, pll->enable);
+ if (ret)
+ goto out;
+
+ ccu_helper_wait_for_lock(pll->common, pll->lock);
+
+out:
+ return notifier_from_errno(ret);
+}
+
+int ccu_pll_notifier_register(struct ccu_pll_nb *pll_nb)
+{
+ pll_nb->clk_nb.notifier_call = ccu_pll_notifier_cb;
+
+ return clk_notifier_register(pll_nb->common->hw.clk,
+&pll_nb->clk_nb);
+}
+
int sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
const struct sunxi_ccu_desc *desc)
{
diff --git a/drivers/clk/sunxi-ng/ccu_common.h
b/drivers/clk/sunxi-ng/ccu_common.h
index 73d81dc58fc5..d6fdd7a789aa 100644
--- a/drivers/clk/sunxi-ng/ccu_common.h
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -83,6 +83,18 @@ struct sunxi_ccu_desc {
void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock);
+struct ccu_pll_nb {
+ struct notifier_block clk_nb;
+ struct ccu_common *common;
+
+ u32 enable;
+ u32 lock;
+};
+
+#define to_ccu_pll_nb(_nb) container_of(_nb, struct ccu_pll_nb, clk_nb)
+
+int ccu_pll_notifier_register(struct ccu_pll_n
[linux-sunxi] [PATCH 0/3] clk: sunxi-ng: gate/ungate PLL CPU clk after rate change
Hi everyone,
This series adds a clk notifier for use on the PLL CPU clks found in
Allwinner SoCs. Some people have observed issues with the design and
implementation of the CPU PLL clock, starting from the A31. Changes
to the PLL clock need a few cycles to stabilize. If the changes are
too drastic, the dividers in particular, there is a good chance that
the system will hang.
Previously we thought that reparenting the CPU clock away from the PLL
while changes were made, and then reparenting it back once it was stable,
should have been enough to mitigate the issue. Unfortunately it was
not. With cpufreq support for A33 recently introduced in commit
03749eb88e63 ("ARM: dts: sun8i: add opp-v2 table for A33"), system hangs
were observed one out of two to three boots, right after userspace
configured cpufreq to switch to the ondemand governor. Other experiments
done by Ondrej Jirman [1] show that it is not enough to just reparent
the CPU clock, but the PLL clock's dividers must not be used.
We suspect the divider changes make the PLL unstable to the point that
it can not recover, possibly not providing any output afterwards. We
lack any hard evidence (oscilloscope readings or hardware implementation
details) to fully explain the behavior. However, if the hardware is
stuck in some undesired state, it is possible to "reset" it, by gating
the PLL, then ungating it.
This series adds a new clk notifier that does exactly that. The clk
notifier is registered on the PLL clock. Whenever its rate is changed,
the notifier comes in and toggles the gate. The notifier should always
be the first one registered. And all consumers of the clock must also
have notifiers on it to temporarily reparent away during the change.
Patches 2 and 3 register this new notifier for the CPU PLL clocks on
the A33 and H3, respectively. With the first 2 patches applied, the
cpufreq related system hangs on the A33 go away.
Given that commit 03749eb88e63 ("ARM: dts: sun8i: add opp-v2 table for
A33") is already in v4.11-rc, I suggest we either try to merge the
first 2 patches for a very late -rc fix, or drop A33 cpufreq support
from v4.11, and add it later once this series is merged.
Regards
ChenYu
[1] http://www.spinics.net/lists/arm-kernel/msg552501.html
Chen-Yu Tsai (3):
clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks
clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate change
clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change
drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 11
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 11
drivers/clk/sunxi-ng/ccu_common.c| 49
drivers/clk/sunxi-ng/ccu_common.h| 12 +
4 files changed, 83 insertions(+)
--
2.11.0
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[linux-sunxi] [PATCH 3/3] clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change
This patch utilizes the new PLL clk notifier to gate then ungate the
PLL CPU clock after rate changes. This should prevent any system hangs
resulting from cpufreq changes to the clk.
Reported-by: Ondrej Jirman
Signed-off-by: Chen-Yu Tsai
Tested-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 4cbc1b701b7c..fc04ef2af1ac 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -1103,6 +1103,13 @@ static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
.num_resets = ARRAY_SIZE(sun50i_h5_ccu_resets),
};
+static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {
+ .common = &pll_cpux_clk.common,
+ /* copy from pll_cpux_clk */
+ .enable = BIT(31),
+ .lock = BIT(28),
+};
+
static struct ccu_mux_nb sun8i_h3_cpu_nb = {
.common = &cpux_clk.common,
.cm = &cpux_clk.mux,
@@ -1130,6 +1137,10 @@ static void __init sunxi_h3_h5_ccu_init(struct
device_node *node,
sunxi_ccu_probe(node, reg, desc);
+ /* Gate then ungate PLL CPU after any rate changes */
+ ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
+
+ /* Reparent CPU during PLL CPU rate changes */
ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
&sun8i_h3_cpu_nb);
}
--
2.11.0
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[linux-sunxi] [PATCH 2/3] clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate change
This patch utilizes the new PLL clk notifier to gate then ungate the
PLL CPU clock after rate changes. This should mitigate the system
hangs observed after the introduction of cpufreq for the A33.
Signed-off-by: Chen-Yu Tsai
Tested-by: Quentin Schulz
---
drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index 56370c2c7f98..8d38e6510e29 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -756,6 +756,13 @@ static const struct sunxi_ccu_desc sun8i_a33_ccu_desc = {
.num_resets = ARRAY_SIZE(sun8i_a33_ccu_resets),
};
+static struct ccu_pll_nb sun8i_a33_pll_cpu_nb = {
+ .common = &pll_cpux_clk.common,
+ /* copy from pll_cpux_clk */
+ .enable = BIT(31),
+ .lock = BIT(28),
+};
+
static struct ccu_mux_nb sun8i_a33_cpu_nb = {
.common = &cpux_clk.common,
.cm = &cpux_clk.mux,
@@ -787,6 +794,10 @@ static void __init sun8i_a33_ccu_setup(struct device_node
*node)
sunxi_ccu_probe(node, reg, &sun8i_a33_ccu_desc);
+ /* Gate then ungate PLL CPU after any rate changes */
+ ccu_pll_notifier_register(&sun8i_a33_pll_cpu_nb);
+
+ /* Reparent CPU during PLL CPU rate changes */
ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
&sun8i_a33_cpu_nb);
}
--
2.11.0
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[linux-sunxi] Re: [PATCH 1/3] clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks
On Thu, Apr 13, 2017 at 3:02 PM, Maxime Ripard wrote: > Hi Chen-Yu, > > On Thu, Apr 13, 2017 at 10:13:52AM +0800, Chen-Yu Tsai wrote: >> In common PLL designs, changes to the dividers take effect almost >> immediately, while changes to the multipliers (implemented as >> dividers in the feedback loop) take a few cycles to work into >> the feedback loop for the PLL to stablize. >> >> Sometimes when the PLL clock rate is changed, the decrease in the >> divider is too much for the decrease in the multiplier to catch up. >> The PLL clock rate will spike, and in some cases, might lock up >> completely. This is especially the case if the divider changed is >> the pre-divider, which affects the reference frequency. >> >> This patch introduces a clk notifier callback that will gate and >> then ungate a clk after a rate change, effectively resetting it, >> so it continues to work, despite any possible lockups. Care must >> be taken to reparent any consumers to other temporary clocks during >> the rate change, and that this notifier callback must be the first >> to be registered. >> >> This is intended to fix occasional lockups with cpufreq on newer >> Allwinner SoCs, such as the A33 and the H3. Previously it was >> thought that reparenting the cpu clock away from the PLL while >> it stabilized was enough, as this worked quite well on the A31. >> >> On the A33, hangs have been observed after cpufreq was recently >> introduced. With the H3, a more thorough test [1] showed that >> reparenting alone isn't enough. The system still locks up unless >> the dividers are limited to 1. >> >> A hunch was if the PLL was stuck in some unknown state, perhaps >> gating then ungating it would bring it back to normal. Tests >> done by Icenowy Zheng using Ondrej's test firmware shows this >> to be a valid solution. >> >> [1] http://www.spinics.net/lists/arm-kernel/msg552501.html >> >> Reported-by: Ondrej Jirman >> Signed-off-by: Chen-Yu Tsai >> Tested-by: Icenowy Zheng >> Tested-by: Quentin Schulz > > Thanks for looking into this, and coming up with a clean solution, and > a great commit log. > > However, I wondering, isn't that notifier just a re-implementation of > CLK_SET_RATE_GATE? They are not the same. AFAIK, CLK_SET_RATE_GATE tells the clk framework that this clk's rate cannot be changed if it is enabled (which means some one is using it). However the clk framework does nothing to actually handle it. It just returns an error. Any consumers are responsible for gating the clock before making changes. This is a nice thing to have, as it can prevent unintended changes to dot clocks or audio clocks used with active output streams. We could consider setting this for the audio and video PLLs. Here we are dealing with the CPU PLL, which, for practical reasons, is always enabled as far as the clk framework is concerned. The reason being the OPPs are never low enough for the CPU clock to use any other parent. To have it disabled, we would have to kick consumers (the CPU clock in this case) to use other clocks, so it's safe, remember which ones we kicked, and then bring them back once everything is done. AFAIK, we, samsung, rockchip, meson, do the temporary reparenting using clk_notifiers to access the mux registers directly. As far as the clk framework is concerned, nothing has changed. I'm not saying it's not possible to support this in the core, but the core already has to do a lot of bookkeeping and recalculation when anything changes. Adding something transient into the process isn't helping. And the reparenting might temporarily violate any downstream requirements. For now, I think clk notifiers is the easier solution for these one off requirements that are pretty much contained in a small part of the system. Regards ChenYu -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH resend v2 03/13] sunxi: Enable AXP221s in I2C mode with the R40 SoC
The R40 SoC uses the AXP221s in I2C mode to supply power. Some regulator's common usages have changed, and also the recommended voltage for existing usages have changed. Update the defaults to match. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- arch/arm/mach-sunxi/pmic_bus.c | 7 +++ board/sunxi/Kconfig| 2 +- drivers/power/Kconfig | 16 ++-- 3 files changed, 18 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c index 7c57f02792b9..f917c3e070a5 100644 --- a/arch/arm/mach-sunxi/pmic_bus.c +++ b/arch/arm/mach-sunxi/pmic_bus.c @@ -41,6 +41,9 @@ int pmic_bus_init(void) p2wi_init(); ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR, AXP221_INIT_DATA); +# elif defined CONFIG_MACH_SUN8I_R40 + /* Nothing. R40 uses the AXP221s in I2C mode */ + ret = 0; # else ret = rsb_init(); if (ret) @@ -65,6 +68,8 @@ int pmic_bus_read(u8 reg, u8 *data) #elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER # ifdef CONFIG_MACH_SUN6I return p2wi_read(reg, data); +# elif defined CONFIG_MACH_SUN8I_R40 + return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); # else return rsb_read(AXP223_RUNTIME_ADDR, reg, data); # endif @@ -80,6 +85,8 @@ int pmic_bus_write(u8 reg, u8 data) #elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER # ifdef CONFIG_MACH_SUN6I return p2wi_write(reg, data); +# elif defined CONFIG_MACH_SUN8I_R40 + return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1); # else return rsb_write(AXP223_RUNTIME_ADDR, reg, data); # endif diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 67ceae35bf9b..9e69c59784af 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -466,7 +466,7 @@ config USB3_VBUS_PIN config I2C0_ENABLE bool "Enable I2C/TWI controller 0" - default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I + default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40 default n if MACH_SUN6I || MACH_SUN8I select CMD_I2C ---help--- diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 64e5bc2f74b4..911ecb1144a6 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -10,7 +10,7 @@ choice prompt "Select Sunxi PMIC Variant" depends on ARCH_SUNXI default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I - default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 + default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40 default AXP818_POWER if MACH_SUN8I_A83T default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I @@ -37,7 +37,7 @@ config AXP209_POWER config AXP221_POWER bool "axp221 / axp223 pmic support" - depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 + depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40 select CMD_POWEROFF ---help--- Select this to enable support for the axp221/axp223 pmic found on most @@ -70,7 +70,7 @@ endchoice config AXP_DCDC1_VOLT int "axp pmic dcdc1 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER - default 3300 if AXP818_POWER + default 3300 if AXP818_POWER || MACH_SUN8I_R40 default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I ---help--- Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to @@ -97,6 +97,7 @@ config AXP_DCDC2_VOLT On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V. On A80 boards dcdc2 powers the GPU and can be left off. On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V. + On R40 boards dcdc2 is VDD-CPU and should be 1.1V config AXP_DCDC3_VOLT int "axp pmic dcdc3 voltage" @@ -104,6 +105,7 @@ config AXP_DCDC3_VOLT default 900 if AXP809_POWER || AXP818_POWER default 1500 if AXP152_POWER default 1250 if AXP209_POWER + default 1100 if MACH_SUN8I_R40 default 1200 if MACH_SUN6I || MACH_SUN8I ---help--- Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to @@ -114,6 +116,7 @@ config AXP_DCDC3_VOLT On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V. On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V. On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V. + On R40 boards dcdc3 is VDD-SYS and VDD-GPU and should be 1.1V. config AXP_DCDC4_VOLT int "axp pmic dcdc4 voltage" @@ -138,13 +141,13 @@ config AXP_DCDC5_VOLT ---help--- Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to
[linux-sunxi] [PATCH resend v2 07/13] sunxi: Provide defaults for R40 DRAM settings
These values were taken from the Banana Pi M2 Ultra fex file found in the released vendor BSP. This is the only publicly available R40 device at the time of this writing. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- board/sunxi/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 9e69c59784af..94d01cb5c1ec 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -203,6 +203,7 @@ config DRAM_TYPE config DRAM_CLK int "sunxi dram clock speed" default 792 if MACH_SUN9I + default 648 if MACH_SUN8I_R40 default 312 if MACH_SUN6I || MACH_SUN8I default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I default 672 if MACH_SUN50I @@ -224,6 +225,7 @@ config DRAM_ZQ int "sunxi dram zq value" default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I default 127 if MACH_SUN7I + default 3881979 if MACH_SUN8I_R40 default 4145117 if MACH_SUN9I default 3881915 if MACH_SUN50I ---help--- @@ -233,6 +235,7 @@ config DRAM_ODT_EN bool "sunxi dram odt enable" default n if !MACH_SUN8I_A23 default y if MACH_SUN8I_A23 + default y if MACH_SUN8I_R40 default y if MACH_SUN50I ---help--- Select this to enable dram odt (on die termination). -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH resend v2 13/13] sunxi: Add support for Bananapi M2 Ultra
The Bananapi M2 Ultra is the first publicly available development board
featuring the R40 SoC.
This patch add barebone dtsi/dts files for the R40 and Bananapi M2 Ultra,
as well as a defconfig for it.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
arch/arm/dts/Makefile| 2 +
arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 69 ++
arch/arm/dts/sun8i-r40.dtsi | 183 +++
board/sunxi/MAINTAINERS | 6 +
configs/Bananapi_M2_Ultra_defconfig | 15 +++
5 files changed, 275 insertions(+)
create mode 100644 arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
create mode 100644 arch/arm/dts/sun8i-r40.dtsi
create mode 100644 configs/Bananapi_M2_Ultra_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ce34e3eeff8a..198693c823c6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -304,6 +304,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-h3-nanopi-neo.dtb \
sun8i-h3-nanopi-neo-air.dtb
+dtb-$(CONFIG_MACH_SUN8I_R40) += \
+ sun8i-r40-bananapi-m2-ultra.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-orangepi-pc2.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
diff --git a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
new file mode 100644
index ..ab471ab0bffb
--- /dev/null
+++ b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-r40.dtsi"
+
+/ {
+ model = "Banana Pi BPI-M2-Ultra";
+ compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi
new file mode 100644
index 0000..48ec2e855a2c
--- /dev/null
+++ b/arch/arm/dts/sun8i-r40.dtsi
@@ -0,0 +1,183 @@
+/*
+ * Copyright 2016 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that
[linux-sunxi] [PATCH resend v2 08/13] gpio: sunxi: Add compatible string for R40 PIO
The PIO on the R40 SoC is mostly compatible with the A20.
Only a few pin functions for mmc2 were added to the PC
pingroup, to support 8 bit eMMCs.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
drivers/gpio/sunxi_gpio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 8d2bb18504ae..3f40e8383001 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -352,6 +352,7 @@ static const struct udevice_id sunxi_gpio_ids[] = {
ID("allwinner,sun8i-a33-pinctrl", a_all),
ID("allwinner,sun8i-a83t-pinctrl", a_all),
ID("allwinner,sun8i-h3-pinctrl",a_all),
+ ID("allwinner,sun8i-r40-pinctrl", a_all),
ID("allwinner,sun9i-a80-pinctrl", a_all),
ID("allwinner,sun6i-a31-r-pinctrl", l_2),
ID("allwinner,sun8i-a23-r-pinctrl", l_1),
--
2.11.0
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[linux-sunxi] [PATCH resend v2 01/13] sunxi: Split up long Kconfig lines
Currently we have some lines in board/sunxi/Kconfig that are very long. These line either provide default values for a set of SoCs, or limit some option to a subset of sunxi SoCs. Fortunately Kconfig makes it easy to split them. The Kconfig language document states If multiple dependencies are defined, they are connected with '&&'. This means we can split existing dependencies at "&&" symbols. This applies to both the "depends on" lines and "if" expressions. This patch splits them up to one symbol per line. This will make it easier to add, remove, or modify one item at a time. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- board/sunxi/Kconfig | 25 - 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index a667c9e5c5c1..bd0019713984 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -159,7 +159,10 @@ endchoice # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" config MACH_SUN8I bool - default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUNXI_H3_H5 || MACH_SUN8I_A83T + default y if MACH_SUN8I_A23 + default y if MACH_SUN8I_A33 + default y if MACH_SUN8I_A83T + default y if MACH_SUNXI_H3_H5 config RESERVE_ALLWINNER_BOOT0_HEADER bool "reserve space for Allwinner boot0 header" @@ -308,9 +311,13 @@ config DRAM_ODT_CORRECTION endif config SYS_CLK_FREQ - default 81600 if MACH_SUN50I + default 100800 if MACH_SUN4I + default 100800 if MACH_SUN5I + default 100800 if MACH_SUN6I default 91200 if MACH_SUN7I - default 100800 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I || MACH_SUN9I + default 100800 if MACH_SUN8I + default 100800 if MACH_SUN9I + default 81600 if MACH_SUN50I config SYS_CONFIG_NAME default "sun4i" if MACH_SUN4I @@ -512,7 +519,10 @@ config AXP_GPIO config VIDEO bool "Enable graphical uboot console on HDMI, LCD or VGA" - depends on !MACH_SUN8I_A83T && !MACH_SUNXI_H3_H5 && !MACH_SUN9I && !MACH_SUN50I + depends on !MACH_SUN8I_A83T + depends on !MACH_SUNXI_H3_H5 + depends on !MACH_SUN9I + depends on !MACH_SUN50I default y ---help--- Say Y here to add support for using a cfb console on the HDMI, LCD @@ -714,7 +724,12 @@ config GMAC_TX_DELAY Set the GMAC Transmit Clock Delay Chain value. config SPL_STACK_R_ADDR - default 0x4fe0 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I + default 0x4fe0 if MACH_SUN4I + default 0x4fe0 if MACH_SUN5I + default 0x4fe0 if MACH_SUN6I + default 0x4fe0 if MACH_SUN7I + default 0x4fe0 if MACH_SUN8I default 0x2fe0 if MACH_SUN9I + default 0x4fe0 if MACH_SUN50I endif -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH resend v2 12/13] sunxi: Add PSCI support for R40
The R40's CPU controls are a combination of sun6i and sun7i.
All controls are in the CPUCFG block, and it seems the R40 does not
have a PRCM block. The core reset, power gating and clamp controls
are grouped like sun6i.
Last, the R40 does not have a secure SRAM block.
This patch adds a PSCI implementation for CPU bring-up and hotplug
for the R40.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
arch/arm/cpu/armv7/sunxi/psci.c | 35 ---
board/sunxi/Kconfig | 3 +++
2 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index 104dc909bc53..b3a34de1aafe 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -27,6 +27,17 @@
#defineGICD_BASE (SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
#defineGICC_BASE (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
+/*
+ * R40 is different from other single cluster SoCs.
+ *
+ * The power clamps are located in the unused space after the per-core
+ * reset controls for core 3. The secondary core entry address register
+ * is in the SRAM controller address range.
+ */
+#define SUN8I_R40_PWROFF (0x110)
+#define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4)
+#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0(0xbc)
+
static void __secure cp15_write_cntp_tval(u32 tval)
{
asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
@@ -68,7 +79,8 @@ static void __secure __mdelay(u32 ms)
static void __secure clamp_release(u32 __maybe_unused *clamp)
{
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_H3)
+ defined(CONFIG_MACH_SUN8I_H3) || \
+ defined(CONFIG_MACH_SUN8I_R40)
u32 tmp = 0x1ff;
do {
tmp >>= 1;
@@ -82,7 +94,8 @@ static void __secure clamp_release(u32 __maybe_unused *clamp)
static void __secure clamp_set(u32 __maybe_unused *clamp)
{
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_H3)
+ defined(CONFIG_MACH_SUN8I_H3) || \
+ defined(CONFIG_MACH_SUN8I_R40)
writel(0xff, clamp);
#endif
}
@@ -115,7 +128,17 @@ static void __secure sunxi_cpu_set_power(int
__always_unused cpu, bool on)
sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
on, 0);
}
-#else /* ! CONFIG_MACH_SUN7I */
+#elif defined CONFIG_MACH_SUN8I_R40
+static void __secure sunxi_cpu_set_power(int cpu, bool on)
+{
+ struct sunxi_cpucfg_reg *cpucfg =
+ (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+
+ sunxi_power_switch((void *)cpucfg + SUN8I_R40_PWR_CLAMP(cpu),
+ (void *)cpucfg + SUN8I_R40_PWROFF,
+ on, 0);
+}
+#else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */
static void __secure sunxi_cpu_set_power(int cpu, bool on)
{
struct sunxi_prcm_reg *prcm =
@@ -213,7 +236,13 @@ int __secure psci_cpu_on(u32 __always_unused unused, u32
mpidr, u32 pc)
psci_save_target_pc(cpu, pc);
/* Set secondary core power on PC */
+#ifdef CONFIG_MACH_SUN8I_R40
+ /* secondary core entry address is programmed differently */
+ writel((u32)&psci_cpu_entry,
+ SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
+#else
writel((u32)&psci_cpu_entry, &cpucfg->priv0);
+#endif
/* Assert reset on target CPU */
writel(0, &cpucfg->cpu[cpu].rst);
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 5bc4ce037f54..811eb47dc17f 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -137,6 +137,9 @@ config MACH_SUN8I_H3
config MACH_SUN8I_R40
bool "sun8i (Allwinner R40)"
select CPU_V7
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
--
2.11.0
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[linux-sunxi] [PATCH resend v2 11/13] sunxi: Fix CPUCFG address for R40
The R40 has the CPUCFG block at the same address as the A20. Fix it. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index ea672fe8449a..88c3f138173f 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -108,7 +108,7 @@ defined(CONFIG_MACH_SUN50I) #define SUNXI_TP_BASE 0x01c25000 #define SUNXI_PMU_BASE 0x01c25400 -#ifdef CONFIG_MACH_SUN7I +#if defined CONFIG_MACH_SUN7I || defined CONFIG_MACH_SUN8I_R40 #define SUNXI_CPUCFG_BASE 0x01c25c00 #endif @@ -167,7 +167,9 @@ defined(CONFIG_MACH_SUN50I) #define SUNXI_RTC_BASE 0x01f0 #define SUNXI_PRCM_BASE0x01f01400 -#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN8I_A83T +#if defined CONFIG_SUNXI_GEN_SUN6I && \ +!defined CONFIG_MACH_SUN8I_A83T && \ +!defined CONFIG_MACH_SUN8I_R40 #define SUNXI_CPUCFG_BASE 0x01f01c00 #endif -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH resend v2 00/13] sunxi: Add support for R40 SoC
Hi everyone,
This is a resend of my Allwinner R40 SoC support series v2.
This is rebased on v2017.05-rc2. Maxime's ack for the first
two patches have been added, and the defconfig has been
regenerated which moved the CONFIG_SPL_I2C_SUPPORT=y line
around.
The patches can also be found here:
https://github.com/wens/u-boot-sunxi/tree/r40
Original v2 cover letter:
This is v2 of my Allwinner R40 SoC support series.
Changes since v1:
- Add Maxime's ack for all but the first patch.
- Add a patch to split up very long Kconfig lines.
This series adds support for the new R40 SoC. The R40 is marketed as the
successor to the A20. It is mostly pin compatible (in software) with the
A20. It has a somewhat similar memory layout, a hybrid of A20 and newer
sun6i gen.. Like the A20, it does not have a PRCM block.
Checkpatch throws out a lot of errors, mostly "no spaces at the start of
a line" or "space prohibited after that open parenthesis '('", but fixing
them does not improve the readability of the code.
Patch 1 splits up some very long Kconfig lines. (new in v2)
Patch 2 introduces the R40 to U-boot, by adding a Kconfig symbol, fixing
up any SoC depends on in Kconfig to disable unsupported features, and
reworking board level pinmuxes.
Patch 3 enables using the AXP221s PMIC in I2C mode. The R40 is paired
with this PMIC, but it does not have a P2WI controller.
Patch 4 fixes the watchdog reset function for R40. The R40's watchdog
register layout is like the A10/A20.
Patch 5 adds mmc pinmux settings for R40.
Patch 6 fixes the PLL lock settings for the R40. The R40's CCU has a
new mode for PLL lock, which can be configured and also switched back
to the old mode. Here we just use the old mode, which is the same as
the other sun6i gen. SoCs.
Patch 7 provides some default DRAM settings for the R40. These were
taken from the Bananapi M2 Ultra, the only R40 board available.
Patch 8 adds the compatible string for the R40 PIO. It is mostly
compatible with the A20, with a few functions gone, and a few new
ones.
Patch 9 adds DRAM initialization support for the R40. The DRAM
controller is very similar to the A64 and H5, however the A15 line
and CSC1 line are muxed on the same pin. Also the PIR_QSGATE bit
must not be set, or DRAM init fails.
Patch 10 enables SPL for R40.
Patch 11 fixes the address of the CPUCFG block on the R40. It is
the same as on the A20.
Patch 12 adds a PSCI implementation for the R40. As the register
layout is slightly erratic, we just use a macro for the ones that
can't fit into the cpucfg register definition structure.
Patch 13 adds a board dts and defconfig for the Bananapi M2 Ultra.
Please have a look.
Regards
ChenYu
Chen-Yu Tsai (13):
sunxi: Split up long Kconfig lines
sunxi: Add initial support for R40
sunxi: Enable AXP221s in I2C mode with the R40 SoC
sunxi: Fix watchdog reset function for R40
sunxi: Add mmc[1-3] pinmux settings for R40
sunxi: Set PLL lock enable bits for R40
sunxi: Provide defaults for R40 DRAM settings
gpio: sunxi: Add compatible string for R40 PIO
sunxi: Use H3/A64 DRAM initialization code for R40
sunxi: Enable SPL for R40
sunxi: Fix CPUCFG address for R40
sunxi: Add PSCI support for R40
sunxi: Add support for Bananapi M2 Ultra
arch/arm/cpu/armv7/sunxi/psci.c | 35 -
arch/arm/dts/Makefile | 2 +
arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts| 69 +
arch/arm/dts/sun8i-r40.dtsi | 183
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 2 +
arch/arm/include/asm/arch-sunxi/cpu.h | 1 +
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 6 +-
arch/arm/include/asm/arch-sunxi/dram.h | 4 +-
arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h | 20 ++-
arch/arm/include/asm/arch-sunxi/timer.h | 5 +-
arch/arm/include/asm/arch-sunxi/watchdog.h | 5 +-
arch/arm/mach-sunxi/Makefile| 1 +
arch/arm/mach-sunxi/board.c | 15 +-
arch/arm/mach-sunxi/clock_sun6i.c | 9 +-
arch/arm/mach-sunxi/cpu_info.c | 2 +
arch/arm/mach-sunxi/dram_sun8i_h3.c | 121 ++--
arch/arm/mach-sunxi/pmic_bus.c | 7 +
board/sunxi/Kconfig | 41 +-
board/sunxi/MAINTAINERS | 6 +
board/sunxi/board.c | 36 -
configs/Bananapi_M2_Ultra_defconfig | 15 ++
drivers/gpio/sunxi_gpio.c | 1 +
drivers/power/Kconfig | 16 ++-
23 files changed, 550 insertions(+), 52 deletions(-)
create mode 100644 arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
create mode 100644 arch/arm/dts/sun8i-r40.dtsi
create mode 100644 configs/Bananapi_M2_Ultra_defconfig
--
2.11.0
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[linux-sunxi] [PATCH resend v2 09/13] sunxi: Use H3/A64 DRAM initialization code for R40
The R40 seems to have a variant of the memory controller found in
the H3 and A64 SoCs. Adapt the code for use on the R40. The changes
are based on released DRAM code and comparing register dumps from
boot0.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
arch/arm/include/asm/arch-sunxi/cpu.h | 1 +
arch/arm/include/asm/arch-sunxi/dram.h | 4 +-
arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h | 20 +++-
arch/arm/mach-sunxi/Makefile| 1 +
arch/arm/mach-sunxi/clock_sun6i.c | 4 +-
arch/arm/mach-sunxi/dram_sun8i_h3.c | 121 +---
6 files changed, 133 insertions(+), 18 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
b/arch/arm/include/asm/arch-sunxi/cpu.h
index e8e670e7e903..caec86526417 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -16,5 +16,6 @@
#define SOCID_A64 0x1689
#define SOCID_H3 0x1680
#define SOCID_H5 0x1718
+#define SOCID_R40 0x1701
#endif /* _SUNXI_CPU_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h
b/arch/arm/include/asm/arch-sunxi/dram.h
index 1dc82205b7df..f452f889f928 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -24,7 +24,9 @@
#include
#elif defined(CONFIG_MACH_SUN8I_A83T)
#include
-#elif defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
+#elif defined(CONFIG_MACH_SUNXI_H3_H5) || \
+ defined(CONFIG_MACH_SUN8I_R40) || \
+ defined(CONFIG_MACH_SUN50I)
#include
#elif defined(CONFIG_MACH_SUN9I)
#include
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
index 25d07d9863c9..2770986b613f 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
@@ -15,7 +15,8 @@
struct sunxi_mctl_com_reg {
u32 cr; /* 0x00 control register */
- u8 res0[0x8]; /* 0x04 */
+ u32 cr_r1; /* 0x04 rank 1 control register (R40 only) */
+ u8 res0[0x4]; /* 0x08 */
u32 tmr;/* 0x0c (unused on H3) */
u32 mcr[16][2]; /* 0x10 */
u32 bwcr; /* 0x90 bandwidth control register */
@@ -63,6 +64,17 @@ struct sunxi_mctl_com_reg {
#define MCTL_CR_DUAL_RANK (0x1 << 0)
#define MCTL_CR_SINGLE_RANK(0x0 << 0)
+/*
+ * CR_R1 is a register found in the R40's DRAM controller. It sets various
+ * parameters for rank 1. Bits [11:0] have the same meaning as the bits in
+ * MCTL_CR, but they apply to rank 1 only. This implies we can have
+ * different chips for rank 1 than rank 0.
+ *
+ * As address line A15 and CS1 chip select for rank 1 are muxed on the same
+ * pin, if single rank is used, A15 must be muxed in.
+ */
+#define MCTL_CR_R1_MUX_A15 (0x1 << 21)
+
#define PROTECT_MAGIC (0x94be6fa3)
struct sunxi_mctl_ctl_reg {
@@ -72,7 +84,8 @@ struct sunxi_mctl_ctl_reg {
u32 clken; /* 0x0c */
u32 pgsr[2];/* 0x10 PHY general status registers */
u32 statr; /* 0x18 */
- u8 res1[0x14]; /* 0x1c */
+ u8 res1[0x10]; /* 0x1c */
+ u32 lp3mr11;/* 0x2c */
u32 mr[4]; /* 0x30 mode registers */
u32 pllgcr; /* 0x40 */
u32 ptr[5]; /* 0x44 PHY timing registers */
@@ -120,7 +133,8 @@ struct sunxi_mctl_ctl_reg {
struct {/* 0x300 DATX8 modules*/
u32 mdlr; /* 0x00 master delay line register */
u32 lcdlr[3]; /* 0x04 local calibrated delay line
registers */
- u32 bdlr[12]; /* 0x10 bit delay line registers */
+ u32 bdlr[11]; /* 0x10 bit delay line registers */
+ u32 sdlr; /* 0x3c output enable bit delay
registers */
u32 gtr;/* 0x40 general timing register */
u32 gcr;/* 0x44 general configuration register
*/
u32 gsr[3]; /* 0x48 general status registers */
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index efab4811ee54..5510aa54353f 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o
obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o
obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o
obj-$(CONFIG_MACH_SUNXI_H3_H5) += dram_sun8i_h3.o
+obj-$(CONFIG_MACH_SUN8I_R40) += dram_sun8i_h3.o
obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o
obj-$(CONFIG_MACH_SUN50I) += dram_sun8i_h3.o
endif
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c
b/arch/arm/mach-sunxi/clock_sun6i.c
index 3c8c53fcf76b..9068c88ab2f8 100644
--- a/arch/arm/mach-sunxi/clock_sun6
[linux-sunxi] [PATCH resend v2 04/13] sunxi: Fix watchdog reset function for R40
The watchdog found on the R40 SoC is the older variant found on the A20.
Add the proper "#if defines" to make it work.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
arch/arm/include/asm/arch-sunxi/timer.h| 5 ++---
arch/arm/include/asm/arch-sunxi/watchdog.h | 5 -
arch/arm/mach-sunxi/board.c| 5 ++---
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/timer.h
b/arch/arm/include/asm/arch-sunxi/timer.h
index a665309803cb..ccdf942534a4 100644
--- a/arch/arm/include/asm/arch-sunxi/timer.h
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -67,7 +67,7 @@ struct sunxi_timer_reg {
struct sunxi_timer timer[6];/* We have 6 timers */
u8 res2[16];
struct sunxi_avs avs;
-#ifdef CONFIG_SUNXI_GEN_SUN4I
+#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
struct sunxi_wdog wdog; /* 0x90 */
/* XXX the following is not accurate for sun5i/sun7i */
struct sunxi_64cnt cnt64; /* 0xa0 */
@@ -77,8 +77,7 @@ struct sunxi_timer_reg {
struct sunxi_tgp tgp[4];
u8 res5[8];
u32 cpu_cfg;
-#endif
-#ifdef CONFIG_SUNXI_GEN_SUN6I
+#elif defined(CONFIG_SUNXI_GEN_SUN6I)
u8 res3[16];
struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/watchdog.h
b/arch/arm/include/asm/arch-sunxi/watchdog.h
index 8108be97bab0..ce6d66485609 100644
--- a/arch/arm/include/asm/arch-sunxi/watchdog.h
+++ b/arch/arm/include/asm/arch-sunxi/watchdog.h
@@ -13,7 +13,10 @@
#define WDT_CTRL_RESTART (0x1 << 0)
#define WDT_CTRL_KEY (0x0a57 << 1)
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) ||
defined(CONFIG_MACH_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || \
+defined(CONFIG_MACH_SUN5I) || \
+defined(CONFIG_MACH_SUN7I) || \
+defined(CONFIG_MACH_SUN8I_R40)
#define WDT_MODE_EN(0x1 << 0)
#define WDT_MODE_RESET_EN (0x1 << 1)
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 5a74c9717d84..6ce07dfe0fd7 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -270,7 +270,7 @@ void board_init_f(ulong dummy)
void reset_cpu(ulong addr)
{
-#ifdef CONFIG_SUNXI_GEN_SUN4I
+#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
static const struct sunxi_wdog *wdog =
&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
@@ -282,8 +282,7 @@ void reset_cpu(ulong addr)
/* sun5i sometimes gets stuck without this */
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
}
-#endif
-#ifdef CONFIG_SUNXI_GEN_SUN6I
+#elif defined(CONFIG_SUNXI_GEN_SUN6I)
static const struct sunxi_wdog *wdog =
((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
--
2.11.0
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[linux-sunxi] [PATCH resend v2 02/13] sunxi: Add initial support for R40
The R40 is the successor to the A20. It is a hybrid of the A20, A33
and the H3.
The R40's PIO controller is compatible with the A20,
Reuse the A20 UART and I2C muxing code by adding the R40's macro.
The display pipeline is the newer DE 2.0 variant.
Block enabling video on R40 for now.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
arch/arm/mach-sunxi/board.c| 10 +++---
arch/arm/mach-sunxi/cpu_info.c | 2 ++
board/sunxi/Kconfig| 7 +++
board/sunxi/board.c| 19 ++-
4 files changed, 30 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 5e03d039433a..5a74c9717d84 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -69,12 +69,14 @@ struct mm_region *mem_map = sunxi_mem_map;
static int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || \
+defined(CONFIG_MACH_SUN7I) || \
+defined(CONFIG_MACH_SUN8I_R40)
/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
-#if defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
#else
@@ -82,7 +84,9 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
#endif
sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
-#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) ||
defined(CONFIG_MACH_SUN7I))
+#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
+defined(CONFIG_MACH_SUN7I) || \
+defined(CONFIG_MACH_SUN8I_R40))
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index 85633ccec216..7851de299ab5 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -87,6 +87,8 @@ int print_cpuinfo(void)
printf("CPU: Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN8I_H3
printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
+#elif defined CONFIG_MACH_SUN8I_R40
+ printf("CPU: Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN9I
puts("CPU: Allwinner A80 (SUN9I)\n");
#elif defined CONFIG_MACH_SUN50I
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index bd0019713984..67ceae35bf9b 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -134,6 +134,11 @@ config MACH_SUN8I_H3
select MACH_SUNXI_H3_H5
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+config MACH_SUN8I_R40
+ bool "sun8i (Allwinner R40)"
+ select CPU_V7
+ select SUNXI_GEN_SUN6I
+
config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7
@@ -163,6 +168,7 @@ config MACH_SUN8I
default y if MACH_SUN8I_A33
default y if MACH_SUN8I_A83T
default y if MACH_SUNXI_H3_H5
+ default y if MACH_SUN8I_R40
config RESERVE_ALLWINNER_BOOT0_HEADER
bool "reserve space for Allwinner boot0 header"
@@ -521,6 +527,7 @@ config VIDEO
bool "Enable graphical uboot console on HDMI, LCD or VGA"
depends on !MACH_SUN8I_A83T
depends on !MACH_SUNXI_H3_H5
+ depends on !MACH_SUN8I_R40
depends on !MACH_SUN9I
depends on !MACH_SUN50I
default y
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index b9660128e5e7..495cb591a9fb 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -394,7 +394,10 @@ int board_mmc_init(bd_t *bis)
void i2c_init_board(void)
{
#ifdef CONFIG_I2C0_ENABLE
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) ||
defined(CONFIG_MACH_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || \
+defined(CONFIG_MACH_SUN5I) || \
+defined(CONFIG_MACH_SUN7I) || \
+defined(CONFIG_MACH_SUN8I_R40)
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
clock_twi_onoff(0, 1);
@@ -410,7 +413,9 @@ void i2c_init_board(void)
#endif
#ifdef CONFIG_I2C1_ENABLE
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || \
+defined(CONFIG_MACH_SUN7I) || \
+defined(CONFIG_MACH_SUN8I_R40)
sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
sunxi_gpio_set_cfgpin(SUNX
[linux-sunxi] [PATCH resend v2 05/13] sunxi: Add mmc[1-3] pinmux settings for R40
The PIO is generally compatible with the A20, except that it routes the
full 8 bits and eMMC reset pins for mmc2.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
board/sunxi/board.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 495cb591a9fb..21ce8348922c 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -199,7 +199,8 @@ static void mmc_pinmux_setup(int sdc)
case 1:
pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
+defined(CONFIG_MACH_SUN8I_R40)
if (pins == SUNXI_GPIO_H) {
/* SDC1: PH22-PH-27 */
for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
@@ -294,6 +295,17 @@ static void mmc_pinmux_setup(int sdc)
sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
}
+#elif defined(CONFIG_MACH_SUN8I_R40)
+ /* SDC2: PC6-PC15, PC24 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
/* SDC2: PC5-PC6, PC8-PC16 */
for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
@@ -320,7 +332,8 @@ static void mmc_pinmux_setup(int sdc)
case 3:
pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
+defined(CONFIG_MACH_SUN8I_R40)
/* SDC3: PI4-PI9 */
for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
--
2.11.0
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[linux-sunxi] [PATCH resend v2 06/13] sunxi: Set PLL lock enable bits for R40
According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has
an extra "PLL lock control" register in the CCU, which controls whether
the individual PLL lock status bits in each PLL's control register work
or not.
This patch enables it for all the PLLs.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 2 ++
arch/arm/mach-sunxi/clock_sun6i.c | 5 +
2 files changed, 7 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 1bfb48bd52df..1aefd5a64c1f 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -142,6 +142,8 @@ struct sunxi_ccm_reg {
u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */
u32 reserved25[5];
u32 ccu_sec_switch; /* 0x2f0 CCU Security Switch, H3 only */
+ u32 reserved26[11];
+ u32 pll_lock_ctrl; /* 0x320 PLL lock control, R40 only */
};
/* apb2 bit field */
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c
b/arch/arm/mach-sunxi/clock_sun6i.c
index 4762fbf0c3f0..3c8c53fcf76b 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -35,6 +35,11 @@ void clock_init_safe(void)
clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
#endif
+#ifdef CONFIG_MACH_SUN8I_R40
+ /* Set PLL lock enable bits and switch to old lock mode */
+ writel(GENMASK(12, 0), &ccm->pll_lock_ctrl);
+#endif
+
clock_set_pll1(40800);
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
--
2.11.0
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[linux-sunxi] [PATCH resend v2 10/13] sunxi: Enable SPL for R40
Now that we can do DRAM initialization for the R40, we can enable SPL support for it. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- board/sunxi/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 94d01cb5c1ec..5bc4ce037f54 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -138,6 +138,7 @@ config MACH_SUN8I_R40 bool "sun8i (Allwinner R40)" select CPU_V7 select SUNXI_GEN_SUN6I + select SUPPORT_SPL config MACH_SUN9I bool "sun9i (Allwinner A80)" -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [PATCH v3 10/12] arm64: allwinner: a64: add DTSI file for AXP803 PMIC
Hi,
On Mon, Apr 17, 2017 at 7:57 PM, Icenowy Zheng wrote:
> As nearly all A64 boards are using AXP803 PMIC, add a DTSI file for it,
> like the old DTSI files for AXP20x/22x, for the common parts of the
> PMIC.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm64/boot/dts/allwinner/axp803.dtsi | 150
> ++
> 1 file changed, 150 insertions(+)
> create mode 100644 arch/arm64/boot/dts/allwinner/axp803.dtsi
>
> diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi
> b/arch/arm64/boot/dts/allwinner/axp803.dtsi
> new file mode 100644
> index ..f0e53a7fffbd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi
> @@ -0,0 +1,150 @@
> +/*
> + * Copyright 2017 Icenowy Zheng
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/*
> + * AXP803 Integrated Power Management Chip
> + * http://files.pine64.org/doc/datasheet/pine64/AXP803_Datasheet_V1.0.pdf
> + */
> +
> +&axp803 {
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + regulators {
> + /* Default work frequency for buck regulators */
> + x-powers,dcdc-freq = <3000>;
> +
> + reg_dcdc1: dcdc1 {
> + regulator-name = "dcdc1";
> + };
> +
> + reg_dcdc2: dcdc2 {
> + regulator-name = "dcdc2";
> + };
> +
> + reg_dcdc3: dcdc3 {
> + regulator-name = "dcdc3";
> + };
> +
> + reg_dcdc4: dcdc4 {
> + regulator-name = "dcdc4";
> + };
> +
> + reg_dcdc5: dcdc5 {
> + regulator-name = "dcdc5";
> + };
> +
> + reg_dcdc6: dcdc6 {
> + regulator-name = "dcdc6";
> + };
> +
> + reg_dc1sw: dc1sw {
> + regulator-name = "dc1sw";
> + };
> +
> + reg_aldo1: aldo1 {
> + regulator-name = "aldo1";
> + };
> +
> + reg_aldo2: aldo2 {
> + regulator-name = "aldo2";
> + };
> +
> + reg_aldo3: aldo3 {
> + regulator-name = "aldo3";
> + };
> +
> + reg_dldo1: dldo1 {
> + regulator-name = "dldo1";
> + };
> +
> + reg_dldo2: dldo2 {
> + regulator-name = "dldo2";
> + };
> +
> + reg_dldo3: dldo3 {
> + regulator-name = "dldo3";
> + };
> +
> + reg_dldo4: dldo4 {
> + regulator-name = "dldo4";
> + };
> +
> + reg_eldo1: eldo1 {
> + regulator-name = "eldo1";
> + };
> +
> + reg_eldo2: eldo2 {
> + regulator-name = "eldo2";
> + };
> +
> + reg_eldo3
[linux-sunxi] [PATCH 1/3] ARM: sun8i: a83t: Drop skeleton.dtsi
skeleton.dtsi is deprecated. Remove it from sun8i-a83t.dtsi and add
the needed device nodes directly.
Also drop an extra, non-style-conforming line in the copyright license
header.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 0ec143773ee9..913aacafe8d5 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -40,15 +40,20 @@
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
-
*/
-#include "skeleton.dtsi"
-
#include
/ {
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ };
+
+ chosen {
+ };
cpus {
#address-cells = <1>;
@@ -146,6 +151,11 @@
};
};
+ memory {
+ reg = <0x4000 0x8000>;
+ device_type = "memory";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
--
2.11.0
--
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[linux-sunxi] [PATCH 0/3] ARM: sun8i: a83t: device tree cleanup
Hi Maxime, Here are a few patches cleaning up sun8i-a83t.dtsi. These get rid of known warnings and deprecated features. I'm sending these now before I send patches that add new stuff. Regards ChenYu Chen-Yu Tsai (3): ARM: sun8i: a83t: Drop skeleton.dtsi ARM: sun8i: a83t: Drop leading zeroes from device node addresses ARM: sun8i: a83t: Rename pinmux setting names .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 2 +- arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 2 +- arch/arm/boot/dts/sun8i-a83t.dtsi | 36 ++ 3 files changed, 25 insertions(+), 15 deletions(-) -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 3/3] ARM: sun8i: a83t: Rename pinmux setting names
The pinmux setting nodes all have an address element in their node
names, however the pinctrl node does not have #address-cells.
Rename the existing pinmux setting nodes and labels in sun8i-a83t.dtsi,
dropping identifiers for functions that only have one possible setting,
and using the pingroup name if the function is identically available on
different pingroups.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 2 +-
arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 2 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 +-
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
index 342e1d33fa1c..aecdeeb368ed 100644
--- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -59,6 +59,6 @@
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_b>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
index 88b1e0970b8d..d2614f101ecc 100644
--- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
@@ -60,6 +60,6 @@
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_b>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 82cb87f21b96..87b99338716b 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -174,7 +174,7 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
- mmc0_pins_a: mmc0@0 {
+ mmc0_pins: mmc0_pins {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
function = "mmc0";
@@ -182,13 +182,13 @@
bias-pull-up;
};
- uart0_pins_a: uart0@0 {
- pins = "PF2", "PF4";
+ uart0_pb_pins: uart0_pb_pins {
+ pins = "PB9", "PB10";
function = "uart0";
};
- uart0_pins_b: uart0@1 {
- pins = "PB9", "PB10";
+ uart0_pf_pins: uart0_pf_pins {
+ pins = "PF2", "PF4";
function = "uart0";
};
};
--
2.11.0
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[linux-sunxi] [PATCH 2/3] ARM: sun8i: a83t: Drop leading zeroes from device node addresses
Kbuild now complains about leading zeroes in the address portion of
device node names.
Get rid of them.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 913aacafe8d5..82cb87f21b96 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -162,7 +162,7 @@
#size-cells = <1>;
ranges;
- pio: pinctrl@01c20800 {
+ pio: pinctrl@1c20800 {
compatible = "allwinner,sun8i-a83t-pinctrl";
interrupts = ,
,
@@ -193,7 +193,7 @@
};
};
- timer@01c20c00 {
+ timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
interrupts = ,
@@ -201,14 +201,14 @@
clocks = <&osc24M>;
};
- watchdog@01c20ca0 {
+ watchdog@1c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = ;
clocks = <&osc24M>;
};
- uart0: serial@01c28000 {
+ uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = ;
@@ -218,7 +218,7 @@
status = "disabled";
};
- gic: interrupt-controller@01c81000 {
+ gic: interrupt-controller@1c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x2000>,
--
2.11.0
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[linux-sunxi] Re: [PATCH 3/3] ARM: sun8i: a83t: Rename pinmux setting names
On Tue, Apr 18, 2017 at 5:04 PM, Maxime Ripard wrote: > On Tue, Apr 18, 2017 at 12:22:05PM +0800, Chen-Yu Tsai wrote: >> The pinmux setting nodes all have an address element in their node >> names, however the pinctrl node does not have #address-cells. >> >> Rename the existing pinmux setting nodes and labels in sun8i-a83t.dtsi, >> dropping identifiers for functions that only have one possible setting, >> and using the pingroup name if the function is identically available on >> different pingroups. >> >> Signed-off-by: Chen-Yu Tsai > > Applied, and I really like the new names. > > Would you make the same patch for everyone? I can. No guarantees on the schedule though. ChenYu -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH 2/3] ARM: sun8i: a83t: Drop leading zeroes from device node addresses
On Tue, Apr 18, 2017 at 5:03 PM, Maxime Ripard
wrote:
> On Tue, Apr 18, 2017 at 12:22:04PM +0800, Chen-Yu Tsai wrote:
>> Kbuild now complains about leading zeroes in the address portion of
>> device node names.
>>
>> Get rid of them.
>>
>> Signed-off-by: Chen-Yu Tsai
>> ---
>> arch/arm/boot/dts/sun8i-a83t.dtsi | 10 +-
>> 1 file changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
>> b/arch/arm/boot/dts/sun8i-a83t.dtsi
>> index 913aacafe8d5..82cb87f21b96 100644
>> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
>> @@ -162,7 +162,7 @@
>> #size-cells = <1>;
>> ranges;
>>
>> - pio: pinctrl@01c20800 {
>> + pio: pinctrl@1c20800 {
>
> As far as I know this breaks Uboot's auto-addition of stdout-path
You're right. It breaks as Uboot has the path to the uarts hard-coded.
That sucks. And from what I can tell, it's not easily solvable by just
switching to serial alias based references. CONS_INDEX won't line up
on the A23/A33 Q8 tablets.
Maybe we can just keep the uart device node the same for now, but fix
all the other ones. We can come back and fix the uart later once we
figure out how to fix Uboot.
Regards
ChenYu
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[linux-sunxi] Re: [PATCH 09/11] drm/sun4i: Support two display pipelines
On Tue, Apr 18, 2017 at 5:57 PM, Maxime Ripard
wrote:
> Hi Chen-Yu,
>
> On Sat, Apr 08, 2017 at 01:30:55AM +0800, Chen-Yu Tsai wrote:
>> Hi,
>>
>> On Thu, Mar 9, 2017 at 10:40 PM, Maxime Ripard
>> wrote:
>> > On Thu, Mar 09, 2017 at 07:20:30PM +0800, Chen-Yu Tsai wrote:
>> >> On Thu, Mar 9, 2017 at 6:36 PM, Maxime Ripard
>> >> wrote:
>> >> > Hi,
>> >> >
>> >> > On Thu, Mar 09, 2017 at 06:05:32PM +0800, Chen-Yu Tsai wrote:
>> >> >> Some Allwinner SoCs have two display pipelines (frontend -> backend ->
>> >> >> tcon).
>> >> >>
>> >> >> Previously we only supported one pipeline. This patch extends the
>> >> >> current driver to support two. It extends the tcon and backend pointers
>> >> >> in sun4i_drv into arrays, and makes the related bind functions store
>> >> >> the pointer into said arrays based on the id fetched from the device
>> >> >> tree. In the case of the tcons, it falls back to a first come order
>> >> >> if no encoders that can be used for differentiating the tcons are
>> >> >> defined. The driver's depth-first traversal of the of graph, coupled
>> >> >> with the increasing address ordering of the of graph endpoints, and
>> >> >> the fact that tcon0 should always be enabled for the tcon/encoder
>> >> >> mux to be accessible, means that tcon1 would always come after tcon0.
>> >> >>
>> >> >> Assignment of the device structure into sun4i_drv is moved to the end
>> >> >> of the bind function, when all possible error checks have passed.
>> >> >>
>> >> >> This patch also drops a trailing 0 in one of the backend probe
>> >> >> messages.
>> >> >>
>> >> >> Signed-off-by: Chen-Yu Tsai
>> >> >> ---
>> >> >> drivers/gpu/drm/sun4i/sun4i_backend.c | 9 +++--
>> >> >> drivers/gpu/drm/sun4i/sun4i_drv.c | 2 +-
>> >> >> drivers/gpu/drm/sun4i/sun4i_drv.h | 6 --
>> >> >> drivers/gpu/drm/sun4i/sun4i_tcon.c| 25 +
>> >> >> 4 files changed, 29 insertions(+), 13 deletions(-)
>> >> >>
>> >> >> diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c
>> >> >> b/drivers/gpu/drm/sun4i/sun4i_backend.c
>> >> >> index f3c92d54c8e4..8d22efd5a9cc 100644
>> >> >> --- a/drivers/gpu/drm/sun4i/sun4i_backend.c
>> >> >> +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
>> >> >> @@ -350,12 +350,15 @@ static int sun4i_backend_bind(struct device
>> >> >> *dev, struct device *master,
>> >> >> if (!backend)
>> >> >> return -ENOMEM;
>> >> >> dev_set_drvdata(dev, backend);
>> >> >> - drv->backend = backend;
>> >> >>
>> >> >> backend->id = sun4i_backend_of_get_id(dev->of_node);
>> >> >> if (backend->id < 0)
>> >> >> return backend->id;
>> >> >>
>> >> >> + /* We only support SUN4I_DRM_MAX_PIPELINES number of backends */
>> >> >> + if (backend->id >= SUN4I_DRM_MAX_PIPELINES)
>> >> >> + return -EINVAL;
>> >> >> +
>> >> >> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> >> >> regs = devm_ioremap_resource(dev, res);
>> >> >> if (IS_ERR(regs))
>> >> >> @@ -364,7 +367,7 @@ static int sun4i_backend_bind(struct device *dev,
>> >> >> struct device *master,
>> >> >> backend->regs = devm_regmap_init_mmio(dev, regs,
>> >> >>
>> >> >> &sun4i_backend_regmap_config);
>> >> >> if (IS_ERR(backend->regs)) {
>> >> >> - dev_err(dev, "Couldn't create the backend0 regmap\n");
>> >> >> + dev_err(dev, "Couldn't create the backend regmap\n");
>> >> >> return PTR_ERR(backend->regs);
>> >> >> }
>> >> >>
>> >> >> @@ -413,6 +416,8 @@ static int sun4i_backend_bind(struct device *dev,
>> >> >> struct device *ma
Re: [linux-sunxi] [PATCH v3 03/12] dt-bindings: make AXP20X compatible strings one per line
On Mon, Apr 17, 2017 at 7:57 PM, Icenowy Zheng wrote: > In the binding documentation of AXP20X mfd, the compatible strings used > to be listed for three per line, which leads to some mess when trying to > add AXP803 compatible string (as we have already AXP806 and AXP809 > compatibles, which is after AXP803 in ascending order). > > Make the compatible strings one per line, so that inserting a new > compatible string will be directly a new line. > > Signed-off-by: Icenowy Zheng Acked-by: Chen-Yu Tsai -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [PATCH v3 07/12] dt-bindings: add AXP803's regulator info
On Mon, Apr 17, 2017 at 7:57 PM, Icenowy Zheng wrote: > AXP803 have the most regulators in currently supported AXP PMICs. > > Add info for the regulators in the dt-bindings document. > > Signed-off-by: Icenowy Zheng > Acked-by: Rob Herring Acked-by: Chen-Yu Tsai -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [PATCH v3 09/12] mfd: axp20x: add axp20x-regulator cell for AXP803
On Mon, Apr 17, 2017 at 7:57 PM, Icenowy Zheng wrote:
> As axp20x-regulator now supports AXP803, add a cell for it.
>
> Signed-off-by: Icenowy Zheng
> ---
> Changes in v3:
> - Make the new cell one-liner.
>
> drivers/mfd/axp20x.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
> index 1dc6235778eb..431b7f118606 100644
> --- a/drivers/mfd/axp20x.c
> +++ b/drivers/mfd/axp20x.c
> @@ -848,7 +848,8 @@ static struct mfd_cell axp803_cells[] = {
> .name = "axp20x-pek",
> .num_resources = ARRAY_SIZE(axp803_pek_resources),
> .resources = axp803_pek_resources,
> - }
> + },
> + { .name = "axp20x-regulator" }
It's best to have a trailing comma, so we don't have to change the line
again when we add more cells, like you just did with the previous line.
Otherwise,
Acked-by: Chen-Yu Tsai
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Re: [linux-sunxi] [PATCH v3 09/12] mfd: axp20x: add axp20x-regulator cell for AXP803
On Tue, Apr 18, 2017 at 6:55 PM, Icenowy Zheng wrote:
>
>
> 于 2017年4月18日 GMT+08:00 下午6:38:09, Chen-Yu Tsai 写到:
>>On Mon, Apr 17, 2017 at 7:57 PM, Icenowy Zheng wrote:
>>> As axp20x-regulator now supports AXP803, add a cell for it.
>>>
>>> Signed-off-by: Icenowy Zheng
>>> ---
>>> Changes in v3:
>>> - Make the new cell one-liner.
>>>
>>> drivers/mfd/axp20x.c | 3 ++-
>>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
>>> index 1dc6235778eb..431b7f118606 100644
>>> --- a/drivers/mfd/axp20x.c
>>> +++ b/drivers/mfd/axp20x.c
>>> @@ -848,7 +848,8 @@ static struct mfd_cell axp803_cells[] = {
>>> .name = "axp20x-pek",
>>> .num_resources =
>>ARRAY_SIZE(axp803_pek_resources),
>>> .resources = axp803_pek_resources,
>>> - }
>>> + },
>>> + { .name = "axp20x-regulator" }
>>
>>It's best to have a trailing comma, so we don't have to change the line
>>again when we add more cells, like you just did with the previous line.
>
> Should I also add it in previous mfd patch? (and remove the addition of the
> comma in this patch)
Since Lee already said he merged it, I suggest you keep it the way it is,
unless he says otherwise. Or your new patches might not apply correctly,
and you waste time doing one more round.
Maintainers don't always push the latest branches, for a number of reasons.
Sometimes it's because the merge window is closed, and you're not supposed
to put anything that's not for the next release into -next. Other times it
might because they are still working through their backlog. Or they may
have just forgotten.
ChenYu
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Re: [linux-sunxi] [PATCH v3 08/12] regulator: axp20x-regulator: add support for AXP803
On Mon, Apr 17, 2017 at 7:57 PM, Icenowy Zheng wrote:
> AXP803 PMIC also have a series of regulators (DCDCs and LDOs)
> controllable via I2C/RSB bus.
>
> Add support for them.
>
> Signed-off-by: Icenowy Zheng
> ---
> Changes in v2:
> - Place AXP803 codes before AXP806/809 ones.
> - Fixed some errors in regulator description.
> - Reuse AXP803 DLDO2 range for AXP806 CLDO2 & AXP809 DLDO1.
>
> drivers/regulator/axp20x-regulator.c | 153
> ++-
> include/linux/mfd/axp20x.h | 37 +
> 2 files changed, 168 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/regulator/axp20x-regulator.c
> b/drivers/regulator/axp20x-regulator.c
> index 0b9d4e3e52c7..2ed15e4a7a82 100644
> --- a/drivers/regulator/axp20x-regulator.c
> +++ b/drivers/regulator/axp20x-regulator.c
[...]
> @@ -492,20 +578,38 @@ static bool axp20x_is_polyphase_slave(struct axp20x_dev
> *axp20x, int id)
> {
> u32 reg = 0;
>
> - /* Only AXP806 has poly-phase outputs */
> - if (axp20x->variant != AXP806_ID)
> - return false;
> + /*
> +* Currently in our supported AXP variants, only AXP806 and AXP803
Nit: mention them in ascending order.
Otherwise,
Acked-by: Chen-Yu Tsai
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[linux-sunxi] [PATCH 0/4] ARM: sunxi: device tree pinctrl clean up and H3 OTG
Hi Maxime, This series has 2 parts. The parts are largely unrelated, though the second part should be applied after the first part, so we don't accidentally mux pins that we shouldn't. Hence I'm sending them together. The first 2 patches clean up the sunxi device tree files, removing pinmux settings for common GPIO pins. These include the enable pins for the common regulators, and the mmc0 card detect pin from the reference designs. The second part, the latter 2 patches, enable USB OTG on the Orangepi PC, PC Plus, Plus 2E, and the Bananapi M2+. The first 3 boards are bunched together, due to how the PC Plus and Plus 2E device trees include the device tree of the Opi PC. Regards ChenYu Chen-Yu Tsai (4): ARM: sunxi: common-regulators: Drop pinmux settings for GPIO pins ARM: sunxi: Drop mmc0_cd_pin_reference_design pinmux setting ARM: sun8i: h3: orangepi-pc: Enable USB OTG ARM: sun8i: h3: bananapi-m2-plus: Enable USB OTG arch/arm/boot/dts/sun4i-a10-a1000.dts | 2 +- arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts | 2 +- arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts| 2 +- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 2 +- arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts | 2 +- arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 2 +- arch/arm/boot/dts/sun4i-a10-hackberry.dts | 2 +- arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts | 6 + arch/arm/boot/dts/sun4i-a10-inet1.dts | 2 +- arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 2 +- arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts | 2 +- .../boot/dts/sun4i-a10-itead-iteaduino-plus.dts| 2 +- arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts | 2 +- arch/arm/boot/dts/sun4i-a10-marsboard.dts | 2 +- arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 2 +- arch/arm/boot/dts/sun4i-a10-mk802.dts | 2 +- arch/arm/boot/dts/sun4i-a10-mk802ii.dts| 2 +- arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 2 +- arch/arm/boot/dts/sun4i-a10-pcduino.dts| 2 +- arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts | 2 +- arch/arm/boot/dts/sun4i-a10.dtsi | 6 - arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 8 -- arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 4 --- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 4 --- arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 4 --- .../boot/dts/sun5i-a13-empire-electronix-d709.dts | 4 --- arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 5 arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 4 --- arch/arm/boot/dts/sun6i-a31-hummingbird.dts| 5 arch/arm/boot/dts/sun7i-a20-cubieboard2.dts| 2 +- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 2 +- arch/arm/boot/dts/sun7i-a20-hummingbird.dts| 2 +- arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 2 +- arch/arm/boot/dts/sun7i-a20-icnova-swac.dts| 2 +- arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 2 +- arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 8 -- arch/arm/boot/dts/sun7i-a20-m3.dts | 2 +- arch/arm/boot/dts/sun7i-a20-mk808c.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts| 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts| 2 +- arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 2 +- arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 6 + arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 2 +- arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 2 +- arch/arm/boot/dts/sun7i-a20.dtsi | 6 - arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts| 22 +++- arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 4 --- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 22 +++- arch/arm/boot/dts/sunxi-common-regulators.dtsi | 30 -- 51 files changed, 78 insertions(+), 138 deletions(-) -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 1/4] ARM: sunxi: common-regulators: Drop pinmux settings for GPIO pins
As part of our effort to move pinctrl/GPIO interlocking into the
driver where it belongs, this patch drops the definition and usage
of the pinmux settings for the common regulators defined in
sunxi-common-regulators.dtsi.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts | 4 ---
arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 8 --
arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 4 ---
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 4 ---
arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 4 ---
.../boot/dts/sun5i-a13-empire-electronix-d709.dts | 4 ---
arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 5
arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 4 ---
arch/arm/boot/dts/sun6i-a31-hummingbird.dts| 5
arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 8 --
arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 4 ---
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 4 ---
arch/arm/boot/dts/sunxi-common-regulators.dtsi | 30 --
13 files changed, 88 deletions(-)
diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
index 85dcf81ab64e..bc4351bb851f 100644
--- a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
@@ -120,10 +120,6 @@
status = "okay";
};
-&usb2_vbus_pin_a {
- pins = "PH6";
-};
-
&usb_otg {
dr_mode = "otg";
status = "okay";
diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts
b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts
index c6f742a7e69f..d2dee8d434bf 100644
--- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts
@@ -136,14 +136,6 @@
status = "okay";
};
-&usb0_vbus_pin_a {
- pins = "PG13";
-};
-
-&usb1_vbus_pin_a {
- pins = "PB10";
-};
-
&usb_otg {
dr_mode = "host";
status = "okay";
diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
index a27c3fa58736..16f839df4227 100644
--- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
@@ -168,10 +168,6 @@
status = "okay";
};
-&usb1_vbus_pin_a {
- pins = "PG13";
-};
-
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index 894f874a5beb..eff36fe1aaa3 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -271,10 +271,6 @@
status = "okay";
};
-&usb0_vbus_pin_a {
- pins = "PG11";
-};
-
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
index ea3e5655a61b..5482be174e12 100644
--- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
@@ -216,10 +216,6 @@
status = "okay";
};
-&usb1_vbus_pin_a {
- pins = "PG12";
-};
-
&usbphy {
usb1_vbus-supply = <®_usb1_vbus>;
status = "okay";
diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
index 34411d27aadf..3dbb0d7c2f8c 100644
--- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
+++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
@@ -207,10 +207,6 @@
status = "okay";
};
-&usb0_vbus_pin_a {
- pins = "PG12";
-};
-
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
index 2489c16f7efa..584fa579ded2 100644
--- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
+++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
@@ -186,7 +186,6 @@
};
®_usb0_vbus {
- pinctrl-0 = <&usb0_vbus_pin_a>;
gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
status = "okay";
};
@@ -202,10 +201,6 @@
status = "okay";
};
-&usb0_vbus_pin_a {
- pins = "PG12";
-};
-
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 95f591bb8ced..38072c7e10e2 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch
[linux-sunxi] [PATCH 4/4] ARM: sun8i: h3: bananapi-m2-plus: Enable USB OTG
The Bananapi M2 Plus has a USB OTG port that can be used in both
powered host mode and peripheral mode. When in peripheral mode,
the port does not power the board. There is no VBUS sensing on
the port.
This patch adds the regulator controlling VBUS on the OTG port,
the GPIO for the ID detect pin, and enables the USB OTG and host
controllers.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index 52acbe111cad..17c7c088cdea 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -92,6 +92,10 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -145,6 +149,10 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
@@ -170,6 +178,11 @@
};
};
+®_usb0_vbus {
+ gpio = <&pio 3 11 GPIO_ACTIVE_HIGH>; /* PD11 */
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
@@ -182,7 +195,14 @@
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {
- /* USB VBUS is on as long as VCC-IO is on */
+ usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ /* USB host VBUS is on as long as VCC-IO is on */
status = "okay";
};
--
2.11.0
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[linux-sunxi] [PATCH 3/4] ARM: sun8i: h3: orangepi-pc: Enable USB OTG
The Orange Pi PC, PC Plus, and Plus 2E all have a USB OTG port
that can be used in both powered host mode and peripheral mode.
When in peripheral mode, the port does not power the board.
There is no VBUS sensing on the port. All three boards have all
related pins routed the same way.
The device tree file for the Orange Pi Plus 2E is based on the
Orange Pi PC Plus, which itself is based on the Orange Pi PC.
Changes to the base Orange Pi PC device tree file affects all 3
boards.
This patch adds the regulator controlling VBUS on the OTG port,
the GPIO for the ID detect pin, and enables the USB OTG and host
controllers.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index f148111c326d..1a044b17d6c6 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -97,6 +97,10 @@
status = "okay";
};
+&ehci0 {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -125,6 +129,10 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
@@ -156,6 +164,11 @@
};
};
+®_usb0_vbus {
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
@@ -180,7 +193,14 @@
status = "disabled";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {
- /* USB VBUS is always on */
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ /* VBUS on USB host ports are always on */
status = "okay";
};
--
2.11.0
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[linux-sunxi] [PATCH 2/4] ARM: sunxi: Drop mmc0_cd_pin_reference_design pinmux setting
As part of our effort to move pinctrl/GPIO interlocking into the
driver where it belongs, this patch drops the definition and usage
of the mmc0_cd_pin_reference_design pinmux setting for the default
mmc0 card detect GPIO pin.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun4i-a10-a1000.dts| 2 +-
arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-hackberry.dts| 2 +-
arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-inet1.dts| 2 +-
arch/arm/boot/dts/sun4i-a10-inet97fv2.dts| 2 +-
arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-marsboard.dts| 2 +-
arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-mk802.dts| 2 +-
arch/arm/boot/dts/sun4i-a10-mk802ii.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-pcduino.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts | 2 +-
arch/arm/boot/dts/sun4i-a10.dtsi | 6 --
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-hummingbird.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts| 2 +-
arch/arm/boot/dts/sun7i-a20-icnova-swac.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-m3.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-mk808c.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts| 2 +-
arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 2 +-
arch/arm/boot/dts/sun7i-a20.dtsi | 6 --
38 files changed, 36 insertions(+), 48 deletions(-)
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts
b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index f2a01fe2bebc..f80d37ddc4c6 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -171,7 +171,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
index 942d739a4384..6b02de592a02 100644
--- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
+++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
@@ -109,7 +109,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
index 17f8c5ec011c..a7d61994b8fd 100644
--- a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
+++ b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
@@ -128,7 +128,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index d844938e2aa7..a698a994e5ff 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -142,7 +142,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIV
Re: [linux-sunxi] Re: [PATCH 2/4] ARM: sunxi: Drop mmc0_cd_pin_reference_design pinmux setting
On Wed, Apr 19, 2017 at 11:36 PM, wrote:
> 在 2017-04-19 13:09，Chen-Yu Tsai 写道：
>>
>> As part of our effort to move pinctrl/GPIO interlocking into the
>> driver where it belongs, this patch drops the definition and usage
>> of the mmc0_cd_pin_reference_design pinmux setting for the default
>> mmc0 card detect GPIO pin.
>>
>> Signed-off-by: Chen-Yu Tsai
[...]
>> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi
>> b/arch/arm/boot/dts/sun7i-a20.dtsi
>> index 93aa55970bd7..c03b59aaec82 100644
>> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
>> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
>> @@ -1190,12 +1190,6 @@
>> bias-pull-up;
>> };
>>
>> - mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
>> - pins = "PH1";
>> - function = "gpio_in";
>> - bias-pull-up;
>
>
> It needs pull up, so shouldn't be dropped.
>
> (Although there may be external pull-up resistors on the board;
> however last time we removed the pull-up on MMC node many boards
> failed, so we cannot rely on external pull-up resistors)
I checked the boards that I have schematics, and the reference design.
All have proper external pull-up resistors for this pin, unlike the
other mmc pins.
If some board doesn't, it really needs to be singled out and handled
separately. Have you encountered any issues?
Regards
ChenYu
>
>> - };
>> -
>> mmc2_pins_a: mmc2@0 {
>> pins = "PC6", "PC7", "PC8",
>>"PC9", "PC10", "PC11";
>
>
> --
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Re: [linux-sunxi] Re: [PATCH v2 1/6] clk: sunxi-ng: Add sun4i/sun7i CCU driver
On Fri, Apr 21, 2017 at 3:59 AM, Priit Laes wrote:
> On Fri, Apr 07, 2017 at 03:38:05PM +0200, Maxime Ripard wrote:
>> Hi Priit,
>>
>> On Tue, Apr 04, 2017 at 08:09:19PM +, Priit Laes wrote:
>> > > > +/* Not documented on A10 */
>> > > > +static SUNXI_CCU_GATE(pll_periph_sata_clk, "pll-periph-sata",
>> > > > "pll-periph",
>> > > > + 0x028, BIT(14), 0);
>> > >
>> > > The rate doesn't come from pll-periph directly, does it?
>> >
>> > So it uses hosc (24MHz parent clock) instead of pll-periph?
>>
>> I never looked too much at this, but it looks more like the input is
>> pll-periph-sata itself.
>
> OK, I think I have now fixed most of the issues thanks to Maxime and Chen-Yu
> and I'm almost ready to send out V3.
>
> From my side there is only single issue remaining - how to create "sata-ext"
> clock?
>
> [snip]
> static struct ccu_div pll_periph_sata_clk = {
> .enable = BIT(14),
> .div= _SUNXI_CCU_DIV(0, 2),
> .common = {
> .prediv = 6,
> .reg= 0x028,
> .features = CCU_FEATURE_ALL_PREDIV,
> .hw.init= CLK_HW_INIT("pll-periph-sata",
> "pll-periph-base",
> &ccu_nk_ops, 0),
> },
> };
>
> static const char* const sata_parents[] = {"pll-periph-sata", "sata-ext"};
> static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
>0x0c8, 24, 1, BIT(31), 0);
> [/snip]
>
> Should I create a fixed-clock node in the dtsi:
>
> sata-ext: clk@0 {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> clock-frequency = <2>;
> clock-output-names = "sata-ext";
> };
You can just leave it missing. You probably shouldn't register it
if it's not populated. The clk core can cope with missing parents,
as long as they aren't all missing.
>
> And would it also need pio definition?
Nope. It has dedicated pins.
ChenYu
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[linux-sunxi] Re: [PATCH 3/3] ARM: sun8i: a83t: Rename pinmux setting names
On Tue, Apr 18, 2017 at 12:22 PM, Chen-Yu Tsai wrote:
> The pinmux setting nodes all have an address element in their node
> names, however the pinctrl node does not have #address-cells.
>
> Rename the existing pinmux setting nodes and labels in sun8i-a83t.dtsi,
> dropping identifiers for functions that only have one possible setting,
> and using the pingroup name if the function is identically available on
> different pingroups.
>
> Signed-off-by: Chen-Yu Tsai
> ---
> arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 2 +-
> arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 2 +-
> arch/arm/boot/dts/sun8i-a83t.dtsi | 10 +-
> 3 files changed, 7 insertions(+), 7 deletions(-)
>
[...]
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
> b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index 82cb87f21b96..87b99338716b 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -174,7 +174,7 @@
> #interrupt-cells = <3>;
> #gpio-cells = <3>;
>
> - mmc0_pins_a: mmc0@0 {
> + mmc0_pins: mmc0_pins {
> pins = "PF0", "PF1", "PF2",
>"PF3", "PF4", "PF5";
> function = "mmc0";
> @@ -182,13 +182,13 @@
> bias-pull-up;
> };
>
> - uart0_pins_a: uart0@0 {
> - pins = "PF2", "PF4";
> + uart0_pb_pins: uart0_pb_pins {
Duh... Forgot to use hyphens instead of underscores in the node names.
I'll send a patch for you to squash in.
ChenYu
> + pins = "PB9", "PB10";
> function = "uart0";
> };
>
> - uart0_pins_b: uart0@1 {
> - pins = "PB9", "PB10";
> + uart0_pf_pins: uart0_pf_pins {
> + pins = "PF2", "PF4";
> function = "uart0";
> };
> };
> --
> 2.11.0
>
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[linux-sunxi] Re: [PATCH v6 1/6] dt-bindings: power: supply: add AXP20X/AXP22X battery DT binding
On Thu, Apr 20, 2017 at 11:58 PM, Rob Herring wrote: > On Tue, Apr 18, 2017 at 09:34:16AM +0200, Quentin Schulz wrote: >> The X-Powers AXP20X and AXP22X PMICs can have a battery as power supply. >> >> This patch adds the DT binding documentation for the battery power >> supply which gets various data from the PMIC, such as the battery status >> (charging, discharging, full, dead), current max limit, current current, >> battery capacity (in percentage), voltage max and min limits, current >> voltage and battery capacity (in Ah). >> >> Signed-off-by: Quentin Schulz >> Acked-by: Chen-Yu Tsai >> Acked-by: Maxime Ripard >> --- >> v6: >> - removed mention to monitored-battery, will be sent when the battery >> framework has been merged, >> >> v5: >> - removed DT property example from monitored-battery, >> >> v4: >> - added monitored-battery optional property, >> - added example with battery, >> >> v3: >> - removed constant charge current property, now should use the WIP >> battery framework, >> >> v2: >> - changed DT node name from ac_power_supply to ac-power-supply, >> - removed io-channels and io-channel-names from DT (the IIO mapping is >> done in the IIO ADC driver now), >> - added x-powers,constant-charge-current property to set the maximal >> default constant current charge of the battery, >> >> .../bindings/power/supply/axp20x_battery.txt | 20 >> >> 1 file changed, 20 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/power/supply/axp20x_battery.txt > > Acked-by: Rob Herring Acked-by: Chen-Yu Tsai -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v2 2/9] drm/sun4i: Use lists to track registered display backends and TCONs
To support multiple display pipelines, we need to keep track of the
multiple display backends and TCONs registered with the driver.
Switch to lists to track registered components. Components are only
appended to their respective lists if the bind process was successful.
The TCON bind function now defers if a backend was not registered.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 6 +-
drivers/gpu/drm/sun4i/sun4i_backend.h | 4
drivers/gpu/drm/sun4i/sun4i_drv.c | 2 ++
drivers/gpu/drm/sun4i/sun4i_drv.h | 4 +++-
drivers/gpu/drm/sun4i/sun4i_tcon.c| 14 --
drivers/gpu/drm/sun4i/sun4i_tcon.h| 4
6 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c
b/drivers/gpu/drm/sun4i/sun4i_backend.c
index d660741ba475..95a77c6a9161 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -19,6 +19,7 @@
#include
#include
+#include
#include
#include "sun4i_backend.h"
@@ -310,7 +311,6 @@ static int sun4i_backend_bind(struct device *dev, struct
device *master,
if (!backend)
return -ENOMEM;
dev_set_drvdata(dev, backend);
- drv->backend = backend;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
regs = devm_ioremap_resource(dev, res);
@@ -369,6 +369,8 @@ static int sun4i_backend_bind(struct device *dev, struct
device *master,
}
}
+ list_add_tail(&backend->list, &drv->backend_list);
+
/* Reset the registers */
for (i = 0x800; i < 0x1000; i += 4)
regmap_write(backend->regs, i, 0);
@@ -400,6 +402,8 @@ static void sun4i_backend_unbind(struct device *dev, struct
device *master,
{
struct sun4i_backend *backend = dev_get_drvdata(dev);
+ list_del(&backend->list);
+
if (of_device_is_compatible(dev->of_node,
"allwinner,sun8i-a33-display-backend"))
sun4i_backend_free_sat(dev);
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.h
b/drivers/gpu/drm/sun4i/sun4i_backend.h
index 83e63cc702b4..9c8287309c65 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.h
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.h
@@ -14,6 +14,7 @@
#define _SUN4I_BACKEND_H_
#include
+#include
#include
#include
@@ -149,6 +150,9 @@ struct sun4i_backend {
struct clk *sat_clk;
struct reset_control*sat_reset;
+
+ /* Backend list management */
+ struct list_headlist;
};
void sun4i_backend_apply_color_correction(struct sun4i_backend *backend);
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 767bbadcc85d..89c51fd6e9af 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -101,6 +101,8 @@ static int sun4i_drv_bind(struct device *dev)
goto free_drm;
}
drm->dev_private = drv;
+ INIT_LIST_HEAD(&drv->backend_list);
+ INIT_LIST_HEAD(&drv->tcon_list);
ret = of_reserved_mem_device_init(dev);
if (ret && ret != -ENODEV) {
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.h
b/drivers/gpu/drm/sun4i/sun4i_drv.h
index 5df50126ff52..835bdb5cc0c2 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.h
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.h
@@ -14,10 +14,12 @@
#define _SUN4I_DRV_H_
#include
+#include
#include
struct sun4i_drv {
- struct sun4i_backend*backend;
+ struct list_headbackend_list;
+ struct list_headtcon_list;
struct sun4i_tcon *tcon;
struct drm_fbdev_cma*fbdev;
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 3ced0b1cef6e..52f37ef9a050 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -26,6 +26,7 @@
#include
#include
+#include "sun4i_backend.h"
#include "sun4i_crtc.h"
#include "sun4i_dotclock.h"
#include "sun4i_drv.h"
@@ -476,14 +477,18 @@ static int sun4i_tcon_bind(struct device *dev, struct
device *master,
{
struct drm_device *drm = data;
struct sun4i_drv *drv = drm->dev_private;
+ struct sun4i_backend *backend;
struct sun4i_tcon *tcon;
int ret;
+ /* Wait for a backend to be registered */
+ if (list_empty(&drv->backend_list))
+ return -EPROBE_DEFER;
+
tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
if (!tcon)
return -ENOMEM;
dev_set_drvdata(dev, tcon);
- drv->tcon = tcon;
tcon->drm = drm;
tcon->dev = dev;
tcon->quirks = of_device_get_match_data(dev);
@@ -528,7 +533,9 @@ static int sun4i_tcon_bind(struct device *dev, struct
device *master,
goto err_fre
[linux-sunxi] [PATCH v2 0/9] drm/sun4i: Support multiple display pipelines
Hi, This is v2 of the series previously named "drm/sun4i: Support two display pipelines". As the name change suggests, the driver now supports any number of pipelines, though the hardware only has 2 or 3. Changes since v1: - Add component endpoint ID numbering scheme to device tree binding. - Use lists to keep references to registered backends and tcons. - Save pointer to device node for backends. - Traverse the device tree of_graph starting from the tcons, going up towards the inputs, and matching the device nodes with the device nodes of registered backends, to find the one linked with the tcon the search started from. - Copy the ID for the tcon from its upstream backend, instead of trying, and possibly failing, to figure it out from the device tree. - Split out hunk dropping trailing 0 from a backend error message. Patch 1 adds the component endpoint ID numbering scheme to the device tree binding. New in v2. Patch 2 adds lists to track registered display backends and TCONs, instead of just one pointer per component type. Previously added arrays of pointers in v1. Patch 3 drops the trailing 0 from one of the backend's bind error messages. This was previously part of the patch "drm/sun4i: Support two display pipelines". Patch 4 adds a function to fetch a backend's ID from the device tree. Unchanged. Patch 5 adds a device node field to the backend data structure and saves a reference to the underlying device node of the backend. New in v2. Patch 6 makes the tcon driver find its upstream backend by traversing the of_graph and matching device nodes against the device nodes of registered backends. New in v2. Patch 7 makes the tcon driver use the ID from its associated backend. New in v2. This is not immediately used in this series, but will be used in similar fashion for downstream encoders to figure out IDs and muxing Patch 8 adds device nodes for sun6i's second display pipeline. Unchanged. Patch 9 enables sun6i's tcon0 by default. Unchanged. With this series, the sun4i drm driver now supports registering multiple display pipelines. However the driver does not guard against setups the hardware does not support, such as driving 2 encoders with incompatible dot clocks from the same source clock. Muxing of downstream encoders is not supported either, as we have no drivers for hardware that uses them. The WiP HDMI driver will be the first. While this series enables the second display pipeline, there's no usable output at the moment. For the A31, the second TCON's panel interface uses the same pins as the Ethernet controller. However Ethernet is used on most boards. Regards ChenYu Chen-Yu Tsai (9): dt-bindings: display: sun4i: Add component endpoint ID numbering scheme drm/sun4i: Use lists to track registered display backends and TCONs drm/sun4i: backend: Drop trailing 0 from backend in error message drm/sun4i: backend: Fetch backend ID from device tree drm/sun4i: backend: Save pointer to device tree node drm/sun4i: tcon: Find matching display backend by device node matching drm/sun4i: tcon: Copy ID from associated backend ARM: dts: sun6i: Add second display pipeline device nodes ARM: dts: sun6i: Enable tcon0 by default .../bindings/display/sunxi/sun4i-drm.txt | 10 ++ arch/arm/boot/dts/sun6i-a31-hummingbird.dts| 1 - arch/arm/boot/dts/sun6i-a31.dtsi | 169 - drivers/gpu/drm/sun4i/sun4i_backend.c | 53 ++- drivers/gpu/drm/sun4i/sun4i_backend.h | 8 + drivers/gpu/drm/sun4i/sun4i_drv.c | 2 + drivers/gpu/drm/sun4i/sun4i_drv.h | 4 +- drivers/gpu/drm/sun4i/sun4i_tcon.c | 62 +++- drivers/gpu/drm/sun4i/sun4i_tcon.h | 6 + 9 files changed, 307 insertions(+), 8 deletions(-) -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v2 9/9] ARM: dts: sun6i: Enable tcon0 by default
tcon0 contains a muxing register used to mux tcon output to downstream
hdmi or mipi dsi encoders. tcon0 must be available for the mux to be
configured.
Whether the display subsystem is enabled or not is now solely controlled
by the display-engine node.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 1 -
arch/arm/boot/dts/sun6i-a31.dtsi| 1 -
2 files changed, 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
index b4c87a23e3f8..55607208468b 100644
--- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -319,7 +319,6 @@
&tcon0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd0_rgb888_pins>;
- status = "okay";
};
&tcon0_out {
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index dfcf64515d7f..d0cede5aaeb5 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -264,7 +264,6 @@
"tcon-ch0",
"tcon-ch1";
clock-output-names = "tcon0-pixel-clock";
- status = "disabled";
ports {
#address-cells = <1>;
--
2.11.0
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[linux-sunxi] [PATCH v2 5/9] drm/sun4i: backend: Save pointer to device tree node
Save a pointer to the backend's underlying device tree node in its
data structure. This will be used later for downstream tcons to find
and match their respective upstream backends.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 1 +
drivers/gpu/drm/sun4i/sun4i_backend.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c
b/drivers/gpu/drm/sun4i/sun4i_backend.c
index 0b4222312e49..e9eca057ff35 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -352,6 +352,7 @@ static int sun4i_backend_bind(struct device *dev, struct
device *master,
return -ENOMEM;
dev_set_drvdata(dev, backend);
+ backend->node = dev->of_node;
backend->id = sun4i_backend_of_get_id(dev->of_node);
if (backend->id < 0)
return backend->id;
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.h
b/drivers/gpu/drm/sun4i/sun4i_backend.h
index 45b7fc110590..6327a2985fe6 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.h
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.h
@@ -15,6 +15,7 @@
#include
#include
+#include
#include
#include
@@ -140,6 +141,7 @@
#define SUN4I_BACKEND_PIPE_OFF(p) (0x5000 + (0x400 * (p)))
struct sun4i_backend {
+ struct device_node *node;
struct regmap *regs;
struct reset_control*reset;
--
2.11.0
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[linux-sunxi] [PATCH v2 4/9] drm/sun4i: backend: Fetch backend ID from device tree
Some Allwinner SoCs have 2 display pipelines, as in 2 of each
components, including the frontend, backend, TCON, and any other
extras.
As the backend and TCON are always paired together and form the CRTC,
we need to know which backend or TCON we are currently probing, so we
can pair them when initializing the CRTC.
This patch figures out the backend's ID from the device tree and stores
it in the backend's data structure. It does this by looking at the "reg"
property of any remote endpoints connected to the backend's input port.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 44 +++
drivers/gpu/drm/sun4i/sun4i_backend.h | 2 ++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c
b/drivers/gpu/drm/sun4i/sun4i_backend.c
index e17e20036aa3..0b4222312e49 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -20,6 +20,7 @@
#include
#include
+#include
#include
#include "sun4i_backend.h"
@@ -289,6 +290,45 @@ static int sun4i_backend_free_sat(struct device *dev) {
return 0;
}
+/*
+ * The display backend can take video output from the display frontend, or
+ * the display enhancement unit on the A80, as input for one it its layers.
+ * This relationship within the display pipeline is encoded in the device
+ * tree with of_graph, and we use it here to figure out which backend, if
+ * there are 2 or more, we are currently probing. The number would be in
+ * the "reg" property of the upstream output port endpoint.
+ */
+static int sun4i_backend_of_get_id(struct device_node *node)
+{
+ struct device_node *port, *ep;
+ int ret = -EINVAL;
+
+ /* input is port 0 */
+ port = of_graph_get_port_by_id(node, 0);
+ if (!port)
+ return -EINVAL;
+
+ /* try finding an upstream endpoint */
+ for_each_available_child_of_node(port, ep) {
+ struct device_node *remote;
+ u32 reg;
+
+ remote = of_parse_phandle(ep, "remote-endpoint", 0);
+ if (!remote)
+ continue;
+
+ ret = of_property_read_u32(remote, "reg", ®);
+ if (ret)
+ continue;
+
+ ret = reg;
+ }
+
+ of_node_put(port);
+
+ return ret;
+}
+
static struct regmap_config sun4i_backend_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
@@ -312,6 +352,10 @@ static int sun4i_backend_bind(struct device *dev, struct
device *master,
return -ENOMEM;
dev_set_drvdata(dev, backend);
+ backend->id = sun4i_backend_of_get_id(dev->of_node);
+ if (backend->id < 0)
+ return backend->id;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
regs = devm_ioremap_resource(dev, res);
if (IS_ERR(regs))
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.h
b/drivers/gpu/drm/sun4i/sun4i_backend.h
index 9c8287309c65..45b7fc110590 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.h
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.h
@@ -151,6 +151,8 @@ struct sun4i_backend {
struct clk *sat_clk;
struct reset_control*sat_reset;
+ int id;
+
/* Backend list management */
struct list_headlist;
};
--
2.11.0
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[linux-sunxi] [PATCH v2 6/9] drm/sun4i: tcon: Find matching display backend by device node matching
With Allwinner's Display Engine 1.0, each TCON's input is tied to a
specific display backend, and the 2 comprise what is known as a crtc
in DRM KMS land: The layer, framebuffer, and compositing functions are
provided by the backend, while the TCON provides the display timing
signals and vblank interrupts. This 1 to 1 relationship is represented
in the device tree. On some systems there is an intermediate DRC
component.
Pointers to both matching components must be provided when initializing
the crtc. As the backend is always registered before the associated
tcon, we can recursively search upwards through the of_graph to find
the matching backend.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 55 +++---
1 file changed, 51 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 52f37ef9a050..4409e7b6c74d 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -472,6 +472,53 @@ struct drm_bridge *sun4i_tcon_find_bridge(struct
device_node *node)
return of_drm_find_bridge(remote) ?: ERR_PTR(-EPROBE_DEFER);
}
+/*
+ * On SoCs with the old display pipeline design (Display Engine 1.0),
+ * the TCON is always tied to just one backend. Hence we can traverse
+ * the of_graph upwards to find the backend our tcon is connected to,
+ * and take its ID as our own.
+ *
+ * We can either identify backends from their compatible strings, which
+ * means maintaining a large list of them. Or, since the backend is
+ * registered and binded before the TCON, we can just go through the
+ * list of registered backends and compare the device node.
+ */
+static struct sun4i_backend *sun4i_tcon_find_backend(struct sun4i_drv *drv,
+struct device_node *node)
+{
+ struct device_node *port, *ep, *remote;
+ struct sun4i_backend *backend;
+
+ port = of_graph_get_port_by_id(node, 0);
+ if (!port)
+ return ERR_PTR(-EINVAL);
+
+ for_each_available_child_of_node(port, ep) {
+ remote = of_graph_get_remote_port_parent(ep);
+ if (!remote)
+ continue;
+
+ /* does this node match any registered backends? */
+ list_for_each_entry(backend, &drv->backend_list, list) {
+ if (remote == backend->node) {
+ of_node_put(remote);
+ of_node_put(port);
+ return backend;
+ }
+ }
+
+ /* keep looking through upstream ports */
+ backend = sun4i_tcon_find_backend(drv, remote);
+ if (!IS_ERR(backend)) {
+ of_node_put(remote);
+ of_node_put(port);
+ return backend;
+ }
+ }
+
+ return ERR_PTR(-EINVAL);
+}
+
static int sun4i_tcon_bind(struct device *dev, struct device *master,
void *data)
{
@@ -481,9 +528,11 @@ static int sun4i_tcon_bind(struct device *dev, struct
device *master,
struct sun4i_tcon *tcon;
int ret;
- /* Wait for a backend to be registered */
- if (list_empty(&drv->backend_list))
+ backend = sun4i_tcon_find_backend(drv, dev->of_node);
+ if (IS_ERR(backend)) {
+ dev_err(dev, "Couldn't find matching backend\n");
return -EPROBE_DEFER;
+ }
tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
if (!tcon)
@@ -533,8 +582,6 @@ static int sun4i_tcon_bind(struct device *dev, struct
device *master,
goto err_free_dotclock;
}
- backend = list_first_entry(&drv->backend_list,
- struct sun4i_backend, list);
tcon->crtc = sun4i_crtc_init(drm, backend, tcon);
if (IS_ERR(tcon->crtc)) {
dev_err(dev, "Couldn't create our CRTC\n");
--
2.11.0
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[linux-sunxi] [PATCH v2 7/9] drm/sun4i: tcon: Copy ID from associated backend
The tcons and backends have a one-to-one relationship. Their IDs,
or indexes in the documentation, are also the same.
Copy the ID from the associated backend and save it in the tcon
structure. This will later be used when we add support for the
output data path muxes.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 1 +
drivers/gpu/drm/sun4i/sun4i_tcon.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 4409e7b6c74d..8301389c411d 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -540,6 +540,7 @@ static int sun4i_tcon_bind(struct device *dev, struct
device *master,
dev_set_drvdata(dev, tcon);
tcon->drm = drm;
tcon->dev = dev;
+ tcon->id = backend->id;
tcon->quirks = of_device_get_match_data(dev);
tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h
b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index 1bda4d183eec..d37e1e2ed60e 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -174,6 +174,8 @@ struct sun4i_tcon {
/* Associated crtc */
struct sun4i_crtc *crtc;
+ int id;
+
/* TCON list management */
struct list_headlist;
};
--
2.11.0
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[linux-sunxi] [PATCH v2 3/9] drm/sun4i: backend: Drop trailing 0 from backend in error message
Now that we support multiple instances of backends, the trailing 0
implying only one backend no longer makes sense.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c
b/drivers/gpu/drm/sun4i/sun4i_backend.c
index 95a77c6a9161..e17e20036aa3 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -320,7 +320,7 @@ static int sun4i_backend_bind(struct device *dev, struct
device *master,
backend->regs = devm_regmap_init_mmio(dev, regs,
&sun4i_backend_regmap_config);
if (IS_ERR(backend->regs)) {
- dev_err(dev, "Couldn't create the backend0 regmap\n");
+ dev_err(dev, "Couldn't create the backend regmap\n");
return PTR_ERR(backend->regs);
}
--
2.11.0
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[linux-sunxi] [PATCH v2 1/9] dt-bindings: display: sun4i: Add component endpoint ID numbering scheme
The Allwinner display pipeline contains many hardware components, some of which can consume data from one of multiple upstream components. The numbering scheme of these components must be encoded into the device tree so the driver can figure out which component out of two or more of the same type it is supposed to use or program. This patch adds the constraint that local endpoint IDs must be the index or number of the remote endpoint's hardware block, for all components in the display pipeline up to the TCONs. Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 10 ++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index 57a8d0610062..7acdbf14ae1c 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -4,6 +4,16 @@ Allwinner A10 Display Pipeline The Allwinner A10 Display pipeline is composed of several components that are going to be documented below: +For the input port of all components up to the TCON in the display +pipeline, if there are multiple components, the local endpoint IDs +must correspond to the index of the upstream block. For example, if +the remote endpoint is Frontend 1, then the local endpoint ID must +be 1. + +Conversely, for the output ports of the same group, the remote endpoint +ID must be the index of the local hardware block. If the local backend +is backend 1, then the remote endpoint ID must be 1. + TV Encoder -- -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v2 8/9] ARM: dts: sun6i: Add second display pipeline device nodes
The Allwinner A31/A31s SoCs have 2 display pipelines, as in 2 display
frontends, backends, and tcons each. The relationship between the
backends and tcons are 1:1, but the frontends can feed either backend.
Add device nodes and of graph nodes describing this relationship.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31.dtsi | 168 ++-
1 file changed, 167 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 9c999d3788f6..dfcf64515d7f 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -232,7 +232,7 @@
de: display-engine {
compatible = "allwinner,sun6i-a31-display-engine";
- allwinner,pipelines = <&fe0>;
+ allwinner,pipelines = <&fe0>, <&fe1>;
status = "disabled";
};
@@ -289,6 +289,43 @@
};
};
+ tcon1: lcd-controller@01c0d000 {
+ compatible = "allwinner,sun6i-a31-tcon";
+ reg = <0x01c0d000 0x1000>;
+ interrupts = ;
+ resets = <&ccu RST_AHB1_LCD1>;
+ reset-names = "lcd";
+ clocks = <&ccu CLK_AHB1_LCD1>,
+<&ccu CLK_LCD1_CH0>,
+<&ccu CLK_LCD1_CH1>;
+ clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+ clock-output-names = "tcon1-pixel-clock";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon1_in_drc1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint =
<&drc1_out_tcon1>;
+ };
+ };
+
+ tcon1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
@@ -896,6 +933,130 @@
reg = <0>;
remote-endpoint = <&be0_in_fe0>;
};
+
+ fe0_out_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_in_fe0>;
+ };
+ };
+ };
+ };
+
+ fe1: display-frontend@01e2 {
+ compatible = "allwinner,sun6i-a31-display-frontend";
+ reg = <0x01e2 0x2>;
+ interrupts = ;
+ clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
+<&ccu CLK_DRAM_FE1>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_AHB1_FE1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe1_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_fe1>;
+ };
+
+ fe1_out_be1: endpoint@1 {
+ reg = <1>;
+
Re: [linux-sunxi] [PATCH 13/15] drm/sun4i: Add HDMI support
Hi, On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard wrote: > The earlier Allwinner SoCs (A10, A10s, A20, A31) have an embedded HDMI > controller. > > That HDMI controller is able to do audio and CEC, but those have been left > out for now. > > Signed-off-by: Maxime Ripard > --- > drivers/gpu/drm/sun4i/Makefile | 5 +- > drivers/gpu/drm/sun4i/sun4i_hdmi.h | 124 ++- > drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c | 128 ++- > drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 449 +- > drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c | 236 +++- > 5 files changed, 942 insertions(+), 0 deletions(-) > create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi.h > create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c > create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c > create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c Applying patch #9608371 using 'git am' Description: [13/15] drm/sun4i: Add HDMI support Applying: drm/sun4i: Add HDMI support .git/rebase-apply/patch:116: trailing whitespace. .git/rebase-apply/patch:531: trailing whitespace. .git/rebase-apply/patch:701: trailing whitespace. warning: 3 lines add whitespace errors. > diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile > index 59b757350a1f..68a0f6244a59 100644 > --- a/drivers/gpu/drm/sun4i/Makefile > +++ b/drivers/gpu/drm/sun4i/Makefile > @@ -7,7 +7,12 @@ sun4i-tcon-y += sun4i_dotclock.o > sun4i-tcon-y += sun4i_crtc.o > sun4i-tcon-y += sun4i_layer.o > > +sun4i-drm-hdmi-y += sun4i_hdmi_enc.o > +sun4i-drm-hdmi-y += sun4i_hdmi_ddc_clk.o > +sun4i-drm-hdmi-y += sun4i_hdmi_tmds_clk.o > + > obj-$(CONFIG_DRM_SUN4I)+= sun4i-drm.o sun4i-tcon.o > obj-$(CONFIG_DRM_SUN4I)+= sun4i_backend.o > obj-$(CONFIG_DRM_SUN4I)+= sun6i_drc.o > +obj-$(CONFIG_DRM_SUN4I)+= sun4i-drm-hdmi.o > obj-$(CONFIG_DRM_SUN4I)+= sun4i_tv.o > diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h > b/drivers/gpu/drm/sun4i/sun4i_hdmi.h > new file mode 100644 > index ..2ad25b8fd3cd > --- /dev/null > +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h > @@ -0,0 +1,124 @@ > +/* > + * Copyright (C) 2016 Maxime Ripard > + * > + * Maxime Ripard > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + */ > + > +#ifndef _SUN4I_HDMI_H_ > +#define _SUN4I_HDMI_H_ > + > +#include > +#include > + > +#define SUN4I_HDMI_CTRL_REG0x004 > +#define SUN4I_HDMI_CTRL_ENABLE BIT(31) > + > +#define SUN4I_HDMI_IRQ_REG 0x008 > +#define SUN4I_HDMI_IRQ_STA_MASK0x73 > +#define SUN4I_HDMI_IRQ_STA_FIFO_OF BIT(1) > +#define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0) > + > +#define SUN4I_HDMI_HPD_REG 0x00c > +#define SUN4I_HDMI_HPD_HIGHBIT(0) > + > +#define SUN4I_HDMI_VID_CTRL_REG0x010 > +#define SUN4I_HDMI_VID_CTRL_ENABLE BIT(31) > +#define SUN4I_HDMI_VID_CTRL_HDMI_MODE BIT(30) > + > +#define SUN4I_HDMI_VID_TIMING_ACT_REG 0x014 > +#define SUN4I_HDMI_VID_TIMING_BP_REG 0x018 > +#define SUN4I_HDMI_VID_TIMING_FP_REG 0x01c > +#define SUN4I_HDMI_VID_TIMING_SPW_REG 0x020 > + > +#define SUN4I_HDMI_VID_TIMING_X(x) x) - 1) & GENMASK(11, 0))) > +#define SUN4I_HDMI_VID_TIMING_Y(y) y) - 1) & GENMASK(11, 0)) > << 16) > + > +#define SUN4I_HDMI_VID_TIMING_POL_REG 0x024 > +#define SUN4I_HDMI_VID_TIMING_POL_TX_CLK(0x3e0 << 16) > +#define SUN4I_HDMI_VID_TIMING_POL_VSYNCBIT(1) > +#define SUN4I_HDMI_VID_TIMING_POL_HSYNCBIT(0) > + > +#define SUN4I_HDMI_AVI_INFOFRAME_REG(n)(0x080 + (n)) > + > +#define SUN4I_HDMI_PAD_CTRL0_REG 0x200 > + > +#define SUN4I_HDMI_PAD_CTRL1_REG 0x204 > +#define SUN4I_HDMI_PAD_CTRL1_HALVE_CLK BIT(6) > + > +#define SUN4I_HDMI_PLL_CTRL_REG0x208 > +#define SUN4I_HDMI_PLL_CTRL_DIV(n) ((n) << 4) > +#define SUN4I_HDMI_PLL_CTRL_DIV_MASK GENMASK(7, 4) > + > +#define SUN4I_HDMI_PLL_DBG0_REG0x20c > +#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT(n) (((n) & 1) << 21) > +#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK BIT(21) > +#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_SHIFT 21 > + > +#define SUN4I_HDMI_PKT_CTRL_REG(n) (0x2f0 + (4 * (n))) > +#define SUN4I_HDMI_PKT_CTRL_TYPE(n, t) ((t) << (((n) % 4) * 4)) > + > +#define SUN4I_HDMI_UNKNOWN_REG 0x300 > +#define SUN4I_HDMI_UNKNOWN_INPUT_SYNC BIT(27) > + > +#define SUN4I_HDMI_DDC_CTRL_REG0x500 > +#define SUN4I_HDMI_DDC_CTRL_ENABLE BIT(31) > +#define SUN4I_HDMI_DDC_CTRL_START_CMD BIT(30) > +#define SUN4I_HDMI_DDC_CTRL_RES
[linux-sunxi] Re: [PATCH v4 13/18] arm64: allwinner: sun50i-a64: add dwmac-sun8i Ethernet driver
On Mon, Apr 24, 2017 at 8:24 PM, Corentin Labbe
wrote:
> On Wed, Apr 12, 2017 at 02:41:53PM +0200, Maxime Ripard wrote:
>> On Wed, Apr 12, 2017 at 01:13:55PM +0200, Corentin Labbe wrote:
>> > The dwmac-sun8i is an Ethernet MAC that supports 10/100/1000 Mbit
>> > connections. It is very similar to the device found in the Allwinner
>> > H3, but lacks the internal 100 Mbit PHY and its associated control
>> > bits.
>> > This adds the necessary bits to the Allwinner A64 SoC .dtsi, but keeps
>> > it disabled at this level.
>> >
>> > Signed-off-by: Corentin Labbe
>> > ---
>> > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 37
>> > +++
>> > 1 file changed, 37 insertions(+)
>> >
>> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> > b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> > index 0b0f4ab..2569827 100644
>> > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> > @@ -287,6 +287,23 @@
>> > bias-pull-up;
>> > };
>> >
>> > + rmii_pins: rmii_pins {
>> > + pins = "PD10", "PD11", "PD13", "PD14",
>> > + "PD17", "PD18", "PD19", "PD20",
>> > + "PD22", "PD23";
>>
>> Please align the wrapped lines on the first pin.
>>
>
> OK
>
>> > + function = "emac";
>> > + drive-strength = <40>;
>>
>> Do you actually need that for all the boards, or only a few of them?
>
> I have tried to use lower value without success on some boards. (opipc/pine64
> in my memory)
FYI we need them for all the boards that use RGMII.
The signals at gigabit speed run at 125 MHz DDR.
For RMII we probably don't need it. Even at 100 Mbps,
it's only 50 MHz SDR. drive-strength = <30> should be
enough.
ChenYu
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Re: [linux-sunxi] [PATCH v4 07/10] mfd: axp20x: add axp20x-regulator cell for AXP803
On Tue, Apr 25, 2017 at 12:01 AM, Icenowy Zheng wrote: > As axp20x-regulator now supports AXP803, add a cell for it. > > Signed-off-by: Icenowy Zheng > Acked-by: Chen-Yu Tsai > --- > Changes in v4: > - Added a trailing comma for new cell, for easier further cell addition. > Changes in v3: > - Make the new cell one-liner. > > drivers/mfd/axp20x.c | 3 ++- > drivers/regulator/axp20x-regulator.c | 6 +++--- Squashed in wrong patch? ChenYu -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 1/3] drm/sun4i: Drop unused tcon pointer
The sun4i DRM driver now uses 2 lists to track backends and tcons.
During the switch, the original tcon pointer was not removed.
As it is now unused, remove it, so other new drivers can't accidentally
use it.
Signed-off-by: Chen-Yu Tsai
---
As mentioned in the cover letter, please squash this into the patch
drm/sun4i: Use lists to track registered display backends and TCONs
---
drivers/gpu/drm/sun4i/sun4i_drv.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.h
b/drivers/gpu/drm/sun4i/sun4i_drv.h
index 835bdb5cc0c2..250c29017ef5 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.h
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.h
@@ -20,7 +20,6 @@
struct sun4i_drv {
struct list_headbackend_list;
struct list_headtcon_list;
- struct sun4i_tcon *tcon;
struct drm_fbdev_cma*fbdev;
};
--
2.11.0
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[linux-sunxi] [PATCH 2/3] drm/sun4i: Set TCON clock inside sun4i_tconX_mode_set
Currently we are configuring the TCON's dot clock or special clock
directly from the encoder mode_set functions. Since we already
provide mode_set helper functions for the TCON's 2 channels, we
can set the respective clock from those helpers, and reduce the
exposure of the TCON's internals.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_rgb.c | 2 --
drivers/gpu/drm/sun4i/sun4i_tcon.c | 6 ++
drivers/gpu/drm/sun4i/sun4i_tv.c | 2 --
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c
b/drivers/gpu/drm/sun4i/sun4i_rgb.c
index 1147451eb993..51ece4c39d7e 100644
--- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
@@ -175,8 +175,6 @@ static void sun4i_rgb_encoder_mode_set(struct drm_encoder
*encoder,
sun4i_tcon0_mode_set(tcon, mode);
- clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
-
/* FIXME: This seems to be board specific */
clk_set_phase(tcon->dclk, 120);
}
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 8301389c411d..29fd829aa54c 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -131,6 +131,9 @@ void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
u8 clk_delay;
u32 val = 0;
+ /* Configure the dot clock */
+ clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
+
/* Adjust clock delay */
clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
@@ -206,6 +209,9 @@ void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
WARN_ON(!tcon->quirks->has_channel_1);
+ /* Configure the dot clock */
+ clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
+
/* Adjust clock delay */
clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index 49c49431a053..542da220818b 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -486,8 +486,6 @@ static void sun4i_tv_mode_set(struct drm_encoder *encoder,
SUN4I_TVE_RESYNC_FIELD : 0));
regmap_write(tv->regs, SUN4I_TVE_SLAVE_REG, 0);
-
- clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
}
static struct drm_encoder_helper_funcs sun4i_tv_helper_funcs = {
--
2.11.0
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[linux-sunxi] [PATCH 0/3] drm/sun4i: More cleanups and fixes
Hi Maxime, The subject is probably getting old. Here are a few more cleanups. Patch 1 should have been part of the patch drm/sun4i: Use lists to track registered display backends and TCONs from my multiple pipeline support series. Please squash it in if you can. Patch 2 just moves setting the TCON clocks back inside the TCON driver. Patch 3 cleans up a DRM driver debug message. Regards ChenYu Chen-Yu Tsai (3): drm/sun4i: Drop unused tcon pointer drm/sun4i: Set TCON clock inside sun4i_tconX_mode_set drm/sun4i: backend: Clarify sun4i_backend_layer_enable debug message drivers/gpu/drm/sun4i/sun4i_backend.c | 3 ++- drivers/gpu/drm/sun4i/sun4i_drv.h | 1 - drivers/gpu/drm/sun4i/sun4i_rgb.c | 2 -- drivers/gpu/drm/sun4i/sun4i_tcon.c| 6 ++ drivers/gpu/drm/sun4i/sun4i_tv.c | 2 -- 5 files changed, 8 insertions(+), 6 deletions(-) -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 3/3] drm/sun4i: backend: Clarify sun4i_backend_layer_enable debug message
sun4i_backend_layer_enable can be called to enable or disable a layer.
However the debug message always says "Enable", which is confusing.
This patch makes the debug message vary according to the enable state.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c
b/drivers/gpu/drm/sun4i/sun4i_backend.c
index e9eca057ff35..e53107418add 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -73,7 +73,8 @@ void sun4i_backend_layer_enable(struct sun4i_backend *backend,
{
u32 val;
- DRM_DEBUG_DRIVER("Enabling layer %d\n", layer);
+ DRM_DEBUG_DRIVER("%sabling layer %d\n", enable ? "En" : "Dis",
+layer);
if (enable)
val = SUN4I_BACKEND_MODCTL_LAY_EN(layer);
--
2.11.0
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Re: [linux-sunxi] [PATCH 13/15] drm/sun4i: Add HDMI support
On Wed, Apr 26, 2017 at 2:50 PM, Maxime Ripard
wrote:
> Hi Chen-Yu,
>
> On Fri, Apr 21, 2017 at 11:17:17PM +0800, Chen-Yu Tsai wrote:
>> Hi,
>>
>> On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
>> wrote:
>> > The earlier Allwinner SoCs (A10, A10s, A20, A31) have an embedded HDMI
>> > controller.
>> >
>> > That HDMI controller is able to do audio and CEC, but those have been left
>> > out for now.
>> >
>> > Signed-off-by: Maxime Ripard
>> > ---
>> > drivers/gpu/drm/sun4i/Makefile | 5 +-
>> > drivers/gpu/drm/sun4i/sun4i_hdmi.h | 124 ++-
>> > drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c | 128 ++-
>> > drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 449 +-
>> > drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c | 236 +++-
>> > 5 files changed, 942 insertions(+), 0 deletions(-)
>> > create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi.h
>> > create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
>> > create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
>> > create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
>>
>> Applying patch #9608371 using 'git am'
>> Description: [13/15] drm/sun4i: Add HDMI support
>> Applying: drm/sun4i: Add HDMI support
>> .git/rebase-apply/patch:116: trailing whitespace.
>>
>> .git/rebase-apply/patch:531: trailing whitespace.
>>
>> .git/rebase-apply/patch:701: trailing whitespace.
>>
>> warning: 3 lines add whitespace errors.
>
> Fixed.
>
>> > +int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *parent)
>> > +{
>> > + struct clk_init_data init;
>> > + struct sun4i_ddc *ddc;
>> > + const char *parent_name;
>> > +
>> > + parent_name = __clk_get_name(parent);
>> > + if (!parent_name)
>> > + return -ENODEV;
>> > +
>> > + ddc = devm_kzalloc(hdmi->dev, sizeof(*ddc), GFP_KERNEL);
>> > + if (!ddc)
>> > + return -ENOMEM;
>> > +
>> > + init.name = "hdmi-ddc";
>> > + init.ops = &sun4i_ddc_ops;
>> > + init.parent_names = &parent_name;
>> > + init.num_parents = 1;
>> > + init.flags = CLK_SET_RATE_PARENT;
>>
>> I don't think this is really needed. It probably doesn't hurt though,
>> since DDC is used when HDMI is not used for displaying, but it might
>> affect any upstream PLLs, which theoretically may affect other users
>> of said PLLs. The DDC clock is slow enough that we should be able to
>> generate a usable clock rate anyway.
>
> Good point, I removed it.
>
>> > + writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) |
>> > + SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay),
>> > + hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG);
>> > +
>> > + x = mode->htotal - mode->hsync_start;
>> > + y = mode->vtotal - mode->vsync_start;
>>
>> I'm a bit skeptical about this one. All the other parameters are not
>> inclusive of other, why would this one be different? Shouldn't it
>> be "Xtotal - Xsync_end" instead?
>
> By the usual meaning of backporch, you're right. However, Allwinner's
> seems to have it's own, which is actually the backporch + sync length.
>
> We also have that on all the other connectors (and TCON), and this was
> confirmed at the time using a scope on an RGB signal.
Yes. On the later SoCs such as the A31, the user manual actually has
timing diagrams showing this.
Unlike the TCON, the HDMI controller's timings lists the front porch
separately, instead of an all inclusive Xtotal. This is what made me
look twice. This should be easy to confirm though. Since the HDMI modes
are well known and can be exactly reproduced on our hardware, we can
just check for any distortions or refresh rate errors.
>
>>
>> > + writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
>> > + hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG);
>> > +
>> > + x = mode->hsync_start - mode->hdisplay;
>> > + y = mode->vsync_start - mode->vdisplay;
>> > + writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
>> > + hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG);
>> > +
>> > + x = mode->hsync_end - mode->hsync_start;
>> > + y = mode->vsync_en
Re: [linux-sunxi] AllWinner H5 - Orange Pi PC 2, power button for ACPI
On Fri, Apr 28, 2017 at 5:24 PM, Menion wrote:
> Hello again
> I have modified the sun50i-h5-orangepi-pc2.dts
>
> r_gpio_keys {
> compatible = "gpio-keys";
>
> sw4 {
> label = "sw4";
> ---linux,code = <0x100>;
> +++linux,code = <0x74>;
> gpios = <0x24 0x0 0x3 0x1>;
> };
> };
>
> Now, 5sec long press of the power button generate a button/power ACPI event
> that can be used with acpid to trigger a power off.
> Does anyone know why this gpio, that on this specific HW, is used (or shall
> be used) for power down, is bind to BTN_0?
>
IIRC this was done on purpose. The button is a simple GPIO trigger.
It does not have the specific function of a power button, like bringing
it back on, or forceful shutdown.
ChenYu
>
> Il giorno domenica 23 aprile 2017 10:29:40 UTC+2, Menion ha scritto:
>>
>> Hi
>> I have tried to monitor the button via evtest, but nothing is detected
>> Can you provide guidance on how modify dts for making this switch
>> generating a key_power event?
>> Bye
>>
>>
>> Il giorno domenica 23 aprile 2017 06:56:01 UTC+2, Icenowy Zheng ha
>> scritto:
>>>
>>>
>>>
>>> 于 2017年4月22日 GMT+08:00 下午8:34:36, Menion 写到:
>>> >That's wrong. I am currently running a Bananapi (A20) with power and
>>> >reset buttons perfectly working and sending acpi events. Also H3 works
>>> >(Orange pi pc 1)
>>>
>>> Banana Pi has PMIC, but Orange Pi PC2 doesn't.
>>>
>>> In the default mainline kernel, the power key on OPi PC2 is not mapped to
>>> the KEY_POWER, but a BTN_x code.
>>>
>>> You may want to alter the device tree for this (The key is a
>>> GPIO-connected one, and used the gpio-keys dt binding)
>>>
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[linux-sunxi] [PATCH v2 6/8] ARM: sun8i: a83t: Add CCU device nodes
Now that we have support for the A83T CCU, add a device node for it,
and replace any existing placeholder clock phandles with the correct
ones.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index c0a1e4f74b89..c9a5d07b2ada 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -162,13 +162,23 @@
#size-cells = <1>;
ranges;
+ ccu: clock@1c2 {
+ compatible = "allwinner,sun8i-a83t-ccu";
+ reg = <0x01c2 0x400>;
+ clocks = <&osc24M>, <&osc16Md512>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
pio: pinctrl@1c20800 {
compatible = "allwinner,sun8i-a83t-pinctrl";
interrupts = ,
,
;
reg = <0x01c20800 0x400>;
- clocks = <&osc24M>;
+ clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
@@ -214,7 +224,8 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc24M>;
+ clocks = <&ccu 53>;
+ resets = <&ccu 40>;
status = "disabled";
};
--
2.11.0
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[linux-sunxi] [PATCH v2 8/8] ARM: sun8i: a83t: Switch to CCU device tree binding macros
Now that the CCU device tree binding headers have been merged, we can
use the properly named macros in the device tree, instead of raw
numbers.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index e12dd7170b8f..050d3e347740 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -44,6 +44,9 @@
#include
+#include
+#include
+
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
@@ -178,7 +181,7 @@
,
;
reg = <0x01c20800 0x400>;
- clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
@@ -225,8 +228,8 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 53>;
- resets = <&ccu 40>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
--
2.11.0
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[linux-sunxi] [PATCH v2 3/8] clk: sunxi-ng: Add class of phase clocks supporting MMC new timing modes
The MMC clocks on newer SoCs, such as the A83T and H3, support the
"new timing mode". Under this mode, the output of the clock is divided
by 2, and the clock delays no longer apply.
Due to how the clock tree is modeled and setup, we need to model
this function in two places, the master mmc clock and the two
child phase clocks. In the mmc clock, we can easily model the
mode bit as an extra variable post-divider. In the phase clocks,
we check the bit and return -ENOTSUPP if the bit is set, signaling
that the phase clocks are not to be used.
This patch introduces a class of phase clocks that checks the
timing mode bit.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu_phase.c | 47
drivers/clk/sunxi-ng/ccu_phase.h | 16 ++
2 files changed, 63 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu_phase.c b/drivers/clk/sunxi-ng/ccu_phase.c
index 400c58ad72fd..e6ff7551c855 100644
--- a/drivers/clk/sunxi-ng/ccu_phase.c
+++ b/drivers/clk/sunxi-ng/ccu_phase.c
@@ -8,6 +8,7 @@
* the License, or (at your option) any later version.
*/
+#include
#include
#include
@@ -124,3 +125,49 @@ const struct clk_ops ccu_phase_ops = {
.get_phase = ccu_phase_get_phase,
.set_phase = ccu_phase_set_phase,
};
+
+/*
+ * The MMC clocks on newer SoCs support the "new timing mode". Under
+ * this mode, the output of the clock is divided by 2, and the clock
+ * delays no longer apply.
+ *
+ * Due to how the clock tree is modeled and setup, we need to model
+ * this function in two places, the master mmc clock and the two
+ * child phase clocks. In the mmc clock, we can easily model the
+ * mode bit as an extra variable post-divider. In the phase clocks,
+ * we check the bit and return -ENOTSUPP if the bit is set, signaling
+ * that the phase clocks are not to be used.
+ *
+ * We do not support runtime configuration of the modes. Instead a
+ * mode is enforced at CCU probe time.
+ */
+#define CCU_MMC_NEW_TIMING_MODEBIT(30)
+
+static int ccu_phase_mmc_new_timing_get_phase(struct clk_hw *hw)
+{
+ struct ccu_phase *phase = hw_to_ccu_phase(hw);
+ u32 reg;
+
+ reg = readl(phase->common.base + phase->common.reg);
+ if (reg & CCU_MMC_NEW_TIMING_MODE)
+ return -ENOTSUPP;
+
+ return ccu_phase_get_phase(hw);
+}
+
+static int ccu_phase_mmc_new_timing_set_phase(struct clk_hw *hw, int degrees)
+{
+ struct ccu_phase *phase = hw_to_ccu_phase(hw);
+ u32 reg;
+
+ reg = readl(phase->common.base + phase->common.reg);
+ if (reg & CCU_MMC_NEW_TIMING_MODE)
+ return -ENOTSUPP;
+
+ return ccu_phase_set_phase(hw, degrees);
+}
+
+const struct clk_ops ccu_phase_mmc_new_timing_ops = {
+ .get_phase = ccu_phase_mmc_new_timing_get_phase,
+ .set_phase = ccu_phase_mmc_new_timing_set_phase,
+};
diff --git a/drivers/clk/sunxi-ng/ccu_phase.h b/drivers/clk/sunxi-ng/ccu_phase.h
index 75a091a4c565..c514d1798cdd 100644
--- a/drivers/clk/sunxi-ng/ccu_phase.h
+++ b/drivers/clk/sunxi-ng/ccu_phase.h
@@ -38,6 +38,20 @@ struct ccu_phase {
} \
}
+#define SUNXI_CCU_PHASE_MMC_NEW_TIMING(_struct, _name, _parent, _reg, \
+ _shift, _width, _flags) \
+ struct ccu_phase _struct = {\
+ .shift = _shift, \
+ .width = _width, \
+ .common = { \
+ .reg= _reg, \
+ .hw.init= CLK_HW_INIT(_name,\
+ _parent, \
+
&ccu_phase_mmc_new_timing_ops, \
+ _flags), \
+ } \
+ }
+
static inline struct ccu_phase *hw_to_ccu_phase(struct clk_hw *hw)
{
struct ccu_common *common = hw_to_ccu_common(hw);
@@ -47,4 +61,6 @@ static inline struct ccu_phase *hw_to_ccu_phase(struct clk_hw
*hw)
extern const struct clk_ops ccu_phase_ops;
+extern const struct clk_ops ccu_phase_mmc_new_timing_ops;
+
#endif /* _CCU_PHASE_H_ */
--
2.11.0
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[linux-sunxi] [PATCH v2 1/8] dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU
The A83T clock control unit is a hybrid of some new style clock designs from the A80, and old style layout from the other Allwinner SoCs. Like the A80, the SoC does not have a low speed 32.768 kHz oscillator. Unlike the A80, there is no clock input either. The only low speed clock available is the internal oscillator which runs at around 16 MHz, divided by 512, yielding a low speed clock around 31.250 kHz. Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index e9c5a1d9834a..34b2a9249a94 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -6,6 +6,7 @@ Required properties : - "allwinner,sun6i-a31-ccu" - "allwinner,sun8i-a23-ccu" - "allwinner,sun8i-a33-ccu" + - "allwinner,sun8i-a83t-ccu" - "allwinner,sun8i-h3-ccu" - "allwinner,sun8i-h3-r-ccu" - "allwinner,sun8i-v3s-ccu" @@ -18,6 +19,7 @@ Required properties : - clocks: phandle to the oscillators feeding the CCU. Two are needed: - "hosc": the high frequency oscillator (usually at 24MHz) - "losc": the low frequency oscillator (usually at 32kHz) + On the A83T, this is the internal 16MHz oscillator divided by 512 - clock-names: Must contain the clock names described just above - #clock-cells : must contain 1 - #reset-cells : must contain 1 -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v2 5/8] clk: sunxi-ng: Add driver for A83T CCU
The A83T clock control unit is a hybrid of some new style clock designs
from the A80, and old style layout from the other Allwinner SoCs.
Like the A80, the SoC does not have a low speed 32.768 kHz oscillator.
Unlike the A80, there is no clock input either. The only low speed clock
available is the internal oscillator which runs at around 16 MHz,
divided by 512, yielding a low speed clock around 31.250 kHz.
Also, the MMC2 module clock supports switching to a "new timing" mode.
This mode divides the clock output by half, and disables the CCU based
clock delays. The MMC controller must be configure to the same mode,
and then use its internal clock delays.
This driver does not support runtime switching of the timing modes.
Instead, the new timing mode is enforced at probe time. Consumers can
check which mode is active by trying to get the current phase delay
of the MMC2 phase clocks, which will return -ENOTSUPP if the new
timing mode is active.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/Kconfig | 10 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 911 +
drivers/clk/sunxi-ng/ccu-sun8i-a83t.h | 64 ++
include/dt-bindings/clock/sun8i-a83t-ccu.h | 140 +
include/dt-bindings/reset/sun8i-a83t-ccu.h | 98
6 files changed, 1224 insertions(+)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-a83t.h
create mode 100644 include/dt-bindings/clock/sun8i-a83t-ccu.h
create mode 100644 include/dt-bindings/reset/sun8i-a83t-ccu.h
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 64088e599404..8bee22563909 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -116,6 +116,16 @@ config SUN8I_A33_CCU
default MACH_SUN8I
depends on MACH_SUN8I || COMPILE_TEST
+config SUN8I_A83T_CCU
+ bool "Support for the Allwinner A83T CCU"
+ select SUNXI_CCU_DIV
+ select SUNXI_CCU_GATE
+ select SUNXI_CCU_NKMP
+ select SUNXI_CCU_NM
+ select SUNXI_CCU_MP
+ select SUNXI_CCU_PHASE
+ default MACH_SUN8I
+
config SUN8I_H3_CCU
bool "Support for the Allwinner H3 CCU"
select SUNXI_CCU_DIV
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 0ec02fe14c50..78028c8f5fa9 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o
obj-$(CONFIG_SUN6I_A31_CCU)+= ccu-sun6i-a31.o
obj-$(CONFIG_SUN8I_A23_CCU)+= ccu-sun8i-a23.o
obj-$(CONFIG_SUN8I_A33_CCU)+= ccu-sun8i-a33.o
+obj-$(CONFIG_SUN8I_A83T_CCU) += ccu-sun8i-a83t.o
obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
obj-$(CONFIG_SUN8I_V3S_CCU)+= ccu-sun8i-v3s.o
obj-$(CONFIG_SUN8I_R_CCU) += ccu-sun8i-r.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
new file mode 100644
index ..e32ef2cac568
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
@@ -0,0 +1,911 @@
+/*
+ * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+#include "ccu_phase.h"
+
+#include "ccu-sun8i-a83t.h"
+
+#define CCU_SUN8I_A83T_LOCK_REG0x208
+
+static struct clk_div_table pll_cpux_p_div_table[] = {
+ { .val = 0, .div = 1 },
+ { .val = 1, .div = 4 },
+ { /* Sentinel */ },
+};
+
+/*
+ * The CPU PLLs are actually NP clocks, but P is /1 or /4, so here we
+ * use the NM clocks with a divider table for M.
+ */
+static struct ccu_nm pll_c0cpux_clk = {
+ .enable = BIT(31),
+ .lock = BIT(0),
+ .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
+ .m = _SUNXI_CCU_DIV_TABLE(16, 1, pll_cpux_p_div_table),
+ .common = {
+ .reg= 0x000,
+ .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
+ .features = CCU_FEATURE_LOCK_REG,
+ .hw.init= CLK_HW_INIT("pll-c0cpux", "osc24M",
+ &ccu_nm_ops, CLK_SET_RATE_UN
[linux-sunxi] [PATCH v2 7/8] ARM: sun8i: a83t: Set clock accuracy for 24MHz oscillator
The datasheets for Allwinner SoCs set strict requirements on the stability of the external crystal oscillators. Add the accuracy for the main 24MHz oscillator to the device tree. Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a83t.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index c9a5d07b2ada..e12dd7170b8f 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -126,6 +126,7 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <2400>; + clock-accuracy = <5>; clock-output-names = "osc24M"; }; -- 2.11.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v2 4/8] clk: sunxi-ng: Support multiple variable pre-dividers
On the A83T, the AHB1 clock has a shared pre-divider on the two
PLL-PERIPH clock parents. To support such instances of shared
pre-dividers, this patch extends the mux clock type to support
multiple variable pre-dividers.
As the pre-dividers are only used to calculate the rate, but
do not participate in the factorization process, this is fairly
straightforward.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-r.c| 10 +-
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 10 +-
drivers/clk/sunxi-ng/ccu_mux.c| 15 ---
drivers/clk/sunxi-ng/ccu_mux.h| 13 -
9 files changed, 51 insertions(+), 47 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index f54114c607df..2bb4cabf802f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -211,6 +211,9 @@ static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
"axi", "pll-periph0" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+ { .index = 3, .shift = 6, .width = 2 },
+};
static struct ccu_div ahb1_clk = {
.div= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
@@ -218,11 +221,8 @@ static struct ccu_div ahb1_clk = {
.shift = 12,
.width = 2,
- .variable_prediv= {
- .index = 3,
- .shift = 6,
- .width = 2,
- },
+ .var_predivs= ahb1_predivs,
+ .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
},
.common = {
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
index 89e68d29bf45..bc9f2ca19233 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -195,6 +195,9 @@ static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu",
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
"axi", "pll-periph" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+ { .index = 3, .shift = 6, .width = 2 },
+};
static struct ccu_div ahb1_clk = {
.div= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
@@ -203,11 +206,8 @@ static struct ccu_div ahb1_clk = {
.shift = 12,
.width = 2,
- .variable_prediv= {
- .index = 3,
- .shift = 6,
- .width = 2,
- },
+ .var_predivs= ahb1_predivs,
+ .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
},
.common = {
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
index 5c6d37bdf247..8a753ed0426d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
@@ -169,6 +169,9 @@ static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
"axi" , "pll-periph" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+ { .index = 3, .shift = 6, .width = 2 },
+};
static struct ccu_div ahb1_clk = {
.div= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
@@ -176,11 +179,8 @@ static struct ccu_div ahb1_clk = {
.shift = 12,
.width = 2,
- .variable_prediv= {
- .index = 3,
- .shift = 6,
- .width = 2,
- },
+ .var_predivs= ahb1_predivs,
+ .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
},
.common = {
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index 8d38e6510e29..10b38dc46f75 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -180,6 +180,9 @@ static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
"axi" , "pll-periph" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+
