Re: [RFC 1/8] usb: gadget: f_uvc: fix potential memory leak

2014-03-07 Thread Sebastian Andrzej Siewior
On 02/28/2014 10:32 AM, Andrzej Pietrasiewicz wrote:
 If uvc-control_buf is successfuly allocated but uvc-control_req
 is not, uvc-control_buf is not freed in the error recovery path.
 With this patch applied uvc-control_buf is freed unconditionally;
 if it happens to be NULL kfree on it is safe anyway.
 
 Signed-off-by: Andrzej Pietrasiewicz andrze...@samsung.com

Acked-by: Sebastian Andrzej Siewior bige...@linutronix.de

This has nothing todo with configfs interface and is something that has
been broken before.

Sebastian
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Re: [PATCH v3] phy: omap-control: update dra7 and am437 usb2 Documentation bindings

2014-03-07 Thread Kishon Vijay Abraham I

Hi,

On Thursday 06 March 2014 09:33 PM, Felipe Balbi wrote:

From: Roger Quadros rog...@ti.com

The dra7-usb2 and am437-usb2 bindings have not yet been used.
Change them to be more elegant.

Acked-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Felipe Balbi ba...@ti.com
---

Here's updated patch with only Documentation. Tell me if it's ok to apply.

Looks like Tony had some suggestion for the compatible value.


  Documentation/devicetree/bindings/phy/ti-phy.txt | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt 
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 41dc132..8694aae 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -9,9 +9,9 @@ Required properties:
  e.g. USB2_PHY on OMAP5.
   ti,control-phy-pipe3 - if it has DPLL and individual Rx  Tx power control
  e.g. USB3 PHY and SATA PHY on OMAP5.
- ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on
+ ti,control-phy-dra7-usb2 - if it has power down register like USB2 PHY on
  DRA7 platform.


ti,control-phy-usb2-dra7 here and..

- ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on
+ ti,control-phy-am437-usb2 - if it has power down register like USB2 PHY on
  AM437 platform.


ti,control-phy-usb2-am437 here.

Thanks
Kishon
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Re: [PATCH v4] phy: omap-control: update dra7 and am437 usb2 Documentation bindings

2014-03-07 Thread Kishon Vijay Abraham I



On Friday 07 March 2014 01:55 PM, Kishon Vijay Abraham I wrote:

From: Felipe Balbi ba...@ti.com

From: Roger Quadros rog...@ti.com


There seems to be some problem with this patch. Pls ignore this.

Thanks
Kishon


The dra7-usb2 and am437-usb2 bindings have not yet been used.
Change them to be more elegant.

Acked-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Felipe Balbi ba...@ti.com
---
Changes from v3:
* changed the compatible name to 'ti,control-phy-usb2-dra7' and
   'ti,control-phy-usb2-am437'

  Documentation/devicetree/bindings/phy/ti-phy.txt | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt 
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 41dc132..8694aae 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -9,9 +9,9 @@ Required properties:
  e.g. USB2_PHY on OMAP5.
   ti,control-phy-pipe3 - if it has DPLL and individual Rx  Tx power control
  e.g. USB3 PHY and SATA PHY on OMAP5.
- ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on
+ ti,control-phy-usb2-dra7 - if it has power down register like USB2 PHY on
  DRA7 platform.
- ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on
+ ti,control-phy-usb2-am437 - if it has power down register like USB2 PHY on
  AM437 platform.
   - reg : Address and length of the register set for the device. It contains
 the address of otghs_control for control-phy-otghs or power register


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[PATCH v4] phy: omap-control: update dra7 and am437 usb2 bindings

2014-03-07 Thread Kishon Vijay Abraham I
From: Roger Quadros rog...@ti.com

The dra7-usb2 and am437-usb2 bindings have not yet been used.
Change them to be more elegant.

Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Changes from v3:
Changed the compatible value to that suggested by Tony.
ti,control-phy-usb2-dra7 and ti,control-phy-usb2-am437.

Changes from v2:
Kept only the drivers/phy part in this patch

 drivers/phy/phy-omap-control.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
index 17fc200..a7e2d7f 100644
--- a/drivers/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -228,11 +228,11 @@ static const struct of_device_id 
omap_control_phy_id_table[] = {
.data = pipe3_data,
},
{
-   .compatible = ti,control-phy-dra7usb2,
+   .compatible = ti,control-phy-usb2-dra7,
.data = dra7usb2_data,
},
{
-   .compatible = ti,control-phy-am437usb2,
+   .compatible = ti,control-phy-usb2-am437,
.data = am437usb2_data,
},
{},
-- 
1.7.9.5

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Re: [PATCH v3] phy: omap-control: update dra7 and am437 usb2 Documentation bindings

2014-03-07 Thread Roger Quadros
Hi Felipe,

On 03/06/2014 06:03 PM, Felipe Balbi wrote:
 From: Roger Quadros rog...@ti.com
 
 The dra7-usb2 and am437-usb2 bindings have not yet been used.
 Change them to be more elegant.
 
 Acked-by: Kishon Vijay Abraham I kis...@ti.com
 Signed-off-by: Roger Quadros rog...@ti.com
 Signed-off-by: Felipe Balbi ba...@ti.com
 ---
 
 Here's updated patch with only Documentation. Tell me if it's ok to apply.
 
  Documentation/devicetree/bindings/phy/ti-phy.txt | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt 
 b/Documentation/devicetree/bindings/phy/ti-phy.txt
 index 41dc132..8694aae 100644
 --- a/Documentation/devicetree/bindings/phy/ti-phy.txt
 +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
 @@ -9,9 +9,9 @@ Required properties:
  e.g. USB2_PHY on OMAP5.
   ti,control-phy-pipe3 - if it has DPLL and individual Rx  Tx power control
  e.g. USB3 PHY and SATA PHY on OMAP5.
 - ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on
 + ti,control-phy-dra7-usb2 - if it has power down register like USB2 PHY on
  DRA7 platform.

this needs to be ti,control-phy-usb2-dra7 as it is easer to grep.

I'll send a new series with updated patches for you and tony.

cheers,
-roger

 - ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on
 + ti,control-phy-am437-usb2 - if it has power down register like USB2 PHY on
  AM437 platform.
   - reg : Address and length of the register set for the device. It contains
 the address of otghs_control for control-phy-otghs or power register
 

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Re: [PATCH 0/2] target refcounting infrastructure fixes for usb

2014-03-07 Thread James Bottomley
On Thu, 2014-03-06 at 15:18 -0800, Sarah Sharp wrote:
 Hi James,
 
 Sorry for the extremely late ack.

That's OK ... my original plan was to send them in the last merge window
even without your ack, but that got a bit derailed, so I'll do it in
this one with.

   These patches work fine when applied
 against 3.14-rc5, and I can't trigger the oops anymore.  Hans' UAS
 patches are going to be queued for 3.15.  Any chance of these patches
 making it into 3.15 as well?

Yes, the plan is to queue for 3.15 and request a delayed backport to
stable in case any of the extensive logic changes triggers another bug
in the field.

James


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[RESEND] [PATCH] xhci: Switch Intel Lynx Point ports to EHCI on shutdown.

2014-03-07 Thread Denis Turischev
The same issue like with Panther Point chipsets. If the USB ports are
switched to xHCI on shutdown, the xHCI host will send a spurious interrupt,
which will wake the system. Some BIOS have work around for this, but not all.
One example is Compulab's mini-desktop, the Intense-PC2.

The bug can be avoided if the USB ports are switched back to EHCI on
shutdown.

Signed-off-by: Denis Turischev de...@compulab.co.il
---
 drivers/usb/host/xhci-pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index 3c898c1..9233d12 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -134,6 +134,8 @@ static void xhci_pci_quirks(struct device *dev, struct 
xhci_hcd *xhci)
 */
if (pdev-subsystem_vendor == PCI_VENDOR_ID_HP)
xhci-quirks |= XHCI_SPURIOUS_WAKEUP;
+
+   xhci-quirks |= XHCI_SPURIOUS_REBOOT;
}
if (pdev-vendor == PCI_VENDOR_ID_ETRON 
pdev-device == PCI_DEVICE_ID_ASROCK_P67) {
-- 1.8.1.2

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[PATCH v3 6/8] ARM: dts: omap5: add sata node

2014-03-07 Thread Roger Quadros
From: Balaji T K balaj...@ti.com

Add support for sata.

[Roger Q] Clean up.

CC: Benoit Cousson bcous...@baylibre.com
CC: Tony Lindgren t...@atomide.com
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
 arch/arm/boot/dts/omap5.dtsi | 40 
 1 file changed, 40 insertions(+)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 88bd327..521caab 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -829,6 +829,46 @@
 
#thermal-sensor-cells = 1;
};
+
+   omap_control_sata: control-phy@4a002374 {
+   compatible = ti,control-phy-pipe3;
+   reg = 0x4a002374 0x4;
+   reg-names = power;
+   clocks = sys_clkin;
+   clock-names = sysclk;
+   };
+
+   /* OCP2SCP3 */
+   ocp2scp@4a09 {
+   compatible = ti,omap-ocp2scp;
+   #address-cells = 1;
+   #size-cells = 1;
+   reg = 0x4a09 0x20;
+   ranges;
+   ti,hwmods = ocp2scp3;
+   sata_phy: phy@4a096000 {
+   compatible = ti,phy-pipe3-sata;
+   reg = 0x4A096000 0x80, /* phy_rx */
+ 0x4A096400 0x64, /* phy_tx */
+ 0x4A096800 0x40; /* pll_ctrl */
+   reg-names = phy_rx, phy_tx, pll_ctrl;
+   ctrl-module = omap_control_sata;
+   clocks = sys_clkin;
+   clock-names = sysclk;
+   #phy-cells = 0;
+   };
+   };
+
+   sata: sata@4a141100 {
+   compatible = snps,dwc-ahci;
+   reg = 0x4a14 0x1100, 0x4a141100 0x7;
+   interrupts = GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH;
+   phys = sata_phy;
+   phy-names = sata-phy;
+   clocks = sata_ref_clk;
+   ti,hwmods = sata;
+   };
+
};
 };
 
-- 
1.8.3.2

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[PATCH v3 8/8] ARM: dts: dra7: add OCP2SCP3 and SATA nodes

2014-03-07 Thread Roger Quadros
From: Balaji T K balaj...@ti.com

Add nodes for OCP2SCP3 bus, SATA controller and SATA PHY.

[Roger Q] Clean up.

CC: Benoit Cousson bcous...@baylibre.com
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
 arch/arm/boot/dts/dra7.dtsi | 39 +++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 9e3caf3..597979b 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -772,6 +772,45 @@
dma-names = tx0, rx0;
status = disabled;
};
+
+   omap_control_sata: control-phy@4a002374 {
+   compatible = ti,control-phy-pipe3;
+   reg = 0x4a002374 0x4;
+   reg-names = power;
+   clocks = sys_clkin1;
+   clock-names = sysclk;
+   };
+
+   /* OCP2SCP3 */
+   ocp2scp@4a09 {
+   compatible = ti,omap-ocp2scp;
+   #address-cells = 1;
+   #size-cells = 1;
+   ranges;
+   reg = 0x4a09 0x20;
+   ti,hwmods = ocp2scp3;
+   sata_phy: phy@4A096000 {
+   compatible = ti,phy-pipe3-sata;
+   reg = 0x4A096000 0x80, /* phy_rx */
+ 0x4A096400 0x64, /* phy_tx */
+ 0x4A096800 0x40; /* pll_ctrl */
+   reg-names = phy_rx, phy_tx, pll_ctrl;
+   ctrl-module = omap_control_sata;
+   clocks = sys_clkin1;
+   clock-names = sysclk;
+   #phy-cells = 0;
+   };
+   };
+
+   sata: sata@4a141100 {
+   compatible = snps,dwc-ahci;
+   reg = 0x4a14 0x1100, 0x4a141100 0x7;
+   interrupts = GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH;
+   phys = sata_phy;
+   phy-names = sata-phy;
+   clocks = sata_ref_clk;
+   ti,hwmods = sata;
+   };
};
 };
 
-- 
1.8.3.2

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[PATCH v3 7/8] ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods

2014-03-07 Thread Roger Quadros
From: Nikhil Devshatwar nikhil...@ti.com

Add hwmods for ocp2scp3 and sata modules.

[Roger Q] Clean up.

CC: Benoit Cousson bcous...@baylibre.com
CC: Paul Walmsley p...@pwsan.com
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Nikhil Devshatwar nikhil...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 ++-
 1 file changed, 26 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c 
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 18f333c..3c9a430 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
},
 };
 
+/* ocp2scp3 */
+static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
+
+/* l4_cfg - ocp2scp3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
+   .master = dra7xx_l4_cfg_hwmod,
+   .slave  = dra7xx_ocp2scp3_hwmod,
+   .clk= l4_root_clk_div,
+   .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
+   .name   = ocp2scp3,
+   .class  = dra7xx_ocp2scp_hwmod_class,
+   .clkdm_name = l3init_clkdm,
+   .prcm = {
+   .omap4 = {
+   .clkctrl_offs = 
DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
+   .context_offs = 
DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
+   .modulemode   = MODULEMODE_HWCTRL,
+   },
+   },
+};
+
 /*
  * 'qspi' class
  *
@@ -1268,9 +1292,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
 };
 
 /* sata */
-static struct omap_hwmod_opt_clk sata_opt_clks[] = {
-   { .role = ref_clk, .clk = sata_ref_clk },
-};
 
 static struct omap_hwmod dra7xx_sata_hwmod = {
.name   = sata,
@@ -1278,6 +1299,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
.clkdm_name = l3init_clkdm,
.flags  = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk   = func_48m_fclk,
+   .mpu_rt_idx = 1,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
@@ -1285,8 +1307,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
.modulemode   = MODULEMODE_SWCTRL,
},
},
-   .opt_clks   = sata_opt_clks,
-   .opt_clks_cnt   = ARRAY_SIZE(sata_opt_clks),
 };
 
 /*
@@ -2683,6 +2703,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] 
__initdata = {
dra7xx_l4_per1__mmc4,
dra7xx_l4_cfg__mpu,
dra7xx_l4_cfg__ocp2scp1,
+   dra7xx_l4_cfg__ocp2scp3,
dra7xx_l3_main_1__qspi,
dra7xx_l4_cfg__sata,
dra7xx_l4_cfg__smartreflex_core,
-- 
1.8.3.2

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[PATCH v3 3/8] phy: ti-pipe3: Add SATA compatible to Documentation binding

2014-03-07 Thread Roger Quadros
SATA PHY needs a new compatible ID. Add it to the DT binding documentation.

Acked-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
 Documentation/devicetree/bindings/phy/ti-phy.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt 
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 96ba29e..4ab9cb1 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -53,7 +53,8 @@ usb2phy@4a0ad080 {
 TI PIPE3 PHY
 
 Required properties:
- - compatible: Should be ti,phy-usb3. ti,omap-usb3 is deprecated.
+ - compatible: Should be ti,phy-usb3 or ti,phy-pipe3-sata.
+   ti,omap-usb3 is deprecated.
  - reg : Address and length of the register set for the device.
  - reg-names: The names of the register addresses corresponding to the 
registers
filled in reg.
-- 
1.8.3.2

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[PATCH v3 5/8] ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods

2014-03-07 Thread Roger Quadros
From: Keshava Munegowda keshava_mgo...@ti.com

Create hwmods for ocp2scp3 and sata modules.

[Roger Q] Clean up.

CC: Benoit Cousson bcous...@baylibre.com
CC: Paul Walmsley p...@pwsan.com
CC: Tony Lindgren t...@atomide.com
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
 arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 73 ++
 1 file changed, 73 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c 
b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index e297d62..227a69f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -1726,6 +1726,77 @@ static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
},
 };
 
+/*
+ * 'ocp2scp' class
+ * bridge to transform ocp interface protocol to scp (serial control port)
+ * protocol
+ */
+/* ocp2scp3 */
+static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
+/* l4_cfg - ocp2scp3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
+   .master = omap54xx_l4_cfg_hwmod,
+   .slave  = omap54xx_ocp2scp3_hwmod,
+   .clk= l4_root_clk_div,
+   .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
+   .name   = ocp2scp3,
+   .class  = omap54xx_ocp2scp_hwmod_class,
+   .clkdm_name = l3init_clkdm,
+   .prcm = {
+   .omap4 = {
+   .clkctrl_offs = 
OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
+   .context_offs = 
OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
+   .modulemode   = MODULEMODE_HWCTRL,
+   },
+   },
+};
+
+/*
+ * 'sata' class
+ * sata:  serial ata interface  gen2 compliant   ( 1 rx/ 1 tx)
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
+   .sysc_offs  = 0x,
+   .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+   .idlemodes  = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+  SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+  MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+   .sysc_fields= omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
+   .name   = sata,
+   .sysc   = omap54xx_sata_sysc,
+};
+
+/* sata */
+static struct omap_hwmod omap54xx_sata_hwmod = {
+   .name   = sata,
+   .class  = omap54xx_sata_hwmod_class,
+   .clkdm_name = l3init_clkdm,
+   .flags  = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+   .main_clk   = func_48m_fclk,
+   .mpu_rt_idx = 1,
+   .prcm = {
+   .omap4 = {
+   .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
+   .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
+   .modulemode   = MODULEMODE_SWCTRL,
+   },
+   },
+};
+
+/* l4_cfg - sata */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
+   .master = omap54xx_l4_cfg_hwmod,
+   .slave  = omap54xx_sata_hwmod,
+   .clk= l3_iclk_div,
+   .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
 
 /*
  * Interfaces
@@ -2399,6 +2470,8 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] 
__initdata = {
omap54xx_l4_cfg__usb_tll_hs,
omap54xx_l4_cfg__usb_otg_ss,
omap54xx_l4_wkup__wd_timer2,
+   omap54xx_l4_cfg__ocp2scp3,
+   omap54xx_l4_cfg__sata,
NULL,
 };
 
-- 
1.8.3.2

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[PATCH v3 4/8] ARM: dts: omap5: Add clocks to USB3 PHY node

2014-03-07 Thread Roger Quadros
The USB3 PHY driver now expects named clocks. Add the
relevant clocks to the USB3 PHY node.

Signed-off-by: Roger Quadros rog...@ti.com
---
 arch/arm/boot/dts/omap5.dtsi | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 859a800..88bd327 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -779,6 +779,12 @@
  0x4a084c00 0x40;
reg-names = phy_rx, phy_tx, pll_ctrl;
ctrl-module = omap_control_usb3phy;
+   clocks = usb_phy_cm_clk32k,
+sys_clkin,
+usb_otg_ss_refclk960m;
+   clock-names =   wkupclk,
+   sysclk,
+   refclk;
#phy-cells = 0;
};
};
-- 
1.8.3.2

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[PATCH v3 2/8] phy: ti-pipe3: Add clocks to PIPE3 PHY Documentation binding

2014-03-07 Thread Roger Quadros
Add wakeup, system and reference clocks to DT binding documentation.

Acked-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
 Documentation/devicetree/bindings/phy/ti-phy.txt | 12 
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt 
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 073a623..96ba29e 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -59,6 +59,12 @@ Required properties:
filled in reg.
  - #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy.
+ - clocks: a list of phandles and clock-specifier pairs, one for each entry in
+   clock-names.
+ - clock-names: should include:
+   * wkupclk - wakeup clock.
+   * sysclk - system clock.
+   * refclk - reference clock.
 
 Optional properties:
  - ctrl-module : phandle of the control module used by PHY driver to power on
@@ -74,4 +80,10 @@ usb3phy@4a084400 {
reg-names = phy_rx, phy_tx, pll_ctrl;
ctrl-module = omap_control_usb;
#phy-cells = 0;
+   clocks = usb_phy_cm_clk32k,
+sys_clkin,
+usb_otg_ss_refclk960m;
+   clock-names =   wkupclk,
+   sysclk,
+   refclk;
 };
-- 
1.8.3.2

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[PATCH v3 1/8] phy: omap-control: update dra7 and am437 usb2 Documentation bindings

2014-03-07 Thread Roger Quadros
The dra7-usb2 and am437-usb2 bindings have not yet been used.
Change them to be more elegant.

Acked-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
 Documentation/devicetree/bindings/phy/ti-phy.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt 
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 5c5b1b0..073a623 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -9,9 +9,9 @@ Required properties:
 e.g. USB2_PHY on OMAP5.
  ti,control-phy-pipe3 - if it has DPLL and individual Rx  Tx power control
 e.g. USB3 PHY and SATA PHY on OMAP5.
- ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on
+ ti,control-phy-usb2-dra7 - if it has power down register like USB2 PHY on
 DRA7 platform.
- ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on
+ ti,control-phy-usb2-am437 - if it has power down register like USB2 PHY on
 AM437 platform.
  - reg : Address and length of the register set for the device. It contains
the address of otghs_control for control-phy-otghs or power register
-- 
1.8.3.2

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Re: BUG: USB Reset-Resume Mechanism does not work for runtime resume

2014-03-07 Thread Oliver Neukum
On Thu, 2014-03-06 at 10:43 -0500, Alan Stern wrote:
 On Thu, 6 Mar 2014, Oliver Neukum wrote:
 
This is extremely tricky, almost academical a question.
We cannot fall back to reset_resume() in this case without
very bad consequences.
If remote wakeup is needed, reset_resume() must not be used.
   
   The only alternative is to logically disconnect the device.  But this 
   conflicts with the persist_enabled flag.
  
  In error handling? It seems to me that persist_enabled is a declaration
  of a goal. What the consequences of reaching that
  goal should be is a legitimate question.
  
It seems to me that the bug in this case is the fallback itself.
From a design viewpoint is probably wrong the unbind a device
in the runtime case. We'd better notify the driver in every case.
If you unbind and rebind you just risk getting into a tight loop.
   
   In this case, turning off the persist flag might help:
   
 echo 0 /sys/bus/usb/devices/.../power/persist
  
  But in case remote wakeup is not requested the device
  should persist.
 
 Then you're suggesting something like this in finish_port_resume()?
 
   status = usb_get_status(udev, USB_RECIP_DEVICE, 0, devstatus);
 
 - /* If a normal resume failed, try doing a reset-resume */
 - if (status  !udev-reset_resume  udev-persist_enabled) {
 + /*
 +  * If a normal resume failed and remote wakeup is disabled,
 +  * try doing a reset-resume.
 +  */
 + if (status  !udev-reset_resume  !udev-do_remote_wakeup 
 + udev-persist_enabled) {
   dev_dbg(udev-dev, retry with reset-resume\n);
   udev-reset_resume = 1;
   goto retry_reset_resume;
 
 Are there any wakeup-enabled devices that this will mess up?

Potentially HID. Now that I think about this it seems to me that
drivers really need to be told about the error condition. For
btusb the error condition cannot be handled. For HID it may mean
a lost key or click at the worst. The driver should react to such
errors by disabling power management, but that requires that it
become aware of such errors.

Regards
Oliver



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[patch 1/2] usb: dwc3: gadget: cut and paste fixups in suspend/resume

2014-03-07 Thread Dan Carpenter
These were cut and paste from the -disconnect function.

Fixes: 30d577b9bcc4 ('usb: dwc3: gadget: call gadget driver's 
-suspend/-resume')
Signed-off-by: Dan Carpenter dan.carpen...@oracle.com

diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index eaf853721fec..95b9eae05617 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2066,7 +2066,7 @@ static void dwc3_disconnect_gadget(struct dwc3 *dwc)
 
 static void dwc3_suspend_gadget(struct dwc3 *dwc)
 {
-   if (dwc-gadget_driver  dwc-gadget_driver-disconnect) {
+   if (dwc-gadget_driver  dwc-gadget_driver-suspend) {
spin_unlock(dwc-lock);
dwc-gadget_driver-suspend(dwc-gadget);
spin_lock(dwc-lock);
@@ -2075,7 +2075,7 @@ static void dwc3_suspend_gadget(struct dwc3 *dwc)
 
 static void dwc3_resume_gadget(struct dwc3 *dwc)
 {
-   if (dwc-gadget_driver  dwc-gadget_driver-disconnect) {
+   if (dwc-gadget_driver  dwc-gadget_driver-resume) {
spin_unlock(dwc-lock);
dwc-gadget_driver-resume(dwc-gadget);
spin_lock(dwc-lock);
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[patch 2/2] usb: dwc3: gadget: remove known conditions

2014-03-07 Thread Dan Carpenter
We know what value is and it upsets static checkers that we appear to
have doubts about it.

Signed-off-by: Dan Carpenter dan.carpen...@oracle.com

diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 95b9eae05617..a7df8120cf82 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -1233,8 +1233,7 @@ int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int 
value)
ret = dwc3_send_gadget_ep_cmd(dwc, dep-number,
DWC3_DEPCMD_SETSTALL, params);
if (ret)
-   dev_err(dwc-dev, failed to %s STALL on %s\n,
-   value ? set : clear,
+   dev_err(dwc-dev, failed to set STALL on %s\n,
dep-name);
else
dep-flags |= DWC3_EP_STALL;
@@ -1242,8 +1241,7 @@ int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int 
value)
ret = dwc3_send_gadget_ep_cmd(dwc, dep-number,
DWC3_DEPCMD_CLEARSTALL, params);
if (ret)
-   dev_err(dwc-dev, failed to %s STALL on %s\n,
-   value ? set : clear,
+   dev_err(dwc-dev, failed to clear STALL on %s\n,
dep-name);
else
dep-flags = ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
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[PATCH 7/8] ARM: dts: dra7: Add USB related nodes

2014-03-07 Thread Roger Quadros
Add nodes for the Super Speed USB controllers, omap-control-usb,
USB2 PHY and USB3 PHY devices.

Remove ocp2scp1 address space from hwmod data as it is
now provided via device tree.

Signed-off-by: Roger Quadros rog...@ti.com
---
 arch/arm/boot/dts/dra7.dtsi   | 110 ++
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c |  10 ---
 2 files changed, 110 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 597979b..1e73900 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -811,6 +811,116 @@
clocks = sata_ref_clk;
ti,hwmods = sata;
};
+
+   omap_control_usb2phy1: control-phy@4a002300 {
+   compatible = ti,control-phy-usb2;
+   reg = 0x4a002300 0x4;
+   reg-names = power;
+   };
+
+   omap_control_usb3phy1: control-phy@4a002370 {
+   compatible = ti,control-phy-pipe3;
+   reg = 0x4a002370 0x4;
+   reg-names = power;
+   };
+
+   omap_control_usb2phy2: control-phy@0x4a002e74 {
+   compatible = ti,control-phy-usb2-dra7;
+   reg = 0x4a002e74 0x4;
+   reg-names = power;
+   };
+
+   /* OCP2SCP1 */
+   ocp2scp@4a08 {
+   compatible = ti,omap-ocp2scp;
+   #address-cells = 1;
+   #size-cells = 1;
+   ranges;
+   reg = 0x4a08 0x20;
+   ti,hwmods = ocp2scp1;
+
+   usb2_phy1: phy@4a084000 {
+   compatible = ti,omap-usb2;
+   reg = 0x4a084000 0x400;
+   ctrl-module = omap_control_usb2phy1;
+   clocks = usb_phy1_always_on_clk32k,
+usb_otg_ss1_refclk960m;
+   clock-names =   wkupclk,
+   refclk;
+   #phy-cells = 0;
+   };
+
+   usb2_phy2: phy@4a085000 {
+   compatible = ti,omap-usb2;
+   reg = 0x4a085000 0x400;
+   ctrl-module = omap_control_usb2phy2;
+   clocks = usb_phy2_always_on_clk32k,
+usb_otg_ss2_refclk960m;
+   clock-names =   wkupclk,
+   refclk;
+   #phy-cells = 0;
+   };
+
+   usb3_phy1: phy@4a084400 {
+   compatible = ti,omap-usb3;
+   reg = 0x4a084400 0x80,
+ 0x4a084800 0x64,
+ 0x4a084c00 0x40;
+   reg-names = phy_rx, phy_tx, pll_ctrl;
+   ctrl-module = omap_control_usb3phy1;
+   clocks = usb_phy3_always_on_clk32k,
+sys_clkin1,
+usb_otg_ss1_refclk960m,
+dpll_core_h13x2_ck;
+   clock-names =   wkupclk,
+   sysclk,
+   refclk,
+   optclk;
+   #phy-cells = 0;
+   };
+   };
+
+   omap_dwc3_1@4888 {
+   compatible = ti,dwc3;
+   ti,hwmods = usb_otg_ss1;
+   reg = 0x4888 0x1;
+   interrupts = 0 77 4;
+   #address-cells = 1;
+   #size-cells = 1;
+   utmi-mode = 2;
+   ranges;
+   usb1: usb@4889 {
+   compatible = snps,dwc3;
+   reg = 0x4889 0x17000;
+   interrupts = 0 76 4;
+   phys = usb2_phy1, usb3_phy1;
+   phy-names = usb2-phy, usb3-phy;
+   tx-fifo-resize;
+   maximum-speed = super-speed;
+   dr_mode = otg;
+   };
+   };
+
+   omap_dwc3_2@488c {
+   compatible = ti,dwc3;
+   ti,hwmods = usb_otg_ss2;
+   reg = 0x488c 0x1;
+   interrupts = 0 92 4;

[PATCH 4/8] phy: omap-usb2: Use generic clock names wkupclk and refclk

2014-03-07 Thread Roger Quadros
As clocks might be named differently on multiple platforms, use a generic
name in the driver and allow device tree node to specify the platform
specific clock name.

Signed-off-by: Roger Quadros rog...@ti.com
---
 drivers/phy/phy-omap-usb2.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index a2205a8..fb5e515 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -275,16 +275,16 @@ static int omap_usb2_probe(struct platform_device *pdev)
if (IS_ERR(phy_provider))
return PTR_ERR(phy_provider);
 
-   phy-wkupclk = devm_clk_get(phy-dev, usb_phy_cm_clk32k);
+   phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
if (IS_ERR(phy-wkupclk)) {
-   dev_err(pdev-dev, unable to get usb_phy_cm_clk32k\n);
+   dev_err(pdev-dev, unable to get wkupclk\n);
return PTR_ERR(phy-wkupclk);
}
clk_prepare(phy-wkupclk);
 
-   phy-optclk = devm_clk_get(phy-dev, usb_otg_ss_refclk960m);
+   phy-optclk = devm_clk_get(phy-dev, refclk);
if (IS_ERR(phy-optclk))
-   dev_vdbg(pdev-dev, unable to get refclk960m\n);
+   dev_dbg(pdev-dev, unable to get refclk\n);
else
clk_prepare(phy-optclk);
 
-- 
1.8.3.2

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[PATCH 3/8] ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss

2014-03-07 Thread Roger Quadros
Add the sysconfig class bits for the Super Speed USB
controllers

Signed-off-by: Roger Quadros rog...@ti.com
---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c 
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 3c9a430..cca24ad 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1752,8 +1752,20 @@ static struct omap_hwmod dra7xx_uart6_hwmod = {
  *
  */
 
+static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
+   .rev_offs   = 0x,
+   .sysc_offs  = 0x0010,
+   .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
+  SYSC_HAS_SIDLEMODE),
+   .idlemodes  = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+  SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+  MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+   .sysc_fields= omap_hwmod_sysc_type2,
+};
+
 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
.name   = usb_otg_ss,
+   .sysc   = dra7xx_usb_otg_ss_sysc,
 };
 
 /* usb_otg_ss1 */
-- 
1.8.3.2

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[PATCH 6/8] ARM: dts: omap4+: Add clocks to USB2 PHY node

2014-03-07 Thread Roger Quadros
The USB2 PHY driver expects named clocks for wakeup clock
and reference clock. Provide this information for USB2 PHY
nodes in OMAP4 and OMAP5 SoC DTS.

Signed-off-by: Roger Quadros rog...@ti.com
---
 arch/arm/boot/dts/omap4.dtsi | 2 ++
 arch/arm/boot/dts/omap5.dtsi | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 4e15be5..2f6cfa6 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -608,6 +608,8 @@
compatible = ti,omap-usb2;
reg = 0x4a0ad080 0x58;
ctrl-module = omap_control_usb2phy;
+   clocks = usb_phy_cm_clk32k;
+   clock-names = wkupclk;
#phy-cells = 0;
};
};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 521caab..bf629bb 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -769,6 +769,8 @@
compatible = ti,omap-usb2;
reg = 0x4a084000 0x7c;
ctrl-module = omap_control_usb2phy;
+   clocks = usb_phy_cm_clk32k, 
usb_otg_ss_refclk960m;
+   clock-names = wkupclk, refclk;
#phy-cells = 0;
};
 
-- 
1.8.3.2

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[PATCH 2/8] ARM: dts: dra7-clock: Add l3init_960m_gfclk clock gate

2014-03-07 Thread Roger Quadros
This clock gate description was missing in older Reference manuals.
It is present on the SoC to provide 960MHz reference clock to the
internal USB PHYs.

Use l3init_960m_gfclk as parent of usb_otg_ss1_refclk960m and
usb_otg_ss2_refclk960m.

CC: Tero Kristo t-kri...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi 
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index e96da9a..b8d3a9d 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1386,6 +1386,14 @@
ti,dividers = 1, 8;
};
 
+   l3init_960m_gfclk: l3init_960m_gfclk {
+   #clock-cells = 0;
+   compatible = ti,gate-clock;
+   clocks = dpll_usb_clkdcoldo;
+   ti,bit-shift = 8;
+   reg = 0x06c0;
+   };
+
dss_32khz_clk: dss_32khz_clk {
#clock-cells = 0;
compatible = ti,gate-clock;
@@ -1533,7 +1541,7 @@
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
#clock-cells = 0;
compatible = ti,gate-clock;
-   clocks = dpll_usb_clkdcoldo;
+   clocks = l3init_960m_gfclk;
ti,bit-shift = 8;
reg = 0x13f0;
};
@@ -1541,7 +1549,7 @@
usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
#clock-cells = 0;
compatible = ti,gate-clock;
-   clocks = dpll_usb_clkdcoldo;
+   clocks = l3init_960m_gfclk;
ti,bit-shift = 8;
reg = 0x1340;
};
-- 
1.8.3.2

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[PATCH 0/8] USB support for DRA7-evm

2014-03-07 Thread Roger Quadros
Hi,

This series enables the 2 USB ports on the DRA7-evm.

Patches are based on on 3.14-rc4 with balbi/next, linux-phy/next,
omap-for-v3.15/dt merged and [1] applied.

[1] - http://article.gmane.org/gmane.linux.drivers.devicetree/65223.

cheers,
-roger

---
Roger Quadros (8):
  CLK: ti: dra7: Initialize USB_DPLL
  ARM: dts: dra7-clock: Add l3init_960m_gfclk clock gate
  ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss
  phy: omap-usb2: Use generic clock names wkupclk and refclk
  phy: omap-usb2: Add clock names to Documentation binding
  ARM: dts: omap4+: Add clocks to USB2 PHY node
  ARM: dts: dra7: Add USB related nodes
  dts: dra7-evm: add USB support

 Documentation/devicetree/bindings/phy/ti-phy.txt |   7 ++
 arch/arm/boot/dts/dra7-evm.dts   |  24 +
 arch/arm/boot/dts/dra7.dtsi  | 110 +++
 arch/arm/boot/dts/dra7xx-clocks.dtsi |  12 ++-
 arch/arm/boot/dts/omap4.dtsi |   2 +
 arch/arm/boot/dts/omap5.dtsi |   2 +
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c|  22 ++---
 drivers/clk/ti/clk-7xx.c |  11 +++
 drivers/phy/phy-omap-usb2.c  |   8 +-
 9 files changed, 182 insertions(+), 16 deletions(-)

-- 
1.8.3.2

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[PATCH 1/8] CLK: ti: dra7: Initialize USB_DPLL

2014-03-07 Thread Roger Quadros
USB_DPLL must be initialized and locked at boot so that
USB modules can work.

Also program USB_DLL_M2 output to half rate.

CC: Mike Turquette mturque...@linaro.org
CC: Tero Kristo t-kri...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
 drivers/clk/ti/clk-7xx.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index 9977653..f89f3c2 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -18,6 +18,7 @@
 
 #define DRA7_DPLL_ABE_DEFFREQ  361267200
 #define DRA7_DPLL_GMAC_DEFFREQ 10
+#define DRA7_DPLL_USB_DEFFREQ  96000
 
 
 static struct ti_dt_clk dra7xx_clks[] = {
@@ -328,5 +329,15 @@ int __init dra7xx_dt_clk_init(void)
if (rc)
pr_err(%s: failed to configure GMAC DPLL!\n, __func__);
 
+   dpll_ck = clk_get_sys(NULL, dpll_usb_ck);
+   rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
+   if (rc)
+   pr_err(%s: failed to configure USB DPLL!\n, __func__);
+
+   dpll_ck = clk_get_sys(NULL, dpll_usb_m2_ck);
+   rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
+   if (rc)
+   pr_err(%s: failed to set USB_DPLL M2 OUT\n, __func__);
+
return rc;
 }
-- 
1.8.3.2

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[PATCH 5/8] phy: omap-usb2: Add clock names to Documentation binding

2014-03-07 Thread Roger Quadros
Add wkupclk and refclk information to DT binding information.

Signed-off-by: Roger Quadros rog...@ti.com
---
 Documentation/devicetree/bindings/phy/ti-phy.txt | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt 
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 4ab9cb1..49c381c 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -36,6 +36,11 @@ Required properties:
  - reg : Address and length of the register set for the device.
  - #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy.
+ - clocks: a list of phandles and clock-specifier pairs, one for each entry in
+   clock-names.
+ - clock-names: should include:
+   * wkupclk - wakeup clock.
+   * refclk - reference clock (optional).
 
 Optional properties:
  - ctrl-module : phandle of the control module used by PHY driver to power on
@@ -48,6 +53,8 @@ usb2phy@4a0ad080 {
reg = 0x4a0ad080 0x58;
ctrl-module = omap_control_usb;
#phy-cells = 0;
+   clocks = usb_phy_cm_clk32k, usb_otg_ss_refclk960m;
+   clock-names = wkupclk, refclk;
 };
 
 TI PIPE3 PHY
-- 
1.8.3.2

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Re: [PATCH 1/8] CLK: ti: dra7: Initialize USB_DPLL

2014-03-07 Thread Tero Kristo

On 03/07/2014 03:09 PM, Roger Quadros wrote:

USB_DPLL must be initialized and locked at boot so that
USB modules can work.

Also program USB_DLL_M2 output to half rate.

CC: Mike Turquette mturque...@linaro.org
CC: Tero Kristo t-kri...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
  drivers/clk/ti/clk-7xx.c | 11 +++
  1 file changed, 11 insertions(+)

diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index 9977653..f89f3c2 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -18,6 +18,7 @@

  #define DRA7_DPLL_ABE_DEFFREQ 361267200
  #define DRA7_DPLL_GMAC_DEFFREQ10
+#define DRA7_DPLL_USB_DEFFREQ  96000


  static struct ti_dt_clk dra7xx_clks[] = {
@@ -328,5 +329,15 @@ int __init dra7xx_dt_clk_init(void)
if (rc)
pr_err(%s: failed to configure GMAC DPLL!\n, __func__);

+   dpll_ck = clk_get_sys(NULL, dpll_usb_ck);
+   rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
+   if (rc)
+   pr_err(%s: failed to configure USB DPLL!\n, __func__);
+
+   dpll_ck = clk_get_sys(NULL, dpll_usb_m2_ck);
+   rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
+   if (rc)
+   pr_err(%s: failed to set USB_DPLL M2 OUT\n, __func__);
+


I would rather see this done using the default-rate mechanism provided here:

https://www.mail-archive.com/linux-omap@vger.kernel.org/msg101300.html

However, this remains to be commented by Mike whether the patch is okay 
or not.


-Tero


return rc;
  }



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Re: [PATCH 2/8] ARM: dts: dra7-clock: Add l3init_960m_gfclk clock gate

2014-03-07 Thread Tero Kristo

On 03/07/2014 03:09 PM, Roger Quadros wrote:

This clock gate description was missing in older Reference manuals.
It is present on the SoC to provide 960MHz reference clock to the
internal USB PHYs.


Can you provide a document reference here?

-Tero



Use l3init_960m_gfclk as parent of usb_otg_ss1_refclk960m and
usb_otg_ss2_refclk960m.

CC: Tero Kristo t-kri...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
  arch/arm/boot/dts/dra7xx-clocks.dtsi | 12 ++--
  1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi 
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index e96da9a..b8d3a9d 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1386,6 +1386,14 @@
ti,dividers = 1, 8;
};

+   l3init_960m_gfclk: l3init_960m_gfclk {
+   #clock-cells = 0;
+   compatible = ti,gate-clock;
+   clocks = dpll_usb_clkdcoldo;
+   ti,bit-shift = 8;
+   reg = 0x06c0;
+   };
+
dss_32khz_clk: dss_32khz_clk {
#clock-cells = 0;
compatible = ti,gate-clock;
@@ -1533,7 +1541,7 @@
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
#clock-cells = 0;
compatible = ti,gate-clock;
-   clocks = dpll_usb_clkdcoldo;
+   clocks = l3init_960m_gfclk;
ti,bit-shift = 8;
reg = 0x13f0;
};
@@ -1541,7 +1549,7 @@
usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
#clock-cells = 0;
compatible = ti,gate-clock;
-   clocks = dpll_usb_clkdcoldo;
+   clocks = l3init_960m_gfclk;
ti,bit-shift = 8;
reg = 0x1340;
};



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Re: [PATCH v2] phy-rcar-gen2-usb: add device tree support

2014-03-07 Thread Sergei Shtylyov

Hello.

On 07-03-2014 9:46, Magnus Damm wrote:


Add support of the device tree probing for the Renesas R-Car generation 2 SoCs
documenting the device tree binding as necessary.



Signed-off-by: Sergei Shtylyov sergei.shtyl...@cogentembedded.com



---
This patch is against the 'next' branch of Felipe Balbi's 'usb.git' repo.



Changes in version 2:
- restored devm_clk_get() call and the error handling logic in the probe()
   method, removed clk_put() call in the remove() method.



  Documentation/devicetree/bindings/usb/rcar-gen2-phy.txt |   29 +++
  drivers/usb/phy/phy-rcar-gen2-usb.c |   42 
++--
  2 files changed, 68 insertions(+), 3 deletions(-)



Index: usb/Documentation/devicetree/bindings/usb/rcar-gen2-phy.txt
===
--- /dev/null
+++ usb/Documentation/devicetree/bindings/usb/rcar-gen2-phy.txt
@@ -0,0 +1,29 @@
+* Renesas R-Car generation 2 USB PHY
+
+This file provides information on what the device node for the R-Car generation
+2 USB PHY contains.
+
+Required properties:
+- compatible: renesas,usb-phy-r8a7790 if the device is a part of R8A7790 SoC.
+ renesas,usb-phy-r8a7791 if the device is a part of R8A7791 SoC.
+- reg: offset and length of the register block.
+- clocks: clock phandle and specifier pair.
+- clock-names: string, clock input name, must be usbhs.
+
+Optional properties:
+- renesas,channel0-pci: boolean, specify when USB channel 0 should be connected
+   to PCI EHCI/OHCI; otherwise, it will be connected to the
+   USBHS controller.
+- renesas,channel2-pci: boolean, specify when USB channel 2 should be connected
+   to PCI EHCI/OHCI; otherwise, it will be connected to the
+   USBSS controller (xHCI).



Thanks for your efforts here, but this DT binding looks like a mix of
software configuration and hardware description.


   I disagree. I have already explained to Mark Rutland how selecting a 
particular controller for a particular USB port should depend on the kind of 
the USB connector used, i.e. the board hardware.



+Example (Lager board):
+
+   usb-phy@e6590100 {
+   compatible = renesas,usb-phy-r8a7790;
+   reg = 0 0xe6590100 0 0x100;
+   clocks = mstp7_clks R8A7790_CLK_HSUSB;
+   clock-names = usbhs;
+   renesas,channel2-pci;
+   };



As an example, instead of relying on renesas,channel0-pci or
renesas,channel2-pci to specify which hard coded software
configuration you want please rework this to expose 3 separate
channels and use DT to point each host controller to the right
channel.


   So you want to expose the channels as virtual devices? Or what do you 
want? Also, it seems almost impossible to represent some USB controllers in DT 
-- such as USBHS in particular.



That will give us the opportunity to perform any kind of run time
selection and not be limited by software policy set by DT.


   Sorry, but I don't see how using DT could help with run-time selection.
Could you please explain?


So this is a NAK on my side. I expect better.


   Thanks for your long awaited feedback.


Thanks,



/ magnus


WBR, Sergei

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Re: Renesas RCar device-tree USB series

2014-03-07 Thread Ben Dooks

On 07/03/14 05:36, Magnus Damm wrote:

Hi Ben,

On Fri, Mar 7, 2014 at 3:01 AM, Ben Dooks ben.do...@codethink.co.uk wrote:

This is a new series covering enabling the RCar series of SoCs USB
with device-tree based booting. It has been tested on the R8A7790
Lager board.

Improvements from the previous series include:

 - mapping usb to the relevant phy by dt
 - better use of existing pci of functions

Note, there is still an issue with the second gigabyte of memory on
the Lager, which with current kernels causes the system to abort on
startup. This series will only work if the top memory area is disabled.


Thanks for these patches. I think they start looking really good.

In my mind there are two outstanding issues:

1) Is the USB core code change acceptable or not?

The patch [PATCH 4/9] usb: phy: check for of_node when getting phy
looks quite fine to me, but I wonder if the USB maintainers will
accept it as-is or require some rework. I would say that the rest of
this series depends on that USB core change.


I'm not sure, but without it we need to hack the PHY driver to
turn on the PHY at start time.


2) Per-port USB PHY driver configuration via DT

Right now each USB host controller points to the same PHY device.
Thanks for working on describing the topology! As you know, the PHY
driver itself handles several USB ports, and I'd like to use DT to
represent the mapping between which PHY port that maps to what USB
Host controller to allow proper run time configuration. Right now in
this version of the series there is no such mapping. Of course, that
depends on proper USB PHY DT bindings...


Hmm, given the shared phy is shared and referenced counted then
I don't /think/ there is much more to be done for this. If we add
more PHYs then I would assume that each one of them would



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[PATCH 0/2] xhci, usbnet: fixes for 3.14

2014-03-07 Thread Mathias Nyman
Hi Greg,

These two xhci scatter-gather related patches should be reverted to avoid
USB 3.0 mass storage regression for users.
Sarah and Alan concluded that this the best choice until proper TD fragmentation
rules are implemented, discussion is here:  

http://marc.info/?l=linux-usbm=139395884021971w=2

The patch xhci 1.0: Limit arbitrarily-aligned scatter gather. was added
to 3.14-rc1 and stable, both patches should be reverted from stable and 3.14

A few mass storage regression cases:
http://marc.info/?l=linux-usbm=139413069718354w=2
http://marc.info/?l=linux-usbm=139411871213253w=2
http://marc.info/?l=linux-usbm=139361293103188w=2

-Mathias

Mathias Nyman (2):
  Revert xhci 1.0: Limit arbitrarily-aligned scatter gather.
  Revert USBNET: ax88179_178a: enable tso if usb host supports sg dma

 drivers/net/usb/ax88179_178a.c |  8 
 drivers/usb/host/xhci.c| 14 +++---
 2 files changed, 3 insertions(+), 19 deletions(-)

-- 
1.8.1.2

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[PATCH 2/2] Revert USBNET: ax88179_178a: enable tso if usb host supports sg dma

2014-03-07 Thread Mathias Nyman
This reverts commit 3804fad45411b48233b48003e33a78f290d227c8.

This commit, together with commit 247bf557273dd775505fb9240d2d152f4f20d304
xhci 1.0: Limit arbitrarily-aligned scatter gather. were
origially added to get xHCI 1.0 hosts and usb ethernet ax88179_178a devices
working together with scatter gather. xHCI 1.0 hosts pose some requirement on 
how transfer
buffers are aligned, setting this requirement for 1.0 hosts caused USB 3.0 mass
storage devices to fail more frequently.

USB 3.0 mass storage devices used to work before 3.14-rc1.  Theoretically,
the TD fragment rules could have caused an occasional disk glitch.
Now the devices *will* fail, instead of theoretically failing.
From a user perspective, this looks like a regression; the USB device obviously
fails on 3.14-rc1, and may sometimes silently fail on prior kernels.

The proper soluition is to implement the TD fragment rules for xHCI 1.0 hosts,
but for now, revert this patch until scatter gather can be properly supported.

Signed-off-by: Mathias Nyman mathias.ny...@linux.intel.com
Cc: stable sta...@vger.kernel.org
---
 drivers/net/usb/ax88179_178a.c | 8 
 1 file changed, 8 deletions(-)

diff --git a/drivers/net/usb/ax88179_178a.c b/drivers/net/usb/ax88179_178a.c
index 955df81..42085e6 100644
--- a/drivers/net/usb/ax88179_178a.c
+++ b/drivers/net/usb/ax88179_178a.c
@@ -1029,20 +1029,12 @@ static int ax88179_bind(struct usbnet *dev, struct 
usb_interface *intf)
dev-mii.phy_id = 0x03;
dev-mii.supports_gmii = 1;
 
-   if (usb_device_no_sg_constraint(dev-udev))
-   dev-can_dma_sg = 1;
-
dev-net-features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  NETIF_F_RXCSUM;
 
dev-net-hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
 NETIF_F_RXCSUM;
 
-   if (dev-can_dma_sg) {
-   dev-net-features |= NETIF_F_SG | NETIF_F_TSO;
-   dev-net-hw_features |= NETIF_F_SG | NETIF_F_TSO;
-   }
-
/* Enable checksum offload */
*tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
   AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
-- 
1.8.1.2

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[PATCH 1/2] Revert xhci 1.0: Limit arbitrarily-aligned scatter gather.

2014-03-07 Thread Mathias Nyman
This reverts commit 247bf557273dd775505fb9240d2d152f4f20d304.

This commit, together with commit 3804fad45411b48233b48003e33a78f290d227c8
USBNET: ax88179_178a: enable tso if usb host supports sg dma were
origially added to get xHCI 1.0 hosts and usb ethernet ax88179_178a devices
working together with scatter gather. xHCI 1.0 hosts pose some requirement on 
how transfer
buffers are aligned, setting this requirement for 1.0 hosts caused USB 3.0 mass
storage devices to fail more frequently.

USB 3.0 mass storage devices used to work before 3.14-rc1.  Theoretically,
the TD fragment rules could have caused an occasional disk glitch.
Now the devices *will* fail, instead of theoretically failing.
From a user perspective, this looks like a regression; the USB device obviously
fails on 3.14-rc1, and may sometimes silently fail on prior kernels.

The proper soluition is to implement the TD fragment rules required, but for now
this patch needs to be reverted to get USB 3.0 mass storage devices working at 
the
level they used to.

Signed-off-by: Mathias Nyman mathias.ny...@linux.intel.com
Cc: stable sta...@vger.kernel.org
---
 drivers/usb/host/xhci.c | 14 +++---
 1 file changed, 3 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 6fe577d..924a6cc 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -4733,6 +4733,9 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t 
get_quirks)
/* Accept arbitrarily long scatter-gather lists */
hcd-self.sg_tablesize = ~0;
 
+   /* support to build packet from discontinuous buffers */
+   hcd-self.no_sg_constraint = 1;
+
/* XHCI controllers don't stop the ep queue on short packets :| */
hcd-self.no_stop_on_short = 1;
 
@@ -4757,14 +4760,6 @@ int xhci_gen_setup(struct usb_hcd *hcd, 
xhci_get_quirks_t get_quirks)
/* xHCI private pointer was set in xhci_pci_probe for the second
 * registered roothub.
 */
-   xhci = hcd_to_xhci(hcd);
-   /*
-* Support arbitrarily aligned sg-list entries on hosts without
-* TD fragment rules (which are currently unsupported).
-*/
-   if (xhci-hci_version  0x100)
-   hcd-self.no_sg_constraint = 1;
-
return 0;
}
 
@@ -4793,9 +4788,6 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t 
get_quirks)
if (xhci-hci_version  0x96)
xhci-quirks |= XHCI_SPURIOUS_SUCCESS;
 
-   if (xhci-hci_version  0x100)
-   hcd-self.no_sg_constraint = 1;
-
/* Make sure the HC is halted. */
retval = xhci_halt(xhci);
if (retval)
-- 
1.8.1.2

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RE: [PATCH 2/2] Revert USBNET: ax88179_178a: enable tso if usb host supports sg dma

2014-03-07 Thread David Laight
From: Mathias Nyman
 This reverts commit 3804fad45411b48233b48003e33a78f290d227c8.
 
 This commit, together with commit 247bf557273dd775505fb9240d2d152f4f20d304
 xhci 1.0: Limit arbitrarily-aligned scatter gather. were
 origially added to get xHCI 1.0 hosts and usb ethernet ax88179_178a devices
 working together with scatter gather. xHCI 1.0 hosts pose some requirement on 
 how transfer
 buffers are aligned, setting this requirement for 1.0 hosts caused USB 3.0 
 mass
 storage devices to fail more frequently.

This patch doesn't need to be reverted.
Provided the xhci driver doesn't set the flag to say that arbitrary scatter
gather is supported (ie usb_device_no_sg_constraint(dev-udev)) is false)
the ax88179_178a driver won't request transmits that need fragmenting.

There is a separate issue in that it does request receives that need
fragmenting.
However if the fragmented receives end up being split by a LINK TRB
the device driver recovers.
The ax88179 hardware doesn't recover when a tx is split.

David



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Re: BUG: USB Reset-Resume Mechanism does not work for runtime resume

2014-03-07 Thread Alan Stern
On Fri, 7 Mar 2014, Oliver Neukum wrote:

  Are there any wakeup-enabled devices that this will mess up?
 
 Potentially HID. Now that I think about this it seems to me that
 drivers really need to be told about the error condition. For
 btusb the error condition cannot be handled. For HID it may mean
 a lost key or click at the worst. The driver should react to such
 errors by disabling power management, but that requires that it
 become aware of such errors.

The only way to notify the driver about the error condition is by a 
reset-resume callback, and btusb has no such callback.

In the case of a mobile device, it seems to me that unbinding and
rebinding is more suitable than disabling power management.  
Especially if these errors are infrequent.

Of course, unbind followed by rebind is a natural side effect of 
logical disconnect.

Earlier, you objected to rebinding on the grounds that it could lead to 
a tight error loop.  Unbinding without rebinding would be essentially 
the same as what the kernel does now.

Alan Stern

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RE: [PATCH 1/2] Revert xhci 1.0: Limit arbitrarily-aligned scatter gather.

2014-03-07 Thread David Laight
From: Mathias Nyman
 This reverts commit 247bf557273dd775505fb9240d2d152f4f20d304.

You need to revert further.
Just don’t set hcd-self.no_sg_constraint ever - since it just
doesn't work.
That will stop the ax88179_178a driver sending fragmented packets.

With the check for aligned non-terminal fragments removed the 
code will be as bad as the earlier releases.

 This commit, together with commit 3804fad45411b48233b48003e33a78f290d227c8
 USBNET: ax88179_178a: enable tso if usb host supports sg dma were
 origially added to get xHCI 1.0 hosts and usb ethernet ax88179_178a devices
 working together with scatter gather. xHCI 1.0 hosts pose some requirement on 
 how transfer
 buffers are aligned, setting this requirement for 1.0 hosts caused USB 3.0 
 mass
 storage devices to fail more frequently.
 
 USB 3.0 mass storage devices used to work before 3.14-rc1.  Theoretically,
 the TD fragment rules could have caused an occasional disk glitch.
 Now the devices *will* fail, instead of theoretically failing.
 From a user perspective, this looks like a regression; the USB device 
 obviously
 fails on 3.14-rc1, and may sometimes silently fail on prior kernels.
 
 The proper soluition is to implement the TD fragment rules required, but for 
 now
 this patch needs to be reverted to get USB 3.0 mass storage devices working 
 at the
 level they used to.
 
 Signed-off-by: Mathias Nyman mathias.ny...@linux.intel.com
 Cc: stable sta...@vger.kernel.org
 ---
  drivers/usb/host/xhci.c | 14 +++---
  1 file changed, 3 insertions(+), 11 deletions(-)
 
 diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
 index 6fe577d..924a6cc 100644
 --- a/drivers/usb/host/xhci.c
 +++ b/drivers/usb/host/xhci.c
 @@ -4733,6 +4733,9 @@ int xhci_gen_setup(struct usb_hcd *hcd, 
 xhci_get_quirks_t get_quirks)
   /* Accept arbitrarily long scatter-gather lists */
   hcd-self.sg_tablesize = ~0;
 
 + /* support to build packet from discontinuous buffers */
 + hcd-self.no_sg_constraint = 1;
 +

Don't add the above - it only looked at by the usbnet code
and in particular the ax88179_178a driver

   /* XHCI controllers don't stop the ep queue on short packets :| */
   hcd-self.no_stop_on_short = 1;
 
 @@ -4757,14 +4760,6 @@ int xhci_gen_setup(struct usb_hcd *hcd, 
 xhci_get_quirks_t get_quirks)
   /* xHCI private pointer was set in xhci_pci_probe for the second
* registered roothub.
*/
 - xhci = hcd_to_xhci(hcd);
 - /*
 -  * Support arbitrarily aligned sg-list entries on hosts without
 -  * TD fragment rules (which are currently unsupported).
 -  */
 - if (xhci-hci_version  0x100)
 - hcd-self.no_sg_constraint = 1;
 -
   return 0;
   }
 
 @@ -4793,9 +4788,6 @@ int xhci_gen_setup(struct usb_hcd *hcd, 
 xhci_get_quirks_t get_quirks)
   if (xhci-hci_version  0x96)
   xhci-quirks |= XHCI_SPURIOUS_SUCCESS;
 
 - if (xhci-hci_version  0x100)
 - hcd-self.no_sg_constraint = 1;
 -
   /* Make sure the HC is halted. */
   retval = xhci_halt(xhci);
   if (retval)
 --
 1.8.1.2
 
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RE: [PATCH 2/2] Revert USBNET: ax88179_178a: enable tso if usb host supports sg dma

2014-03-07 Thread Alan Stern
On Fri, 7 Mar 2014, David Laight wrote:

 From: Mathias Nyman
  This reverts commit 3804fad45411b48233b48003e33a78f290d227c8.
  
  This commit, together with commit 247bf557273dd775505fb9240d2d152f4f20d304
  xhci 1.0: Limit arbitrarily-aligned scatter gather. were
  origially added to get xHCI 1.0 hosts and usb ethernet ax88179_178a devices
  working together with scatter gather. xHCI 1.0 hosts pose some requirement 
  on how transfer
  buffers are aligned, setting this requirement for 1.0 hosts caused USB 3.0 
  mass
  storage devices to fail more frequently.
 
 This patch doesn't need to be reverted.

Yes, it does.

 Provided the xhci driver doesn't set the flag to say that arbitrary scatter
 gather is supported (ie usb_device_no_sg_constraint(dev-udev)) is false)
 the ax88179_178a driver won't request transmits that need fragmenting.

True.  But xhci-hcd _will_ set the flag, because of patch 1 in this 
series.  In other words, patch 1 makes patch 2 necessary.

Alan Stern

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Re: BUG: USB Reset-Resume Mechanism does not work for runtime resume

2014-03-07 Thread Oliver Neukum
On Fri, 2014-03-07 at 10:14 -0500, Alan Stern wrote:
 On Fri, 7 Mar 2014, Oliver Neukum wrote:
 
   Are there any wakeup-enabled devices that this will mess up?
  
  Potentially HID. Now that I think about this it seems to me that
  drivers really need to be told about the error condition. For
  btusb the error condition cannot be handled. For HID it may mean
  a lost key or click at the worst. The driver should react to such
  errors by disabling power management, but that requires that it
  become aware of such errors.
 
 The only way to notify the driver about the error condition is by a 
 reset-resume callback, and btusb has no such callback.

I wouldn't object to adding reset_resume() provided you add an error
flag and usbcore can deal with a failure.

 In the case of a mobile device, it seems to me that unbinding and
 rebinding is more suitable than disabling power management.  
 Especially if these errors are infrequent.

It breaks opened fds.

 Of course, unbind followed by rebind is a natural side effect of 
 logical disconnect.
 
 Earlier, you objected to rebinding on the grounds that it could lead to 
 a tight error loop.  Unbinding without rebinding would be essentially 
 the same as what the kernel does now.

Yes, I much prefer drivers to be notified.

Regards
Oliver



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RE: [PATCH 1/2] Revert xhci 1.0: Limit arbitrarily-aligned scatter gather.

2014-03-07 Thread Alan Stern
On Fri, 7 Mar 2014, David Laight wrote:

 From: Mathias Nyman
  This reverts commit 247bf557273dd775505fb9240d2d152f4f20d304.
 
 You need to revert further.
 Just don�t set hcd-self.no_sg_constraint ever - since it just
 doesn't work.

No; it does work most of the time.

If hcd-self.no_sg_constraint wasn't sent, then certain commands would 
fail always, instead of failing occasionally.

Alan Stern

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Re: BUG: USB Reset-Resume Mechanism does not work for runtime resume

2014-03-07 Thread Alan Stern
On Fri, 7 Mar 2014, Oliver Neukum wrote:

 On Fri, 2014-03-07 at 10:14 -0500, Alan Stern wrote:
  On Fri, 7 Mar 2014, Oliver Neukum wrote:
  
Are there any wakeup-enabled devices that this will mess up?
   
   Potentially HID. Now that I think about this it seems to me that
   drivers really need to be told about the error condition. For
   btusb the error condition cannot be handled. For HID it may mean
   a lost key or click at the worst. The driver should react to such
   errors by disabling power management, but that requires that it
   become aware of such errors.
  
  The only way to notify the driver about the error condition is by a 
  reset-resume callback, and btusb has no such callback.
 
 I wouldn't object to adding reset_resume() provided you add an error
 flag and usbcore can deal with a failure.

What would you like usbcore to do?  Could btusb's reset-resume callback 
(if such a routine were written) do the same thing?

  In the case of a mobile device, it seems to me that unbinding and
  rebinding is more suitable than disabling power management.  
  Especially if these errors are infrequent.
 
 It breaks opened fds.

Of course.  So does logical disconnect.  And while never resuming the 
class driver doesn't break opened fds, it leaves them unusable, which 
is just as bad.  The only way to avoid blowing away the old connections 
is to have a reset-resume callback -- and even that might not be able 
to do it.

The advantage of not disabling power management is that you don't drain 
the battery.  If the user knows that the bluetooth device's power 
management is unreliable then the user can manually disable runtime 
suspend.

  Of course, unbind followed by rebind is a natural side effect of 
  logical disconnect.
  
  Earlier, you objected to rebinding on the grounds that it could lead to 
  a tight error loop.  Unbinding without rebinding would be essentially 
  the same as what the kernel does now.
 
 Yes, I much prefer drivers to be notified.

Then we need to add a reset-resume callback to btusb.

Alan Stern

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RE: [PATCH 33/76] uas: Pack iu struct definitions

2014-03-07 Thread David Laight
From: Of Sarah Sharp
 From: Hans de Goede hdego...@redhat.com
 
 The iu struct definitions are usb packet definitions, so no alignment should
 happen. Notice that assuming 32 bit alignment this does not make any
 difference at all.
 
 Signed-off-by: Hans de Goede hdego...@redhat.com
 Signed-off-by: Sarah Sharp sarah.a.sh...@linux.intel.com
 ---
  include/linux/usb/uas.h | 10 +-
  1 file changed, 5 insertions(+), 5 deletions(-)
 
 diff --git a/include/linux/usb/uas.h b/include/linux/usb/uas.h
 index 772b66bcdd7d..3fc8e8b9f043 100644
 --- a/include/linux/usb/uas.h
 +++ b/include/linux/usb/uas.h
 @@ -9,7 +9,7 @@ struct iu {
   __u8 iu_id;
   __u8 rsvd1;
   __be16 tag;
 -};
 +} __attribute__((__packed__));

I don't want to block these patches, but the above will make
a difference.

On cpus that don't support misaligned memory transfers the
compiler will have to generate code that does byte accesses
and shifts in order to access 16 and 32 bit members of packed
structures.

So you should really only mark structures as packed if they
will occur on misaligned boundaries.

If a structure has a single field that is misaligned (eg a
64bit field at a 4n+4 offset) then the single field can be
marked with (eg) __attribute__((aligned(4))) that will remove
the padding and only force multiple memory access for that
one member.

David



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RE: [PATCH 2/2] Revert USBNET: ax88179_178a: enable tso if usb host supports sg dma

2014-03-07 Thread David Laight
From: Alan Stern 
 On Fri, 7 Mar 2014, David Laight wrote:
 
  From: Mathias Nyman
   This reverts commit 3804fad45411b48233b48003e33a78f290d227c8.
  
   This commit, together with commit 247bf557273dd775505fb9240d2d152f4f20d304
   xhci 1.0: Limit arbitrarily-aligned scatter gather. were
   origially added to get xHCI 1.0 hosts and usb ethernet ax88179_178a 
   devices
   working together with scatter gather. xHCI 1.0 hosts pose some 
   requirement on how transfer
   buffers are aligned, setting this requirement for 1.0 hosts caused USB 
   3.0 mass
   storage devices to fail more frequently.
 
  This patch doesn't need to be reverted.
 
 Yes, it does.
 
  Provided the xhci driver doesn't set the flag to say that arbitrary scatter
  gather is supported (ie usb_device_no_sg_constraint(dev-udev)) is false)
  the ax88179_178a driver won't request transmits that need fragmenting.
 
 True.  But xhci-hcd _will_ set the flag, because of patch 1 in this
 series.  In other words, patch 1 makes patch 2 necessary.

I was reading patch 2 first.
It would seem to be better to modify patch 1 - so it doesn't set the flag.
Then the changes are limited to the usb tree, and the change to net wouldn't
need to be reapplied in order to test scatter-gather when it is properly fixed.

David



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Re: [PATCH 5/8] phy: omap-usb2: Add clock names to Documentation binding

2014-03-07 Thread Felipe Balbi
On Fri, Mar 07, 2014 at 03:09:08PM +0200, Roger Quadros wrote:
 Add wkupclk and refclk information to DT binding information.
 
 Signed-off-by: Roger Quadros rog...@ti.com
 ---

so, should I take this one ?

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RE: [PATCH 1/2] Revert xhci 1.0: Limit arbitrarily-aligned scatter gather.

2014-03-07 Thread David Laight
From: Alan Stern
 On Fri, 7 Mar 2014, David Laight wrote:
 
  From: Mathias Nyman
   This reverts commit 247bf557273dd775505fb9240d2d152f4f20d304.
 
  You need to revert further.
  Just don?t set hcd-self.no_sg_constraint ever - since it just
  doesn't work.
 
 No; it does work most of the time.
 
 If hcd-self.no_sg_constraint wasn't sent, then certain commands would
 fail always, instead of failing occasionally.

The point is that the no_sg_constraint was added in order to allow
the ax88179_178a driver to send arbitrarily aligned transfers.
Nothing else looks at it (well didn't when I scanned the tree a while back).

In effect all the other transfer requests were assumed to be suitably
aligned.

The check that caused things to fail was the one added to xhci relatively
recently that verified the alignment of the fragments.

David



Re: [PATCH 5/8] phy: omap-usb2: Add clock names to Documentation binding

2014-03-07 Thread Kishon Vijay Abraham I

Felipe,

On Friday 07 March 2014 09:34 PM, Felipe Balbi wrote:

On Fri, Mar 07, 2014 at 03:09:08PM +0200, Roger Quadros wrote:

Add wkupclk and refclk information to DT binding information.

Signed-off-by: Roger Quadros rog...@ti.com
---


so, should I take this one ?


yes.. the ti-phy.txt is only in your tree.

Thanks
Kishon




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Re: [PATCH 5/8] phy: omap-usb2: Add clock names to Documentation binding

2014-03-07 Thread Felipe Balbi
On Fri, Mar 07, 2014 at 09:53:03PM +0530, Kishon Vijay Abraham I wrote:
 Felipe,
 
 On Friday 07 March 2014 09:34 PM, Felipe Balbi wrote:
 On Fri, Mar 07, 2014 at 03:09:08PM +0200, Roger Quadros wrote:
 Add wkupclk and refclk information to DT binding information.
 
 Signed-off-by: Roger Quadros rog...@ti.com
 ---
 
 so, should I take this one ?
 
 yes.. the ti-phy.txt is only in your tree.

yeah, I know that, but I need to know if this is safe to be applied as
in it won't change anymore.

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Re: Renesas RCar device-tree USB series

2014-03-07 Thread Sergei Shtylyov

Hello.

On 03/07/2014 05:30 PM, Ben Dooks wrote:


This is a new series covering enabling the RCar series of SoCs USB
with device-tree based booting. It has been tested on the R8A7790
Lager board.



Improvements from the previous series include:



 - mapping usb to the relevant phy by dt
 - better use of existing pci of functions



Note, there is still an issue with the second gigabyte of memory on
the Lager, which with current kernels causes the system to abort on
startup. This series will only work if the top memory area is disabled.



Thanks for these patches. I think they start looking really good.



In my mind there are two outstanding issues:


[...]


2) Per-port USB PHY driver configuration via DT
Right now each USB host controller points to the same PHY device.
Thanks for working on describing the topology! As you know, the PHY
driver itself handles several USB ports, and I'd like to use DT to
represent the mapping between which PHY port that maps to what USB
Host controller to allow proper run time configuration. Right now in
this version of the series there is no such mapping. Of course, that
depends on proper USB PHY DT bindings...



Hmm, given the shared phy is shared and referenced counted then
I don't /think/ there is much more to be done for this. If we add
more PHYs then I would assume that each one of them would


   It seems you didn't finish the sentence...

WBR, Sergei

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Re: Renesas RCar device-tree USB series

2014-03-07 Thread Ben Dooks

On 07/03/14 17:30, Sergei Shtylyov wrote:

Hello.

On 03/07/2014 05:30 PM, Ben Dooks wrote:


This is a new series covering enabling the RCar series of SoCs USB
with device-tree based booting. It has been tested on the R8A7790
Lager board.



Improvements from the previous series include:



 - mapping usb to the relevant phy by dt
 - better use of existing pci of functions



Note, there is still an issue with the second gigabyte of memory on
the Lager, which with current kernels causes the system to abort on
startup. This series will only work if the top memory area is disabled.



Thanks for these patches. I think they start looking really good.



In my mind there are two outstanding issues:


[...]


2) Per-port USB PHY driver configuration via DT
Right now each USB host controller points to the same PHY device.
Thanks for working on describing the topology! As you know, the PHY
driver itself handles several USB ports, and I'd like to use DT to
represent the mapping between which PHY port that maps to what USB
Host controller to allow proper run time configuration. Right now in
this version of the series there is no such mapping. Of course, that
depends on proper USB PHY DT bindings...



Hmm, given the shared phy is shared and referenced counted then
I don't /think/ there is much more to be done for this. If we add
more PHYs then I would assume that each one of them would


It seems you didn't finish the sentence...


I deleted the last bit by accident.

have their own phy driver instance



WBR, Sergei




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RE: [PATCH 2/2] Revert USBNET: ax88179_178a: enable tso if usb host supports sg dma

2014-03-07 Thread Alan Stern
On Fri, 7 Mar 2014, David Laight wrote:

 From: Alan Stern 
  On Fri, 7 Mar 2014, David Laight wrote:
  
   From: Mathias Nyman
This reverts commit 3804fad45411b48233b48003e33a78f290d227c8.
   
This commit, together with commit 
247bf557273dd775505fb9240d2d152f4f20d304
xhci 1.0: Limit arbitrarily-aligned scatter gather. were
origially added to get xHCI 1.0 hosts and usb ethernet ax88179_178a 
devices
working together with scatter gather. xHCI 1.0 hosts pose some 
requirement on how transfer
buffers are aligned, setting this requirement for 1.0 hosts caused USB 
3.0 mass
storage devices to fail more frequently.
  
   This patch doesn't need to be reverted.
  
  Yes, it does.
  
   Provided the xhci driver doesn't set the flag to say that arbitrary 
   scatter
   gather is supported (ie usb_device_no_sg_constraint(dev-udev)) is false)
   the ax88179_178a driver won't request transmits that need fragmenting.
  
  True.  But xhci-hcd _will_ set the flag, because of patch 1 in this
  series.  In other words, patch 1 makes patch 2 necessary.
 
 I was reading patch 2 first.
 It would seem to be better to modify patch 1 - so it doesn't set the flag.
 Then the changes are limited to the usb tree, and the change to net wouldn't
 need to be reapplied in order to test scatter-gather when it is properly 
 fixed.

 The point is that the no_sg_constraint was added in order to allow
 the ax88179_178a driver to send arbitrarily aligned transfers.
 Nothing else looks at it (well didn't when I scanned the tree a while back).

 In effect all the other transfer requests were assumed to be suitably
 aligned.   

 The check that caused things to fail was the one added to xhci relatively
 recently that verified the alignment of the fragments.

(Actually the check was added to usbcore, not to xhci-hcd.)

The _real_ problem here seems to be that no_sg_constraint is
ambiguous.  Originally it was meant to refer to the constraint that all
SG elements except the last must be a multiple of the maxpacket size.  
For that purpose, the check added to usbcore was entirely appropriate,
as was setting the flag in xhci-hcd.

But now it turns out that the ax88179 driver is violating a _different_
constraint: that Link TRBs must occur only at 1-KB boundaries.  The 
no_sg_constraint flag was never meant to describe this.  In other 
words, the flag issue is separate from the problem facing ax88179.

The appropriate way to address this new problem for the future is to
remove the second constraint by adding correct support for TD
fragments into xhci-hcd.  The appropriate way to address the problem
right now in the -stable kernels is to prevent ax88179 from using SG -- 
and not by abusing the no_sg_constraint flag, which is not directly 
related to the TD fragment problem.

Alan Stern

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Re: [PATCH 1/8] CLK: ti: dra7: Initialize USB_DPLL

2014-03-07 Thread Tony Lindgren
* Tero Kristo t-kri...@ti.com [140307 05:46]:
 On 03/07/2014 03:09 PM, Roger Quadros wrote:
 USB_DPLL must be initialized and locked at boot so that
 USB modules can work.
 
 Also program USB_DLL_M2 output to half rate.
 
 CC: Mike Turquette mturque...@linaro.org
 CC: Tero Kristo t-kri...@ti.com
 Signed-off-by: Roger Quadros rog...@ti.com
 ---
   drivers/clk/ti/clk-7xx.c | 11 +++
   1 file changed, 11 insertions(+)
 
 diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
 index 9977653..f89f3c2 100644
 --- a/drivers/clk/ti/clk-7xx.c
 +++ b/drivers/clk/ti/clk-7xx.c
 @@ -18,6 +18,7 @@
 
   #define DRA7_DPLL_ABE_DEFFREQ  361267200
   #define DRA7_DPLL_GMAC_DEFFREQ 10
 +#define DRA7_DPLL_USB_DEFFREQ   96000
 
 
   static struct ti_dt_clk dra7xx_clks[] = {
 @@ -328,5 +329,15 @@ int __init dra7xx_dt_clk_init(void)
  if (rc)
  pr_err(%s: failed to configure GMAC DPLL!\n, __func__);
 
 +dpll_ck = clk_get_sys(NULL, dpll_usb_ck);
 +rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
 +if (rc)
 +pr_err(%s: failed to configure USB DPLL!\n, __func__);
 +
 +dpll_ck = clk_get_sys(NULL, dpll_usb_m2_ck);
 +rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
 +if (rc)
 +pr_err(%s: failed to set USB_DPLL M2 OUT\n, __func__);
 +
 
 I would rather see this done using the default-rate mechanism provided here:
 
 https://www.mail-archive.com/linux-omap@vger.kernel.org/msg101300.html
 
 However, this remains to be commented by Mike whether the patch is
 okay or not.

Yes let's wait for that and not add hacks for new features.

Regards,

Tony
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[PATCH 1/9] usb: chipidea: usbmisc: Add USB Host support for i.MX25/i.MX35 CPUs

2014-03-07 Thread Denis Carikli
Signed-off-by: Denis Carikli de...@eukrea.com
---
 drivers/usb/chipidea/usbmisc_imx.c |   59 
 1 file changed, 59 insertions(+)

diff --git a/drivers/usb/chipidea/usbmisc_imx.c 
b/drivers/usb/chipidea/usbmisc_imx.c
index cd061ab..d956ad0 100644
--- a/drivers/usb/chipidea/usbmisc_imx.c
+++ b/drivers/usb/chipidea/usbmisc_imx.c
@@ -21,6 +21,26 @@
 #define MX25_USB_PHY_CTRL_OFFSET   0x08
 #define MX25_BM_EXTERNAL_VBUS_DIVIDER  BIT(23)
 
+#define MXC_EHCI_INTERFACE_SINGLE_UNI  (2  0)
+#define MXC_EHCI_INTERFACE_DIFF_UNI(0  0)
+#define MXC_EHCI_INTERFACE_MASK(0xf)
+
+#define MX25_OTG_SIC_SHIFT 29
+#define MX25_OTG_SIC_MASK  (0x3  MX25_OTG_SIC_SHIFT)
+#define MX25_OTG_PM_BITBIT(24)
+#define MX25_OTG_PP_BITBIT(11)
+#define MX25_OTG_OCPOL_BIT (1  3)
+
+#define MX25_H1_SIC_SHIFT  21
+#define MX25_H1_SIC_MASK   (0x3  MX25_H1_SIC_SHIFT)
+#define MX25_H1_PP_BIT BIT(18)
+#define MX25_H1_PM_BIT BIT(16)
+#define MX25_H1_IPPUE_UP_BIT   BIT(7)
+#define MX25_H1_IPPUE_DOWN_BIT BIT(6)
+#define MX25_H1_TLL_BITBIT(5)
+#define MX25_H1_USBTE_BIT  BIT(4)
+#define MX25_H1_OCPOL_BIT  (1  2)
+
 #define MX27_H1_PM_BIT BIT(8)
 #define MX27_H2_PM_BIT BIT(16)
 #define MX27_OTG_PM_BITBIT(24)
@@ -50,6 +70,40 @@ struct imx_usbmisc {
 
 static struct imx_usbmisc *usbmisc;
 
+static int usbmisc_imx25_init(struct imx_usbmisc_data *data)
+{
+   void __iomem *reg = NULL;
+   unsigned long flags;
+   u32 val = 0;
+
+   if (data-index  1)
+   return -EINVAL;
+
+   spin_lock_irqsave(usbmisc-lock, flags);
+   switch (data-index) {
+   case 0:
+   val = readl(usbmisc-base);
+   val = ~(MX25_OTG_SIC_MASK | MX25_OTG_PP_BIT);
+   val |= (MXC_EHCI_INTERFACE_DIFF_UNI  MXC_EHCI_INTERFACE_MASK) 
 MX25_OTG_SIC_SHIFT;
+   val |= (MX25_OTG_PM_BIT | MX25_OTG_OCPOL_BIT);
+   writel(val, usbmisc-base);
+   break;
+   case 1:
+   val = readl(usbmisc-base);
+   val = ~(MX25_H1_SIC_MASK | MX25_H1_PP_BIT |  
MX25_H1_IPPUE_UP_BIT);
+   val |= (MXC_EHCI_INTERFACE_SINGLE_UNI  
MXC_EHCI_INTERFACE_MASK)  MX25_H1_SIC_SHIFT;
+   val |= (MX25_H1_PM_BIT | MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
+   MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT);
+
+   writel(val, usbmisc-base);
+
+   break;
+   }
+   spin_unlock_irqrestore(usbmisc-lock, flags);
+
+   return 0;
+}
+
 static int usbmisc_imx25_post(struct imx_usbmisc_data *data)
 {
void __iomem *reg;
@@ -159,6 +213,7 @@ static int usbmisc_imx6q_init(struct imx_usbmisc_data *data)
 }
 
 static const struct usbmisc_ops imx25_usbmisc_ops = {
+   .init = usbmisc_imx25_init,
.post = usbmisc_imx25_post,
 };
 
@@ -200,6 +255,10 @@ static const struct of_device_id usbmisc_imx_dt_ids[] = {
.data = imx25_usbmisc_ops,
},
{
+   .compatible = fsl,imx35-usbmisc,
+   .data = imx25_usbmisc_ops,
+   },
+   {
.compatible = fsl,imx27-usbmisc,
.data = imx27_usbmisc_ops,
},
-- 
1.7.9.5

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[PATCH 3/9] ARM: dts: mbimxsd51 baseboard: Add USB host support

2014-03-07 Thread Denis Carikli
Signed-off-by: Denis Carikli de...@eukrea.com
---
 .../boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts  |   47 
 1 file changed, 47 insertions(+)

diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts 
b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
index 5cec4f3..4d970b3 100644
--- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
+++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
@@ -151,6 +151,29 @@
MX51_PAD_CSI1_D9__GPIO3_13 0x1f5
;
};
+
+   pinctrl_usbh1: usbh1grp {
+   fsl,pins = 
+   MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
+   MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
+   MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
+   MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
+   MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
+   MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
+   MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
+   MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
+   MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
+   MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
+   MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
+   MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
+   ;
+   };
+
+   pinctrl_usbh1_vbus: usbh1-vbusgrp {
+   fsl,pins = 
+   MX51_PAD_EIM_CS3__GPIO2_28 0x1f5
+   ;
+   };
};
 };
 
@@ -173,3 +196,27 @@
fsl,uart-has-rtscts;
status = okay;
 };
+
+usbh1 {
+   pinctrl-names = default;
+   pinctrl-0 = pinctrl_usbh1;
+   phy_type = ulpi;
+   dr_mode = host;
+   status = okay;
+};
+
+usbotg {
+   phy_type = utmi_wide;
+   dr_mode = host;
+   status = okay;
+};
+
+usbphy0 {
+   pinctrl-names = default;
+   pinctrl-0 = pinctrl_usbh1_vbus;
+   reset-gpios = gpio2 28 GPIO_ACTIVE_LOW;
+};
+
+usbphy1 {
+   clock-frequency = 1920;
+};
-- 
1.7.9.5

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[PATCH 2/9] ARM: dts: i.MX51: Add a second usbphy.

2014-03-07 Thread Denis Carikli
Signed-off-by: Denis Carikli de...@eukrea.com
---
 arch/arm/boot/dts/imx51.dtsi |8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index e508e6f..917b6ed 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -100,6 +100,13 @@
clocks = clks IMX5_CLK_USB_PHY_GATE;
clock-names = main_clk;
};
+
+   usbphy1: usbphy@1 {
+   compatible = usb-nop-xceiv;
+   reg = 1;
+   clocks = clks IMX5_CLK_USB_PHY_GATE;
+   clock-names = main_clk;
+   };
};
 
soc {
@@ -239,6 +246,7 @@
interrupts = 14;
clocks = clks IMX5_CLK_USBOH3_GATE;
fsl,usbmisc = usbmisc 1;
+   fsl,usbphy = usbphy1;
status = disabled;
};
 
-- 
1.7.9.5

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[PATCH 4/9] ARM: dts: imx25.dtsi: Fix USB support.

2014-03-07 Thread Denis Carikli
From: Fabio Estevam fabio.este...@freescale.com

This patch was adapted from the thread named
USB Host support for mx25 on linux-usb@vger.kernel.org

Signed-off-by: Denis Carikli de...@eukrea.com
---
 arch/arm/boot/dts/imx25.dtsi |9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 77bb743..ab5c282 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -483,13 +483,11 @@
};
 
usbphy1: usbphy@1 {
-   compatible = nop-usbphy;
-   status = disabled;
+   compatible = usb-nop-xceiv;
};
 
usbphy2: usbphy@2 {
-   compatible = nop-usbphy;
-   status = disabled;
+   compatible = usb-nop-xceiv;
};
 
usbotg: usb@53ff4000 {
@@ -499,6 +497,7 @@
clocks = clks 9, clks 70, clks 8;
clock-names = ipg, ahb, per;
fsl,usbmisc = usbmisc 0;
+   fsl,usbphy = usbphy1;
status = disabled;
};
 
@@ -509,6 +508,7 @@
clocks = clks 9, clks 70, clks 8;
clock-names = ipg, ahb, per;
fsl,usbmisc = usbmisc 1;
+   fsl,usbphy = usbphy2;
status = disabled;
};
 
@@ -518,7 +518,6 @@
clocks = clks 9, clks 70, clks 8;
clock-names = ipg, ahb, per;
reg = 0x53ff4600 0x00f;
-   status = disabled;
};
 
dryice@53ffc000 {
-- 
1.7.9.5

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[PATCH 5/9] ARM: dts: mbimxsd25 baseboard: Add USB host support

2014-03-07 Thread Denis Carikli
Signed-off-by: Denis Carikli de...@eukrea.com
---
 .../boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts  |   13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts 
b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
index 62fb3da..58c606f 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -172,3 +172,16 @@
fsl,uart-has-rtscts;
status = okay;
 };
+
+usbhost1 {
+   phy_type = serial;
+   dr_mode = host;
+   status = okay;
+};
+
+usbotg {
+   phy_type = utmi;
+   dr_mode = host;
+   external-vbus-divider;
+   status = okay;
+};
-- 
1.7.9.5

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[PATCH 6/9] ARM: dts: i.MX35: Add USB support.

2014-03-07 Thread Denis Carikli
Signed-off-by: Denis Carikli de...@eukrea.com
---
 arch/arm/boot/dts/imx35.dtsi |   11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index e59ccb4..1c15b56 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -292,6 +292,15 @@
status = disabled;
};
 
+   usbphy0: usbphy@0 {
+   compatible = usb-nop-xceiv;
+   };
+
+   usbphy1: usbphy@1 {
+   compatible = usb-nop-xceiv;
+   };
+
+
usbotg: usb@53ff4000 {
compatible = fsl,imx35-usb, fsl,imx27-usb;
reg = 0x53ff4000 0x0200;
@@ -299,6 +308,7 @@
clocks = clks 9, clks 73, clks 28;
clock-names = ipg, ahb, per;
fsl,usbmisc = usbmisc 0;
+   fsl,usbphy = usbphy0;
status = disabled;
};
 
@@ -309,6 +319,7 @@
clocks = clks 9, clks 73, clks 28;
clock-names = ipg, ahb, per;
fsl,usbmisc = usbmisc 1;
+   fsl,usbphy = usbphy1;
status = disabled;
};
 
-- 
1.7.9.5

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[PATCH 7/9] ARM: dts: mbimxsd35 baseboard: Add USB host support.

2014-03-07 Thread Denis Carikli
Signed-off-by: Denis Carikli de...@eukrea.com
---
 .../boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts  |   12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts 
b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
index 71197b9..d27f02e 100644
--- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
+++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
@@ -150,3 +150,15 @@
fsl,uart-has-rtscts;
status = okay;
 };
+
+usbhost1 {
+   phy_type = serial;
+   status = okay;
+};
+
+usbotg {
+   phy_type = utmi;
+   dr_mode = host;
+   external-vbus-divider;
+   status = okay;
+};
-- 
1.7.9.5

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[PATCH 8/9] ARM: imx_v6_v7_defconfig: Enable drivers for i.MX51 USB Host support.

2014-03-07 Thread Denis Carikli
Signed-off-by: Denis Carikli de...@eukrea.com
---
 arch/arm/configs/imx_v6_v7_defconfig |2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/imx_v6_v7_defconfig 
b/arch/arm/configs/imx_v6_v7_defconfig
index 09e9743..772f14f 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -209,8 +209,10 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_CHIPIDEA=y
 CONFIG_USB_CHIPIDEA_UDC=y
 CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_OTG_FSM=y
 CONFIG_NOP_USB_XCEIV=y
 CONFIG_USB_MXS_PHY=y
+CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_ETH=m
 CONFIG_USB_MASS_STORAGE=m
-- 
1.7.9.5

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RE: [PATCH 2/2] Revert USBNET: ax88179_178a: enable tso if usb host supports sg dma

2014-03-07 Thread David Laight
From: 
 On Fri, 7 Mar 2014, David Laight wrote:
 
  From: Alan Stern
   On Fri, 7 Mar 2014, David Laight wrote:
  
From: Mathias Nyman
 This reverts commit 3804fad45411b48233b48003e33a78f290d227c8.

 This commit, together with commit 
 247bf557273dd775505fb9240d2d152f4f20d304
 xhci 1.0: Limit arbitrarily-aligned scatter gather. were
 origially added to get xHCI 1.0 hosts and usb ethernet ax88179_178a 
 devices
 working together with scatter gather. xHCI 1.0 hosts pose some 
 requirement on how transfer
 buffers are aligned, setting this requirement for 1.0 hosts caused 
 USB 3.0 mass
 storage devices to fail more frequently.
   
This patch doesn't need to be reverted.
  
   Yes, it does.
  
Provided the xhci driver doesn't set the flag to say that arbitrary 
scatter
gather is supported (ie usb_device_no_sg_constraint(dev-udev)) is 
false)
the ax88179_178a driver won't request transmits that need fragmenting.
  
   True.  But xhci-hcd _will_ set the flag, because of patch 1 in this
   series.  In other words, patch 1 makes patch 2 necessary.
 
  I was reading patch 2 first.
  It would seem to be better to modify patch 1 - so it doesn't set the flag.
  Then the changes are limited to the usb tree, and the change to net wouldn't
  need to be reapplied in order to test scatter-gather when it is properly 
  fixed.
 
  The point is that the no_sg_constraint was added in order to allow
  the ax88179_178a driver to send arbitrarily aligned transfers.
  Nothing else looks at it (well didn't when I scanned the tree a while back).
 
  In effect all the other transfer requests were assumed to be suitably
  aligned.
 
  The check that caused things to fail was the one added to xhci relatively
  recently that verified the alignment of the fragments.
 
 (Actually the check was added to usbcore, not to xhci-hcd.)
 
 The _real_ problem here seems to be that no_sg_constraint is
 ambiguous.  Originally it was meant to refer to the constraint that all
 SG elements except the last must be a multiple of the maxpacket size.
 For that purpose, the check added to usbcore was entirely appropriate,
 as was setting the flag in xhci-hcd.

Probably true - but the only code that looked at it was in usbnet.
The check in usbcore is very recent.

 But now it turns out that the ax88179 driver is violating a _different_
 constraint: that Link TRBs must occur only at 1-KB boundaries.  The
 no_sg_constraint flag was never meant to describe this.  In other
 words, the flag issue is separate from the problem facing ax88179.

Really that means that the xhci controller couldn't actually support the
alignments it said it could - rather than the ax88179 driver sending
packets that didn't meet that the rules.

 The appropriate way to address this new problem for the future is to
 remove the second constraint by adding correct support for TD
 fragments into xhci-hcd.

Indeed.

 The appropriate way to address the problem
 right now in the -stable kernels is to prevent ax88179 from using SG --
 and not by abusing the no_sg_constraint flag, which is not directly
 related to the TD fragment problem.

I'd say that if the no_sg_constraint flag is set the ax88179 driver
could reasonably expect to send its fragment lists.

So it is best not to set the no_sg_constraint flag, and then remove
the checks against it that are needed to allow the transfers from
the disk system not be rejected - even though we know that some
of them might not actually work.

Otherwise you'll need to add yet another flag when the sg support
is fixed.

David



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Re: [PATCH 1/9] usb: chipidea: usbmisc: Add USB Host support for i.MX25/i.MX35 CPUs

2014-03-07 Thread Sergei Shtylyov

Hello.

On 03/07/2014 08:04 PM, Denis Carikli wrote:


Signed-off-by: Denis Carikli de...@eukrea.com
---
  drivers/usb/chipidea/usbmisc_imx.c |   59 
  1 file changed, 59 insertions(+)



diff --git a/drivers/usb/chipidea/usbmisc_imx.c 
b/drivers/usb/chipidea/usbmisc_imx.c
index cd061ab..d956ad0 100644
--- a/drivers/usb/chipidea/usbmisc_imx.c
+++ b/drivers/usb/chipidea/usbmisc_imx.c
@@ -21,6 +21,26 @@
  #define MX25_USB_PHY_CTRL_OFFSET  0x08
  #define MX25_BM_EXTERNAL_VBUS_DIVIDER BIT(23)

+#define MXC_EHCI_INTERFACE_SINGLE_UNI  (2  0)
+#define MXC_EHCI_INTERFACE_DIFF_UNI(0  0)
+#define MXC_EHCI_INTERFACE_MASK(0xf)
+
+#define MX25_OTG_SIC_SHIFT 29
+#define MX25_OTG_SIC_MASK  (0x3  MX25_OTG_SIC_SHIFT)
+#define MX25_OTG_PM_BITBIT(24)
+#define MX25_OTG_PP_BITBIT(11)
+#define MX25_OTG_OCPOL_BIT (1  3)


   Hm, why not BIT(3). Though frankly speaking, I don't think (x  n) macros 
go together well with BIT() ones.



+
+#define MX25_H1_SIC_SHIFT  21
+#define MX25_H1_SIC_MASK   (0x3  MX25_H1_SIC_SHIFT)
+#define MX25_H1_PP_BIT BIT(18)
+#define MX25_H1_PM_BIT BIT(16)
+#define MX25_H1_IPPUE_UP_BIT   BIT(7)
+#define MX25_H1_IPPUE_DOWN_BIT BIT(6)
+#define MX25_H1_TLL_BITBIT(5)
+#define MX25_H1_USBTE_BIT  BIT(4)
+#define MX25_H1_OCPOL_BIT  (1  2)


   BIT(2)?

WBR, Sergei

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Re: [PATCH 33/76] uas: Pack iu struct definitions

2014-03-07 Thread Hans de Goede
Hi,

On 03/07/2014 04:41 PM, David Laight wrote:
 From: Of Sarah Sharp
 From: Hans de Goede hdego...@redhat.com

 The iu struct definitions are usb packet definitions, so no alignment should
 happen. Notice that assuming 32 bit alignment this does not make any
 difference at all.

 Signed-off-by: Hans de Goede hdego...@redhat.com
 Signed-off-by: Sarah Sharp sarah.a.sh...@linux.intel.com
 ---
  include/linux/usb/uas.h | 10 +-
  1 file changed, 5 insertions(+), 5 deletions(-)

 diff --git a/include/linux/usb/uas.h b/include/linux/usb/uas.h
 index 772b66bcdd7d..3fc8e8b9f043 100644
 --- a/include/linux/usb/uas.h
 +++ b/include/linux/usb/uas.h
 @@ -9,7 +9,7 @@ struct iu {
  __u8 iu_id;
  __u8 rsvd1;
  __be16 tag;
 -};
 +} __attribute__((__packed__));
 
 I don't want to block these patches, but the above will make
 a difference.
 
 On cpus that don't support misaligned memory transfers the
 compiler will have to generate code that does byte accesses
 and shifts in order to access 16 and 32 bit members of packed
 structures.
 
 So you should really only mark structures as packed if they
 will occur on misaligned boundaries.

This is not about alignment, this is about holes in the
structure not being allowed, as it represents on the wire data
which has no holes in it.

Since we cannot know in advance what the alignment rules for
members inside structures on new archs will be, the only
way to ensure this is to pack the struct.

Note that *ALL* usb device drivers do the same.

Regards,

Hans
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Re: Bug#738113: linux-image-3.12-1-amd64: regression in xhci_hcd: USB3 doesn't work anymore

2014-03-07 Thread Sarah Sharp
On Tue, Feb 11, 2014 at 06:11:09PM +0100, Andreas Cadhalpun wrote:
 Hi,
 
 thanks for looking into the issue.

 On 11.02.2014 17:40, Sarah Sharp wrote:
 On Sat, Feb 08, 2014 at 03:56:31AM +, Ben Hutchings wrote:
 For the benefit of other developers, that change is a revert of commit
 459d3c146117 ('usb: xhci: Link TRB must not occur within a USB payload
 burst') plus this effective revert of commit fc76051c453b ('USB: XHCI:
 mark no_sg_constraint'):
 
 I hope that's unrelated.  I was effectively going to do the same thing
 upstream (except allow the no_sg_constraint to be set on 0.96 and
 earlier hosts).
 
 I don't know what else changed from 3.12.8-1 to 3.12.9-1, but this
 was the only point in the changelog mentioning xhci.

Alan and I concluded that the cause of this issue is clearing the
no_sg_constraint flag for 1.0 xHCI hosts.  The patches to revert the
commits that caused the issues are on their way to the USB subsystem
maintainer (Greg):

http://marc.info/?l=linux-kernelm=139420433008427w=2
http://marc.info/?l=linux-kernelm=139420429908418w=2
http://marc.info/?l=linux-kernelm=139420432208425w=2

The second commit is needed, since once we allow arbitrarily-aligned
scatter-gather, the ASIX driver will use it, which causes the USB to
ethernet adapter to drop packets occasionally.

So we're basically back where we started before 3.12.  Scatter-gather
isn't supported on the ASIX driver, and mass storage scatter-gather
works fine.  We'll fix the ethernet driver case in 3.16 once we
implement TD fragments.

Sarah Sharp

 
 What does `sudo lspci` show as the manufacturer of your host controller?
 
 The host controller is:
 00:14.0 USB controller [0c03]: Intel Corporation 8 Series/C220 Series
 Chipset Family USB xHCI [8086:8c31] (rev 05) (prog-if 30 [XHCI])
   Subsystem: Lenovo Device [17aa:3978]
   Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
 Stepping- SERR- FastB2B- DisINTx+
   Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium TAbort-
 TAbort- MAbort- SERR- PERR- INTx-
   Latency: 0
   Interrupt: pin A routed to IRQ 46
   Region 0: Memory at b570 (64-bit, non-prefetchable) [size=64K]
   Capabilities: access denied
   Kernel driver in use: xhci_hcd
 
 More information about my setup (including this) can be found in the
 original bug report:
 http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=738113
 
 Have you also tried reverting commit
 9df89d85b407690afa46ddfbccc80bec6869971d usbcore: set lpm_capable field
 for LPM capable root hubs?  It enables USB 3.0 Link PM for non-Intel
 host controllers, which is not what I intended, and could cause issues
 with other host controllers.  A patch to revert that was sent to Greg
 last week, but it looks like it hasn't gotten into Linus' tree yet.
 
 Not sure if that would help, as I have an Intel host controller.
 
 Best regards,
 Andreas
 
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Re: [PATCH 33/76] uas: Pack iu struct definitions

2014-03-07 Thread Alan Stern
On Fri, 7 Mar 2014, Hans de Goede wrote:

  diff --git a/include/linux/usb/uas.h b/include/linux/usb/uas.h
  index 772b66bcdd7d..3fc8e8b9f043 100644
  --- a/include/linux/usb/uas.h
  +++ b/include/linux/usb/uas.h
  @@ -9,7 +9,7 @@ struct iu {
 __u8 iu_id;
 __u8 rsvd1;
 __be16 tag;
  -};
  +} __attribute__((__packed__));
  
  I don't want to block these patches, but the above will make
  a difference.
  
  On cpus that don't support misaligned memory transfers the
  compiler will have to generate code that does byte accesses
  and shifts in order to access 16 and 32 bit members of packed
  structures.
  
  So you should really only mark structures as packed if they
  will occur on misaligned boundaries.
 
 This is not about alignment, this is about holes in the
 structure not being allowed, as it represents on the wire data
 which has no holes in it.
 
 Since we cannot know in advance what the alignment rules for
 members inside structures on new archs will be, the only
 way to ensure this is to pack the struct.

Is that really true?  I mean, does it seem at all reasonable that _any_ 
architecture in the future will align __u8 values on something stricter 
than byte boundaries?  Or __be16 values on something other than 2-byte 
boundaries?

There's a second aspect to this: Can we ever have an instance of this
structure starting at a non-aligned address?  For instances that are
created in memory, the answer is No.  But for instances that are
embedded in data received in a USB packet, the answer is Yes -- at
least, in principle.  (Maybe in practice some particular structures
such as usb_ctrlrequest only ever occur at the start of a packet and so
are properly aligned, but I wouldn't want to depend on this.)

 Note that *ALL* usb device drivers do the same.

That doesn't mean they are necessarily right...

Alan Stern

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Re: [PATCH v10 1/4] phy: core: Add an exported of_phy_get function

2014-03-07 Thread Tobias Jakobi
Kamil Debski wrote:
 Previously the of_phy_get function took a struct device * and
 was declared static. It was impossible to call it from
 another driver and thus it was impossible to get phy defined
 for a given node. The old function was renamed to _of_phy_get
 and was left for internal use. of_phy_get function was added
 and it was exported. The function enables to get a phy for
 a given device tree node.

 Signed-off-by: Kamil Debski k.deb...@samsung.com
 ---
  drivers/phy/phy-core.c  |   45 -
  include/linux/phy/phy.h |6 ++
  2 files changed, 42 insertions(+), 9 deletions(-)

Tested-by: Tobias Jakobi tjak...@math.uni-bielefeld.de

USB PHY was tested on an ODROID-X2 (Exynos4412 SoC) with patches from
Kamil's previous patchset to enable the usage of the new PHY in EHCI and
OCHI.

With best wishes,
Tobias

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Re: [PATCH v10 3/4] phy: Add new Exynos USB 2.0 PHY driver

2014-03-07 Thread Tobias Jakobi
Kamil Debski wrote:
 Add a new driver for the Exynos USB 2.0 PHY. The new driver uses the generic
 PHY framework. The driver includes support for the Exynos 4x10 and 4x12
 SoC families.

 Signed-off-by: Kamil Debski k.deb...@samsung.com
 ---
  .../devicetree/bindings/phy/samsung-phy.txt|   53 
  Documentation/phy/samsung-usb2.txt |  135 
  drivers/phy/Kconfig|   29 ++
  drivers/phy/Makefile   |3 +
  drivers/phy/phy-exynos4210-usb2.c  |  261 
  drivers/phy/phy-exynos4x12-usb2.c  |  328 
 
  drivers/phy/phy-samsung-usb2.c |  222 +
  drivers/phy/phy-samsung-usb2.h |   66 
  8 files changed, 1097 insertions(+)
  create mode 100644 Documentation/phy/samsung-usb2.txt
  create mode 100644 drivers/phy/phy-exynos4210-usb2.c
  create mode 100644 drivers/phy/phy-exynos4x12-usb2.c
  create mode 100644 drivers/phy/phy-samsung-usb2.c
  create mode 100644 drivers/phy/phy-samsung-usb2.h

Tested-by: Tobias Jakobi tjak...@math.uni-bielefeld.de

USB PHY was tested on an ODROID-X2 (Exynos4412 SoC) with patches from
Kamil's previous patchset to enable the usage of the new PHY in EHCI and
OCHI.

With best wishes,
Tobias

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Re: [PATCH v10 2/4] phy: core: Add devm_of_phy_get to phy-core

2014-03-07 Thread Tobias Jakobi
Kamil Debski wrote:
 Adding devm_of_phy_get will allow to get phys by supplying a
 pointer to the struct device_node instead of struct device.

 Signed-off-by: Kamil Debski k.deb...@samsung.com
 ---
  drivers/phy/phy-core.c  |   31 +++
  include/linux/phy/phy.h |8 
  2 files changed, 39 insertions(+)
Tested-by: Tobias Jakobi tjak...@math.uni-bielefeld.de

USB PHY was tested on an ODROID-X2 (Exynos4412 SoC) with patches from
Kamil's previous patchset to enable the usage of the new PHY in EHCI and
OCHI.

With best wishes,
Tobias

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Re: [PATCH v10 4/4] phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driver

2014-03-07 Thread Tobias Jakobi
Kamil Debski wrote:
 Add support for Exynos 5250. This driver is to replace the old
 USB 2.0 PHY driver.

 Signed-off-by: Kamil Debski k.deb...@samsung.com
 ---
  .../devicetree/bindings/phy/samsung-phy.txt|1 +
  drivers/phy/Kconfig|   11 +
  drivers/phy/Makefile   |1 +
  drivers/phy/phy-exynos5250-usb2.c  |  404 
 
  drivers/phy/phy-samsung-usb2.c |6 +
  drivers/phy/phy-samsung-usb2.h |1 +
  6 files changed, 424 insertions(+)
  create mode 100644 drivers/phy/phy-exynos5250-usb2.c

Tested-by: Tobias Jakobi tjak...@math.uni-bielefeld.de

USB PHY was tested on an ODROID-X2 (Exynos4412 SoC) with patches from
Kamil's previous patchset to enable the usage of the new PHY in EHCI and
OCHI.

With best wishes,
Tobias

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Re: [PATCH 2/3] usb: wusbcore: combine iso transfer result frame reads when possible

2014-03-07 Thread Greg KH
On Thu, Mar 06, 2014 at 12:53:38PM -0600, Thomas Pugliese wrote:
 When reading the transfer result data for an isochronous in request, if 
 the current frame actual_length is contiguous with the next frame and 
 actual_length is a multiple of the DTI endpoint max packet size, combine 
 the current frame with the next frame in a single URB.  This reduces the 
 number of URBs that must be submitted in that case which increases 
 performance and reduces CPU interrupt overhead.
 
 Signed-off-by: Thomas Pugliese thomas.pugli...@gmail.com
 ---
  drivers/usb/wusbcore/wa-xfer.c | 104 
 +
  1 file changed, 75 insertions(+), 29 deletions(-)

This patch fails to apply to my tree:

checking file drivers/usb/wusbcore/wa-xfer.c
Hunk #5 FAILED at 2593.
1 out of 7 hunks FAILED


So I've stopped here in applying this series.  Can you please fix this
up and resend?

thanks,

greg k-h
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Re: [GIT PULL] xhci: Streams and UAS cleanups, misc cleanups for 3.15

2014-03-07 Thread Greg Kroah-Hartman
On Thu, Mar 06, 2014 at 04:07:03PM -0800, Sarah Sharp wrote:
 The following changes since commit 3c1b2c3ecd3122fe6dded7b012f74021144d95b2:
 
   USB: sisusb: Use static const, fix typo (2014-03-03 08:54:30 -0800)
 
 are available in the git repository at:
 
   git://git.kernel.org/pub/scm/linux/kernel/git/sarah/xhci.git 
 tags/for-usb-next-2014-03-06

Pulled and pushed out, thanks.

greg k-h
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Re: [PATCH 2/3] usb: wusbcore: combine iso transfer result frame reads when possible

2014-03-07 Thread Thomas Pugliese


On Fri, 7 Mar 2014, Greg KH wrote:

 On Thu, Mar 06, 2014 at 12:53:38PM -0600, Thomas Pugliese wrote:
  When reading the transfer result data for an isochronous in request, if 
  the current frame actual_length is contiguous with the next frame and 
  actual_length is a multiple of the DTI endpoint max packet size, combine 
  the current frame with the next frame in a single URB.  This reduces the 
  number of URBs that must be submitted in that case which increases 
  performance and reduces CPU interrupt overhead.
  
  Signed-off-by: Thomas Pugliese thomas.pugli...@gmail.com
  ---
   drivers/usb/wusbcore/wa-xfer.c | 104 
  +
   1 file changed, 75 insertions(+), 29 deletions(-)
 
 This patch fails to apply to my tree:
 
 checking file drivers/usb/wusbcore/wa-xfer.c
 Hunk #5 FAILED at 2593.
 1 out of 7 hunks FAILED
 
 
 So I've stopped here in applying this series.  Can you please fix this
 up and resend?
 
 thanks,
 
 greg k-h
 

Looks like a one line comment change that I forgot to pull in messed up 
the diff context.  I'll resend the last two patches re-diffed correctly.

Thomas
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Re: [PATCH net-next 0/7] r8152: tx/rx improvement

2014-03-07 Thread David Miller
From: Hayes Wang hayesw...@realtek.com
Date: Fri, 7 Mar 2014 11:04:33 +0800

  - Select the suitable spin lock for each function.
  - Add additional check to reduce the spin lock.
  - Up the priority of the tx to avoid interrupted by rx.
  - Support rx checksum, large send, and IPv6 hw checksum.

Series applied, thanks.

Note that if you ever add -ndo_poll_controller support to this driver,
you will have to revert your spin_lock_irq{save,restore}() changes to
your -ndo_start_xmit.

Because the transmit function can indeed be invoked from hard IRQ
context once you support netpoll.
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[PATCH v2 0/2] usb: wusbcore: HWA performance optimizations

2014-03-07 Thread Thomas Pugliese
This is a resend of two previously sent patches that failed to apply

This series includes a set of performance optimizations for the HWA 
which improve webcam image quality and CPU utilization for isochronous 
read transfers.

Thomas Pugliese (2):
  usb: wusbcore: combine iso transfer result frame reads when possible
  usb: wusbcore: use multiple urbs for HWA iso transfer result frame reads

 drivers/usb/wusbcore/wa-hc.c   |   2 -
 drivers/usb/wusbcore/wa-hc.h   |  15 ++-
 drivers/usb/wusbcore/wa-xfer.c | 275 -
 3 files changed, 199 insertions(+), 93 deletions(-)

-- 
1.8.3.2

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[PATCH v2 2/2] usb: wusbcore: use multiple urbs for HWA iso transfer result frame reads

2014-03-07 Thread Thomas Pugliese
Submit multiple concurrent urbs for HWA isochronous transfer result data 
frame reads.  This keeps the read pipeline full and significantly 
improves performance in cases where the frame reads cannot be combined 
because they are not contiguous or multiples of the max packet size.

Signed-off-by: Thomas Pugliese thomas.pugli...@gmail.com
---
 drivers/usb/wusbcore/wa-hc.c   |   2 -
 drivers/usb/wusbcore/wa-hc.h   |  15 +++-
 drivers/usb/wusbcore/wa-xfer.c | 191 ++---
 3 files changed, 134 insertions(+), 74 deletions(-)

diff --git a/drivers/usb/wusbcore/wa-hc.c b/drivers/usb/wusbcore/wa-hc.c
index 368360f..252c7bd 100644
--- a/drivers/usb/wusbcore/wa-hc.c
+++ b/drivers/usb/wusbcore/wa-hc.c
@@ -75,8 +75,6 @@ void __wa_destroy(struct wahc *wa)
if (wa-dti_urb) {
usb_kill_urb(wa-dti_urb);
usb_put_urb(wa-dti_urb);
-   usb_kill_urb(wa-buf_in_urb);
-   usb_put_urb(wa-buf_in_urb);
}
kfree(wa-dti_buf);
wa_nep_destroy(wa);
diff --git a/drivers/usb/wusbcore/wa-hc.h b/drivers/usb/wusbcore/wa-hc.h
index 7510960..f2a8d29 100644
--- a/drivers/usb/wusbcore/wa-hc.h
+++ b/drivers/usb/wusbcore/wa-hc.h
@@ -125,7 +125,8 @@ struct wa_rpipe {
 
 enum wa_dti_state {
WA_DTI_TRANSFER_RESULT_PENDING,
-   WA_DTI_ISOC_PACKET_STATUS_PENDING
+   WA_DTI_ISOC_PACKET_STATUS_PENDING,
+   WA_DTI_BUF_IN_DATA_PENDING
 };
 
 enum wa_quirks {
@@ -146,6 +147,8 @@ enum wa_vendor_specific_requests {
WA_REQ_ALEREON_FEATURE_SET = 0x01,
WA_REQ_ALEREON_FEATURE_CLEAR = 0x00,
 };
+
+#define WA_MAX_BUF_IN_URBS 4
 /**
  * Instance of a HWA Host Controller
  *
@@ -216,7 +219,9 @@ struct wahc {
u32 dti_isoc_xfer_in_progress;
u8  dti_isoc_xfer_seg;
struct urb *dti_urb;/* URB for reading xfer results */
-   struct urb *buf_in_urb; /* URB for reading data in */
+   /* URBs for reading data in */
+   struct urb buf_in_urbs[WA_MAX_BUF_IN_URBS];
+   int active_buf_in_urbs; /* number of buf_in_urbs active. */
struct edc dti_edc; /* DTI error density counter */
void *dti_buf;
size_t dti_buf_size;
@@ -286,6 +291,8 @@ static inline void wa_rpipe_init(struct wahc *wa)
 
 static inline void wa_init(struct wahc *wa)
 {
+   int index;
+
edc_init(wa-nep_edc);
atomic_set(wa-notifs_queued, 0);
wa-dti_state = WA_DTI_TRANSFER_RESULT_PENDING;
@@ -299,6 +306,10 @@ static inline void wa_init(struct wahc *wa)
INIT_WORK(wa-xfer_error_work, wa_process_errored_transfers_run);
wa-dto_in_use = 0;
atomic_set(wa-xfer_id_count, 1);
+   /* init the buf in URBs */
+   for (index = 0; index  WA_MAX_BUF_IN_URBS; ++index)
+   usb_init_urb((wa-buf_in_urbs[index]));
+   wa-active_buf_in_urbs = 0;
 }
 
 /**
diff --git a/drivers/usb/wusbcore/wa-xfer.c b/drivers/usb/wusbcore/wa-xfer.c
index f930bbb..c8e2a47 100644
--- a/drivers/usb/wusbcore/wa-xfer.c
+++ b/drivers/usb/wusbcore/wa-xfer.c
@@ -2159,9 +2159,9 @@ static void wa_complete_remaining_xfer_segs(struct 
wa_xfer *xfer,
}
 }
 
-/* Populate the wa-buf_in_urb based on the current isoc transfer state. */
-static int __wa_populate_buf_in_urb_isoc(struct wahc *wa, struct wa_xfer *xfer,
-   struct wa_seg *seg)
+/* Populate the given urb based on the current isoc transfer state. */
+static int __wa_populate_buf_in_urb_isoc(struct wahc *wa,
+   struct urb *buf_in_urb, struct wa_xfer *xfer, struct wa_seg *seg)
 {
int urb_start_frame = seg-isoc_frame_index + seg-isoc_frame_offset;
int seg_index, total_len = 0, urb_frame_index = urb_start_frame;
@@ -2171,7 +2171,7 @@ static int __wa_populate_buf_in_urb_isoc(struct wahc *wa, 
struct wa_xfer *xfer,
int next_frame_contiguous;
struct usb_iso_packet_descriptor *iso_frame;
 
-   BUG_ON(wa-buf_in_urb-status == -EINPROGRESS);
+   BUG_ON(buf_in_urb-status == -EINPROGRESS);
 
/*
 * If the current frame actual_length is contiguous with the next frame
@@ -2201,68 +2201,68 @@ static int __wa_populate_buf_in_urb_isoc(struct wahc 
*wa, struct wa_xfer *xfer,
 ((iso_frame-actual_length % dti_packet_size) == 0));
 
/* this should always be 0 before a resubmit. */
-   wa-buf_in_urb-num_mapped_sgs  = 0;
-   wa-buf_in_urb-transfer_dma = xfer-urb-transfer_dma +
+   buf_in_urb-num_mapped_sgs  = 0;
+   buf_in_urb-transfer_dma = xfer-urb-transfer_dma +
iso_frame_desc[urb_start_frame].offset;
-   wa-buf_in_urb-transfer_buffer_length = total_len;
-   wa-buf_in_urb-transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
-   wa-buf_in_urb-transfer_buffer = NULL;
-   wa-buf_in_urb-sg = NULL;
-   wa-buf_in_urb-num_sgs = 0;
-   wa-buf_in_urb-context = seg;
+   buf_in_urb-transfer_buffer_length = total_len;
+   

Re: [PATCH v2] phy-rcar-gen2-usb: add device tree support

2014-03-07 Thread Sergei Shtylyov

Hello.

On 03/07/2014 05:27 PM, Sergei Shtylyov wrote:


Add support of the device tree probing for the Renesas R-Car generation 2 SoCs
documenting the device tree binding as necessary.



Signed-off-by: Sergei Shtylyov sergei.shtyl...@cogentembedded.com



---
This patch is against the 'next' branch of Felipe Balbi's 'usb.git' repo.



Changes in version 2:
- restored devm_clk_get() call and the error handling logic in the probe()
   method, removed clk_put() call in the remove() method.



  Documentation/devicetree/bindings/usb/rcar-gen2-phy.txt |   29 +++
  drivers/usb/phy/phy-rcar-gen2-usb.c |   42
++--
  2 files changed, 68 insertions(+), 3 deletions(-)



Index: usb/Documentation/devicetree/bindings/usb/rcar-gen2-phy.txt
===
--- /dev/null
+++ usb/Documentation/devicetree/bindings/usb/rcar-gen2-phy.txt
@@ -0,0 +1,29 @@
+* Renesas R-Car generation 2 USB PHY
+
+This file provides information on what the device node for the R-Car
generation
+2 USB PHY contains.
+
+Required properties:
+- compatible: renesas,usb-phy-r8a7790 if the device is a part of R8A7790
SoC.
+ renesas,usb-phy-r8a7791 if the device is a part of R8A7791
SoC.
+- reg: offset and length of the register block.
+- clocks: clock phandle and specifier pair.
+- clock-names: string, clock input name, must be usbhs.
+
+Optional properties:
+- renesas,channel0-pci: boolean, specify when USB channel 0 should be
connected
+   to PCI EHCI/OHCI; otherwise, it will be connected
to the
+   USBHS controller.
+- renesas,channel2-pci: boolean, specify when USB channel 2 should be
connected
+   to PCI EHCI/OHCI; otherwise, it will be connected
to the
+   USBSS controller (xHCI).



Thanks for your efforts here, but this DT binding looks like a mix of
software configuration and hardware description.



I disagree. I have already explained to Mark Rutland how selecting a
particular controller for a particular USB port should depend on the kind of
the USB connector used, i.e. the board hardware.



+Example (Lager board):
+
+   usb-phy@e6590100 {
+   compatible = renesas,usb-phy-r8a7790;
+   reg = 0 0xe6590100 0 0x100;
+   clocks = mstp7_clks R8A7790_CLK_HSUSB;
+   clock-names = usbhs;
+   renesas,channel2-pci;
+   };



As an example, instead of relying on renesas,channel0-pci or
renesas,channel2-pci to specify which hard coded software
configuration you want please rework this to expose 3 separate
channels and use DT to point each host controller to the right
channel.



So you want to expose the channels as virtual devices? Or what do you
want?


   OK, let's assume you want either virtual PHYs or channel subnodes in the 
PHY node we have now. Now what the PHY driver should do with all these 
phandles pointing from the controller nodes to the PHY nodes or the channel 
subnodes? Scan all device tree in search of the nodes having certain prop and 
get info from such nodes on how to program the channel MUXing register using 
their compatible props? Sorry, that doesn't appeal to me at all.
   Now if we got the phandles pointing from the PHY node back to the selected 
controllers, things would look somewhat better. Yet it still looks like an 
unnecessary complication of what I'm proposing and so doesn't appeal to me 
much either.

   So, what's your intent here (other than to make my life harder :-)?


Also, it seems almost impossible to represent some USB controllers in DT
-- such as USBHS in particular.


   I've spent several days staring at the various USBHS code and I'm going to 
send you a more detailed report on USBHS vs DT issues.


[...]


So this is a NAK on my side. I expect better.



Thanks for your long awaited feedback.


   I'm not convinced that what you're proposing is indeed better though.


Thanks,



/ magnus


WBR, Sergei

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Re: [PATCH 4/9] ARM: dts: imx25.dtsi: Fix USB support.

2014-03-07 Thread Fabio Estevam
Hi Denis,

On Fri, Mar 7, 2014 at 2:04 PM, Denis Carikli de...@eukrea.com wrote:
 From: Fabio Estevam fabio.este...@freescale.com

 This patch was adapted from the thread named
 USB Host support for mx25 on linux-usb@vger.kernel.org

Good job, thanks for working on this series!

I will test it next week.

Thanks,

Fabio Estevam
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[GIT PULL] USB patches for v3.15

2014-03-07 Thread Felipe Balbi
Hi Greg,

Here's my pull request for v3.15 merge window.

This pull request contains patches which have been soaking in linux-next for
quite a bit of time. I also ran everything through my 150 randconfigs script
(which uses some seeds of my own).

Please, consider merging it on top of your greg/usb-next branch.

Note that this pull request is based off of an old commit on your usb-next
branch because I was out for a while on vacations and wanted to avoid
duplicated commits.

cheers


The following changes since commit 6d36b6f313738e99fc8b903697f8ecf06add29aa:

  phy-core: Don't allow building phy-core as a module (2014-02-15 12:28:39 
-0800)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git tags/usb-for-v3.15

for you to fetch changes up to 4b76e14d95f7b69e71eabc002dcb0dcb9ebb5340:

  phy: ti-pipe3: Add SATA compatible to Documentation binding (2014-03-07 
10:03:47 -0600)


usb: patches for v3.15

another substantial pull request with new features all over
the place.

dwc3 got a bit closer towards hibernation support with after
a few patches re-factoring code to be reused for hibernation.
Also in dwc3 two new workarounds for known silicon bugs have
been implemented, some randconfig build errors have been fixed,
and it was taught about the new generic phy layer.

MUSB on AM335x now supports isochronous transfers thanks to
George Cherian's work.

The atmel_usba driver got two crash fixes: one when no endpoint
was specified in DeviceTree data and another when stopping the UDC
in DEBUG builds.

Function FS got a much needed fix to ffs_epfile_io() which was
copying too much data to userspace in some cases.

The printer gadget got a fix for a possible deadlock and plugged
a memory leak.

Ethernet drivers now use NAPI for RX which gives improved throughput.

Other than that, the usual miscelaneous fixes, cleanups, and
the like.

Signed-of-by: Felipe Balbi ba...@ti.com


Alexandre Belloni (1):
  usb: gadget: atmel_usba: fix crash when no endpoint are specified

Andrzej Pietrasiewicz (4):
  usb: gadget: FunctionFS: dereference ffs_dev conditionally
  usb: gadget: code cleanup
  usb: gadget: FunctionFS: staticize functions used only in f_fs.c
  usb: gadget: FunctionFS: use consistent naming with regard to ffs_lock

Bo Shen (2):
  usb: gadget: at91: fix the number of endpoint parameter
  usb: gadget: at91: using USBA_NR_DMAS for DMA channels

Chuansheng Liu (1):
  usb: gadget: return the right length in ffs_epfile_io()

Dan Carpenter (3):
  usb: gadget: gr_udc: remove some unneeded error handling
  usb: dwc3: gadget: cut and paste fixups in suspend/resume
  usb: dwc3: gadget: remove known conditions

Felipe Balbi (15):
  usb: musb: avoid NULL pointer dereference
  usb: dwc3: gadget: always enable IOC on bulk/interrupt transfers
  usb: dwc3: core: define bit 10 of GCTL register
  usb: dwc3: workaround: clock gating issues
  usb: dwc3: workaround: bogus hibernation events
  usb: dwc3: cleanup struct dwc3
  usb: dwc3: add has_hibernation flag
  usb: dwc3: core: allocate scratch buffers
  usb: dwc3: core: fix indentation
  usb: dwc3: gadget: set KEEP_CONNECT in case of hibernation
  usb: dwc3: gadget: make sure HIRD threshold is 0 in superspeed
  usb: dwc3: gadget: call gadget driver's -suspend/-resume
  usb: dwc3: gadget: pre-start Stream transfers when they're queued
  usb: dwc3: fix randconfig build errors
  usb: dwc3: define more revisions

Geert Uytterhoeven (1):
  usb: musb: USB_MUSB_DUAL_ROLE/USB_MUSB_GADGET should depend on HAS_DMA

George Cherian (4):
  usb: musb: musb_host: Enable ISOCH IN handling for AM335x host
  usb: musb: musb_cppi41: Make CPPI aware of high bandwidth transfers
  usb: musb: musb_cppi41: Handle ISOCH differently and not use the hrtimer.
  usb: musb: musb_cppi41: Dont reprogram DMA if tear down is initiated

Gregory CLEMENT (1):
  usb: gadget: atmel_usba: fix crashed during stopping when DEBUG is enabled

Huang Rui (1):
  usb: dwc3: fix wrong bit mask in dwc3_event_devt

Jingoo Han (1):
  usb: gadget: s3c-hsotg: use %pad for dma_addr_t

Julia Lawall (1):
  usb: gadget: fix error return code

Kishon Vijay Abraham I (3):
  Documentation: dt bindings: move ..usb/usb-phy.txt to ..phy/ti-phy.txt
  usb: dwc3: core: support optional PHYs
  usb: dwc3: adapt dwc3 core to use Generic PHY Framework

Li Jun (1):
  usb: phy: fsm: update OTG HNP state transition conditions according to 
OTG and EH 2.0 spec.

Manu Gautam (1):
  usb: gadget: f_fs: Add support for SuperSpeed Mode

Marek Szyprowski (1):
  usb: gadget: s3c-hsotg: add proper suspend/resume support

Markus Pargmann (2):
  usb: musb: dsps, use devm_kzalloc
  usb: musb: dsps, debugfs files

Matt 

Re: [GIT PULL] USB patches for v3.15

2014-03-07 Thread Greg KH
On Fri, Mar 07, 2014 at 06:30:45PM -0600, Felipe Balbi wrote:
 Hi Greg,
 
 Here's my pull request for v3.15 merge window.
 
 This pull request contains patches which have been soaking in linux-next for
 quite a bit of time. I also ran everything through my 150 randconfigs script
 (which uses some seeds of my own).
 
 Please, consider merging it on top of your greg/usb-next branch.
 
 Note that this pull request is based off of an old commit on your usb-next
 branch because I was out for a while on vacations and wanted to avoid
 duplicated commits.
 
 cheers
 
 
 The following changes since commit 6d36b6f313738e99fc8b903697f8ecf06add29aa:
 
   phy-core: Don't allow building phy-core as a module (2014-02-15 12:28:39 
 -0800)

Pulled and pushed out, thanks.

greg k-h
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MAX3421E: device giving NAKs forever?

2014-03-07 Thread David Mosberger
So the MAX3421E driver is working quite well but one problem I'm
seeing is that after running devices for a while, they seem to get
into a mode where a bulk out transfer gets stuck soliciting and
endless stream of NAKs.  The MAX3421E retries NAK'd transfers in the
next frame again, only to get the same response, forever.  I see this
both with a mass storage device and a WIFI adapter (which is
specifically advertised as being USB 1.1 compatible).  Anybody have
any ideas where that might be coming from?

  --david
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Re: MAX3421E: device giving NAKs forever?

2014-03-07 Thread Felipe Balbi
On Fri, Mar 07, 2014 at 06:16:03PM -0700, David Mosberger wrote:
 So the MAX3421E driver is working quite well but one problem I'm
 seeing is that after running devices for a while, they seem to get
 into a mode where a bulk out transfer gets stuck soliciting and
 endless stream of NAKs.  The MAX3421E retries NAK'd transfers in the
 next frame again, only to get the same response, forever.  I see this
 both with a mass storage device and a WIFI adapter (which is
 specifically advertised as being USB 1.1 compatible).  Anybody have
 any ideas where that might be coming from?

take a look at usbmon and capture some traces of a live session. We need
pre- and post- data. The more the merrier ;-)

You can read about usbmon on Documentation/usb/usbmon.txt in your kernel
source tree.

cheers and good luck

-- 
balbi


signature.asc
Description: Digital signature


Re: [PATCH 1/9] usb: chipidea: usbmisc: Add USB Host support for i.MX25/i.MX35 CPUs

2014-03-07 Thread Alexander Shiyan
Пятница,  7 марта 2014, 18:04 +01:00 от Denis Carikli de...@eukrea.com:
 Signed-off-by: Denis Carikli de...@eukrea.com
 ---
  drivers/usb/chipidea/usbmisc_imx.c |   59 
 
  1 file changed, 59 insertions(+)
 
 diff --git a/drivers/usb/chipidea/usbmisc_imx.c 
 b/drivers/usb/chipidea/usbmisc_imx.c
 index cd061ab..d956ad0 100644
 --- a/drivers/usb/chipidea/usbmisc_imx.c
 +++ b/drivers/usb/chipidea/usbmisc_imx.c
...
 + val = readl(usbmisc-base);
 + val = ~(MX25_OTG_SIC_MASK | MX25_OTG_PP_BIT);
 + val |= (MXC_EHCI_INTERFACE_DIFF_UNI  MXC_EHCI_INTERFACE_MASK) 
  MX25_OTG_SIC_SHIFT;
 + val |= (MX25_OTG_PM_BIT | MX25_OTG_OCPOL_BIT);
 + writel(val, usbmisc-base);

At the moment, we only enable/disable interface and manage overcurrent option
in the usbmisc driver.
Is it worth it to handle type of interface here?

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Re: [PATCH v10 2/4] phy: core: Add devm_of_phy_get to phy-core

2014-03-07 Thread Kishon Vijay Abraham I

Tobias,

On Saturday 08 March 2014 01:04 AM, Tobias Jakobi wrote:

Kamil Debski wrote:

Adding devm_of_phy_get will allow to get phys by supplying a
pointer to the struct device_node instead of struct device.

Signed-off-by: Kamil Debski k.deb...@samsung.com
---
  drivers/phy/phy-core.c  |   31 +++
  include/linux/phy/phy.h |8 
  2 files changed, 39 insertions(+)

Tested-by: Tobias Jakobi tjak...@math.uni-bielefeld.de


Thanks for testing these patches. However I've already queued all these 
patches so won't be able to add your 'Tested-by' :-s


Thanks
Kishon
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Re: [PATCH v3] u_ether: move hardware transmit to RX workqueue

2014-03-07 Thread clanlab.proj
Hi Dave and Greg,

On Fri, Mar 7, 2014 at 12:04 AM, Felipe Balbi ba...@ti.com wrote:
 Hi,

 On Thu, Mar 06, 2014 at 11:42:49PM +0800, Weinn Jheng wrote:
 In order to reduce the interrupt times in the embedded system,
 a receiving workqueue is introduced.
 This modification also enhanced the overall throughput as the
 benefits of reducing interrupt occurrence.

 Signed-off-by: Weinn Jheng clanlab.p...@gmail.com
 Cc: David Brownell dbrown...@users.sourceforge.net
 Cc: David S. Miller da...@davemloft.net

 Dave, does this look ok from NAPI point of view ?

I've found the another patch NAPI version has been taken by Greg.
But I didn't remembered I've seen the further comment from Dave.
Since the performance will be a little bit slower then work queue
according to my experiment before.
Could someone please give me the comment about the decisions of pros and cons?
Because I have no idea if there will be further improvement is needed
for patching NAPI version to work queue.

Thanks!

Best regards,
Weinn Jheng
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