Re: dwc2 gadget issues

[Randy Li]

You don't need to send me a private mail, I would suggest you CC me next 
time.


On 02/24/2017 03:27 AM, Heiko Stuebner wrote:

Hi Francesco,

Am Donnerstag, 23. Februar 2017, 19:11:37 CET schrieb Francesco Lavra:

I'm having trouble getting the RK3288 OTG controller (the one at
ff58) to work in peripheral mode. I'm using a Firefly Reload board,
and I know the hardware is fine because I can successfully use the port
in device mode with U-Boot's mass storage gadget driver.
Under Linux, the OTG port works fine when used in host mode, but fails
to work in device mode: nothing happens when the a USB host is plugged
into the OTG port, not even a single interrupt is generated by the
controller. I'm using the latest device tree definitions from
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git.


you shouldn't use my tree as base for any real work :-) . Best to use the
regular mainline kernel or alternatively try linux-next to get all recent usb
changes schedules for the next release.



Tried with different gadget drivers (g_audio, g_ether, g_mass_storage),
but it makes no difference.

I tried g_ether and g_serial, it looks fine for me.

Tried also forcing peripheral mode in the device tree, with dr_mode =
"peripheral", to no avail.

Are there any known problems with the RK3288 OTG controller?


In general the controller is a dwc2 and there was quite some activity on the
driver recently. So maybe really try linux-next first and see if any of the
changes included there improve the situation.

I've included some usb lists + people, maybe they know if anything recent may
have changed things.



Here is the relevant log when the dwc2 driver is loaded at boot:

[1.376935] ff58.usb supply vusb_d not found, using dummy regulator
[1.383683] ff58.usb supply vusb_a not found, using dummy regulator
[1.390627] dwc2 ff58.usb: dwc2_core_reset() HANG! Soft Reset
GRSTCTL=8001
[1.509048] dwc2 ff58.usb: dwc2_wait_for_mode: Couldn't set
device mode
[1.750626] dwc2 ff58.usb: dwc2_check_param_tx_fifo_sizes:
Invalid parameter g-tx-fifo-size, setting to default average
[1.761828] dwc2 ff58.usb: dwc2_check_param_tx_fifo_sizes:
Invalid parameter g_tx_fifo_size[1]=104
[1.771192] dwc2 ff58.usb: dwc2_check_param_tx_fifo_sizes:
Invalid parameter g_tx_fifo_size[2]=104
[1.780529] dwc2 ff58.usb: dwc2_check_param_tx_fifo_sizes:
Invalid parameter g_tx_fifo_size[3]=104
[1.789888] dwc2 ff58.usb: dwc2_check_param_tx_fifo_sizes:
Invalid parameter g_tx_fifo_size[4]=104
[1.799245] dwc2 ff58.usb: dwc2_check_param_tx_fifo_sizes:
Invalid parameter g_tx_fifo_size[5]=104
[1.808614] dwc2 ff58.usb: dwc2_check_param_tx_fifo_sizes:
Invalid parameter g_tx_fifo_size[6]=104
[1.817993] usb 1-1: new high-speed USB device number 2 using dwc2
[1.824390] dwc2 ff58.usb: EPs: 10, dedicated fifos, 972 entries
in SPRAM
[1.832098] dwc2 ff58.usb: DWC OTG Controller
[1.836924] dwc2 ff58.usb: new USB bus registered, assigned bus
number 2
[1.844125] dwc2 ff58.usb: irq 41, io mem 0xff58
[1.849747] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002
[1.856598] usb usb2: New USB device strings: Mfr=3, Product=2,
SerialNumber=1
[1.863875] usb usb2: Product: DWC OTG Controller
[1.868601] usb usb2: Manufacturer: Linux 4.8.1+ dwc2_hsotg
[1.874215] usb usb2: SerialNumber: ff58.usb

and this is what I get when I load a gadget driver (in this case, g_audio):

[   19.848590] dwc2 ff58.usb: bound driver g_audio
[   19.853816] dwc2 ff58.usb: dwc2_hsotg_enqueue_setup: failed queue
(-11)



Heiko

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[PATCH v10 1/2] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Randy Li]

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit) in chip, which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Signed-off-by: Randy Li <ay...@soulik.info>
Acked-by: John Youn <johny...@synopsys.com>
---
 drivers/usb/dwc2/core.h  |  1 +
 drivers/usb/dwc2/core_intr.c | 11 +++
 drivers/usb/dwc2/platform.c  |  9 +
 3 files changed, 21 insertions(+)

diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 9548d3e..0cd5896 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -919,6 +919,7 @@ struct dwc2_hsotg {
unsigned int ll_hw_enabled:1;
 
struct phy *phy;
+   struct work_struct phy_rst_work;
struct usb_phy *uphy;
struct dwc2_hsotg_plat *plat;
struct regulator_bulk_data 
supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)];
diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index 5b228ba..bf1c029 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg 
*hsotg)
 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 {
int ret;
+   struct device_node *np = hsotg->dev->of_node;
 
/* Clear interrupt */
dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
@@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct 
dwc2_hsotg *hsotg)
/* Restart the Phy Clock */
pcgcctl &= ~PCGCTL_STOPPCLK;
dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+
+   /*
+* It is a quirk in Rockchip RK3288, causing by
+* a hardware bug. This will propagate out and
+* eventually we'll re-enumerate the device.
+* Not great but the best we can do.
+*/
+   if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
+   schedule_work(>phy_rst_work);
+
mod_timer(>wkp_timer,
  jiffies + msecs_to_jiffies(71));
} else {
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 4fc8c60..8ef278e 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -207,6 +207,14 @@ int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
return ret;
 }
 
+/* Only used to reset usb phy at interrupter runtime */
+static void dwc2_reset_phy_work(struct work_struct *data)
+{
+   struct dwc2_hsotg *hsotg = container_of(data, struct dwc2_hsotg,
+   phy_rst_work);
+   phy_reset(hsotg->phy);
+}
+
 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
 {
int i, ret;
@@ -251,6 +259,7 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
return ret;
}
}
+   INIT_WORK(>phy_rst_work, dwc2_reset_phy_work);
 
if (!hsotg->phy) {
hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
-- 
2.7.4

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[PATCH v10 2/2] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

[Randy Li]

The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288
has a hardware errata that causes everything to get confused when we get
a remote wakeup.  We'll use the reset that's in the CRU to reset the
port when it's in a bad state.

Note that we add the reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata.  Only the host port gets the
quirk property, though.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 arch/arm/boot/dts/rk3288.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 4fad133..c779365 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -858,6 +858,8 @@
clocks = < SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBOTG_PHY>;
+   reset-names = "phy-reset";
};
 
usbphy1: usb-phy@334 {
@@ -874,6 +876,8 @@
clocks = < SCLK_OTGPHY2>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBHOST1_PHY>;
+   reset-names = "phy-reset";
};
};
};
-- 
2.7.4

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[PATCH v10 0/2] the fixup for the USB HOST1 at rk3288 platform

[Randy Li]

changelog:
v10
 minior fixup
v9
 use a work_queue to reset usb phy to prevent access mutex lock at interrupter
 runtime.
v8
  minior fixup
v7
  add the forgot dummy phy_reset() for the generic phy is disabled.
v7
  Some minor fixup
v6
  Send the last two patches
v5
  A few modification at style, add the missing doc in the last 
  commit.
v4
  1. Adding the reset callback in struct phy_ops.
  2. Moving the reset into phy rockchip usb.
  3. Trying to call a reset when dwc2 wakeup in rk3288.
v3
 Rebased from previous commit
v2
 Rebased from previous commit
v1
 orignal from google

Randy Li (2):
  usb: dwc2: assert phy reset when waking up in rk3288 platform
  ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

 arch/arm/boot/dts/rk3288.dtsi |  4 
 drivers/usb/dwc2/core.h   |  1 +
 drivers/usb/dwc2/core_intr.c  | 11 +++
 drivers/usb/dwc2/platform.c   |  9 +
 4 files changed, 25 insertions(+)

-- 
2.7.4

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[PATCH] phy: Add reset callback for not generic phy

[Randy Li]

I forget to add a dummy function in case the CONFIG_GENERIC_PHY
is disabled.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 include/linux/phy/phy.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index ee1bed7..78bb0d7 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -253,6 +253,13 @@ static inline int phy_set_mode(struct phy *phy, enum 
phy_mode mode)
return -ENOSYS;
 }
 
+static inline int phy_reset(struct phy *phy)
+{
+   if (!phy)
+   return 0;
+   return -ENOSYS;
+}
+
 static inline int phy_get_bus_width(struct phy *phy)
 {
return -ENOSYS;
-- 
2.7.4

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[PATCH v9 2/2] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

[Randy Li]

The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288
has a hardware errata that causes everything to get confused when we get
a remote wakeup.  We'll use the reset that's in the CRU to reset the
port when it's in a bad state.

Note that we add the reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata.  Only the host port gets the
quirk property, though.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 arch/arm/boot/dts/rk3288.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 2f814ff..4ef058c 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -859,6 +859,8 @@
clocks = < SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBOTG_PHY>;
+   reset-names = "phy-reset";
};
 
usbphy1: usb-phy@334 {
@@ -875,6 +877,8 @@
clocks = < SCLK_OTGPHY2>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBHOST1_PHY>;
+   reset-names = "phy-reset";
};
};
};
-- 
2.7.4

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[PATCH v9 0/2] the fixup for the USB HOST1 at rk3288 platform

[Randy Li]

changelog:
v9
 use a work_queue to reset usb phy to prevent access mutex lock at interrupter
 runtime.
v8
  minior fixup
v7
  add the forgot dummy phy_reset() for the generic phy is disabled.
v7
  Some minor fixup
v6
  Send the last two patches
v5
  A few modification at style, add the missing doc in the last 
  commit.
v4
  1. Adding the reset callback in struct phy_ops.
  2. Moving the reset into phy rockchip usb.
  3. Trying to call a reset when dwc2 wakeup in rk3288.
v3
 Rebased from previous commit
v2
 Rebased from previous commit
v1
 orignal from google

Randy Li (2):
  usb: dwc2: assert phy reset when waking up in rk3288 platform
  ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

 arch/arm/boot/dts/rk3288.dtsi |  4 
 drivers/usb/dwc2/core.h   |  1 +
 drivers/usb/dwc2/core_intr.c  | 11 +++
 drivers/usb/dwc2/platform.c   |  9 +
 4 files changed, 25 insertions(+)

-- 
2.7.4

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[PATCH v9 1/2] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Randy Li]

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit) in chip, which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 drivers/usb/dwc2/core.h  |  1 +
 drivers/usb/dwc2/core_intr.c | 11 +++
 drivers/usb/dwc2/platform.c  |  9 +
 3 files changed, 21 insertions(+)

diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 2a21a04..e91ddbc 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -859,6 +859,7 @@ struct dwc2_hsotg {
unsigned int ll_hw_enabled:1;
 
struct phy *phy;
+   struct work_struct phy_rst_work;
struct usb_phy *uphy;
struct dwc2_hsotg_plat *plat;
struct regulator_bulk_data 
supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)];
diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index d85c5c9..c3d2168 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg 
*hsotg)
 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 {
int ret;
+   struct device_node *np = hsotg->dev->of_node;
 
/* Clear interrupt */
dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
@@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct 
dwc2_hsotg *hsotg)
/* Restart the Phy Clock */
pcgcctl &= ~PCGCTL_STOPPCLK;
dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+
+   /*
+* It is a quirk in Rockchip RK3288, causing by
+* a hardware bug. This will propagate out and
+* eventually we'll re-enumerate the device. 
+* Not great but the best we can do 
+*/
+   if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
+   schedule_work(>phy_rst_work);
+
mod_timer(>wkp_timer,
  jiffies + msecs_to_jiffies(71));
} else {
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 8e1728b..65953cf 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -366,6 +366,14 @@ int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
return ret;
 }
 
+/* Only used to reset usb phy at interrupter runtime */
+static void dwc2_reset_phy_work(struct work_struct *data)
+{
+   struct dwc2_hsotg *hsotg = container_of(data, struct dwc2_hsotg,
+   phy_rst_work);
+   phy_reset(hsotg->phy);
+}
+
 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
 {
int i, ret;
@@ -410,6 +418,7 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
return ret;
}
}
+   INIT_WORK(>phy_rst_work, dwc2_reset_phy_work);
 
if (!hsotg->phy) {
hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
-- 
2.7.4

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Re: [PATCH v8 2/3] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Randy Li]

On 10/20/2016 06:58 AM, John Youn wrote:

On 10/15/2016 8:07 AM, 陈豪 wrote:

2016-09-25 2:50 GMT+08:00 Randy Li <ay...@soulik.info>:

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit) in chip, which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 drivers/usb/dwc2/core_intr.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index d85c5c9..af27edc 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg 
*hsotg)
 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 {
int ret;
+   struct device_node *np = hsotg->dev->of_node;

/* Clear interrupt */
dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
@@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct 
dwc2_hsotg *hsotg)
/* Restart the Phy Clock */
pcgcctl &= ~PCGCTL_STOPPCLK;
dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+
+   /*
+* It is a quirk in Rockchip RK3288, causing by
+* a hardware bug. This will propagate out and
+* eventually we'll re-enumerate the device.
+* Not great but the best we can do.
+*/
+   if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
+   phy_reset(hsotg->phy);


It will call mutex_lock in phy_reset.



+
mod_timer(>wkp_timer,
  jiffies + msecs_to_jiffies(71));
} else {
--
2.7.4



What is the status of this patch？
Sleeping calls(phy_reset ==> mutex) shouldn't be used in irq handler.
Randy will correct that？



Yes, that's right, I missed that.

It will have to be fixed.

I am still thinking a method to instead it.


Regards,
John




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Randy Li
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[PATCH v8 1/3] phy: Add reset callback for not generic phy

[Randy Li]

I forget to add a dummy function in case the CONFIG_GENERIC_PHY
is disabled.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 include/linux/phy/phy.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index ee1bed7..78bb0d7 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -253,6 +253,13 @@ static inline int phy_set_mode(struct phy *phy, enum 
phy_mode mode)
return -ENOSYS;
 }
 
+static inline int phy_reset(struct phy *phy)
+{
+   if (!phy)
+   return 0;
+   return -ENOSYS;
+}
+
 static inline int phy_get_bus_width(struct phy *phy)
 {
return -ENOSYS;
-- 
2.7.4

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[PATCH v8 2/3] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Randy Li]

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit) in chip, which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 drivers/usb/dwc2/core_intr.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index d85c5c9..af27edc 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg 
*hsotg)
 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 {
int ret;
+   struct device_node *np = hsotg->dev->of_node;
 
/* Clear interrupt */
dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
@@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct 
dwc2_hsotg *hsotg)
/* Restart the Phy Clock */
pcgcctl &= ~PCGCTL_STOPPCLK;
dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+
+   /*
+* It is a quirk in Rockchip RK3288, causing by
+* a hardware bug. This will propagate out and
+* eventually we'll re-enumerate the device.
+* Not great but the best we can do.
+*/
+   if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
+   phy_reset(hsotg->phy);
+
mod_timer(>wkp_timer,
  jiffies + msecs_to_jiffies(71));
} else {
-- 
2.7.4

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[PATCH v8 0/3] the fixup for the USB HOST1 at rk3288 platform

[Randy Li]

  At this stage it is the only "full features" and well verified 
USB EHCI controller in this platform. More review is always necessary.

Although V7 is almost fine but a forget a dummy function for the phy
system.

changelog:
v7
  add the forgot dummy phy_reset() for the generic phy is disabled.
v7
  Some minor fixup
v6
  Send the last two patches
v5
  A few modification at style, add the missing doc in the last 
  commit.
v4
  1. Adding the reset callback in struct phy_ops.
  2. Moving the reset into phy rockchip usb.
  3. Trying to call a reset when dwc2 wakeup in rk3288.
v3
 Rebased from previous commit
v2
 Rebased from previous commit
v1
 orignal from google

Randy Li (3):
  phy: Add reset callback for not generic phy
  usb: dwc2: assert phy reset when waking up in rk3288 platform
  ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

 arch/arm/boot/dts/rk3288.dtsi |  4 
 drivers/usb/dwc2/core_intr.c  | 11 +++
 include/linux/phy/phy.h   |  7 +++
 3 files changed, 22 insertions(+)

-- 
2.7.4

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[PATCH v8 3/3] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

[Randy Li]

The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288
has a hardware errata that causes everything to get confused when we get
a remote wakeup.  We'll use the reset that's in the CRU to reset the
port when it's in a bad state.

Note that we add the reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata.  Only the host port gets the
quirk property, though.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 arch/arm/boot/dts/rk3288.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 2cf1eb2..b87f421 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -859,6 +859,8 @@
clocks = < SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBOTG_PHY>;
+   reset-names = "phy-reset";
};
 
usbphy1: usb-phy@334 {
@@ -875,6 +877,8 @@
clocks = < SCLK_OTGPHY2>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBHOST1_PHY>;
+   reset-names = "phy-reset";
};
};
};
-- 
2.7.4

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[RESEND PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Randy Li]

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit) in chip, which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 drivers/usb/dwc2/core_intr.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index d85c5c9..af27edc 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg 
*hsotg)
 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 {
int ret;
+   struct device_node *np = hsotg->dev->of_node;
 
/* Clear interrupt */
dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
@@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct 
dwc2_hsotg *hsotg)
/* Restart the Phy Clock */
pcgcctl &= ~PCGCTL_STOPPCLK;
dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+
+   /*
+* It is a quirk in Rockchip RK3288, causing by
+* a hardware bug. This will propagate out and
+* eventually we'll re-enumerate the device.
+* Not great but the best we can do.
+*/
+   if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
+   phy_reset(hsotg->phy);
+
mod_timer(>wkp_timer,
  jiffies + msecs_to_jiffies(71));
} else {
-- 
2.7.4

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[RESEND PATCH v7 4/4] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

[Randy Li]

The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288
has a hardware errata that causes everything to get confused when we get
a remote wakeup.  We'll use the reset that's in the CRU to reset the
port when it's in a bad state.

Note that we add the reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata.  Only the host port gets the
quirk property, though.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 arch/arm/boot/dts/rk3288.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 17ec2e2..34de803 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -857,6 +857,8 @@
clocks = < SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBOTG_PHY>;
+   reset-names = "phy-reset";
};
 
usbphy1: usb-phy@334 {
@@ -873,6 +875,8 @@
clocks = < SCLK_OTGPHY2>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBHOST1_PHY>;
+   reset-names = "phy-reset";
};
};
};
-- 
2.7.4

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[RESEND PATCH v7 2/4] phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during wakeup

[Randy Li]

It is a hardware bug in RK3288, the only way to solve it is to
reset the phy.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 .../devicetree/bindings/phy/rockchip-usb-phy.txt |  3 +++
 drivers/phy/phy-rockchip-usb.c   | 20 
 2 files changed, 23 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt 
b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
index cc6be96..57dc388 100644
--- a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -27,6 +27,9 @@ Optional Properties:
 - clocks : phandle + clock specifier for the phy clocks
 - clock-names: string, clock name, must be "phyclk"
 - #clock-cells: for users of the phy-pll, should be 0
+- reset-names: Only allow the following entries:
+ - phy-reset
+- resets: Must contain an entry for each entry in reset-names.
 
 Example:
 
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
index 2a7381f..734987f 100644
--- a/drivers/phy/phy-rockchip-usb.c
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 
 static int enable_usb_uart;
 
@@ -64,6 +65,7 @@ struct rockchip_usb_phy {
struct clk_hw   clk480m_hw;
struct phy  *phy;
booluart_enabled;
+   struct reset_control *reset;
 };
 
 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
@@ -144,9 +146,23 @@ static int rockchip_usb_phy_power_on(struct phy *_phy)
return clk_prepare_enable(phy->clk480m);
 }
 
+static int rockchip_usb_phy_reset(struct phy *_phy)
+{
+   struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+
+   if (phy->reset) {
+   reset_control_assert(phy->reset);
+   udelay(10);
+   reset_control_deassert(phy->reset);
+   }
+
+   return 0;
+}
+
 static const struct phy_ops ops = {
.power_on   = rockchip_usb_phy_power_on,
.power_off  = rockchip_usb_phy_power_off,
+   .reset  = rockchip_usb_phy_reset,
.owner  = THIS_MODULE,
 };
 
@@ -185,6 +201,10 @@ static int rockchip_usb_phy_init(struct 
rockchip_usb_phy_base *base,
return -EINVAL;
}
 
+   rk_phy->reset = of_reset_control_get(child, "phy-reset");
+   if (IS_ERR(rk_phy->reset))
+   rk_phy->reset = NULL;
+
rk_phy->reg_offset = reg_offset;
 
rk_phy->clk = of_clk_get_by_name(child, "phyclk");
-- 
2.7.4

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[RESEND PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform

[Randy Li]

  At this stage it is the only "full features" and well verified 
USB EHCI controller in this platform. More review is always necessary.

Changelog:
 - v7:
adding a wrapper for the reset operation for phy
using that wrapper
 - v6:
move pwms pinctrl to pwms node
fix the order of the dtb file in Makefile
 - v5:
   - correct the mail format
 - v4:
   - re-order some nodes in alphabetical order
   - fix some minor bugs
   - add a entry in vendor list
 - v3:
   - fixing the rtc clock, using clock source from PMIC
   - enable the tmu
   - enable the fimc for elite board
   - suuport the audio codec at elite board
   - fixing minor bugs in the last commit
 - v2:
   - removing rtc node
 the clock source driver is not done yet.
   - adding exynos-bus
   - fixing the MFC

Randy Li (4):
  phy: Add reset callback
  phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during
wakeup
  usb: dwc2: assert phy reset when waking up in rk3288 platform
  ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

 .../devicetree/bindings/phy/rockchip-usb-phy.txt |  3 +++
 arch/arm/boot/dts/rk3288.dtsi|  4 
 drivers/phy/phy-core.c   | 14 ++
 drivers/phy/phy-rockchip-usb.c   | 20 
 drivers/usb/dwc2/core_intr.c | 11 +++
 include/linux/phy/phy.h  |  3 +++
 6 files changed, 55 insertions(+)

-- 
2.7.4

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[PATCH 2/4] phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during wakeup

[Randy Li]

It is a hardware bug in RK3288, the only way to solve it is to
reset the phy.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 .../devicetree/bindings/phy/rockchip-usb-phy.txt |  3 +++
 drivers/phy/phy-rockchip-usb.c   | 20 
 2 files changed, 23 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt 
b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
index cc6be96..57dc388 100644
--- a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -27,6 +27,9 @@ Optional Properties:
 - clocks : phandle + clock specifier for the phy clocks
 - clock-names: string, clock name, must be "phyclk"
 - #clock-cells: for users of the phy-pll, should be 0
+- reset-names: Only allow the following entries:
+ - phy-reset
+- resets: Must contain an entry for each entry in reset-names.
 
 Example:
 
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
index 2a7381f..734987f 100644
--- a/drivers/phy/phy-rockchip-usb.c
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 
 static int enable_usb_uart;
 
@@ -64,6 +65,7 @@ struct rockchip_usb_phy {
struct clk_hw   clk480m_hw;
struct phy  *phy;
booluart_enabled;
+   struct reset_control *reset;
 };
 
 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
@@ -144,9 +146,23 @@ static int rockchip_usb_phy_power_on(struct phy *_phy)
return clk_prepare_enable(phy->clk480m);
 }
 
+static int rockchip_usb_phy_reset(struct phy *_phy)
+{
+   struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+
+   if (phy->reset) {
+   reset_control_assert(phy->reset);
+   udelay(10);
+   reset_control_deassert(phy->reset);
+   }
+
+   return 0;
+}
+
 static const struct phy_ops ops = {
.power_on   = rockchip_usb_phy_power_on,
.power_off  = rockchip_usb_phy_power_off,
+   .reset  = rockchip_usb_phy_reset,
.owner  = THIS_MODULE,
 };
 
@@ -185,6 +201,10 @@ static int rockchip_usb_phy_init(struct 
rockchip_usb_phy_base *base,
return -EINVAL;
}
 
+   rk_phy->reset = of_reset_control_get(child, "phy-reset");
+   if (IS_ERR(rk_phy->reset))
+   rk_phy->reset = NULL;
+
rk_phy->reg_offset = reg_offset;
 
rk_phy->clk = of_clk_get_by_name(child, "phyclk");
-- 
2.7.4

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[PATCH 0/4] the fix for the USB HOST1 at rk3288 platform

[Randy Li]

  At this stage it is the only "full features" and well verified 
USB EHCI controller in this platform. More review is always necessary.

Changelog:
 - v7:
adding a wrapper for the reset operation for phy
using that wrapper
 - v6:
move pwms pinctrl to pwms node
fix the order of the dtb file in Makefile
 - v5:
   - correct the mail format
 - v4:
   - re-order some nodes in alphabetical order
   - fix some minor bugs
   - add a entry in vendor list
 - v3:
   - fixing the rtc clock, using clock source from PMIC
   - enable the tmu
   - enable the fimc for elite board
   - suuport the audio codec at elite board
   - fixing minor bugs in the last commit
 - v2:
   - removing rtc node
 the clock source driver is not done yet.
   - adding exynos-bus
   - fixing the MFC

Randy Li (4):
  phy: Add reset callback
  phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during
wakeup
  usb: dwc2: assert phy reset when waking up in rk3288 platform
  ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

 .../devicetree/bindings/phy/rockchip-usb-phy.txt |  3 +++
 arch/arm/boot/dts/rk3288.dtsi|  4 
 drivers/phy/phy-core.c   | 14 ++
 drivers/phy/phy-rockchip-usb.c   | 20 
 drivers/usb/dwc2/core_intr.c | 11 +++
 include/linux/phy/phy.h  |  3 +++
 6 files changed, 55 insertions(+)

-- 
2.7.4

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[PATCH 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Randy Li]

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit) in chip, which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 drivers/usb/dwc2/core_intr.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index d85c5c9..5b9b671 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg 
*hsotg)
 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 {
int ret;
+   struct device_node *np = hsotg->dev->of_node;
 
/* Clear interrupt */
dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
@@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct 
dwc2_hsotg *hsotg)
/* Restart the Phy Clock */
pcgcctl &= ~PCGCTL_STOPPCLK;
dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+
+   /*
+* It is a quirk in Rockchip RK3288, causing by
+* a hardware bug. This will propagate out and
+* eventually we'll re-enumerate the device. 
+* Not great but the best we can do 
+*/
+   if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
+   phy_reset(hsotg->phy);
+
mod_timer(>wkp_timer,
  jiffies + msecs_to_jiffies(71));
} else {
-- 
2.7.4

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[PATCH 4/4] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

[Randy Li]

The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288
has a hardware errata that causes everything to get confused when we get
a remote wakeup.  We'll use the reset that's in the CRU to reset the
port when it's in a bad state.

Note that we add the reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata.  Only the host port gets the
quirk property, though.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 arch/arm/boot/dts/rk3288.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 17ec2e2..34de803 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -857,6 +857,8 @@
clocks = < SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBOTG_PHY>;
+   reset-names = "phy-reset";
};
 
usbphy1: usb-phy@334 {
@@ -873,6 +875,8 @@
clocks = < SCLK_OTGPHY2>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBHOST1_PHY>;
+   reset-names = "phy-reset";
};
};
};
-- 
2.7.4

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[PATCH 1/4] phy: Add reset callback

[Randy Li]

The only use for this is for solving a hardware design problem in
usb of Rockchip RK3288.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 drivers/phy/phy-core.c  | 14 ++
 include/linux/phy/phy.h |  3 +++
 2 files changed, 17 insertions(+)

diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 8eca906..32e838d 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -357,6 +357,20 @@ int phy_set_mode(struct phy *phy, enum phy_mode mode)
 }
 EXPORT_SYMBOL_GPL(phy_set_mode);
 
+int phy_reset(struct phy *phy)
+{
+   int ret;
+   if (!phy || !phy->ops->reset)
+   return 0;
+
+   mutex_lock(>mutex);
+   ret = phy->ops->reset(phy);
+   mutex_unlock(>mutex);
+
+   return ret;
+}
+EXPORT_SYMBOL_GPL(phy_reset);
+
 /**
  * _of_phy_get() - lookup and obtain a reference to a phy by phandle
  * @np: device_node for which to get the phy
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index f08b672..7978df6 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -36,6 +36,7 @@ enum phy_mode {
  * @power_on: powering on the phy
  * @power_off: powering off the phy
  * @set_mode: set the mode of the phy
+ * @reset: reseting the phy
  * @owner: the module owner containing the ops
  */
 struct phy_ops {
@@ -44,6 +45,7 @@ struct phy_ops {
int (*power_on)(struct phy *phy);
int (*power_off)(struct phy *phy);
int (*set_mode)(struct phy *phy, enum phy_mode mode);
+   int (*reset)(struct phy *phy);
struct module *owner;
 };
 
@@ -136,6 +138,7 @@ int phy_exit(struct phy *phy);
 int phy_power_on(struct phy *phy);
 int phy_power_off(struct phy *phy);
 int phy_set_mode(struct phy *phy, enum phy_mode mode);
+int phy_reset(struct phy *phy);
 static inline int phy_get_bus_width(struct phy *phy)
 {
return phy->attrs.bus_width;
-- 
2.7.4

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[PATCH v7 4/4] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

[Randy Li]

The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288
has a hardware errata that causes everything to get confused when we get
a remote wakeup.  We'll use the reset that's in the CRU to reset the
port when it's in a bad state.

Note that we add the reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata.  Only the host port gets the
quirk property, though.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 arch/arm/boot/dts/rk3288.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 17ec2e2..34de803 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -857,6 +857,8 @@
clocks = < SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBOTG_PHY>;
+   reset-names = "phy-reset";
};
 
usbphy1: usb-phy@334 {
@@ -873,6 +875,8 @@
clocks = < SCLK_OTGPHY2>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBHOST1_PHY>;
+   reset-names = "phy-reset";
};
};
};
-- 
2.7.4

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[PATCH v7 1/4] phy: Add reset callback

[Randy Li]

The only use for this is for solving a hardware design problem in
usb of Rockchip RK3288.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 include/linux/phy/phy.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index f08b672..4d34607 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -36,6 +36,7 @@ enum phy_mode {
  * @power_on: powering on the phy
  * @power_off: powering off the phy
  * @set_mode: set the mode of the phy
+ * @reset: reseting the phy
  * @owner: the module owner containing the ops
  */
 struct phy_ops {
@@ -44,6 +45,7 @@ struct phy_ops {
int (*power_on)(struct phy *phy);
int (*power_off)(struct phy *phy);
int (*set_mode)(struct phy *phy, enum phy_mode mode);
+   int (*reset)(struct phy *phy);
struct module *owner;
 };
 
-- 
2.7.4

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[PATCH v7 2/4] phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during wakeup

[Randy Li]

It is a hardware bug in RK3288, the only way to solve it is to
reset the phy.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 .../devicetree/bindings/phy/rockchip-usb-phy.txt |  3 +++
 drivers/phy/phy-rockchip-usb.c   | 20 
 2 files changed, 23 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt 
b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
index cc6be96..57dc388 100644
--- a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -27,6 +27,9 @@ Optional Properties:
 - clocks : phandle + clock specifier for the phy clocks
 - clock-names: string, clock name, must be "phyclk"
 - #clock-cells: for users of the phy-pll, should be 0
+- reset-names: Only allow the following entries:
+ - phy-reset
+- resets: Must contain an entry for each entry in reset-names.
 
 Example:
 
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
index 2a7381f..734987f 100644
--- a/drivers/phy/phy-rockchip-usb.c
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 
 static int enable_usb_uart;
 
@@ -64,6 +65,7 @@ struct rockchip_usb_phy {
struct clk_hw   clk480m_hw;
struct phy  *phy;
booluart_enabled;
+   struct reset_control *reset;
 };
 
 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
@@ -144,9 +146,23 @@ static int rockchip_usb_phy_power_on(struct phy *_phy)
return clk_prepare_enable(phy->clk480m);
 }
 
+static int rockchip_usb_phy_reset(struct phy *_phy)
+{
+   struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+
+   if (phy->reset) {
+   reset_control_assert(phy->reset);
+   udelay(10);
+   reset_control_deassert(phy->reset);
+   }
+
+   return 0;
+}
+
 static const struct phy_ops ops = {
.power_on   = rockchip_usb_phy_power_on,
.power_off  = rockchip_usb_phy_power_off,
+   .reset  = rockchip_usb_phy_reset,
.owner  = THIS_MODULE,
 };
 
@@ -185,6 +201,10 @@ static int rockchip_usb_phy_init(struct 
rockchip_usb_phy_base *base,
return -EINVAL;
}
 
+   rk_phy->reset = of_reset_control_get(child, "phy-reset");
+   if (IS_ERR(rk_phy->reset))
+   rk_phy->reset = NULL;
+
rk_phy->reg_offset = reg_offset;
 
rk_phy->clk = of_clk_get_by_name(child, "phyclk");
-- 
2.7.4

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[PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform

[Randy Li]

changelog:
v7
  Some minor fixup
v6
  Send the last two patches
v5
  A few modification at style, add the missing doc in the last 
  commit.
v4
  1. Adding the reset callback in struct phy_ops.
  2. Moving the reset into phy rockchip usb.
  3. Trying to call a reset when dwc2 wakeup in rk3288.
v3
 Rebased from previous commit.

Randy Li (4):
  phy: Add reset callback
  phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during
wakeup
  usb: dwc2: assert phy reset when waking up in rk3288 platform
  ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

 .../devicetree/bindings/phy/rockchip-usb-phy.txt |  3 +++
 arch/arm/boot/dts/rk3288.dtsi|  4 
 drivers/phy/phy-rockchip-usb.c   | 20 
 drivers/usb/dwc2/core_intr.c | 12 
 include/linux/phy/phy.h  |  2 ++
 5 files changed, 41 insertions(+)

-- 
2.7.4

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[PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Randy Li]

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit) in chip, which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 drivers/usb/dwc2/core_intr.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index d85c5c9..08485b7 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg 
*hsotg)
 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 {
int ret;
+   struct device_node *np = hsotg->dev->of_node;
 
/* Clear interrupt */
dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
@@ -379,6 +380,17 @@ static void dwc2_handle_wakeup_detected_intr(struct 
dwc2_hsotg *hsotg)
/* Restart the Phy Clock */
pcgcctl &= ~PCGCTL_STOPPCLK;
dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+
+   /*
+* It is a quirk in Rockchip RK3288, causing by
+* a hardware bug. This will propagate out and
+* eventually we'll re-enumerate the device. 
+* Not great but the best we can do 
+*/
+   if (of_device_is_compatible(np, "rockchip,rk3288-usb")
+   && (NULL != hsotg->phy->ops->reset))
+   hsotg->phy->ops->reset(hsotg->phy);
+
mod_timer(>wkp_timer,
  jiffies + msecs_to_jiffies(71));
} else {
-- 
2.7.4

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Re: [RESEND PATCH 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Randy Li]

On 08/24/2016 04:46 AM, John Youn wrote:

On 8/21/2016 12:32 PM, Randy Li wrote:

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit) in chip, which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 drivers/usb/dwc2/core_intr.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index d85c5c9..f57c48a 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg 
*hsotg)
 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 {
int ret;
+   struct device_node *np = hsotg->dev->of_node;

/* Clear interrupt */
dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
@@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct 
dwc2_hsotg *hsotg)
/* Restart the Phy Clock */
pcgcctl &= ~PCGCTL_STOPPCLK;
dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+
+   /*
+* It is a quirk in Rockchip RK3288, causing by
+* a hardware bug. This will propagate out and
+* eventually we'll re-enumerate the device.
+* Not great but the best we can do


Remove the trailing whitespaces in this comment.

Run scripts/checkpatch.pl to catch these.

I see.



+*/
+   if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
+   hsotg->phy->ops->reset(hsotg->phy);
+


You should probably check for NULL before calling the reset()
callback.

Sure.


Also, I'd rather see a generic quirk property that you set for your
platform.

Something like "phy_reset_on_wakeup_quirk".
But Rob Herring want me to implied by the SoC specific compatible 
string. I agree with him. It is certainly bug in RK3288 platform.

It is no found no the other platform.


Also, try to preserve the version tag in your subject for all the
patches so that we can easily identify the latest version of the
series, like:

[PATCH v5 3/4] ...

And, typically "RESEND" means there are no code change.

I see, I just make up my mind whether code style is new version
before. I won't again.

Thank you very much.


Regards,
John

___
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--
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[RESEND PATCH 4/4] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

[Randy Li]

The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288
has a hardware errata that causes everything to get confused when we get
a remote wakeup.  We'll use the reset that's in the CRU to reset the
port when it's in a bad state.

Note that we add the reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata.  Only the host port gets the
quirk property, though.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 arch/arm/boot/dts/rk3288.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 48ca4e4..de54604 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -855,6 +855,8 @@
clocks = < SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBOTG_PHY>;
+   reset-names = "phy-reset";
};
 
usbphy1: usb-phy@334 {
@@ -871,6 +873,8 @@
clocks = < SCLK_OTGPHY2>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBHOST1_PHY>;
+   reset-names = "phy-reset";
};
};
};
-- 
2.7.4

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[RESEND PATCH 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Randy Li]

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit) in chip, which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 drivers/usb/dwc2/core_intr.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index d85c5c9..f57c48a 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg 
*hsotg)
 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 {
int ret;
+   struct device_node *np = hsotg->dev->of_node;
 
/* Clear interrupt */
dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
@@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct 
dwc2_hsotg *hsotg)
/* Restart the Phy Clock */
pcgcctl &= ~PCGCTL_STOPPCLK;
dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+
+   /* 
+* It is a quirk in Rockchip RK3288, causing by
+* a hardware bug. This will propagate out and
+* eventually we'll re-enumerate the device. 
+* Not great but the best we can do 
+*/
+   if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
+   hsotg->phy->ops->reset(hsotg->phy);
+
mod_timer(>wkp_timer,
  jiffies + msecs_to_jiffies(71));
} else {
-- 
2.7.4

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[PATCH 0/4 v5] usb: dwc2: fix the usb host for host port at RK32

[Randy Li]

Hello All:
 This version would move reset into phy. I wanted to implement a hard
code version but I meet some problem with ioremap reset controller,
in order to keep my word, I offer this version this time.

Changelog:
v5
  A few modification at style, add the missing doc in the last 
  commit.
v4
  1. Adding the reset callback in struct phy_ops.
  2. Moving the reset into phy rockchip usb.
  3. Trying to call a reset when dwc2 wakeup in rk3288.
v3
 Rebased from previous commit.

Randy Li (4):
  phy: Add reset callback
  phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during
wakeup
  usb: dwc2: assert phy reset when waking up in rk3288 platform
  ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

 arch/arm/boot/dts/rk3288.dtsi  |  5 +
 drivers/phy/phy-rockchip-usb.c | 20 
 drivers/usb/dwc2/core_intr.c   |  9 +
 include/linux/phy/phy.h|  2 ++
 4 files changed, 36 insertions(+)

-- 
2.7.4

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[PATCH 1/4] phy: Add reset callback

[Randy Li]

The only use for this is for solving a hardware design problem in
usb of Rockchip RK3288.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 include/linux/phy/phy.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index f08b672..4d34607 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -36,6 +36,7 @@ enum phy_mode {
  * @power_on: powering on the phy
  * @power_off: powering off the phy
  * @set_mode: set the mode of the phy
+ * @reset: reseting the phy
  * @owner: the module owner containing the ops
  */
 struct phy_ops {
@@ -44,6 +45,7 @@ struct phy_ops {
int (*power_on)(struct phy *phy);
int (*power_off)(struct phy *phy);
int (*set_mode)(struct phy *phy, enum phy_mode mode);
+   int (*reset)(struct phy *phy);
struct module *owner;
 };
 
-- 
2.7.4

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[PATCH 4/4] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

[Randy Li]

The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288
has a hardware errata that causes everything to get confused when we get
a remote wakeup.  We'll use the reset that's in the CRU to reset the
port when it's in a bad state.

Note that we add the reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata.  Only the host port gets the
quirk property, though.

This patch came from Doug Anderson <diand...@chromium.org> originally.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 arch/arm/boot/dts/rk3288.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 48ca4e4..646f49d 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -855,6 +855,8 @@
clocks = < SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBOTG_PHY>;
+   reset-names = "phy-reset";
};
 
usbphy1: usb-phy@334 {
@@ -871,6 +873,9 @@
clocks = < SCLK_OTGPHY2>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBHOST1_PHY>;
+   reset-names = "phy-reset";
+
};
};
};
-- 
2.7.4

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[PATCH 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Randy Li]

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit) in chip, which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

The original patches came from Doug Anderson <diand...@chromium.org>.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 drivers/usb/dwc2/core_intr.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index d85c5c9..f57c48a 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg 
*hsotg)
 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 {
int ret;
+   struct device_node *np = hsotg->dev->of_node;
 
/* Clear interrupt */
dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
@@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct 
dwc2_hsotg *hsotg)
/* Restart the Phy Clock */
pcgcctl &= ~PCGCTL_STOPPCLK;
dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+
+   /* 
+* It is a quirk in Rockchip RK3288, causing by
+* a hardware bug. This will propagate out and
+* eventually we'll re-enumerate the device. 
+* Not great but the best we can do 
+*/
+   if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
+   hsotg->phy->ops->reset(hsotg->phy);
+
mod_timer(>wkp_timer,
  jiffies + msecs_to_jiffies(71));
} else {
-- 
2.7.4

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[PATCH 2/4] phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during wakeup

[Randy Li]

It is a hardware bug in RK3288, the only way to solve it is to
reset the phy.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 .../devicetree/bindings/phy/rockchip-usb-phy.txt |  3 +++
 drivers/phy/phy-rockchip-usb.c   | 20 
 2 files changed, 23 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt 
b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
index cc6be96..57dc388 100644
--- a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -27,6 +27,9 @@ Optional Properties:
 - clocks : phandle + clock specifier for the phy clocks
 - clock-names: string, clock name, must be "phyclk"
 - #clock-cells: for users of the phy-pll, should be 0
+- reset-names: Only allow the following entries:
+ - phy-reset
+- resets: Must contain an entry for each entry in reset-names.
 
 Example:
 
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
index 2a7381f..734987f 100644
--- a/drivers/phy/phy-rockchip-usb.c
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 
 static int enable_usb_uart;
 
@@ -64,6 +65,7 @@ struct rockchip_usb_phy {
struct clk_hw   clk480m_hw;
struct phy  *phy;
booluart_enabled;
+   struct reset_control *reset;
 };
 
 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
@@ -144,9 +146,23 @@ static int rockchip_usb_phy_power_on(struct phy *_phy)
return clk_prepare_enable(phy->clk480m);
 }
 
+static int rockchip_usb_phy_reset(struct phy *_phy)
+{
+   struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+
+   if (phy->reset) {
+   reset_control_assert(phy->reset);
+   udelay(10);
+   reset_control_deassert(phy->reset);
+   }
+
+   return 0;
+}
+
 static const struct phy_ops ops = {
.power_on   = rockchip_usb_phy_power_on,
.power_off  = rockchip_usb_phy_power_off,
+   .reset  = rockchip_usb_phy_reset,
.owner  = THIS_MODULE,
 };
 
@@ -185,6 +201,10 @@ static int rockchip_usb_phy_init(struct 
rockchip_usb_phy_base *base,
return -EINVAL;
}
 
+   rk_phy->reset = of_reset_control_get(child, "phy-reset");
+   if (IS_ERR(rk_phy->reset))
+   rk_phy->reset = NULL;
+
rk_phy->reg_offset = reg_offset;
 
rk_phy->clk = of_clk_get_by_name(child, "phyclk");
-- 
2.7.4

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[PATCH 2/4] phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during wakeup

[Randy Li]

It is a hardware bug in RK3288, the only way to solve it is to
reset the phy.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 drivers/phy/phy-rockchip-usb.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
index 2a7381f..734987f 100644
--- a/drivers/phy/phy-rockchip-usb.c
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 
 static int enable_usb_uart;
 
@@ -64,6 +65,7 @@ struct rockchip_usb_phy {
struct clk_hw   clk480m_hw;
struct phy  *phy;
booluart_enabled;
+   struct reset_control *reset;
 };
 
 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
@@ -144,9 +146,23 @@ static int rockchip_usb_phy_power_on(struct phy *_phy)
return clk_prepare_enable(phy->clk480m);
 }
 
+static int rockchip_usb_phy_reset(struct phy *_phy)
+{
+   struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+
+   if (phy->reset) {
+   reset_control_assert(phy->reset);
+   udelay(10);
+   reset_control_deassert(phy->reset);
+   }
+
+   return 0;
+}
+
 static const struct phy_ops ops = {
.power_on   = rockchip_usb_phy_power_on,
.power_off  = rockchip_usb_phy_power_off,
+   .reset  = rockchip_usb_phy_reset,
.owner  = THIS_MODULE,
 };
 
@@ -185,6 +201,10 @@ static int rockchip_usb_phy_init(struct 
rockchip_usb_phy_base *base,
return -EINVAL;
}
 
+   rk_phy->reset = of_reset_control_get(child, "phy-reset");
+   if (IS_ERR(rk_phy->reset))
+   rk_phy->reset = NULL;
+
rk_phy->reg_offset = reg_offset;
 
rk_phy->clk = of_clk_get_by_name(child, "phyclk");
-- 
2.7.4

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[PATCH 4/4] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

[Randy Li]

The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288
has a hardware errata that causes everything to get confused when we get
a remote wakeup.  We'll use the reset that's in the CRU to reset the
port when it's in a bad state.

Note that we add the reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata.  Only the host port gets the
quirk property, though.

This patch came from Doug Anderson <diand...@chromium.org> originally.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 arch/arm/boot/dts/rk3288.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 48ca4e4..646f49d 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -855,6 +855,8 @@
clocks = < SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBOTG_PHY>;
+   reset-names = "phy-reset";
};
 
usbphy1: usb-phy@334 {
@@ -871,6 +873,9 @@
clocks = < SCLK_OTGPHY2>;
clock-names = "phyclk";
#clock-cells = <0>;
+   resets = < SRST_USBHOST1_PHY>;
+   reset-names = "phy-reset";
+
};
};
};
-- 
2.7.4

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[PATCH 1/4] phy: Add reset callback

[Randy Li]

The only use for this is for solving a hardware design problem in
usb of Rockchip RK3288.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 include/linux/phy/phy.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index f08b672..4d34607 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -36,6 +36,7 @@ enum phy_mode {
  * @power_on: powering on the phy
  * @power_off: powering off the phy
  * @set_mode: set the mode of the phy
+ * @reset: reseting the phy
  * @owner: the module owner containing the ops
  */
 struct phy_ops {
@@ -44,6 +45,7 @@ struct phy_ops {
int (*power_on)(struct phy *phy);
int (*power_off)(struct phy *phy);
int (*set_mode)(struct phy *phy, enum phy_mode mode);
+   int (*reset)(struct phy *phy);
struct module *owner;
 };
 
-- 
2.7.4

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[PATCH 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Randy Li]

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit) in chip, which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

The original patches came from Doug Anderson <diand...@chromium.org>.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 drivers/usb/dwc2/core_intr.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index d85c5c9..c31c3fe 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg 
*hsotg)
 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 {
int ret;
+   struct device_node *np = hsotg->dev->of_node;
 
/* Clear interrupt */
dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
@@ -379,6 +380,14 @@ static void dwc2_handle_wakeup_detected_intr(struct 
dwc2_hsotg *hsotg)
/* Restart the Phy Clock */
pcgcctl &= ~PCGCTL_STOPPCLK;
dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+
+   /* It is a quirk in Rockchip RK3288, causing by
+* a hardware bug. This will propagate out and
+* eventually we'll re-enumerate the device. 
+* Not great but the best we can do */
+   if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
+   hsotg->phy->ops->reset(hsotg->phy);
+
mod_timer(>wkp_timer,
  jiffies + msecs_to_jiffies(71));
} else {
-- 
2.7.4

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[PATCH 0/4 v4] usb: dwc2: fix the usb host for host port at RK32

[Randy Li]

Hello All:
 This version would move reset into phy. I wanted to implement a hard
code version but I meet some problem with ioremap reset controller,
in order to keep my word, I offer this version this time.

Randy Li (4):
  phy: Add reset callback
  phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during
wakeup
  usb: dwc2: assert phy reset when waking up in rk3288 platform
  ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

 arch/arm/boot/dts/rk3288.dtsi  |  5 +
 drivers/phy/phy-rockchip-usb.c | 20 
 drivers/usb/dwc2/core_intr.c   |  9 +
 include/linux/phy/phy.h|  2 ++
 4 files changed, 36 insertions(+)

-- 
2.7.4

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Re: [PATCH 1/2] usb: dwc2: optionally assert phy "full reset" when waking up

[Randy Li]

On 08/16/2016 06:19 AM, John Youn wrote:

On 7/19/2016 5:06 AM, Randy Li wrote:

From: Doug Anderson <diand...@chromium.org>

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend). The problem is caused by a design fault in IC, Rockchip
have confirmed it and fix this problem in the future IC model.

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit), which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Yunzhi Li <l...@rock-chips.com>
Reviewed-by: Randy Li <randy...@rock-chips.com>
---
 Documentation/devicetree/bindings/usb/dwc2.txt |  7 +++
 drivers/usb/dwc2/core.h|  5 +
 drivers/usb/dwc2/core_intr.c   | 14 ++
 drivers/usb/dwc2/platform.c| 13 +
 4 files changed, 39 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt 
b/Documentation/devicetree/bindings/usb/dwc2.txt
index 20a68bf..40c63ae 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -20,6 +20,13 @@ Refer to clk/clock-bindings.txt for generic clock consumer 
properties
 Optional properties:
 - phys: phy provider specifier
 - phy-names: shall be "usb2-phy"
+- snps,need-phy-full-reset-on-wake: if present indicates that we need to reset
+  the PHY when we detect a wakeup due to a hardware errata.  If present you
+  must specify a "phy-full-reset" reset.
+
+Resets:
+- phy-full-reset (optional): Fully resets the PHY (Only used by rk3288 Soc).
+
 Refer to phy/phy-bindings.txt for generic phy consumer properties
 - dr_mode: shall be one of "host", "peripheral" and "otg"
   Refer to usb/generic.txt
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index dec0b21..951abe0 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -719,8 +719,11 @@ struct dwc2_hregs_backup {
  * @hcd_enabledHost mode sub-driver initialization indicator.
  * @gadget_enabled Peripheral mode sub-driver initialization indicator.
  * @ll_hw_enabled  Status of low-level hardware resources.
+ * @need_phy_full_reset_on_wake: Quirk saying that we should assert
+ *   phy_full_reset on a remote wakeup.
  * @phy:The otg phy transceiver structure for phy control.
  * @uphy:   The otg phy transceiver structure for old USB phy 
control.
+ * @phy_full_reset: Reset control for the PHY's "full reset".
  * @plat:   The platform specific configuration data. This can be 
removed once
  *  all SoCs support usb transceiver.
  * @supplies:   Definition of USB power supplies
@@ -853,9 +856,11 @@ struct dwc2_hsotg {
unsigned int hcd_enabled:1;
unsigned int gadget_enabled:1;
unsigned int ll_hw_enabled:1;
+   unsigned int need_phy_full_reset_on_wake:1;

struct phy *phy;
struct usb_phy *uphy;
+   struct reset_control *phy_full_reset;
struct dwc2_hsotg_plat *plat;
struct regulator_bulk_data 
supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)];
u32 phyif;
diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index d85c5c9..53d8327 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -45,6 +45,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 

 #include 
@@ -379,6 +380,19 @@ static void dwc2_handle_wakeup_detected_intr(struct 
dwc2_hsotg *hsotg)
/* Restart the Phy Clock */
pcgcctl &= ~PCGCTL_STOPPCLK;
dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+
+   /*
+* If we've got this quirk then the PHY is stuck upon
+* wakeup.  Assert reset.  This will propagate out and
+* eventually we'll re-enumerate the device.  Not great
+* but the best we can do.
+*/
+   if (hsotg->need_phy_full_reset_on_wake) {
+ 

Re: [PATCH 1/2] usb: dwc2: optionally assert phy "full reset" when waking up

[Randy Li]

Thank you for reviewing, if you agree with my opinion, I would implement 
a new version as soon as  possible.



On 07/20/2016 09:36 AM, Rob Herring wrote:

On Tue, Jul 19, 2016 at 08:05:33PM +0800, Randy Li wrote:

From: Doug Anderson <diand...@chromium.org>

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend). The problem is caused by a design fault in IC, Rockchip
have confirmed it and fix this problem in the future IC model.

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit), which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Yunzhi Li <l...@rock-chips.com>
Reviewed-by: Randy Li <randy...@rock-chips.com>
---
  Documentation/devicetree/bindings/usb/dwc2.txt |  7 +++
  drivers/usb/dwc2/core.h|  5 +
  drivers/usb/dwc2/core_intr.c   | 14 ++
  drivers/usb/dwc2/platform.c| 13 +
  4 files changed, 39 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt 
b/Documentation/devicetree/bindings/usb/dwc2.txt
index 20a68bf..40c63ae 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -20,6 +20,13 @@ Refer to clk/clock-bindings.txt for generic clock consumer 
properties
  Optional properties:
  - phys: phy provider specifier
  - phy-names: shall be "usb2-phy"
+- snps,need-phy-full-reset-on-wake: if present indicates that we need to reset

Bikeshedding, but 'snps,full-phy-reset-on-wake' is slightly shorter.

However, this isn't really even needed. It should be implied by the SoC
specific compatible string.

I would.



+  the PHY when we detect a wakeup due to a hardware errata.  If present you
+  must specify a "phy-full-reset" reset.
+
+Resets:
+- phy-full-reset (optional): Fully resets the PHY (Only used by rk3288 Soc).

This property belows in the phy node as that is where the reset is
attached to and why is it not using the standard binding "resets"?
Because the struct phy_ops doesn't have something like reset method. It 
is impossible to make a phy reset now. Also maybe it is not need to 
define a reset at dts, just implied do that reset that in code(as the 
way to reset is always same and only used by rk3288).


Rob



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Randy Li
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[PATCH 1/2] usb: dwc2: optionally assert phy "full reset" when waking up

[Randy Li]

From: Doug Anderson <diand...@chromium.org>

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend). The problem is caused by a design fault in IC, Rockchip
have confirmed it and fix this problem in the future IC model.

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit), which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Yunzhi Li <l...@rock-chips.com>
Reviewed-by: Randy Li <randy...@rock-chips.com>
---
 Documentation/devicetree/bindings/usb/dwc2.txt |  7 +++
 drivers/usb/dwc2/core.h|  5 +
 drivers/usb/dwc2/core_intr.c   | 14 ++
 drivers/usb/dwc2/platform.c| 13 +
 4 files changed, 39 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt 
b/Documentation/devicetree/bindings/usb/dwc2.txt
index 20a68bf..40c63ae 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -20,6 +20,13 @@ Refer to clk/clock-bindings.txt for generic clock consumer 
properties
 Optional properties:
 - phys: phy provider specifier
 - phy-names: shall be "usb2-phy"
+- snps,need-phy-full-reset-on-wake: if present indicates that we need to reset
+  the PHY when we detect a wakeup due to a hardware errata.  If present you
+  must specify a "phy-full-reset" reset.
+
+Resets:
+- phy-full-reset (optional): Fully resets the PHY (Only used by rk3288 Soc).
+
 Refer to phy/phy-bindings.txt for generic phy consumer properties
 - dr_mode: shall be one of "host", "peripheral" and "otg"
   Refer to usb/generic.txt
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index dec0b21..951abe0 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -719,8 +719,11 @@ struct dwc2_hregs_backup {
  * @hcd_enabledHost mode sub-driver initialization indicator.
  * @gadget_enabled Peripheral mode sub-driver initialization indicator.
  * @ll_hw_enabled  Status of low-level hardware resources.
+ * @need_phy_full_reset_on_wake: Quirk saying that we should assert
+ *   phy_full_reset on a remote wakeup.
  * @phy:The otg phy transceiver structure for phy control.
  * @uphy:   The otg phy transceiver structure for old USB phy 
control.
+ * @phy_full_reset: Reset control for the PHY's "full reset".
  * @plat:   The platform specific configuration data. This can be 
removed once
  *  all SoCs support usb transceiver.
  * @supplies:   Definition of USB power supplies
@@ -853,9 +856,11 @@ struct dwc2_hsotg {
unsigned int hcd_enabled:1;
unsigned int gadget_enabled:1;
unsigned int ll_hw_enabled:1;
+   unsigned int need_phy_full_reset_on_wake:1;
 
struct phy *phy;
struct usb_phy *uphy;
+   struct reset_control *phy_full_reset;
struct dwc2_hsotg_plat *plat;
struct regulator_bulk_data 
supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)];
u32 phyif;
diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index d85c5c9..53d8327 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -45,6 +45,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -379,6 +380,19 @@ static void dwc2_handle_wakeup_detected_intr(struct 
dwc2_hsotg *hsotg)
/* Restart the Phy Clock */
pcgcctl &= ~PCGCTL_STOPPCLK;
dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+
+   /*
+* If we've got this quirk then the PHY is stuck upon
+* wakeup.  Assert reset.  This will propagate out and
+* eventually we'll re-enumerate the device.  Not great
+* but the best we can do.
+*/
+   if (hsotg->need_phy_full_reset_on_wake) {
+   reset_control_assert(hsotg->phy_full_reset);
+

[PATCH 2/2] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

[Randy Li]

From: Doug Anderson 

The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288
has a hardware errata that causes everything to get confused when we get
a remote wakeup.  We'll use the reset that's in the CRU to reset the
port when it's in a bad state.

Note that we add the reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata.  Only the host port gets the
quirk property, though.

Signed-off-by: Douglas Anderson 
---
 arch/arm/boot/dts/rk3288.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 3b44ef3..94fa26f 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -578,6 +578,9 @@
dr_mode = "host";
phys = <>;
phy-names = "usb2-phy";
+   resets = < SRST_USBHOST1_PHY>;
+   reset-names = "phy-full-reset";
+   snps,need-phy-full-reset-on-wake;
status = "disabled";
};
 
@@ -595,6 +598,8 @@
g-use-dma;
phys = <>;
phy-names = "usb2-phy";
+   resets = < SRST_USBOTG_PHY>;
+   reset-names = "phy-full-reset";
status = "disabled";
};
 
-- 
2.7.4


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[PATCH v3 0/2] usb: dwc2: fix the usb host for host port at RK3288

[Randy Li]

Hi, the implementation of Doug is thought quick but the Herring 
want to use this problem in autosuspend. Unfortunately, It is a fault
in hardware, onyl would happened at Rockchip RK3288 now.

So I suggest to accept this idea. It may be better if dropped
the dts,  as it is an issue only for RK3288, just hard-code to
source code. If maintainer would agree with the later one, I would
send the other version to the list.

Thank you for using of Rockchip.

Doug Anderson (2):
  usb: dwc2: optionally assert phy "full reset" when waking up
  ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

 Documentation/devicetree/bindings/usb/dwc2.txt |  7 +++
 arch/arm/boot/dts/rk3288.dtsi  |  5 +
 drivers/usb/dwc2/core.h|  5 +
 drivers/usb/dwc2/core_intr.c   | 14 ++
 drivers/usb/dwc2/platform.c| 13 +
 5 files changed, 44 insertions(+)

-- 
2.7.4


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Re: need some info about WCH ch341

[Randy Li]

于 2013年01月18日 08:21, Greg KH 写道:

On Fri, Jan 18, 2013 at 08:12:33AM +0800, Randy Li wrote:

I am going to write the driver for ch341a SPI function. When I
readed the driver/usb/serial/ch341.c , I think that ch341 use vender
usb request and request type( non-standard usb request and request
type) or I may be wrong. But how does the writer of ch341.c knew
those infomation, I don't find those info from official pdf?

I don't know where the information came from, does it matter?
I want to write a driver for its SPI function, I think I need to know 
the meanings of those usb request and request type in the serial driver 
of ch341 and where it is from .

P.S ch341 is a serial of chips including ch341a, ch341t, ch341h,
ch341a is full funtions but t and h aren't.

So you are saying the existing ch341 driver doesn't support all of the
chips you need it to?  Feel free to send patches that add support for
the other chips.
I mean the comment at the begining of ch341.c may need some change, but 
it doesn't matter.

thanks,

greg k-h
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Thank you


-
ayaka
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