Re: [PATCH 4/5] phy: add Marvell HSIC 28nm PHY

2015-05-26 Thread Kishon Vijay Abraham I 

Hi,

On Saturday 23 May 2015 01:24 AM, Rob Herring wrote:

On Thu, May 21, 2015 at 7:51 AM, Kishon Vijay Abraham I kis...@ti.com wrote:

On Thursday 21 May 2015 06:15 PM, Kishon Vijay Abraham I wrote:


Hi,

On Thursday 14 May 2015 04:18 AM, Rob Herring wrote:


Add PHY driver for the Marvell HSIC 28nm PHY. This PHY is found in
PXA1928
SOC.


[...]


+   writel(readl(base + PHY_28NM_HSIC_CTRL) 
~PHY_28NM_HSIC_S2H_HSIC_EN,
+   base + PHY_28NM_HSIC_CTRL);
+
+   clk_disable_unprepare(mv_phy-clk);
+   return 0;
+}
+
+static const struct phy_ops hsic_ops = {
+   .init   = mv_hsic_phy_init,
+   .power_on   = mv_hsic_phy_power_on,
+   .power_off  = mv_hsic_phy_power_off,



exit callback is missing? Shouldn't we turn off the PLLs in exit callback?


I really don't understand the division of the ops functions. It seems
backwards to me. Don't you need to power on the phy before you can
initialize it? Or init is supposed to be s/w init of some kind.


Generally the order is init and then power on. During init the driver can 
perform the various setting for initializing the PHY which includes PLL 
programming, calibration etc.. And then power on which actually starts the PHY 
so that PHY can now transfer and receive data.

AFAICT, all the drivers just call init and power_on back to back.



Also add the .owner member since this driver can be used as module.


Strange. Generally an ops struct just has ops.


phy-core has a call to try_module_get with this .owner so that the module is 
not removed after phy_get. Maybe we can make phy-core to handle it in some 
other way. Need to check.


Thanks
Kishon
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Re: [PATCH 4/5] phy: add Marvell HSIC 28nm PHY

2015-05-22 Thread Rob Herring 
On Thu, May 21, 2015 at 7:51 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
 On Thursday 21 May 2015 06:15 PM, Kishon Vijay Abraham I wrote:

 Hi,

 On Thursday 14 May 2015 04:18 AM, Rob Herring wrote:

 Add PHY driver for the Marvell HSIC 28nm PHY. This PHY is found in
 PXA1928
 SOC.

[...]

 +   writel(readl(base + PHY_28NM_HSIC_CTRL) 
 ~PHY_28NM_HSIC_S2H_HSIC_EN,
 +   base + PHY_28NM_HSIC_CTRL);
 +
 +   clk_disable_unprepare(mv_phy-clk);
 +   return 0;
 +}
 +
 +static const struct phy_ops hsic_ops = {
 +   .init   = mv_hsic_phy_init,
 +   .power_on   = mv_hsic_phy_power_on,
 +   .power_off  = mv_hsic_phy_power_off,


 exit callback is missing? Shouldn't we turn off the PLLs in exit callback?

I really don't understand the division of the ops functions. It seems
backwards to me. Don't you need to power on the phy before you can
initialize it? Or init is supposed to be s/w init of some kind.
AFAICT, all the drivers just call init and power_on back to back.


 Also add the .owner member since this driver can be used as module.

Strange. Generally an ops struct just has ops.

Rob
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Re: [PATCH 4/5] phy: add Marvell HSIC 28nm PHY

2015-05-21 Thread Kishon Vijay Abraham I 

Hi,

On Thursday 14 May 2015 04:18 AM, Rob Herring wrote:

Add PHY driver for the Marvell HSIC 28nm PHY. This PHY is found in PXA1928
SOC.

Signed-off-by: Rob Herring r...@kernel.org
Cc: Kishon Vijay Abraham I kis...@ti.com
---
  drivers/phy/Kconfig   |  10 +++
  drivers/phy/Makefile  |   1 +
  drivers/phy/phy-mv-hsic.c | 208 ++
  3 files changed, 219 insertions(+)
  create mode 100644 drivers/phy/phy-mv-hsic.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index ef7634f..cfcae72 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -52,6 +52,16 @@ config PHY_EXYNOS_MIPI_VIDEO
  Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
  and EXYNOS SoCs.

+config PHY_MV_HSIC
+   tristate Marvell USB HSIC 28nm PHY Driver
+   select GENERIC_PHY
+   help
+ Enable this to support Marvell USB HSIC PHY driver for Marvell
+ SoC. This driver will do the PHY initialization and shutdown.
+ The PHY driver will be used by Marvell ehci driver.
+
+ To compile this driver as a module, choose M here.
+
  config PHY_MV_USB2
tristate Marvell USB 2.0 28nm PHY Driver
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 768e55a..472bf0a 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY)+= 
phy-armada375-usb2.o
  obj-$(CONFIG_BCM_KONA_USB2_PHY)   += phy-bcm-kona-usb2.o
  obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
  obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)   += phy-exynos-mipi-video.o
+obj-$(CONFIG_PHY_MV_HSIC)  += phy-mv-hsic.o
  obj-$(CONFIG_PHY_MV_USB2) += phy-mv-usb2.o
  obj-$(CONFIG_PHY_MVEBU_SATA)  += phy-mvebu-sata.o
  obj-$(CONFIG_PHY_MIPHY28LP)   += phy-miphy28lp.o
diff --git a/drivers/phy/phy-mv-hsic.c b/drivers/phy/phy-mv-hsic.c
new file mode 100644
index 000..aa6cccd
--- /dev/null
+++ b/drivers/phy/phy-mv-hsic.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (C) 2015 Linaro, Ltd.
+ * Rob Herring r...@kernel.org
+ *
+ * Based on vendor driver:
+ * Copyright (C) 2013 Marvell Inc.
+ * Author: Chao Xie xiechao.m...@gmail.com
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include linux/delay.h
+#include linux/slab.h
+#include linux/of.h
+#include linux/io.h
+#include linux/err.h
+#include linux/clk.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/phy/phy.h
+
+#define PHY_28NM_HSIC_CTRL 0x08
+#define PHY_28NM_HSIC_IMPCAL_CAL   0x18
+#define PHY_28NM_HSIC_PLL_CTRL01   0x1c
+#define PHY_28NM_HSIC_PLL_CTRL20x20
+#define PHY_28NM_HSIC_INT  0x28
+
+#define PHY_28NM_HSIC_PLL_SELLPFR_SHIFT26
+#define PHY_28NM_HSIC_PLL_FBDIV_SHIFT  0
+#define PHY_28NM_HSIC_PLL_REFDIV_SHIFT 9
+
+#define PHY_28NM_HSIC_S2H_PU_PLL   BIT(10)
+#define PHY_28NM_HSIC_H2S_PLL_LOCK BIT(15)
+#define PHY_28NM_HSIC_S2H_HSIC_EN  BIT(7)
+#define S2H_DRV_SE0_4RESUMEBIT(14)
+#define PHY_28NM_HSIC_H2S_IMPCAL_DONE  BIT(27)
+
+#define PHY_28NM_HSIC_CONNECT_INT  BIT(1)
+#define PHY_28NM_HSIC_HS_READY_INT BIT(2)
+
+struct mv_hsic_phy {
+   struct phy  *phy;
+   struct platform_device  *pdev;
+   void __iomem*base;
+   struct clk  *clk;
+};
+
+static bool wait_for_reg(void __iomem *reg, u32 mask, unsigned long timeout)
+{
+   timeout += jiffies;
+   while (time_is_after_eq_jiffies(timeout)) {
+   if ((readl(reg)  mask) == mask)
+   return true;
+   msleep(1);
+   }
+   return false;
+}
+
+static int mv_hsic_phy_init(struct phy *phy)
+{
+   struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy);
+   struct platform_device *pdev = mv_phy-pdev;
+   void __iomem *base = mv_phy-base;
+
+   clk_prepare_enable(mv_phy-clk);
+
+   /* Set reference clock */
+   writel(0x1  PHY_28NM_HSIC_PLL_SELLPFR_SHIFT |
+   0xf0  PHY_28NM_HSIC_PLL_FBDIV_SHIFT |
+   0xd  PHY_28NM_HSIC_PLL_REFDIV_SHIFT,
+   base + PHY_28NM_HSIC_PLL_CTRL01);
+
+   /* Turn on PLL */
+   writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) |
+   PHY_28NM_HSIC_S2H_PU_PLL,
+   base + PHY_28NM_HSIC_PLL_CTRL2);
+
+   /* Make sure PHY PLL is locked */
+   if

Re: [PATCH 4/5] phy: add Marvell HSIC 28nm PHY

2015-05-21 Thread Kishon Vijay Abraham I 



On Thursday 21 May 2015 06:15 PM, Kishon Vijay Abraham I wrote:

Hi,

On Thursday 14 May 2015 04:18 AM, Rob Herring wrote:

Add PHY driver for the Marvell HSIC 28nm PHY. This PHY is found in PXA1928
SOC.

Signed-off-by: Rob Herring r...@kernel.org
Cc: Kishon Vijay Abraham I kis...@ti.com
---
   drivers/phy/Kconfig   |  10 +++
   drivers/phy/Makefile  |   1 +
   drivers/phy/phy-mv-hsic.c | 208 
++
   3 files changed, 219 insertions(+)
   create mode 100644 drivers/phy/phy-mv-hsic.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index ef7634f..cfcae72 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -52,6 +52,16 @@ config PHY_EXYNOS_MIPI_VIDEO
  Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
  and EXYNOS SoCs.

+config PHY_MV_HSIC
+   tristate Marvell USB HSIC 28nm PHY Driver
+   select GENERIC_PHY
+   help
+ Enable this to support Marvell USB HSIC PHY driver for Marvell
+ SoC. This driver will do the PHY initialization and shutdown.
+ The PHY driver will be used by Marvell ehci driver.
+
+ To compile this driver as a module, choose M here.
+
   config PHY_MV_USB2
tristate Marvell USB 2.0 28nm PHY Driver
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 768e55a..472bf0a 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY)+= 
phy-armada375-usb2.o
   obj-$(CONFIG_BCM_KONA_USB2_PHY)  += phy-bcm-kona-usb2.o
   obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO)+= phy-exynos-dp-video.o
   obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)  += phy-exynos-mipi-video.o
+obj-$(CONFIG_PHY_MV_HSIC)  += phy-mv-hsic.o
   obj-$(CONFIG_PHY_MV_USB2)+= phy-mv-usb2.o
   obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
   obj-$(CONFIG_PHY_MIPHY28LP)  += phy-miphy28lp.o
diff --git a/drivers/phy/phy-mv-hsic.c b/drivers/phy/phy-mv-hsic.c
new file mode 100644
index 000..aa6cccd
--- /dev/null
+++ b/drivers/phy/phy-mv-hsic.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (C) 2015 Linaro, Ltd.
+ * Rob Herring r...@kernel.org
+ *
+ * Based on vendor driver:
+ * Copyright (C) 2013 Marvell Inc.
+ * Author: Chao Xie xiechao.m...@gmail.com
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include linux/delay.h
+#include linux/slab.h
+#include linux/of.h
+#include linux/io.h
+#include linux/err.h
+#include linux/clk.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/phy/phy.h
+
+#define PHY_28NM_HSIC_CTRL 0x08
+#define PHY_28NM_HSIC_IMPCAL_CAL   0x18
+#define PHY_28NM_HSIC_PLL_CTRL01   0x1c
+#define PHY_28NM_HSIC_PLL_CTRL20x20
+#define PHY_28NM_HSIC_INT  0x28
+
+#define PHY_28NM_HSIC_PLL_SELLPFR_SHIFT26
+#define PHY_28NM_HSIC_PLL_FBDIV_SHIFT  0
+#define PHY_28NM_HSIC_PLL_REFDIV_SHIFT 9
+
+#define PHY_28NM_HSIC_S2H_PU_PLL   BIT(10)
+#define PHY_28NM_HSIC_H2S_PLL_LOCK BIT(15)
+#define PHY_28NM_HSIC_S2H_HSIC_EN  BIT(7)
+#define S2H_DRV_SE0_4RESUMEBIT(14)
+#define PHY_28NM_HSIC_H2S_IMPCAL_DONE  BIT(27)
+
+#define PHY_28NM_HSIC_CONNECT_INT  BIT(1)
+#define PHY_28NM_HSIC_HS_READY_INT BIT(2)
+
+struct mv_hsic_phy {
+   struct phy  *phy;
+   struct platform_device  *pdev;
+   void __iomem*base;
+   struct clk  *clk;
+};
+
+static bool wait_for_reg(void __iomem *reg, u32 mask, unsigned long timeout)
+{
+   timeout += jiffies;
+   while (time_is_after_eq_jiffies(timeout)) {
+   if ((readl(reg)  mask) == mask)
+   return true;
+   msleep(1);
+   }
+   return false;
+}
+
+static int mv_hsic_phy_init(struct phy *phy)
+{
+   struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy);
+   struct platform_device *pdev = mv_phy-pdev;
+   void __iomem *base = mv_phy-base;
+
+   clk_prepare_enable(mv_phy-clk);
+
+   /* Set reference clock */
+   writel(0x1  PHY_28NM_HSIC_PLL_SELLPFR_SHIFT |
+   0xf0  PHY_28NM_HSIC_PLL_FBDIV_SHIFT |
+   0xd  PHY_28NM_HSIC_PLL_REFDIV_SHIFT,
+   base + PHY_28NM_HSIC_PLL_CTRL01);
+
+   /* Turn on PLL */
+   writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) |
+   PHY_28NM_HSIC_S2H_PU_PLL,
+   base +