RE: [PATCH v4 3/4] ARM: Exynos5250: Add clock information for dwc3-exynos

2013-01-29 Thread Kukjin Kim 
Vivek Gautam wrote:
 
 Hi Tomasz,
 
 
 On Wed, Jan 16, 2013 at 8:35 PM, Vivek Gautam
 gautamvivek1...@gmail.com wrote:
  Hi Tomasz,
 
 
  On Wed, Jan 16, 2013 at 1:19 PM, Tomasz Figa tomasz.f...@gmail.com
 wrote:
  Hi Vivek,
 
  Don't you need also some clkdev lookup entry to make the clock
available
  in the driver?
 
 
  This clock source we added with a motive of completion, however it's
  not being used as of now.
  As far as i could see the lookup structure contains clocks for devices
  having multiple instances.
  Do you feel that i should be adding an entry in clk_lookup structure ?
  May be i am missing here something. Can you please elaborate on the
  use-case of clk_lookup
  entries.
 
 
 Any suggestions on this please ?
 
Just note, I think you can do it based on Samsung common clock is for all of
exynos stuff which will be done in a couple of days. Sorry for late it,
because there were some problems.

Thanks.

- Kukjin

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Re: [PATCH v4 3/4] ARM: Exynos5250: Add clock information for dwc3-exynos

2013-01-28 Thread Vivek Gautam 
Hi Tomasz,


On Wed, Jan 16, 2013 at 8:35 PM, Vivek Gautam gautamvivek1...@gmail.com wrote:
 Hi Tomasz,


 On Wed, Jan 16, 2013 at 1:19 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
 Hi Vivek,

 Don't you need also some clkdev lookup entry to make the clock available
 in the driver?


 This clock source we added with a motive of completion, however it's
 not being used as of now.
 As far as i could see the lookup structure contains clocks for devices
 having multiple instances.
 Do you feel that i should be adding an entry in clk_lookup structure ?
 May be i am missing here something. Can you please elaborate on the
 use-case of clk_lookup
 entries.


As indicated above sclk_usbdrd30 is added with a motive of
completion, however it's
not being used as of now.
And usbdrd30 is the actual device clock used, where 'drd30' is just
an indicative of
'dual role device and usb 3.0'. So the clock name 'usbdrd30' is the
usb 3.0 clock for drd.

Am i missing something that you wanted to convey here ?


 On Tuesday 15 of January 2013 19:08:31 Vivek Gautam wrote:
 Adding necessary device clock to exynos5 needed for
 the DWC3 controller.

 Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
 ---
  arch/arm/mach-exynos/clock-exynos5.c |   24 
  1 files changed, 24 insertions(+), 0 deletions(-)

 diff --git a/arch/arm/mach-exynos/clock-exynos5.c
 b/arch/arm/mach-exynos/clock-exynos5.c index 0208c3a..13af020 100644
 --- a/arch/arm/mach-exynos/clock-exynos5.c
 +++ b/arch/arm/mach-exynos/clock-exynos5.c
 @@ -757,6 +757,11 @@ static struct clk exynos5_init_clocks_off[] = {
   .enable = exynos5_clk_ip_fsys_ctrl ,
   .ctrlbit= (1  18),
   }, {
 + .name   = usbdrd30,
 + .parent = exynos5_clk_aclk_200.clk,
 + .enable = exynos5_clk_ip_fsys_ctrl,
 + .ctrlbit= (1  19),
 + }, {
   .name   = usbotg,
   .enable = exynos5_clk_ip_fsys_ctrl,
   .ctrlbit= (1  7),
 @@ -1035,6 +1040,16 @@ static struct clksrc_sources exynos5_clkset_group
 = { .nr_sources   = ARRAY_SIZE(exynos5_clkset_group_list),
  };

 +struct clk *exynos5_clkset_usbdrd30_list[] = {
 + [0] = exynos5_clk_mout_mpll.clk,
 + [1] = exynos5_clk_mout_cpll.clk,
 +};
 +
 +struct clksrc_sources exynos5_clkset_usbdrd30 = {
 + .sources= exynos5_clkset_usbdrd30_list,
 + .nr_sources = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
 +};
 +
  /* Possible clock sources for aclk_266_gscl_sub Mux */
  static struct clk *clk_src_gscl_266_list[] = {
   [0] = clk_ext_xtal_mux,
 @@ -1329,6 +1344,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
   .parent = exynos5_clk_mout_cpll.clk,
   },
   .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3
 },
 + }, {
 + .clk= {
 + .name   = sclk_usbdrd30,
 + .enable = exynos5_clksrc_mask_fsys_ctrl,
 + .ctrlbit= (1  28),
 + },
 + .sources = exynos5_clkset_usbdrd30,
 + .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size =
 1 },
 + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size =
 4 },
   },
  };




-- 
Thanks  Regards
Vivek
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Re: [PATCH v4 3/4] ARM: Exynos5250: Add clock information for dwc3-exynos

2013-01-23 Thread Vivek Gautam 
Hi Tomasz,


On Wed, Jan 16, 2013 at 8:35 PM, Vivek Gautam gautamvivek1...@gmail.com wrote:
 Hi Tomasz,


 On Wed, Jan 16, 2013 at 1:19 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
 Hi Vivek,

 Don't you need also some clkdev lookup entry to make the clock available
 in the driver?


 This clock source we added with a motive of completion, however it's
 not being used as of now.
 As far as i could see the lookup structure contains clocks for devices
 having multiple instances.
 Do you feel that i should be adding an entry in clk_lookup structure ?
 May be i am missing here something. Can you please elaborate on the
 use-case of clk_lookup
 entries.


Any suggestions on this please ?


 On Tuesday 15 of January 2013 19:08:31 Vivek Gautam wrote:
 Adding necessary device clock to exynos5 needed for
 the DWC3 controller.

 Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
 ---
  arch/arm/mach-exynos/clock-exynos5.c |   24 
  1 files changed, 24 insertions(+), 0 deletions(-)

 diff --git a/arch/arm/mach-exynos/clock-exynos5.c
 b/arch/arm/mach-exynos/clock-exynos5.c index 0208c3a..13af020 100644
 --- a/arch/arm/mach-exynos/clock-exynos5.c
 +++ b/arch/arm/mach-exynos/clock-exynos5.c
 @@ -757,6 +757,11 @@ static struct clk exynos5_init_clocks_off[] = {
   .enable = exynos5_clk_ip_fsys_ctrl ,
   .ctrlbit= (1  18),
   }, {
 + .name   = usbdrd30,
 + .parent = exynos5_clk_aclk_200.clk,
 + .enable = exynos5_clk_ip_fsys_ctrl,
 + .ctrlbit= (1  19),
 + }, {
   .name   = usbotg,
   .enable = exynos5_clk_ip_fsys_ctrl,
   .ctrlbit= (1  7),
 @@ -1035,6 +1040,16 @@ static struct clksrc_sources exynos5_clkset_group
 = { .nr_sources   = ARRAY_SIZE(exynos5_clkset_group_list),
  };

 +struct clk *exynos5_clkset_usbdrd30_list[] = {
 + [0] = exynos5_clk_mout_mpll.clk,
 + [1] = exynos5_clk_mout_cpll.clk,
 +};
 +
 +struct clksrc_sources exynos5_clkset_usbdrd30 = {
 + .sources= exynos5_clkset_usbdrd30_list,
 + .nr_sources = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
 +};
 +
  /* Possible clock sources for aclk_266_gscl_sub Mux */
  static struct clk *clk_src_gscl_266_list[] = {
   [0] = clk_ext_xtal_mux,
 @@ -1329,6 +1344,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
   .parent = exynos5_clk_mout_cpll.clk,
   },
   .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3
 },
 + }, {
 + .clk= {
 + .name   = sclk_usbdrd30,
 + .enable = exynos5_clksrc_mask_fsys_ctrl,
 + .ctrlbit= (1  28),
 + },
 + .sources = exynos5_clkset_usbdrd30,
 + .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size =
 1 },
 + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size =
 4 },
   },
  };





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Thanks  Regards
Vivek
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[PATCH v4 3/4] ARM: Exynos5250: Add clock information for dwc3-exynos

2013-01-15 Thread Vivek Gautam 
Adding necessary device clock to exynos5 needed for
the DWC3 controller.

Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
 arch/arm/mach-exynos/clock-exynos5.c |   24 
 1 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos5.c 
b/arch/arm/mach-exynos/clock-exynos5.c
index 0208c3a..13af020 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -757,6 +757,11 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_fsys_ctrl ,
.ctrlbit= (1  18),
}, {
+   .name   = usbdrd30,
+   .parent = exynos5_clk_aclk_200.clk,
+   .enable = exynos5_clk_ip_fsys_ctrl,
+   .ctrlbit= (1  19),
+   }, {
.name   = usbotg,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit= (1  7),
@@ -1035,6 +1040,16 @@ static struct clksrc_sources exynos5_clkset_group = {
.nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
 };
 
+struct clk *exynos5_clkset_usbdrd30_list[] = {
+   [0] = exynos5_clk_mout_mpll.clk,
+   [1] = exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_usbdrd30 = {
+   .sources= exynos5_clkset_usbdrd30_list,
+   .nr_sources = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
+};
+
 /* Possible clock sources for aclk_266_gscl_sub Mux */
 static struct clk *clk_src_gscl_266_list[] = {
[0] = clk_ext_xtal_mux,
@@ -1329,6 +1344,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
.parent = exynos5_clk_mout_cpll.clk,
},
.reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+   }, {
+   .clk= {
+   .name   = sclk_usbdrd30,
+   .enable = exynos5_clksrc_mask_fsys_ctrl,
+   .ctrlbit= (1  28),
+   },
+   .sources = exynos5_clkset_usbdrd30,
+   .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 1 
},
+   .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size = 
4 },
},
 };
 
-- 
1.7.6.5

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Re: [PATCH v4 3/4] ARM: Exynos5250: Add clock information for dwc3-exynos

2013-01-15 Thread Tomasz Figa 
Hi Vivek,

Don't you need also some clkdev lookup entry to make the clock available 
in the driver?

Best regards,
Tomasz

On Tuesday 15 of January 2013 19:08:31 Vivek Gautam wrote:
 Adding necessary device clock to exynos5 needed for
 the DWC3 controller.
 
 Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
 ---
  arch/arm/mach-exynos/clock-exynos5.c |   24 
  1 files changed, 24 insertions(+), 0 deletions(-)
 
 diff --git a/arch/arm/mach-exynos/clock-exynos5.c
 b/arch/arm/mach-exynos/clock-exynos5.c index 0208c3a..13af020 100644
 --- a/arch/arm/mach-exynos/clock-exynos5.c
 +++ b/arch/arm/mach-exynos/clock-exynos5.c
 @@ -757,6 +757,11 @@ static struct clk exynos5_init_clocks_off[] = {
   .enable = exynos5_clk_ip_fsys_ctrl ,
   .ctrlbit= (1  18),
   }, {
 + .name   = usbdrd30,
 + .parent = exynos5_clk_aclk_200.clk,
 + .enable = exynos5_clk_ip_fsys_ctrl,
 + .ctrlbit= (1  19),
 + }, {
   .name   = usbotg,
   .enable = exynos5_clk_ip_fsys_ctrl,
   .ctrlbit= (1  7),
 @@ -1035,6 +1040,16 @@ static struct clksrc_sources exynos5_clkset_group
 = { .nr_sources   = ARRAY_SIZE(exynos5_clkset_group_list),
  };
 
 +struct clk *exynos5_clkset_usbdrd30_list[] = {
 + [0] = exynos5_clk_mout_mpll.clk,
 + [1] = exynos5_clk_mout_cpll.clk,
 +};
 +
 +struct clksrc_sources exynos5_clkset_usbdrd30 = {
 + .sources= exynos5_clkset_usbdrd30_list,
 + .nr_sources = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
 +};
 +
  /* Possible clock sources for aclk_266_gscl_sub Mux */
  static struct clk *clk_src_gscl_266_list[] = {
   [0] = clk_ext_xtal_mux,
 @@ -1329,6 +1344,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
   .parent = exynos5_clk_mout_cpll.clk,
   },
   .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 
},
 + }, {
 + .clk= {
 + .name   = sclk_usbdrd30,
 + .enable = exynos5_clksrc_mask_fsys_ctrl,
 + .ctrlbit= (1  28),
 + },
 + .sources = exynos5_clkset_usbdrd30,
 + .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 
1 },
 + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size = 
4 },
   },
  };
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