[RFC 1/2] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core
From: "Ivan T. Ivanov"
Signed-off-by: Ivan T. Ivanov
---
.../devicetree/bindings/usb/msm-ssusb.txt | 49 +++
drivers/usb/phy/Kconfig| 11 +
drivers/usb/phy/Makefile |2 +
drivers/usb/phy/phy-msm-dwc3-usb2.c| 342 +
drivers/usb/phy/phy-msm-dwc3-usb3.c| 389
5 files changed, 793 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb2.c
create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb3.c
diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt
b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
new file mode 100644
index 000..550b496
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
@@ -0,0 +1,49 @@
+MSM SuperSpeed USB3.0 SoC controllers
+
+Required properities :
+- compatible sould be "qcom,dwc3-usb2";
+- reg : offset and length of the register set in the memory map
+- clocks: <&cxo>, <&usb2a_phy_sleep_cxc>;
+- clock-names: "xo", "sleep_a_clk";
+-supply: phandle to the regulator device tree node
+Required "supply-name" examples are:
+ "v1p8" : 1.8v supply for HSPHY
+ "v3p3" : 3.3v supply for HSPHY
+ "vbus" : vbus supply for host mode
+ "vddcx" : vdd supply for HS-PHY digital circuit operation
+
+Required properities :
+- compatible sould be "qcom,dwc3-usb3";
+- reg : offset and length of the register set in the memory map
+- clocks: <&cxo>, <&usb30_mock_utmi_cxc>;
+- clock-names: "xo", "ref_clk";
+-supply: phandle to the regulator device tree node
+Required "supply-name" examples are:
+ "v1p8" : 1.8v supply for SS-PHY
+ "vddcx" : vdd supply for SS-PHY digital circuit operation
+
+Example device nodes:
+
+ dwc3_usb2: phy@f92f8800 {
+ compatible = "qcom,dwc3-usb2";
+ reg = <0xf92f8800 0x30>;
+
+ clocks = <&cxo>, <&usb2a_phy_sleep_cxc>;
+ clock-names = "xo", "sleep_a_clk";
+
+ vbus-supply = <&supply>;
+ vddcx-supply = <&supply>;
+ v1p8-supply = <&supply>;
+ v3p3-supply = <&supply>;
+ };
+
+ dwc3_usb3: phy@f92f8830 {
+ compatible = "qcom,dwc3-usb3";
+ reg = <0xf92f8830 0x30>;
+
+ clocks = <&cxo>, <&usb30_mock_utmi_cxc>;
+ clock-names = "xo", "ref_clk";
+
+ vddcx-supply = <&supply>;
+ v1p8-supply = <&supply>;
+ };
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 5443958..40e83b5 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -202,6 +202,17 @@ config USB_RCAR_PHY
To compile this driver as a module, choose M here: the
module will be called phy-rcar-usb.
+config USB_MSM_DWC3_PHYS
+ tristate "Qualcomm DWC3 USB controller PHY's support"
+ depends on (USB || USB_GADGET) && ARCH_MSM
+ select USB_PHY
+ help
+ Enable this to support the USB PHY transceivers on MSM chips with
+ DWC3 USB core. It handles PHY initialization, clock management
+ required after resetting the hardware and power management.
+ This driver is required even for peripheral only or host only
+ mode configurations.
+
config USB_ULPI
bool "Generic ULPI Transceiver Driver"
depends on ARM
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 98730ca..53355ec 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -24,6 +24,8 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += phy-tegra-usb.o
obj-$(CONFIG_USB_GPIO_VBUS)+= phy-gpio-vbus-usb.o
obj-$(CONFIG_USB_ISP1301) += phy-isp1301.o
obj-$(CONFIG_USB_MSM_OTG) += phy-msm-usb.o
+obj-$(CONFIG_USB_MSM_DWC3_PHYS)+= phy-msm-dwc3-usb2.o
+obj-$(CONFIG_USB_MSM_DWC3_PHYS)+= phy-msm-dwc3-usb3.o
obj-$(CONFIG_USB_MV_OTG) += phy-mv-usb.o
obj-$(CONFIG_USB_MXS_PHY) += phy-mxs-usb.o
obj-$(CONFIG_USB_RCAR_PHY) += phy-rcar-usb.o
diff --git a/drivers/usb/phy/phy-msm-dwc3-usb2.c
b/drivers/usb/phy/phy-msm-dwc3-usb2.c
new file mode 100644
index 000..174c72c
--- /dev/null
+++ b/drivers/usb/phy/phy-msm-dwc3-usb2.c
@@ -0,0 +1,342 @@
+/* Copyright (c) 2013, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+
Re: [RFC 1/2] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core
On Tue, 2013-08-06 at 12:53 +0100, Ivan T. Ivanov wrote:
> From: "Ivan T. Ivanov"
>
> Signed-off-by: Ivan T. Ivanov
I am sure that the information in the subject is more than enough for
you, but would you care to give some more background for the commit log?
Where can we find such controllers? What is DWC3 core? Is it
Qualcomm-specific block, or does it come from one of the IP providers
like Synopsys or Cadence?
> .../devicetree/bindings/usb/msm-ssusb.txt | 49 +++
> drivers/usb/phy/Kconfig| 11 +
> drivers/usb/phy/Makefile |2 +
> drivers/usb/phy/phy-msm-dwc3-usb2.c| 342 +
> drivers/usb/phy/phy-msm-dwc3-usb3.c| 389
>
> 5 files changed, 793 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
> create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb2.c
> create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb3.c
>
> diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> new file mode 100644
> index 000..550b496
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> @@ -0,0 +1,49 @@
> +MSM SuperSpeed USB3.0 SoC controllers
I understand that the device always come in doublets? As in: are nodes
for both USB2 and 3 always required?
> +Required properities :
> +- compatible sould be "qcom,dwc3-usb2";
> +- reg : offset and length of the register set in the memory map
> +- clocks: <&cxo>, <&usb2a_phy_sleep_cxc>;
> +- clock-names: "xo", "sleep_a_clk";
> +-supply: phandle to the regulator device tree node
> +Required "supply-name" examples are:
So required or examples? ;-)
> + "v1p8" : 1.8v supply for HSPHY
> + "v3p3" : 3.3v supply for HSPHY
> + "vbus" : vbus supply for host mode
> + "vddcx" : vdd supply for HS-PHY digital circuit operation
>
> +Required properities :
> +- compatible sould be "qcom,dwc3-usb3";
> +- reg : offset and length of the register set in the memory map
> +- clocks: <&cxo>, <&usb30_mock_utmi_cxc>;
> +- clock-names: "xo", "ref_clk";
> +-supply: phandle to the regulator device tree node
> +Required "supply-name" examples are:
> + "v1p8" : 1.8v supply for SS-PHY
> + "vddcx" : vdd supply for SS-PHY digital circuit operation
> +
> +Example device nodes:
> +
> + dwc3_usb2: phy@f92f8800 {
> + compatible = "qcom,dwc3-usb2";
> + reg = <0xf92f8800 0x30>;
> +
> + clocks = <&cxo>, <&usb2a_phy_sleep_cxc>;
> + clock-names = "xo", "sleep_a_clk";
> +
> + vbus-supply = <&supply>;
> + vddcx-supply = <&supply>;
> + v1p8-supply = <&supply>;
> + v3p3-supply = <&supply>;
> + };
> +
> + dwc3_usb3: phy@f92f8830 {
> + compatible = "qcom,dwc3-usb3";
> + reg = <0xf92f8830 0x30>;
> +
> + clocks = <&cxo>, <&usb30_mock_utmi_cxc>;
> + clock-names = "xo", "ref_clk";
> +
> + vddcx-supply = <&supply>;
> + v1p8-supply = <&supply>;
> + };
Note that I had a look at the bindings only - I don't feel competent to
review the drivers/usb part of the patch...
Thanks!
Pawel
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Re: [RFC 1/2] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core
Hi,
On Tue, 2013-08-06 at 13:12 +0100, Pawel Moll wrote:
> On Tue, 2013-08-06 at 12:53 +0100, Ivan T. Ivanov wrote:
> > From: "Ivan T. Ivanov"
> >
> > Signed-off-by: Ivan T. Ivanov
>
> I am sure that the information in the subject is more than enough for
> you, but would you care to give some more background for the commit log?
> Where can we find such controllers? What is DWC3 core? Is it
> Qualcomm-specific block, or does it come from one of the IP providers
> like Synopsys or Cadence?
>
You are right, I have to add more info here. DesignWare USB Core could
also be found in TI OMAP's and Samasung SoC's, at least. And it is
IP from Synopsys. Usually SoC vendors wrap it with additional logic,
which provides required clocks and power supplies.
> > .../devicetree/bindings/usb/msm-ssusb.txt | 49 +++
> > drivers/usb/phy/Kconfig| 11 +
> > drivers/usb/phy/Makefile |2 +
> > drivers/usb/phy/phy-msm-dwc3-usb2.c| 342 +
> > drivers/usb/phy/phy-msm-dwc3-usb3.c| 389
> >
> > 5 files changed, 793 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb2.c
> > create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb3.c
> >
> > diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > new file mode 100644
> > index 000..550b496
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > @@ -0,0 +1,49 @@
> > +MSM SuperSpeed USB3.0 SoC controllers
>
> I understand that the device always come in doublets? As in: are nodes
> for both USB2 and 3 always required?
The core dwc3 driver expects 2 USB PHY interfaces, so both nodes
are mandatory.
>
> > +Required properities :
> > +- compatible sould be "qcom,dwc3-usb2";
> > +- reg : offset and length of the register set in the memory map
> > +- clocks: <&cxo>, <&usb2a_phy_sleep_cxc>;
> > +- clock-names: "xo", "sleep_a_clk";
> > +-supply: phandle to the regulator device tree node
> > +Required "supply-name" examples are:
>
> So required or examples? ;-)
It should be Required, will fix this.
>
> > + "v1p8" : 1.8v supply for HSPHY
> > + "v3p3" : 3.3v supply for HSPHY
> > + "vbus" : vbus supply for host mode
> > + "vddcx" : vdd supply for HS-PHY digital circuit operation
> >
> > +Required properities :
> > +- compatible sould be "qcom,dwc3-usb3";
> > +- reg : offset and length of the register set in the memory map
> > +- clocks: <&cxo>, <&usb30_mock_utmi_cxc>;
> > +- clock-names: "xo", "ref_clk";
> > +-supply: phandle to the regulator device tree node
> > +Required "supply-name" examples are:
> > + "v1p8" : 1.8v supply for SS-PHY
> > + "vddcx" : vdd supply for SS-PHY digital circuit operation
> > +
> > +Example device nodes:
> > +
> > + dwc3_usb2: phy@f92f8800 {
> > + compatible = "qcom,dwc3-usb2";
> > + reg = <0xf92f8800 0x30>;
> > +
> > + clocks = <&cxo>, <&usb2a_phy_sleep_cxc>;
> > + clock-names = "xo", "sleep_a_clk";
> > +
> > + vbus-supply = <&supply>;
> > + vddcx-supply = <&supply>;
> > + v1p8-supply = <&supply>;
> > + v3p3-supply = <&supply>;
> > + };
> > +
> > + dwc3_usb3: phy@f92f8830 {
> > + compatible = "qcom,dwc3-usb3";
> > + reg = <0xf92f8830 0x30>;
> > +
> > + clocks = <&cxo>, <&usb30_mock_utmi_cxc>;
> > + clock-names = "xo", "ref_clk";
> > +
> > + vddcx-supply = <&supply>;
> > + v1p8-supply = <&supply>;
> > + };
>
> Note that I had a look at the bindings only - I don't feel competent to
> review the drivers/usb part of the patch...
Sure, thank you.
Ivan
>
> Thanks!
>
> Pawel
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Re: [RFC 1/2] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core
On Tue, Aug 06, 2013 at 12:53:10PM +0100, Ivan T. Ivanov wrote:
> From: "Ivan T. Ivanov"
>
> Signed-off-by: Ivan T. Ivanov
> ---
> .../devicetree/bindings/usb/msm-ssusb.txt | 49 +++
> drivers/usb/phy/Kconfig| 11 +
> drivers/usb/phy/Makefile |2 +
> drivers/usb/phy/phy-msm-dwc3-usb2.c| 342 +
> drivers/usb/phy/phy-msm-dwc3-usb3.c| 389
>
> 5 files changed, 793 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
> create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb2.c
> create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb3.c
>
> diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> new file mode 100644
> index 000..550b496
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> @@ -0,0 +1,49 @@
> +MSM SuperSpeed USB3.0 SoC controllers
> +
> +Required properities :
> +- compatible sould be "qcom,dwc3-usb2";
> +- reg : offset and length of the register set in the memory map
> +- clocks: <&cxo>, <&usb2a_phy_sleep_cxc>;
Huh? That doesn't describe what these are. These would be better
explained with a reference to clock-names and a basic description as to
what the input's called, what it drives, etc, as you've done done for
the *-supply properties.
> +- clock-names: "xo", "sleep_a_clk";
> +-supply: phandle to the regulator device tree node
> +Required "supply-name" examples are:
> + "v1p8" : 1.8v supply for HSPHY
> + "v3p3" : 3.3v supply for HSPHY
> + "vbus" : vbus supply for host mode
> + "vddcx" : vdd supply for HS-PHY digital circuit operation
> +
> +Required properities :
> +- compatible sould be "qcom,dwc3-usb3";
> +- reg : offset and length of the register set in the memory map
> +- clocks: <&cxo>, <&usb30_mock_utmi_cxc>;
Similarly, this doesn't describe what the clocks are.
> +- clock-names: "xo", "ref_clk";
> +-supply: phandle to the regulator device tree node
> +Required "supply-name" examples are:
> + "v1p8" : 1.8v supply for SS-PHY
> + "vddcx" : vdd supply for SS-PHY digital circuit operation
> +
> +Example device nodes:
> +
> + dwc3_usb2: phy@f92f8800 {
> + compatible = "qcom,dwc3-usb2";
> + reg = <0xf92f8800 0x30>;
> +
> + clocks = <&cxo>, <&usb2a_phy_sleep_cxc>;
> + clock-names = "xo", "sleep_a_clk";
> +
> + vbus-supply = <&supply>;
> + vddcx-supply = <&supply>;
> + v1p8-supply = <&supply>;
> + v3p3-supply = <&supply>;
> + };
> +
> + dwc3_usb3: phy@f92f8830 {
> + compatible = "qcom,dwc3-usb3";
> + reg = <0xf92f8830 0x30>;
> +
> + clocks = <&cxo>, <&usb30_mock_utmi_cxc>;
> + clock-names = "xo", "ref_clk";
> +
> + vddcx-supply = <&supply>;
> + v1p8-supply = <&supply>;
> + };
Those regster banks look suspiciously close. Are these the same IP
block? Can they ever appear separately?
Do the drivers not trample each other when messing with shared clocks
and regulators?
Thanks,
Mark.
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Re: [RFC 1/2] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core
Hi,
On Tue, 2013-08-06 at 15:03 +0100, Mark Rutland wrote:
> On Tue, Aug 06, 2013 at 12:53:10PM +0100, Ivan T. Ivanov wrote:
> > From: "Ivan T. Ivanov"
> >
> > Signed-off-by: Ivan T. Ivanov
> > ---
> > .../devicetree/bindings/usb/msm-ssusb.txt | 49 +++
> > drivers/usb/phy/Kconfig| 11 +
> > drivers/usb/phy/Makefile |2 +
> > drivers/usb/phy/phy-msm-dwc3-usb2.c| 342 +
> > drivers/usb/phy/phy-msm-dwc3-usb3.c| 389
> >
> > 5 files changed, 793 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb2.c
> > create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb3.c
> >
> > diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > new file mode 100644
> > index 000..550b496
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > @@ -0,0 +1,49 @@
> > +MSM SuperSpeed USB3.0 SoC controllers
> > +
> > +Required properities :
> > +- compatible sould be "qcom,dwc3-usb2";
> > +- reg : offset and length of the register set in the memory map
> > +- clocks: <&cxo>, <&usb2a_phy_sleep_cxc>;
>
> Huh? That doesn't describe what these are. These would be better
> explained with a reference to clock-names and a basic description as to
> what the input's called, what it drives, etc, as you've done done for
> the *-supply properties.
Ok, I will fix this.
>
> > +- clock-names: "xo", "sleep_a_clk";
> > +-supply: phandle to the regulator device tree node
> > +Required "supply-name" examples are:
> > + "v1p8" : 1.8v supply for HSPHY
> > + "v3p3" : 3.3v supply for HSPHY
> > + "vbus" : vbus supply for host mode
> > + "vddcx" : vdd supply for HS-PHY digital circuit operation
> > +
> > +Required properities :
> > +- compatible sould be "qcom,dwc3-usb3";
> > +- reg : offset and length of the register set in the memory map
> > +- clocks: <&cxo>, <&usb30_mock_utmi_cxc>;
>
> Similarly, this doesn't describe what the clocks are.
Understood.
>
> > +- clock-names: "xo", "ref_clk";
> > +-supply: phandle to the regulator device tree node
> > +Required "supply-name" examples are:
> > + "v1p8" : 1.8v supply for SS-PHY
> > + "vddcx" : vdd supply for SS-PHY digital circuit operation
> > +
> > +Example device nodes:
> > +
> > + dwc3_usb2: phy@f92f8800 {
> > + compatible = "qcom,dwc3-usb2";
> > + reg = <0xf92f8800 0x30>;
> > +
> > + clocks = <&cxo>, <&usb2a_phy_sleep_cxc>;
> > + clock-names = "xo", "sleep_a_clk";
> > +
> > + vbus-supply = <&supply>;
> > + vddcx-supply = <&supply>;
> > + v1p8-supply = <&supply>;
> > + v3p3-supply = <&supply>;
> > + };
> > +
> > + dwc3_usb3: phy@f92f8830 {
> > + compatible = "qcom,dwc3-usb3";
> > + reg = <0xf92f8830 0x30>;
> > +
> > + clocks = <&cxo>, <&usb30_mock_utmi_cxc>;
> > + clock-names = "xo", "ref_clk";
> > +
> > + vddcx-supply = <&supply>;
> > + v1p8-supply = <&supply>;
> > + };
>
>
> Those regster banks look suspiciously close. Are these the same IP
> block? Can they ever appear separately?
>
They are part of the wrapper Qualcomm logic around Synopsys USB3 core.
In this sense they are part of the one IP, I believe. Manage them from
separate drivers simplify code.
> Do the drivers not trample each other when messing with shared clocks
> and regulators?
>
Regulators and clocks have reference counting, right?, so this should
be safe. Even if they are part of the one driver, clocks and regulators
could be switched off only if both PHY's do not use them.
Thanks,
Ivan
> Thanks,
> Mark.
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Re: [RFC 1/2] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core
On Tue, Aug 06, 2013 at 03:36:33PM +0100, Ivan T. Ivanov wrote:
> Hi,
>
> On Tue, 2013-08-06 at 15:03 +0100, Mark Rutland wrote:
> > On Tue, Aug 06, 2013 at 12:53:10PM +0100, Ivan T. Ivanov wrote:
> > > From: "Ivan T. Ivanov"
> > >
> > > Signed-off-by: Ivan T. Ivanov
> > > ---
> > > .../devicetree/bindings/usb/msm-ssusb.txt | 49 +++
> > > drivers/usb/phy/Kconfig| 11 +
> > > drivers/usb/phy/Makefile |2 +
> > > drivers/usb/phy/phy-msm-dwc3-usb2.c| 342
> > > +
> > > drivers/usb/phy/phy-msm-dwc3-usb3.c| 389
> > >
> > > 5 files changed, 793 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > > create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb2.c
> > > create mode 100644 drivers/usb/phy/phy-msm-dwc3-usb3.c
> > >
> > > diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > > b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > > new file mode 100644
> > > index 000..550b496
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> > > @@ -0,0 +1,49 @@
> > > +MSM SuperSpeed USB3.0 SoC controllers
> > > +
> > > +Required properities :
> > > +- compatible sould be "qcom,dwc3-usb2";
> > > +- reg : offset and length of the register set in the memory map
> > > +- clocks: <&cxo>, <&usb2a_phy_sleep_cxc>;
> >
> > Huh? That doesn't describe what these are. These would be better
> > explained with a reference to clock-names and a basic description as to
> > what the input's called, what it drives, etc, as you've done done for
> > the *-supply properties.
>
> Ok, I will fix this.
>
> >
> > > +- clock-names: "xo", "sleep_a_clk";
> > > +-supply: phandle to the regulator device tree node
> > > +Required "supply-name" examples are:
> > > + "v1p8" : 1.8v supply for HSPHY
> > > + "v3p3" : 3.3v supply for HSPHY
> > > + "vbus" : vbus supply for host mode
> > > + "vddcx" : vdd supply for HS-PHY digital circuit operation
> > > +
> > > +Required properities :
> > > +- compatible sould be "qcom,dwc3-usb3";
> > > +- reg : offset and length of the register set in the memory map
> > > +- clocks: <&cxo>, <&usb30_mock_utmi_cxc>;
> >
> > Similarly, this doesn't describe what the clocks are.
>
> Understood.
>
> >
> > > +- clock-names: "xo", "ref_clk";
> > > +-supply: phandle to the regulator device tree node
> > > +Required "supply-name" examples are:
> > > + "v1p8" : 1.8v supply for SS-PHY
> > > + "vddcx" : vdd supply for SS-PHY digital circuit operation
> > > +
> > > +Example device nodes:
> > > +
> > > + dwc3_usb2: phy@f92f8800 {
> > > + compatible = "qcom,dwc3-usb2";
> > > + reg = <0xf92f8800 0x30>;
> > > +
> > > + clocks = <&cxo>, <&usb2a_phy_sleep_cxc>;
> > > + clock-names = "xo", "sleep_a_clk";
> > > +
> > > + vbus-supply = <&supply>;
> > > + vddcx-supply = <&supply>;
> > > + v1p8-supply = <&supply>;
> > > + v3p3-supply = <&supply>;
> > > + };
> > > +
> > > + dwc3_usb3: phy@f92f8830 {
> > > + compatible = "qcom,dwc3-usb3";
> > > + reg = <0xf92f8830 0x30>;
> > > +
> > > + clocks = <&cxo>, <&usb30_mock_utmi_cxc>;
> > > + clock-names = "xo", "ref_clk";
> > > +
> > > + vddcx-supply = <&supply>;
> > > + v1p8-supply = <&supply>;
> > > + };
> >
> >
> > Those regster banks look suspiciously close. Are these the same IP
> > block? Can they ever appear separately?
> >
>
> They are part of the wrapper Qualcomm logic around Synopsys USB3 core.
> In this sense they are part of the one IP, I believe. Manage them from
> separate drivers simplify code.
Hmmm. I'm not entirely certain on this. On the one hand, they're
separate IP blocks, and have lgoically separate drivers, so describing
them as two devices makes sense. On the other hand, they've been fused
into one IP block with shared resources. Describing them as two devices
probably makes sense given you have the wrapper driver.
>
> > Do the drivers not trample each other when messing with shared clocks
> > and regulators?
> >
>
> Regulators and clocks have reference counting, right?, so this should
> be safe. Even if they are part of the one driver, clocks and regulators
> could be switched off only if both PHY's do not use them.
Ok, I just wanted to be sure this had been considered :)
Thanks,
Mark.
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