Re: [PATCH v3] usb: phy: mxs: Add DT bindings to configure TX settings

[Peter Chen]

On Mon, Jun 13, 2016 at 04:40:55PM -0400, Jaret Cantu wrote:
> >
> >According to your previous information, the single formula can't be used
> >to get D_CAL value, do you have any good ways except for using a table?
> 
> That is not exactly what I said:
> 
> "I can't find any formula which would hit all of those same
> percentages **without rounding up.**"
> 

Sorry, my careless.

> I did find a formula that hits all of the percentages with rounding
> up, and I listed this formula (in shell form) previously. The
> rounding (+ (119-80)/2) just makes it look a little more awkward
> than I would like:
> 
> $ for d in 119 116 114 112 109 106 103 100 97 95 93 90 88 86 83 79;
> do echo "$d="$(( ( (119-$d) * 0xf + (119-80)/2 ) / (119-80) ));
> d=$((d+1)); done
> 119=0
> 116=1
> 114=2
> 112=3
> 109=4
> 106=5
> 103=6
> 100=7
> 97=8
> 95=9
> 93=10
> 90=11
> 88=12
> 86=13
> 83=14
> 79=15
> 
> These current percentage/register value pairs match the D_CAL table.
> 
> 
> > Sending the patch for new algorithm to speed up this issue please.
> >
> There were also some Documentation changes from between when I
> created this patch and the current HOL for which I had to modify the
> patch.

I will review and test your v4 patch, thanks.

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Peter Chen
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Re: [PATCH v3] usb: phy: mxs: Add DT bindings to configure TX settings

[Jaret Cantu]

On 06/11/2016 11:25 PM, Peter Chen wrote:

On Thu, Jun 09, 2016 at 02:07:52PM -0400, Justin Waters wrote:

Peter,

On Wed, Jun 8, 2016 at 10:41 PM, Peter Chen  wrote:

On Thu, Jun 9, 2016 at 5:27 AM, Jaret Cantu  wrote:

On 03/23/2016 10:21 PM, Peter Chen wrote:


On Wed, Mar 23, 2016 at 02:17:27PM -0400, Jaret Cantu wrote:


On 03/23/2016 01:37 PM, Jaret Cantu wrote:


On 03/23/2016 12:36 AM, Peter Chen wrote:


On Mon, Mar 21, 2016 at 12:32:27PM -0400, Jaret Cantu wrote:


The TX settings can be calibrated for particular hardware.  The
phy is reset by Linux, so this cannot be handled by the bootloader.

The TRM mentions that the maximum resistance should be used for the
DN/DP calibration in order to pass USB certification.

The values for the TX registers are poorly described in the TRM.
The meanings of the register values were taken from another
Freescale-provided document:
https://community.freescale.com/message/566147#comment-566912

Signed-off-by: Jaret Cantu 
---
v3. Added unit suffix (-ohms) to tx-cal-45-d*

v2. Copying devicetree list
  Removed prettifying extra whitespace
  Removed unnecessary register rewrite on resume
  Use min and max constants for clarity

   .../devicetree/bindings/phy/mxs-usb-phy.txt|   10 
   drivers/usb/phy/phy-mxs-usb.c  |   58

   2 files changed, 68 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
index 379b84a..1d25b04 100644
--- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
@@ -12,6 +12,16 @@ Required properties:
   - interrupts: Should contain phy interrupt
   - fsl,anatop: phandle for anatop register, it is only for imx6 SoC
series

+
+if (!of_property_read_u32(np, "fsl,tx-d-cal", ) &&
+val >= MXS_PHY_TX_D_CAL_MIN && val <= MXS_PHY_TX_D_CAL_MAX) {
+/* scale to 4-bit value */
+val = (MXS_PHY_TX_D_CAL_MAX - val) * 0xF
+/ (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN);
+mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0);
+mxs_phy->tx_reg_set  |= GM_USBPHY_TX_D_CAL(val);
+}
+



I have tested "tx-d-cal", but it seems incorrect according to the xls
you
have provided, would you please check it again or am I wrong?



Gah! You're right. Some of the D_CAL values need to be rounded up to
match the xls.  And even then, the value for 86 still doesn't play nice.
   I was really hoping to avoid using a table for these values.

The TXCALDP/DN values use a much simpler 1-to-1 scale across the 16
possible register values and so are unaffected by a similar issue.  I
rechecked their numbers just to be sure.



The solution looks to be to scale D_CAL starting from 80 instead of
79.  If you look at the xls listing, the jump from 79 to 83 is the
only time two adjacent register values result in a change greater
than 2% or 3%.

This will result in some code ugliness as the minimum allowed
percentage (79), per the Freescale document, and the point at which
we are scaling the percentage values to register values (80) are
different.

And, as mentioned before, the values will also have to be rounded up.

This quick shell code confirms that these sorts of calculations
match up with the values in the spreadsheet:

for d in 119 116 114 112 109 106 103 100 97 95 93 90 88 86 83 79; do
echo "$d="$(( ( (119-$d) * 0xf + (119-80)/2 ) / (119-80) ));
d=$((d+1)); done


I can't find any formula which would hit all of those same
percentages without rounding up.



Then, we had to use table for it. Besides, IC team confirms the default
value and the step for TXCAL45DP/DN are changed at next generation SoCs,
so I am wondering how we describe it at binding doc.



Which next gen SoC would this be?  The MX7?  The documentation for the USB
PHY in that reference manual is even sparser than the one for the MX6 in
regards to these register values.



Here, I mean i.mx8



Currently, there is no support in the mainline kernel for the i.MX8.
Do you mean to say that this feature is blocked until the i.MX8 is
supported in the mainline kernel? Or that we would be required to add
the register definitions for the i.MX8 as a prerequisite? Wouldn't it
make more sense to add support to the driver as part of the i.MX8
enablement, especially considering no documentation is freely
available at this time?


The MX7 manual does still mention that HW_USBPHY_TX_TXCAL45DP and
HW_USBPHY_TX_TXCAL45DN should both be set to zero, but there is no listing
as to the location of these registers, let alone their defaults/step values.

Do you know where we could get the default and step values for the TXCAL
registers on the new SoC?  This information had to come from a Freescale
community thread for the MX6 since it wasn't defined clearly elsewhere.


In theory, these information should be 

Re: [PATCH v3] usb: phy: mxs: Add DT bindings to configure TX settings

[Peter Chen]

On Thu, Jun 09, 2016 at 02:07:52PM -0400, Justin Waters wrote:
> Peter,
> 
> On Wed, Jun 8, 2016 at 10:41 PM, Peter Chen  wrote:
> > On Thu, Jun 9, 2016 at 5:27 AM, Jaret Cantu  wrote:
> >> On 03/23/2016 10:21 PM, Peter Chen wrote:
> >>>
> >>> On Wed, Mar 23, 2016 at 02:17:27PM -0400, Jaret Cantu wrote:
> 
>  On 03/23/2016 01:37 PM, Jaret Cantu wrote:
> >
> > On 03/23/2016 12:36 AM, Peter Chen wrote:
> >>
> >> On Mon, Mar 21, 2016 at 12:32:27PM -0400, Jaret Cantu wrote:
> >>>
> >>> The TX settings can be calibrated for particular hardware.  The
> >>> phy is reset by Linux, so this cannot be handled by the bootloader.
> >>>
> >>> The TRM mentions that the maximum resistance should be used for the
> >>> DN/DP calibration in order to pass USB certification.
> >>>
> >>> The values for the TX registers are poorly described in the TRM.
> >>> The meanings of the register values were taken from another
> >>> Freescale-provided document:
> >>> https://community.freescale.com/message/566147#comment-566912
> >>>
> >>> Signed-off-by: Jaret Cantu 
> >>> ---
> >>> v3. Added unit suffix (-ohms) to tx-cal-45-d*
> >>>
> >>> v2. Copying devicetree list
> >>>  Removed prettifying extra whitespace
> >>>  Removed unnecessary register rewrite on resume
> >>>  Use min and max constants for clarity
> >>>
> >>>   .../devicetree/bindings/phy/mxs-usb-phy.txt|   10 
> >>>   drivers/usb/phy/phy-mxs-usb.c  |   58
> >>> 
> >>>   2 files changed, 68 insertions(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
> >>> b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
> >>> index 379b84a..1d25b04 100644
> >>> --- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
> >>> +++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
> >>> @@ -12,6 +12,16 @@ Required properties:
> >>>   - interrupts: Should contain phy interrupt
> >>>   - fsl,anatop: phandle for anatop register, it is only for imx6 SoC
> >>> series
> >>>
> >>> +
> >>> +if (!of_property_read_u32(np, "fsl,tx-d-cal", ) &&
> >>> +val >= MXS_PHY_TX_D_CAL_MIN && val <= MXS_PHY_TX_D_CAL_MAX) {
> >>> +/* scale to 4-bit value */
> >>> +val = (MXS_PHY_TX_D_CAL_MAX - val) * 0xF
> >>> +/ (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN);
> >>> +mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0);
> >>> +mxs_phy->tx_reg_set  |= GM_USBPHY_TX_D_CAL(val);
> >>> +}
> >>> +
> >>
> >>
> >> I have tested "tx-d-cal", but it seems incorrect according to the xls
> >> you
> >> have provided, would you please check it again or am I wrong?
> >
> >
> > Gah! You're right. Some of the D_CAL values need to be rounded up to
> > match the xls.  And even then, the value for 86 still doesn't play nice.
> >   I was really hoping to avoid using a table for these values.
> >
> > The TXCALDP/DN values use a much simpler 1-to-1 scale across the 16
> > possible register values and so are unaffected by a similar issue.  I
> > rechecked their numbers just to be sure.
> 
> 
>  The solution looks to be to scale D_CAL starting from 80 instead of
>  79.  If you look at the xls listing, the jump from 79 to 83 is the
>  only time two adjacent register values result in a change greater
>  than 2% or 3%.
> 
>  This will result in some code ugliness as the minimum allowed
>  percentage (79), per the Freescale document, and the point at which
>  we are scaling the percentage values to register values (80) are
>  different.
> 
>  And, as mentioned before, the values will also have to be rounded up.
> 
>  This quick shell code confirms that these sorts of calculations
>  match up with the values in the spreadsheet:
> 
>  for d in 119 116 114 112 109 106 103 100 97 95 93 90 88 86 83 79; do
>  echo "$d="$(( ( (119-$d) * 0xf + (119-80)/2 ) / (119-80) ));
>  d=$((d+1)); done
> 
> 
>  I can't find any formula which would hit all of those same
>  percentages without rounding up.
> 
> >>>
> >>> Then, we had to use table for it. Besides, IC team confirms the default
> >>> value and the step for TXCAL45DP/DN are changed at next generation SoCs,
> >>> so I am wondering how we describe it at binding doc.
> >>>
> >>
> >> Which next gen SoC would this be?  The MX7?  The documentation for the USB
> >> PHY in that reference manual is even sparser than the one for the MX6 in
> >> regards to these register values.
> >>
> >
> > Here, I mean i.mx8
> >
> 
> Currently, there is no support in the mainline kernel for the i.MX8.
> Do you mean to say that this feature is 

Re: [PATCH v3] usb: phy: mxs: Add DT bindings to configure TX settings

[Justin Waters]

Peter,

On Wed, Jun 8, 2016 at 10:41 PM, Peter Chen  wrote:
> On Thu, Jun 9, 2016 at 5:27 AM, Jaret Cantu  wrote:
>> On 03/23/2016 10:21 PM, Peter Chen wrote:
>>>
>>> On Wed, Mar 23, 2016 at 02:17:27PM -0400, Jaret Cantu wrote:

 On 03/23/2016 01:37 PM, Jaret Cantu wrote:
>
> On 03/23/2016 12:36 AM, Peter Chen wrote:
>>
>> On Mon, Mar 21, 2016 at 12:32:27PM -0400, Jaret Cantu wrote:
>>>
>>> The TX settings can be calibrated for particular hardware.  The
>>> phy is reset by Linux, so this cannot be handled by the bootloader.
>>>
>>> The TRM mentions that the maximum resistance should be used for the
>>> DN/DP calibration in order to pass USB certification.
>>>
>>> The values for the TX registers are poorly described in the TRM.
>>> The meanings of the register values were taken from another
>>> Freescale-provided document:
>>> https://community.freescale.com/message/566147#comment-566912
>>>
>>> Signed-off-by: Jaret Cantu 
>>> ---
>>> v3. Added unit suffix (-ohms) to tx-cal-45-d*
>>>
>>> v2. Copying devicetree list
>>>  Removed prettifying extra whitespace
>>>  Removed unnecessary register rewrite on resume
>>>  Use min and max constants for clarity
>>>
>>>   .../devicetree/bindings/phy/mxs-usb-phy.txt|   10 
>>>   drivers/usb/phy/phy-mxs-usb.c  |   58
>>> 
>>>   2 files changed, 68 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
>>> b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
>>> index 379b84a..1d25b04 100644
>>> --- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
>>> +++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
>>> @@ -12,6 +12,16 @@ Required properties:
>>>   - interrupts: Should contain phy interrupt
>>>   - fsl,anatop: phandle for anatop register, it is only for imx6 SoC
>>> series
>>>
>>> +
>>> +if (!of_property_read_u32(np, "fsl,tx-d-cal", ) &&
>>> +val >= MXS_PHY_TX_D_CAL_MIN && val <= MXS_PHY_TX_D_CAL_MAX) {
>>> +/* scale to 4-bit value */
>>> +val = (MXS_PHY_TX_D_CAL_MAX - val) * 0xF
>>> +/ (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN);
>>> +mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0);
>>> +mxs_phy->tx_reg_set  |= GM_USBPHY_TX_D_CAL(val);
>>> +}
>>> +
>>
>>
>> I have tested "tx-d-cal", but it seems incorrect according to the xls
>> you
>> have provided, would you please check it again or am I wrong?
>
>
> Gah! You're right. Some of the D_CAL values need to be rounded up to
> match the xls.  And even then, the value for 86 still doesn't play nice.
>   I was really hoping to avoid using a table for these values.
>
> The TXCALDP/DN values use a much simpler 1-to-1 scale across the 16
> possible register values and so are unaffected by a similar issue.  I
> rechecked their numbers just to be sure.


 The solution looks to be to scale D_CAL starting from 80 instead of
 79.  If you look at the xls listing, the jump from 79 to 83 is the
 only time two adjacent register values result in a change greater
 than 2% or 3%.

 This will result in some code ugliness as the minimum allowed
 percentage (79), per the Freescale document, and the point at which
 we are scaling the percentage values to register values (80) are
 different.

 And, as mentioned before, the values will also have to be rounded up.

 This quick shell code confirms that these sorts of calculations
 match up with the values in the spreadsheet:

 for d in 119 116 114 112 109 106 103 100 97 95 93 90 88 86 83 79; do
 echo "$d="$(( ( (119-$d) * 0xf + (119-80)/2 ) / (119-80) ));
 d=$((d+1)); done


 I can't find any formula which would hit all of those same
 percentages without rounding up.

>>>
>>> Then, we had to use table for it. Besides, IC team confirms the default
>>> value and the step for TXCAL45DP/DN are changed at next generation SoCs,
>>> so I am wondering how we describe it at binding doc.
>>>
>>
>> Which next gen SoC would this be?  The MX7?  The documentation for the USB
>> PHY in that reference manual is even sparser than the one for the MX6 in
>> regards to these register values.
>>
>
> Here, I mean i.mx8
>

Currently, there is no support in the mainline kernel for the i.MX8.
Do you mean to say that this feature is blocked until the i.MX8 is
supported in the mainline kernel? Or that we would be required to add
the register definitions for the i.MX8 as a prerequisite? Wouldn't it
make more sense to add support to the driver as part of the i.MX8
enablement, especially considering no documentation is 

Re: [PATCH v3] usb: phy: mxs: Add DT bindings to configure TX settings

[Peter Chen]

On Thu, Jun 9, 2016 at 5:27 AM, Jaret Cantu  wrote:
> On 03/23/2016 10:21 PM, Peter Chen wrote:
>>
>> On Wed, Mar 23, 2016 at 02:17:27PM -0400, Jaret Cantu wrote:
>>>
>>> On 03/23/2016 01:37 PM, Jaret Cantu wrote:

 On 03/23/2016 12:36 AM, Peter Chen wrote:
>
> On Mon, Mar 21, 2016 at 12:32:27PM -0400, Jaret Cantu wrote:
>>
>> The TX settings can be calibrated for particular hardware.  The
>> phy is reset by Linux, so this cannot be handled by the bootloader.
>>
>> The TRM mentions that the maximum resistance should be used for the
>> DN/DP calibration in order to pass USB certification.
>>
>> The values for the TX registers are poorly described in the TRM.
>> The meanings of the register values were taken from another
>> Freescale-provided document:
>> https://community.freescale.com/message/566147#comment-566912
>>
>> Signed-off-by: Jaret Cantu 
>> ---
>> v3. Added unit suffix (-ohms) to tx-cal-45-d*
>>
>> v2. Copying devicetree list
>>  Removed prettifying extra whitespace
>>  Removed unnecessary register rewrite on resume
>>  Use min and max constants for clarity
>>
>>   .../devicetree/bindings/phy/mxs-usb-phy.txt|   10 
>>   drivers/usb/phy/phy-mxs-usb.c  |   58
>> 
>>   2 files changed, 68 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
>> b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
>> index 379b84a..1d25b04 100644
>> --- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
>> +++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
>> @@ -12,6 +12,16 @@ Required properties:
>>   - interrupts: Should contain phy interrupt
>>   - fsl,anatop: phandle for anatop register, it is only for imx6 SoC
>> series
>>
>> +
>> +if (!of_property_read_u32(np, "fsl,tx-d-cal", ) &&
>> +val >= MXS_PHY_TX_D_CAL_MIN && val <= MXS_PHY_TX_D_CAL_MAX) {
>> +/* scale to 4-bit value */
>> +val = (MXS_PHY_TX_D_CAL_MAX - val) * 0xF
>> +/ (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN);
>> +mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0);
>> +mxs_phy->tx_reg_set  |= GM_USBPHY_TX_D_CAL(val);
>> +}
>> +
>
>
> I have tested "tx-d-cal", but it seems incorrect according to the xls
> you
> have provided, would you please check it again or am I wrong?


 Gah! You're right. Some of the D_CAL values need to be rounded up to
 match the xls.  And even then, the value for 86 still doesn't play nice.
   I was really hoping to avoid using a table for these values.

 The TXCALDP/DN values use a much simpler 1-to-1 scale across the 16
 possible register values and so are unaffected by a similar issue.  I
 rechecked their numbers just to be sure.
>>>
>>>
>>> The solution looks to be to scale D_CAL starting from 80 instead of
>>> 79.  If you look at the xls listing, the jump from 79 to 83 is the
>>> only time two adjacent register values result in a change greater
>>> than 2% or 3%.
>>>
>>> This will result in some code ugliness as the minimum allowed
>>> percentage (79), per the Freescale document, and the point at which
>>> we are scaling the percentage values to register values (80) are
>>> different.
>>>
>>> And, as mentioned before, the values will also have to be rounded up.
>>>
>>> This quick shell code confirms that these sorts of calculations
>>> match up with the values in the spreadsheet:
>>>
>>> for d in 119 116 114 112 109 106 103 100 97 95 93 90 88 86 83 79; do
>>> echo "$d="$(( ( (119-$d) * 0xf + (119-80)/2 ) / (119-80) ));
>>> d=$((d+1)); done
>>>
>>>
>>> I can't find any formula which would hit all of those same
>>> percentages without rounding up.
>>>
>>
>> Then, we had to use table for it. Besides, IC team confirms the default
>> value and the step for TXCAL45DP/DN are changed at next generation SoCs,
>> so I am wondering how we describe it at binding doc.
>>
>
> Which next gen SoC would this be?  The MX7?  The documentation for the USB
> PHY in that reference manual is even sparser than the one for the MX6 in
> regards to these register values.
>

Here, I mean i.mx8

> The MX7 manual does still mention that HW_USBPHY_TX_TXCAL45DP and
> HW_USBPHY_TX_TXCAL45DN should both be set to zero, but there is no listing
> as to the location of these registers, let alone their defaults/step values.
>
> Do you know where we could get the default and step values for the TXCAL
> registers on the new SoC?  This information had to come from a Freescale
> community thread for the MX6 since it wasn't defined clearly elsewhere.

In theory, these information should be listed at SoC reference manual.

BR,
Peter
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Re: [PATCH v3] usb: phy: mxs: Add DT bindings to configure TX settings

[Jaret Cantu]

On 03/23/2016 10:21 PM, Peter Chen wrote:

On Wed, Mar 23, 2016 at 02:17:27PM -0400, Jaret Cantu wrote:

On 03/23/2016 01:37 PM, Jaret Cantu wrote:

On 03/23/2016 12:36 AM, Peter Chen wrote:

On Mon, Mar 21, 2016 at 12:32:27PM -0400, Jaret Cantu wrote:

The TX settings can be calibrated for particular hardware.  The
phy is reset by Linux, so this cannot be handled by the bootloader.

The TRM mentions that the maximum resistance should be used for the
DN/DP calibration in order to pass USB certification.

The values for the TX registers are poorly described in the TRM.
The meanings of the register values were taken from another
Freescale-provided document:
https://community.freescale.com/message/566147#comment-566912

Signed-off-by: Jaret Cantu 
---
v3. Added unit suffix (-ohms) to tx-cal-45-d*

v2. Copying devicetree list
 Removed prettifying extra whitespace
 Removed unnecessary register rewrite on resume
 Use min and max constants for clarity

  .../devicetree/bindings/phy/mxs-usb-phy.txt|   10 
  drivers/usb/phy/phy-mxs-usb.c  |   58

  2 files changed, 68 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
index 379b84a..1d25b04 100644
--- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
@@ -12,6 +12,16 @@ Required properties:
  - interrupts: Should contain phy interrupt
  - fsl,anatop: phandle for anatop register, it is only for imx6 SoC
series

+
+if (!of_property_read_u32(np, "fsl,tx-d-cal", ) &&
+val >= MXS_PHY_TX_D_CAL_MIN && val <= MXS_PHY_TX_D_CAL_MAX) {
+/* scale to 4-bit value */
+val = (MXS_PHY_TX_D_CAL_MAX - val) * 0xF
+/ (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN);
+mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0);
+mxs_phy->tx_reg_set  |= GM_USBPHY_TX_D_CAL(val);
+}
+


I have tested "tx-d-cal", but it seems incorrect according to the xls you
have provided, would you please check it again or am I wrong?


Gah! You're right. Some of the D_CAL values need to be rounded up to
match the xls.  And even then, the value for 86 still doesn't play nice.
  I was really hoping to avoid using a table for these values.

The TXCALDP/DN values use a much simpler 1-to-1 scale across the 16
possible register values and so are unaffected by a similar issue.  I
rechecked their numbers just to be sure.


The solution looks to be to scale D_CAL starting from 80 instead of
79.  If you look at the xls listing, the jump from 79 to 83 is the
only time two adjacent register values result in a change greater
than 2% or 3%.

This will result in some code ugliness as the minimum allowed
percentage (79), per the Freescale document, and the point at which
we are scaling the percentage values to register values (80) are
different.

And, as mentioned before, the values will also have to be rounded up.

This quick shell code confirms that these sorts of calculations
match up with the values in the spreadsheet:

for d in 119 116 114 112 109 106 103 100 97 95 93 90 88 86 83 79; do
echo "$d="$(( ( (119-$d) * 0xf + (119-80)/2 ) / (119-80) ));
d=$((d+1)); done


I can't find any formula which would hit all of those same
percentages without rounding up.



Then, we had to use table for it. Besides, IC team confirms the default
value and the step for TXCAL45DP/DN are changed at next generation SoCs,
so I am wondering how we describe it at binding doc.



Which next gen SoC would this be?  The MX7?  The documentation for the 
USB PHY in that reference manual is even sparser than the one for the 
MX6 in regards to these register values.


The MX7 manual does still mention that HW_USBPHY_TX_TXCAL45DP and 
HW_USBPHY_TX_TXCAL45DN should both be set to zero, but there is no 
listing as to the location of these registers, let alone their 
defaults/step values.


Do you know where we could get the default and step values for the TXCAL 
registers on the new SoC?  This information had to come from a Freescale 
community thread for the MX6 since it wasn't defined clearly elsewhere.

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Re: [PATCH v3] usb: phy: mxs: Add DT bindings to configure TX settings

[Peter Chen]

On Wed, Mar 30, 2016 at 01:29:34PM +0300, Felipe Balbi wrote:
> 
> Hi,
> 
> Peter Chen  writes:
> > [ text/plain ]
> > On Wed, Mar 23, 2016 at 02:17:27PM -0400, Jaret Cantu wrote:
> >> On 03/23/2016 01:37 PM, Jaret Cantu wrote:
> >> >On 03/23/2016 12:36 AM, Peter Chen wrote:
> >> >>On Mon, Mar 21, 2016 at 12:32:27PM -0400, Jaret Cantu wrote:
> >> >>>The TX settings can be calibrated for particular hardware.  The
> >> >>>phy is reset by Linux, so this cannot be handled by the bootloader.
> >> >>>
> >> >>>The TRM mentions that the maximum resistance should be used for the
> >> >>>DN/DP calibration in order to pass USB certification.
> >> >>>
> >> >>>The values for the TX registers are poorly described in the TRM.
> >> >>>The meanings of the register values were taken from another
> >> >>>Freescale-provided document:
> >> >>>https://community.freescale.com/message/566147#comment-566912
> >> >>>
> >> >>>Signed-off-by: Jaret Cantu 
> >> >>>---
> >> >>>v3. Added unit suffix (-ohms) to tx-cal-45-d*
> >> >>>
> >> >>>v2. Copying devicetree list
> >> >>> Removed prettifying extra whitespace
> >> >>> Removed unnecessary register rewrite on resume
> >> >>> Use min and max constants for clarity
> >> >>>
> >> >>>  .../devicetree/bindings/phy/mxs-usb-phy.txt|   10 
> >> >>>  drivers/usb/phy/phy-mxs-usb.c  |   58
> >> >>>
> >> >>>  2 files changed, 68 insertions(+)
> >> >>>
> >> >>>diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
> >> >>>b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
> >> >>>index 379b84a..1d25b04 100644
> >> >>>--- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
> >> >>>+++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
> >> >>>@@ -12,6 +12,16 @@ Required properties:
> >> >>>  - interrupts: Should contain phy interrupt
> >> >>>  - fsl,anatop: phandle for anatop register, it is only for imx6 SoC
> >> >>>series
> >> >>>
> >> >>>+
> >> >>>+if (!of_property_read_u32(np, "fsl,tx-d-cal", ) &&
> >> >>>+val >= MXS_PHY_TX_D_CAL_MIN && val <= MXS_PHY_TX_D_CAL_MAX) {
> >> >>>+/* scale to 4-bit value */
> >> >>>+val = (MXS_PHY_TX_D_CAL_MAX - val) * 0xF
> >> >>>+/ (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN);
> >> >>>+mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0);
> >> >>>+mxs_phy->tx_reg_set  |= GM_USBPHY_TX_D_CAL(val);
> >> >>>+}
> >> >>>+
> >> >>
> >> >>I have tested "tx-d-cal", but it seems incorrect according to the xls you
> >> >>have provided, would you please check it again or am I wrong?
> >> >
> >> >Gah! You're right. Some of the D_CAL values need to be rounded up to
> >> >match the xls.  And even then, the value for 86 still doesn't play nice.
> >> >  I was really hoping to avoid using a table for these values.
> >> >
> >> >The TXCALDP/DN values use a much simpler 1-to-1 scale across the 16
> >> >possible register values and so are unaffected by a similar issue.  I
> >> >rechecked their numbers just to be sure.
> >> 
> >> The solution looks to be to scale D_CAL starting from 80 instead of
> >> 79.  If you look at the xls listing, the jump from 79 to 83 is the
> >> only time two adjacent register values result in a change greater
> >> than 2% or 3%.
> >> 
> >> This will result in some code ugliness as the minimum allowed
> >> percentage (79), per the Freescale document, and the point at which
> >> we are scaling the percentage values to register values (80) are
> >> different.
> >> 
> >> And, as mentioned before, the values will also have to be rounded up.
> >> 
> >> This quick shell code confirms that these sorts of calculations
> >> match up with the values in the spreadsheet:
> >> 
> >> for d in 119 116 114 112 109 106 103 100 97 95 93 90 88 86 83 79; do
> >> echo "$d="$(( ( (119-$d) * 0xf + (119-80)/2 ) / (119-80) ));
> >> d=$((d+1)); done
> >> 
> >> 
> >> I can't find any formula which would hit all of those same
> >> percentages without rounding up.
> >> 
> >
> > Then, we had to use table for it. Besides, IC team confirms the default 
> > value and the step for TXCAL45DP/DN are changed at next generation SoCs,
> > so I am wondering how we describe it at binding doc.
> 
> so I take it we're not yet ready to move forward with this ?
> 

No, we still haven't a formal solution.

-- 
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Peter Chen
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Re: [PATCH v3] usb: phy: mxs: Add DT bindings to configure TX settings

[Felipe Balbi]

Hi,

Peter Chen  writes:
> [ text/plain ]
> On Wed, Mar 23, 2016 at 02:17:27PM -0400, Jaret Cantu wrote:
>> On 03/23/2016 01:37 PM, Jaret Cantu wrote:
>> >On 03/23/2016 12:36 AM, Peter Chen wrote:
>> >>On Mon, Mar 21, 2016 at 12:32:27PM -0400, Jaret Cantu wrote:
>> >>>The TX settings can be calibrated for particular hardware.  The
>> >>>phy is reset by Linux, so this cannot be handled by the bootloader.
>> >>>
>> >>>The TRM mentions that the maximum resistance should be used for the
>> >>>DN/DP calibration in order to pass USB certification.
>> >>>
>> >>>The values for the TX registers are poorly described in the TRM.
>> >>>The meanings of the register values were taken from another
>> >>>Freescale-provided document:
>> >>>https://community.freescale.com/message/566147#comment-566912
>> >>>
>> >>>Signed-off-by: Jaret Cantu 
>> >>>---
>> >>>v3. Added unit suffix (-ohms) to tx-cal-45-d*
>> >>>
>> >>>v2. Copying devicetree list
>> >>> Removed prettifying extra whitespace
>> >>> Removed unnecessary register rewrite on resume
>> >>> Use min and max constants for clarity
>> >>>
>> >>>  .../devicetree/bindings/phy/mxs-usb-phy.txt|   10 
>> >>>  drivers/usb/phy/phy-mxs-usb.c  |   58
>> >>>
>> >>>  2 files changed, 68 insertions(+)
>> >>>
>> >>>diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
>> >>>b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
>> >>>index 379b84a..1d25b04 100644
>> >>>--- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
>> >>>+++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
>> >>>@@ -12,6 +12,16 @@ Required properties:
>> >>>  - interrupts: Should contain phy interrupt
>> >>>  - fsl,anatop: phandle for anatop register, it is only for imx6 SoC
>> >>>series
>> >>>
>> >>>+
>> >>>+if (!of_property_read_u32(np, "fsl,tx-d-cal", ) &&
>> >>>+val >= MXS_PHY_TX_D_CAL_MIN && val <= MXS_PHY_TX_D_CAL_MAX) {
>> >>>+/* scale to 4-bit value */
>> >>>+val = (MXS_PHY_TX_D_CAL_MAX - val) * 0xF
>> >>>+/ (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN);
>> >>>+mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0);
>> >>>+mxs_phy->tx_reg_set  |= GM_USBPHY_TX_D_CAL(val);
>> >>>+}
>> >>>+
>> >>
>> >>I have tested "tx-d-cal", but it seems incorrect according to the xls you
>> >>have provided, would you please check it again or am I wrong?
>> >
>> >Gah! You're right. Some of the D_CAL values need to be rounded up to
>> >match the xls.  And even then, the value for 86 still doesn't play nice.
>> >  I was really hoping to avoid using a table for these values.
>> >
>> >The TXCALDP/DN values use a much simpler 1-to-1 scale across the 16
>> >possible register values and so are unaffected by a similar issue.  I
>> >rechecked their numbers just to be sure.
>> 
>> The solution looks to be to scale D_CAL starting from 80 instead of
>> 79.  If you look at the xls listing, the jump from 79 to 83 is the
>> only time two adjacent register values result in a change greater
>> than 2% or 3%.
>> 
>> This will result in some code ugliness as the minimum allowed
>> percentage (79), per the Freescale document, and the point at which
>> we are scaling the percentage values to register values (80) are
>> different.
>> 
>> And, as mentioned before, the values will also have to be rounded up.
>> 
>> This quick shell code confirms that these sorts of calculations
>> match up with the values in the spreadsheet:
>> 
>> for d in 119 116 114 112 109 106 103 100 97 95 93 90 88 86 83 79; do
>> echo "$d="$(( ( (119-$d) * 0xf + (119-80)/2 ) / (119-80) ));
>> d=$((d+1)); done
>> 
>> 
>> I can't find any formula which would hit all of those same
>> percentages without rounding up.
>> 
>
> Then, we had to use table for it. Besides, IC team confirms the default 
> value and the step for TXCAL45DP/DN are changed at next generation SoCs,
> so I am wondering how we describe it at binding doc.

so I take it we're not yet ready to move forward with this ?

-- 
balbi


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Description: PGP signature

Re: [PATCH v3] usb: phy: mxs: Add DT bindings to configure TX settings

[Jaret Cantu]

On 03/23/2016 01:37 PM, Jaret Cantu wrote:

On 03/23/2016 12:36 AM, Peter Chen wrote:

On Mon, Mar 21, 2016 at 12:32:27PM -0400, Jaret Cantu wrote:

The TX settings can be calibrated for particular hardware.  The
phy is reset by Linux, so this cannot be handled by the bootloader.

The TRM mentions that the maximum resistance should be used for the
DN/DP calibration in order to pass USB certification.

The values for the TX registers are poorly described in the TRM.
The meanings of the register values were taken from another
Freescale-provided document:
https://community.freescale.com/message/566147#comment-566912

Signed-off-by: Jaret Cantu 
---
v3. Added unit suffix (-ohms) to tx-cal-45-d*

v2. Copying devicetree list
 Removed prettifying extra whitespace
 Removed unnecessary register rewrite on resume
 Use min and max constants for clarity

  .../devicetree/bindings/phy/mxs-usb-phy.txt|   10 
  drivers/usb/phy/phy-mxs-usb.c  |   58

  2 files changed, 68 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
index 379b84a..1d25b04 100644
--- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
@@ -12,6 +12,16 @@ Required properties:
  - interrupts: Should contain phy interrupt
  - fsl,anatop: phandle for anatop register, it is only for imx6 SoC
series

+
+if (!of_property_read_u32(np, "fsl,tx-d-cal", ) &&
+val >= MXS_PHY_TX_D_CAL_MIN && val <= MXS_PHY_TX_D_CAL_MAX) {
+/* scale to 4-bit value */
+val = (MXS_PHY_TX_D_CAL_MAX - val) * 0xF
+/ (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN);
+mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0);
+mxs_phy->tx_reg_set  |= GM_USBPHY_TX_D_CAL(val);
+}
+


I have tested "tx-d-cal", but it seems incorrect according to the xls you
have provided, would you please check it again or am I wrong?


Gah! You're right. Some of the D_CAL values need to be rounded up to
match the xls.  And even then, the value for 86 still doesn't play nice.
  I was really hoping to avoid using a table for these values.

The TXCALDP/DN values use a much simpler 1-to-1 scale across the 16
possible register values and so are unaffected by a similar issue.  I
rechecked their numbers just to be sure.


The solution looks to be to scale D_CAL starting from 80 instead of 79. 
 If you look at the xls listing, the jump from 79 to 83 is the only 
time two adjacent register values result in a change greater than 2% or 3%.


This will result in some code ugliness as the minimum allowed percentage 
(79), per the Freescale document, and the point at which we are scaling 
the percentage values to register values (80) are different.


And, as mentioned before, the values will also have to be rounded up.

This quick shell code confirms that these sorts of calculations match up 
with the values in the spreadsheet:


for d in 119 116 114 112 109 106 103 100 97 95 93 90 88 86 83 79; do 
echo "$d="$(( ( (119-$d) * 0xf + (119-80)/2 ) / (119-80) )); d=$((d+1)); 
done



I can't find any formula which would hit all of those same percentages 
without rounding up.







dts changes:

+ {
+   fsl,tx-d-cal = <109>;
+};
+
+ {
+   fsl,tx-d-cal = <106>;
+};
+

The phy1's tx-d-cal is 0x3, and phy2's tx-d-cal is 0x4 after PHY
initialization,
but according to xls, it should be 0x4 and 0x5.


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Re: [PATCH v3] usb: phy: mxs: Add DT bindings to configure TX settings

[Jaret Cantu]

On 03/23/2016 12:36 AM, Peter Chen wrote:

On Mon, Mar 21, 2016 at 12:32:27PM -0400, Jaret Cantu wrote:

The TX settings can be calibrated for particular hardware.  The
phy is reset by Linux, so this cannot be handled by the bootloader.

The TRM mentions that the maximum resistance should be used for the
DN/DP calibration in order to pass USB certification.

The values for the TX registers are poorly described in the TRM.
The meanings of the register values were taken from another
Freescale-provided document:
https://community.freescale.com/message/566147#comment-566912

Signed-off-by: Jaret Cantu 
---
v3. Added unit suffix (-ohms) to tx-cal-45-d*

v2. Copying devicetree list
 Removed prettifying extra whitespace
 Removed unnecessary register rewrite on resume
 Use min and max constants for clarity

  .../devicetree/bindings/phy/mxs-usb-phy.txt|   10 
  drivers/usb/phy/phy-mxs-usb.c  |   58 
  2 files changed, 68 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt 
b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
index 379b84a..1d25b04 100644
--- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
@@ -12,6 +12,16 @@ Required properties:
  - interrupts: Should contain phy interrupt
  - fsl,anatop: phandle for anatop register, it is only for imx6 SoC series

+
+   if (!of_property_read_u32(np, "fsl,tx-d-cal", ) &&
+   val >= MXS_PHY_TX_D_CAL_MIN && val <= MXS_PHY_TX_D_CAL_MAX) {
+   /* scale to 4-bit value */
+   val = (MXS_PHY_TX_D_CAL_MAX - val) * 0xF
+   / (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN);
+   mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0);
+   mxs_phy->tx_reg_set  |= GM_USBPHY_TX_D_CAL(val);
+   }
+


I have tested "tx-d-cal", but it seems incorrect according to the xls you
have provided, would you please check it again or am I wrong?


Gah! You're right. Some of the D_CAL values need to be rounded up to 
match the xls.  And even then, the value for 86 still doesn't play nice. 
 I was really hoping to avoid using a table for these values.


The TXCALDP/DN values use a much simpler 1-to-1 scale across the 16 
possible register values and so are unaffected by a similar issue.  I 
rechecked their numbers just to be sure.




dts changes:

+ {
+   fsl,tx-d-cal = <109>;
+};
+
+ {
+   fsl,tx-d-cal = <106>;
+};
+

The phy1's tx-d-cal is 0x3, and phy2's tx-d-cal is 0x4 after PHY initialization,
but according to xls, it should be 0x4 and 0x5.


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Re: [PATCH v3] usb: phy: mxs: Add DT bindings to configure TX settings

[Rob Herring]

On Mon, Mar 21, 2016 at 12:32:27PM -0400, Jaret Cantu wrote:
> The TX settings can be calibrated for particular hardware.  The
> phy is reset by Linux, so this cannot be handled by the bootloader.
> 
> The TRM mentions that the maximum resistance should be used for the
> DN/DP calibration in order to pass USB certification.
> 
> The values for the TX registers are poorly described in the TRM.
> The meanings of the register values were taken from another
> Freescale-provided document:
> https://community.freescale.com/message/566147#comment-566912
> 
> Signed-off-by: Jaret Cantu 
> ---
> v3. Added unit suffix (-ohms) to tx-cal-45-d*
> 
> v2. Copying devicetree list
> Removed prettifying extra whitespace
> Removed unnecessary register rewrite on resume
> Use min and max constants for clarity
> 
>  .../devicetree/bindings/phy/mxs-usb-phy.txt|   10 
>  drivers/usb/phy/phy-mxs-usb.c  |   58 
> 
>  2 files changed, 68 insertions(+)

Acked-by: Rob Herring 
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Re: [PATCH v3] usb: phy: mxs: Add DT bindings to configure TX settings

[Peter Chen]

On Mon, Mar 21, 2016 at 12:32:27PM -0400, Jaret Cantu wrote:
> The TX settings can be calibrated for particular hardware.  The
> phy is reset by Linux, so this cannot be handled by the bootloader.
> 
> The TRM mentions that the maximum resistance should be used for the
> DN/DP calibration in order to pass USB certification.
> 
> The values for the TX registers are poorly described in the TRM.
> The meanings of the register values were taken from another
> Freescale-provided document:
> https://community.freescale.com/message/566147#comment-566912
> 
> Signed-off-by: Jaret Cantu 
> ---
> v3. Added unit suffix (-ohms) to tx-cal-45-d*
> 
> v2. Copying devicetree list
> Removed prettifying extra whitespace
> Removed unnecessary register rewrite on resume
> Use min and max constants for clarity
> 
>  .../devicetree/bindings/phy/mxs-usb-phy.txt|   10 
>  drivers/usb/phy/phy-mxs-usb.c  |   58 
> 
>  2 files changed, 68 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt 
> b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
> index 379b84a..1d25b04 100644
> --- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
> @@ -12,6 +12,16 @@ Required properties:
>  - interrupts: Should contain phy interrupt
>  - fsl,anatop: phandle for anatop register, it is only for imx6 SoC series
>  
> +
> + if (!of_property_read_u32(np, "fsl,tx-d-cal", ) &&
> + val >= MXS_PHY_TX_D_CAL_MIN && val <= MXS_PHY_TX_D_CAL_MAX) {
> + /* scale to 4-bit value */
> + val = (MXS_PHY_TX_D_CAL_MAX - val) * 0xF
> + / (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN);
> + mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0);
> + mxs_phy->tx_reg_set  |= GM_USBPHY_TX_D_CAL(val);
> + }
> +

I have tested "tx-d-cal", but it seems incorrect according to the xls you
have provided, would you please check it again or am I wrong?

dts changes:

+ {
+   fsl,tx-d-cal = <109>;
+};
+
+ {
+   fsl,tx-d-cal = <106>;
+};
+

The phy1's tx-d-cal is 0x3, and phy2's tx-d-cal is 0x4 after PHY 
initialization, 
but according to xls, it should be 0x4 and 0x5.

-- 
Best Regards,
Peter Chen
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Re: [PATCH v3] usb: phy: mxs: Add DT bindings to configure TX settings

[Peter Chen]

On Tue, Mar 22, 2016 at 12:32 AM, Jaret Cantu  wrote:
> The TX settings can be calibrated for particular hardware.  The
> phy is reset by Linux, so this cannot be handled by the bootloader.
>
> The TRM mentions that the maximum resistance should be used for the
> DN/DP calibration in order to pass USB certification.
>
> The values for the TX registers are poorly described in the TRM.
> The meanings of the register values were taken from another
> Freescale-provided document:
> https://community.freescale.com/message/566147#comment-566912
>

I am checking with IC team about this value, and if this value can be
adapted for all SoCs
which use this PHY.  Felipe, please hold on queue this patch, thanks.

Peter

> Signed-off-by: Jaret Cantu 
> ---
> v3. Added unit suffix (-ohms) to tx-cal-45-d*
>
> v2. Copying devicetree list
> Removed prettifying extra whitespace
> Removed unnecessary register rewrite on resume
> Use min and max constants for clarity
>
>  .../devicetree/bindings/phy/mxs-usb-phy.txt|   10 
>  drivers/usb/phy/phy-mxs-usb.c  |   58 
> 
>  2 files changed, 68 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt 
> b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
> index 379b84a..1d25b04 100644
> --- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
> @@ -12,6 +12,16 @@ Required properties:
>  - interrupts: Should contain phy interrupt
>  - fsl,anatop: phandle for anatop register, it is only for imx6 SoC series
>
> +Optional properties:
> +- fsl,tx-cal-45-dn-ohms: Integer [30-55]. Resistance (in ohms) of switchable
> +  high-speed trimming resistor connected in parallel with the 45 ohm resistor
> +  that terminates the DN output signal. Default: 45
> +- fsl,tx-cal-45-dp-ohms: Integer [30-55]. Resistance (in ohms) of switchable
> +  high-speed trimming resistor connected in parallel with the 45 ohm resistor
> +  that terminates the DP output signal. Default: 45
> +- fsl,tx-d-cal: Integer [79-119]. Current trimming value (as a percentage) of
> +  the 17.78mA TX reference current. Default: 100
> +
>  Example:
>  usbphy1: usbphy@020c9000 {
> compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
> diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c
> index 00bfea0..6c6b12c 100644
> --- a/drivers/usb/phy/phy-mxs-usb.c
> +++ b/drivers/usb/phy/phy-mxs-usb.c
> @@ -27,6 +27,7 @@
>  #define DRIVER_NAME "mxs_phy"
>
>  #define HW_USBPHY_PWD  0x00
> +#define HW_USBPHY_TX   0x10
>  #define HW_USBPHY_CTRL 0x30
>  #define HW_USBPHY_CTRL_SET 0x34
>  #define HW_USBPHY_CTRL_CLR 0x38
> @@ -38,6 +39,10 @@
>  #define HW_USBPHY_IP_SET   0x94
>  #define HW_USBPHY_IP_CLR   0x98
>
> +#define GM_USBPHY_TX_TXCAL45DP(x)(((x) & 0xf) << 16)
> +#define GM_USBPHY_TX_TXCAL45DN(x)(((x) & 0xf) << 8)
> +#define GM_USBPHY_TX_D_CAL(x)(((x) & 0xf) << 0)
> +
>  #define BM_USBPHY_CTRL_SFTRST  BIT(31)
>  #define BM_USBPHY_CTRL_CLKGATE BIT(30)
>  #define BM_USBPHY_CTRL_OTG_ID_VALUEBIT(27)
> @@ -115,6 +120,12 @@
>   */
>  #define MXS_PHY_NEED_IP_FIXBIT(3)
>
> +/* Minimum and maximum values for device tree entries */
> +#define MXS_PHY_TX_CAL45_MIN   30
> +#define MXS_PHY_TX_CAL45_MAX   55
> +#define MXS_PHY_TX_D_CAL_MIN   79
> +#define MXS_PHY_TX_D_CAL_MAX   119
> +
>  struct mxs_phy_data {
> unsigned int flags;
>  };
> @@ -164,6 +175,8 @@ struct mxs_phy {
> const struct mxs_phy_data *data;
> struct regmap *regmap_anatop;
> int port_id;
> +   u32 tx_reg_set;
> +   u32 tx_reg_mask;
>  };
>
>  static inline bool is_imx6q_phy(struct mxs_phy *mxs_phy)
> @@ -185,6 +198,20 @@ static void mxs_phy_clock_switch_delay(void)
> usleep_range(300, 400);
>  }
>
> +static void mxs_phy_tx_init(struct mxs_phy *mxs_phy)
> +{
> +   void __iomem *base = mxs_phy->phy.io_priv;
> +   u32 phytx;
> +
> +   /* Update TX register if there is anything to write */
> +   if (mxs_phy->tx_reg_mask) {
> +   phytx = readl(base + HW_USBPHY_TX);
> +   phytx &= ~mxs_phy->tx_reg_mask;
> +   phytx |= mxs_phy->tx_reg_set;
> +   writel(phytx, base + HW_USBPHY_TX);
> +   }
> +}
> +
>  static int mxs_phy_hw_init(struct mxs_phy *mxs_phy)
>  {
> int ret;
> @@ -214,6 +241,8 @@ static int mxs_phy_hw_init(struct mxs_phy *mxs_phy)
> if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX)
> writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET);
>
> +   mxs_phy_tx_init(mxs_phy);
> +
>