Re: [linux-yocto] [kernel-cache][PATCH 10/11] common-pc: Enable DesignWare PWM & SPI Controller support
> -Original Message- > From: linux-yocto@lists.yoctoproject.org yo...@lists.yoctoproject.org> On Behalf Of Bruce Ashfield > Sent: Thursday, March 9, 2023 5:51 AM > To: Saini, Naveen Kumar > Cc: linux-yocto@lists.yoctoproject.org > Subject: Re: [linux-yocto] [kernel-cache][PATCH 10/11] common-pc: Enable > DesignWare PWM & SPI Controller support > > In message: [linux-yocto] [kernel-cache][PATCH 10/11] common-pc: Enable > DesignWare PWM & SPI Controller support on 06/03/2023 Naveen Saini > wrote: > > > Signed-off-by: Naveen Saini > > --- > > bsp/common-pc/common-pc-drivers.cfg | 9 + > > 1 file changed, 9 insertions(+) > > > > diff --git a/bsp/common-pc/common-pc-drivers.cfg > > b/bsp/common-pc/common-pc-drivers.cfg > > index 5e2018d6..0d2672bc 100644 > > --- a/bsp/common-pc/common-pc-drivers.cfg > > +++ b/bsp/common-pc/common-pc-drivers.cfg > > @@ -62,3 +62,12 @@ CONFIG_EEPROM_AT24=m > > > > CONFIG_NVME_CORE=y > > CONFIG_BLK_DEV_NVME=y > > + > > +# DesignWare PWM Controller > > +CONFIG_PWM_DWC=m > > + > > +# DesignWare SPI controller core support CONFIG_SPI_DESIGNWARE=m > > +CONFIG_SPI_DW_DMA=y CONFIG_SPI_DW_PCI=m > CONFIG_SPI_DW_MMIO=m > > Out of curiosity, why did these specific drivers get enabled in common-pc- > drivers, versus a named feature that could be included ? Yes, it should be included as named feature. I will do that. > > Bruce > > > -- > > 2.25.1 > > > > > > > > > -=-=-=-=-=-=-=-=-=-=-=- Links: You receive all messages sent to this group. View/Reply Online (#12257): https://lists.yoctoproject.org/g/linux-yocto/message/12257 Mute This Topic: https://lists.yoctoproject.org/mt/97420988/21656 Group Owner: linux-yocto+ow...@lists.yoctoproject.org Unsubscribe: https://lists.yoctoproject.org/g/linux-yocto/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [linux-yocto] [kernel-cache][PATCH 01/11] features: drop RANDOM_TRUST_CPU
Hi Bruce, Thank you for reviewing. > -Original Message- > From: Bruce Ashfield > Sent: Thursday, March 9, 2023 6:00 AM > To: Saini, Naveen Kumar > Cc: linux-yocto@lists.yoctoproject.org > Subject: Re: [linux-yocto] [kernel-cache][PATCH 01/11] features: drop > RANDOM_TRUST_CPU > > Hi Naveen, > > I commented directly on one of the patches, and this 1/11 in particular is > clear, but the other patches in the series are a little bit less unclear as > to the > overall goal. > > As Paul mentioned, a 0/N for the series would have helped explain the > motivation. Yes, will make sure I provide that next time. > > I didn't reply directly to the review and thread that started, as everyone had > valid points to make. We have a balance to strike between enablement and > also providing a streamlined base configuration. > > I'm adding the following, so it'll be captured in the archives: > > Generic demo and "works everywhere" configs have their place, and in our > model, they are built up using the kernel features on top of a tuned baseline > configuration. It is easier to add than to remove. So we turn on as little as > possible, then have the kernel types, followed by kernel features triggered > by distro or recipe space coordinated features. > > The baseline machine configurations shouldn't be guessing what the distro or > image needs, and the distro or image shouldn't be undoing things that are > done by the baseline configuration to tune/slim it down. Those baseline > configs need to serve all the kernel types, they are also additive (for the > most part .. tiny is the outlier), not subtractive. > > All that being said, the review and comments are exactly what I like to see. > As we keep in mind that the machine/baseline configuration cannot possibly > be all things to all configurations. Not all users of the kernel-cache have to > adhere to the guidelines we have for the reference boards, kernel types, > etc, but we can certainly try and guide them in that direction, which is the > point of the shared repository of configuration fragments .. and that's what > we are doing here. > > What the intel boards are doing, actually is quite close to what I described > above. These are named features, and are included versus just adding the > configs to a giant .cfg/.scc file. That means that someone doing a new BSP > could decide what type of functionality to build on top of the baseline "it > boots" configuration. Maybe some of the fragments doing most of the > including could be named a bit differently, or be split a bit .. but that is > something we can do as different functionality needs are found on the ends > of the new > -> old board spectrum. > > So my only real question was whether or not we can split the fragments out > of common-pc, into a named fragment. For the ones being added in this series, I guess we can move them to a separate named .scc/.cfg instead of including in intel-common- drivers.scc. We can also create a new config for intel-skylake-64 machine (which enables relatively newer hardware) in meta-intel which can then turn on these features by default. Or, we can just enable the features in .scc via KERNEL_FEATURES in meta-intel so it's easier to disable or override if required. Please let us know what you think. > > That, and I assume this is for master, since you mentioned 6.2. Yes, this is for master/6.2. Thanks, Naveen > > Bruce > > In message: [linux-yocto] [kernel-cache][PATCH 01/11] features: drop > RANDOM_TRUST_CPU on 06/03/2023 Naveen Saini wrote: > > > This option is no longer present in v6.2 as the following commit removed it: > > > https://github.com/torvalds/linux/commit/b9b01a5625b5a9e9d96d14d4a813 > a > > 54e8a124f4b > > > > Signed-off-by: Naveen Saini > > --- > > bsp/intel-common/intel-common-drivers.scc | 1 - > > features/random/random.cfg| 2 -- > > features/random/random.scc| 5 - > > kern-features.rc | 1 - > > 4 files changed, 9 deletions(-) > > delete mode 100644 features/random/random.cfg delete mode 100644 > > features/random/random.scc > > > > diff --git a/bsp/intel-common/intel-common-drivers.scc > > b/bsp/intel-common/intel-common-drivers.scc > > index 59dc6750..33451730 100644 > > --- a/bsp/intel-common/intel-common-drivers.scc > > +++ b/bsp/intel-common/intel-common-drivers.scc > > @@ -85,7 +85,6 @@ include features/input/keyboard-gpio.scc include > > features/ciphers/ciphers.scc include features/pci-iov/pci-iov.scc > > include features/intel-tco/intel-tco.scc -include > > features/random/random.scc > > > > # default policy for standard kernels include > > cfg/usb-mass-storage.scc diff --git a/features/random/random.cfg > > b/features/random/random.cfg deleted file mode 100644 index > > bacab3cb.. > > --- a/features/random/random.cfg > > +++ /dev/null > > @@ -1,2 +0,0 @@ > > -# SPDX-License-Identifier: MIT > > -CONFIG_RANDOM_TRUST_CPU=y > > diff --git
Re: [linux-yocto] [PATCH] tty: serial: fsl_lpuart: don't break the on-going transfer when global reset
Hi bruce
Please help merge this patch to v5.15/standard/nxp-sdk-5.15/nxp-soc and
v5.15/standard/preempt-rt/nxp-sdk-5.15/nxp-soc branches
thanks
xiaolei
From: linux-yocto@lists.yoctoproject.org
on behalf of Xiaolei Wang via lists.yoctoproject.org
Sent: Monday, March 13, 2023 9:44 PM
To: bruce.ashfi...@gmail.com
Cc: linux-yocto@lists.yoctoproject.org
Subject: [linux-yocto] [PATCH] tty: serial: fsl_lpuart: don't break the
on-going transfer when global reset
From: Sherry Sun
commit 76bad3f88750f8cc465c489e6846249e0bc3d8f5 from upstream.
lpuart_global_reset() shouldn't break the on-going transmit engine, need
to recover the on-going data transfer after reset.
This can help earlycon here, since commit 60f361722ad2 ("serial:
fsl_lpuart: Reset prior to registration") moved lpuart_global_reset()
before uart_add_one_port(), earlycon is writing during global reset,
as global reset will disable the TX and clear the baud rate register,
which caused the earlycon cannot work any more after reset, needs to
restore the baud rate and re-enable the transmitter to recover the
earlycon write.
Also move the lpuart_global_reset() down, then we can reuse the
lpuart32_tx_empty() without declaration.
Fixes: bd5305dcabbc ("tty: serial: fsl_lpuart: do software reset for imx7ulp
and imx8qxp")
Signed-off-by: Sherry Sun
Link: https://lore.kernel.org/r/20221024085844.22786-1-sherry@nxp.com
Signed-off-by: Greg Kroah-Hartman
Signed-off-by: Xiaolei Wang
---
drivers/tty/serial/fsl_lpuart.c | 75 +
1 file changed, 48 insertions(+), 27 deletions(-)
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index 3f8fe874905d..5eae048950b5 100644
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -433,33 +433,6 @@ static unsigned int lpuart_get_baud_clk_rate(struct
lpuart_port *sport)
#define lpuart_enable_clks(x) __lpuart_enable_clks(x, true)
#define lpuart_disable_clks(x) __lpuart_enable_clks(x, false)
-static int lpuart_global_reset(struct lpuart_port *sport)
-{
- struct uart_port *port = >port;
- void __iomem *global_addr;
- int ret;
-
- if (uart_console(port))
- return 0;
-
- ret = clk_prepare_enable(sport->ipg_clk);
- if (ret) {
- dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n",
ret);
- return ret;
- }
-
- if (is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) ||
is_imx8qxp_lpuart(sport)) {
- global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
- writel(UART_GLOBAL_RST, global_addr);
- usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
- writel(0, global_addr);
- usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
- }
-
- clk_disable_unprepare(sport->ipg_clk);
- return 0;
-}
-
static void lpuart_stop_tx(struct uart_port *port)
{
unsigned char temp;
@@ -2845,6 +2818,54 @@ static int lpuart_attach_pd(struct device *dev)
return 0;
}
+static int lpuart_global_reset(struct lpuart_port *sport)
+{
+ struct uart_port *port = >port;
+ void __iomem *global_addr;
+ unsigned long ctrl, bd;
+ unsigned int val = 0;
+ int ret;
+
+ ret = clk_prepare_enable(sport->ipg_clk);
+ if (ret) {
+ dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n",
ret);
+ return ret;
+ }
+
+ if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
+ /*
+* If the transmitter is used by earlycon, wait for transmit
engine to
+* complete and then reset.
+ */
+ ctrl = lpuart32_read(port, UARTCTRL);
+ if (ctrl & UARTCTRL_TE) {
+ bd = lpuart32_read(>port, UARTBAUD);
+ if (read_poll_timeout(lpuart32_tx_empty, val, val, 1,
10, false,
+ port)) {
+ dev_warn(sport->port.dev,
+ "timeout waiting for transmit engine to
complete\n");
+ clk_disable_unprepare(sport->ipg_clk);
+ return 0;
+ }
+ }
+
+ global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
+ writel(UART_GLOBAL_RST, global_addr);
+ usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
+ writel(0, global_addr);
+ usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
+
+ /* Recover the transmitter for earlycon. */
+ if (ctrl & UARTCTRL_TE) {
+ lpuart32_write(port, bd, UARTBAUD);
+ lpuart32_write(port, ctrl, UARTCTRL);
+ }
+
[linux-yocto] [PATCH] tty: serial: fsl_lpuart: don't break the on-going transfer when global reset
From: Sherry Sun
commit 76bad3f88750f8cc465c489e6846249e0bc3d8f5 from upstream.
lpuart_global_reset() shouldn't break the on-going transmit engine, need
to recover the on-going data transfer after reset.
This can help earlycon here, since commit 60f361722ad2 ("serial:
fsl_lpuart: Reset prior to registration") moved lpuart_global_reset()
before uart_add_one_port(), earlycon is writing during global reset,
as global reset will disable the TX and clear the baud rate register,
which caused the earlycon cannot work any more after reset, needs to
restore the baud rate and re-enable the transmitter to recover the
earlycon write.
Also move the lpuart_global_reset() down, then we can reuse the
lpuart32_tx_empty() without declaration.
Fixes: bd5305dcabbc ("tty: serial: fsl_lpuart: do software reset for imx7ulp
and imx8qxp")
Signed-off-by: Sherry Sun
Link: https://lore.kernel.org/r/20221024085844.22786-1-sherry@nxp.com
Signed-off-by: Greg Kroah-Hartman
Signed-off-by: Xiaolei Wang
---
drivers/tty/serial/fsl_lpuart.c | 75 +
1 file changed, 48 insertions(+), 27 deletions(-)
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index 3f8fe874905d..5eae048950b5 100644
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -433,33 +433,6 @@ static unsigned int lpuart_get_baud_clk_rate(struct
lpuart_port *sport)
#define lpuart_enable_clks(x) __lpuart_enable_clks(x, true)
#define lpuart_disable_clks(x) __lpuart_enable_clks(x, false)
-static int lpuart_global_reset(struct lpuart_port *sport)
-{
- struct uart_port *port = >port;
- void __iomem *global_addr;
- int ret;
-
- if (uart_console(port))
- return 0;
-
- ret = clk_prepare_enable(sport->ipg_clk);
- if (ret) {
- dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n",
ret);
- return ret;
- }
-
- if (is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) ||
is_imx8qxp_lpuart(sport)) {
- global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
- writel(UART_GLOBAL_RST, global_addr);
- usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
- writel(0, global_addr);
- usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
- }
-
- clk_disable_unprepare(sport->ipg_clk);
- return 0;
-}
-
static void lpuart_stop_tx(struct uart_port *port)
{
unsigned char temp;
@@ -2845,6 +2818,54 @@ static int lpuart_attach_pd(struct device *dev)
return 0;
}
+static int lpuart_global_reset(struct lpuart_port *sport)
+{
+ struct uart_port *port = >port;
+ void __iomem *global_addr;
+ unsigned long ctrl, bd;
+ unsigned int val = 0;
+ int ret;
+
+ ret = clk_prepare_enable(sport->ipg_clk);
+ if (ret) {
+ dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n",
ret);
+ return ret;
+ }
+
+ if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
+ /*
+* If the transmitter is used by earlycon, wait for transmit
engine to
+* complete and then reset.
+ */
+ ctrl = lpuart32_read(port, UARTCTRL);
+ if (ctrl & UARTCTRL_TE) {
+ bd = lpuart32_read(>port, UARTBAUD);
+ if (read_poll_timeout(lpuart32_tx_empty, val, val, 1,
10, false,
+ port)) {
+ dev_warn(sport->port.dev,
+ "timeout waiting for transmit engine to
complete\n");
+ clk_disable_unprepare(sport->ipg_clk);
+ return 0;
+ }
+ }
+
+ global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
+ writel(UART_GLOBAL_RST, global_addr);
+ usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
+ writel(0, global_addr);
+ usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
+
+ /* Recover the transmitter for earlycon. */
+ if (ctrl & UARTCTRL_TE) {
+ lpuart32_write(port, bd, UARTBAUD);
+ lpuart32_write(port, ctrl, UARTCTRL);
+ }
+
}
+
+ clk_disable_unprepare(sport->ipg_clk);
+ return 0;
+}
+
static int lpuart_probe(struct platform_device *pdev)
{
const struct lpuart_soc_data *sdata =
of_device_get_match_data(>dev);
--
2.25.1
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