[linux-yocto]: [kernel/kernel-rt]: nxp-ls1028: kernel patches to improve graphics

2023-05-10 Thread Meng Li via lists.yoctoproject.org
From: Limeng 

Hi Bruce,

The 2 patches are used to improve graphics for NXP ls1028 BSP
So, could you please help merge these patches into linux-ycoto kernel, both 
below 2 branchs?
v6.1/standard/nxp-sdk-6.1/nxp-soc
v6.1/standard/preempt-rt/nxp-sdk-6.1/nxp-soc

diffstat info as below:

 Kconfig|1 +
 cdns-mhdp-dp.c |   16 
 2 files changed, 5 insertions(+), 12 deletions(-)


thanks,
Limeng

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[linux-yocto] [PATCH 2/2] drivers: drm: cadence: select DRM_DISPLAY_HDMI_HELPER if Cadence HDCP driver is enabled

2023-05-10 Thread Meng Li via lists.yoctoproject.org
According to commit 4fc8cb47fcfd("drm/display: Move HDMI
Helpers into display-helper module "), it needs to select
DRM_DISPLAY_HDMI_HELPER if Cadence HDCP driver is enabled.

Signed-off-by: Meng Li 
---
 drivers/gpu/drm/bridge/cadence/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig 
b/drivers/gpu/drm/bridge/cadence/Kconfig
index 736b107fab74..78f0fd4bc143 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -30,6 +30,7 @@ config DRM_CDNS_MHDP
tristate "Cadence MHDP COMMON API driver"
select DRM_DISPLAY_DP_HELPER
select DRM_DISPLAY_HELPER
+   select DRM_DISPLAY_HDMI_HELPER
select DRM_DISPLAY_HDCP_HELPER
select DRM_KMS_HELPER
select DRM_PANEL_BRIDGE
-- 
2.40.1


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[linux-yocto] [PATCH 1/2] Revert "gpu: drm: bridge: improve the function of getting training status"

2023-05-10 Thread Meng Li via lists.yoctoproject.org
This reverts commit 1d6d6a6a2d8704ae641b4439fad0a2d45ecc8372.

After upgrading u-boot to version 2022.04, this patch is no longer
needed.

Signed-off-by: Meng Li 
---
 drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c | 16 
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c 
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c
index 46fc27dba884..299e533d6b52 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c
@@ -233,21 +233,13 @@ static int cdns_mhdp_get_training_status(struct 
cdns_mhdp_device *mhdp)
if (ret)
goto err_get_training_status;
 
-   if (of_machine_is_compatible("fsl,ls1028a-rdb"))
-   ret = cdns_mhdp_mailbox_validate_receive(mhdp, 
MB_MODULE_ID_DP_TX,
-   DPTX_READ_LINK_STAT,
-   sizeof(status) - 3);
-   else
-   ret = cdns_mhdp_mailbox_validate_receive(mhdp, 
MB_MODULE_ID_DP_TX,
-   DPTX_READ_LINK_STAT,
-   sizeof(status));
+   ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX,
+DPTX_READ_LINK_STAT,
+sizeof(status));
if (ret)
goto err_get_training_status;
 
-   if (of_machine_is_compatible("fsl,ls1028a-rdb"))
-   ret = cdns_mhdp_mailbox_read_receive(mhdp, status, 
sizeof(status) - 3);
-   else
-   ret = cdns_mhdp_mailbox_read_receive(mhdp, status, 
sizeof(status));
+   ret = cdns_mhdp_mailbox_read_receive(mhdp, status, sizeof(status));
if (ret)
goto err_get_training_status;
 
-- 
2.40.1


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Re: [linux-yocto][v6.1] nxp-s32g: aptiv dts files

2023-05-10 Thread Bruce Ashfield
In message: [linux-yocto][v6.1] nxp-s32g: aptiv dts files
on 10/05/2023 quanyang.w...@windriver.com wrote:

> From: Quanyang Wang 
> 
> Hi Bruce,
> Would you please help merge these 5 patches to the branches:
>   v6.1/standard/preempt-rt/nxp-sdk-5.15/nxp-s32g
>   v6.1/standard/nxp-sdk-5.15/nxp-s32g

merged.

Bruce

> Thanks,
> Quanyang
> 
> Quanyang Wang (5):
>   dts: Aptiv-FL: add dts file for Aptiv CVC-FL board
>   dts: Aptiv-FL: disable unsupported device nodes
>   dts: Aptiv-FL: add correct pinctrls for pfe interfaces for Aptiv-FL
> board
>   dts: Aptiv-FL: disable flexcan3
>   dts: Aptiv-FL: refactor Aptiv CVC FL s32g399a dts files
> 
>  arch/arm64/boot/dts/freescale/Makefile|   2 +
>  .../dts/freescale/s32g399a-cvc-fl-pfems.dts   |  23 +
>  .../boot/dts/freescale/s32g399a-cvc-fl.dts|  14 +
>  .../boot/dts/freescale/s32g399a-cvc-fl.dtsi   |  28 +
>  .../boot/dts/freescale/s32gxxxa-cvc-fl.dtsi   | 854 ++
>  5 files changed, 921 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/s32g399a-cvc-fl-pfems.dts
>  create mode 100644 arch/arm64/boot/dts/freescale/s32g399a-cvc-fl.dts
>  create mode 100644 arch/arm64/boot/dts/freescale/s32g399a-cvc-fl.dtsi
>  create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi
> 
> -- 
> 2.36.1
> 

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Re: [linux-yocto] [yocto-kernel-cache][yocto-6.1][PATCH] bsp: aptiv-s32g: add support for Aptiv FL board

2023-05-10 Thread Bruce Ashfield
In message: [yocto-kernel-cache][yocto-6.1][PATCH] bsp: aptiv-s32g: add support 
for Aptiv FL board
on 10/05/2023 quanyang.w...@windriver.com wrote:

> From: Quanyang Wang 
> 
> Add scc and cfg files for Aptiv FL board.

merged.

Bruce

> 
> Signed-off-by: Quanyang Wang 
> ---
> Hi Bruce,
> Would you please help merge this patch to the branch:
>   yocto-6.1
> Thanks,
> Quanyang
> ---
>  bsp/aptiv-s32g/aptiv-cvc-fl-preempt-rt.scc |   7 +
>  bsp/aptiv-s32g/aptiv-cvc.cfg   | 177 +
>  bsp/aptiv-s32g/aptiv-cvc.scc   |   7 +
>  3 files changed, 191 insertions(+)
>  create mode 100644 bsp/aptiv-s32g/aptiv-cvc-fl-preempt-rt.scc
>  create mode 100644 bsp/aptiv-s32g/aptiv-cvc.cfg
>  create mode 100644 bsp/aptiv-s32g/aptiv-cvc.scc
> 
> diff --git a/bsp/aptiv-s32g/aptiv-cvc-fl-preempt-rt.scc 
> b/bsp/aptiv-s32g/aptiv-cvc-fl-preempt-rt.scc
> new file mode 100644
> index 00..d8a0c51af0
> --- /dev/null
> +++ b/bsp/aptiv-s32g/aptiv-cvc-fl-preempt-rt.scc
> @@ -0,0 +1,7 @@
> +# SPDX-License-Identifier: MIT
> +define KMACHINE aptiv-cvc-fl
> +define KTYPE preempt-rt
> +define KARCH arm64
> +
> +include ktypes/preempt-rt
> +include aptiv-cvc.scc
> diff --git a/bsp/aptiv-s32g/aptiv-cvc.cfg b/bsp/aptiv-s32g/aptiv-cvc.cfg
> new file mode 100644
> index 00..5714cb9c74
> --- /dev/null
> +++ b/bsp/aptiv-s32g/aptiv-cvc.cfg
> @@ -0,0 +1,177 @@
> +# SPDX-License-Identifier: MIT
> +..
> +.WARNING
> +.
> +. This file is a kernel configuration fragment, and not a full kernel
> +. configuration file.  The final kernel configuration is made up of
> +. an assembly of processed fragments, each of which is designed to
> +. capture a specific part of the final configuration (e.g. platform
> +. configuration, feature configuration, and board specific hardware
> +. configuration).  For more information on kernel configuration, please
> +. consult the product documentation.
> +.
> +..
> +
> +CONFIG_ARM64=y
> +CONFIG_ARCH_NXP=y
> +CONFIG_ARCH_S32=y
> +CONFIG_SOC_S32CC=y
> +CONFIG_SCHED_MC=y
> +CONFIG_ARM_SMMU=y
> +
> +CONFIG_PINCTRL_S32CC=y
> +
> +CONFIG_CPU_IDLE=y
> +CONFIG_ARM_PSCI_CPUIDLE=y
> +CONFIG_CPU_FREQ=y
> +CONFIG_CPU_FREQ_STAT=y
> +CONFIG_CPU_FREQ_GOV_POWERSAVE=y
> +CONFIG_CPU_FREQ_GOV_USERSPACE=y
> +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
> +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
> +
> +CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y
> +#To keep align with SDK, unset the ARM_SCMI_POWER_DOMAIN config
> +# CONFIG_ARM_SCMI_POWER_DOMAIN is not set
> +
> +#CAN
> +CONFIG_CAN=y
> +CONFIG_CAN_VCAN=y
> +CONFIG_CAN_SLCAN=y
> +CONFIG_CAN_FLEXCAN=m
> +
> +#Ethernet
> +CONFIG_STMMAC_ETH=y
> +CONFIG_DWMAC_DWC_QOS_ETH=y
> +
> +#Serial
> +CONFIG_SERIAL_AMBA_PL011=y
> +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
> +CONFIG_SERIAL_FSL_LINFLEXUART=y
> +CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
> +
> +#SPI
> +CONFIG_SPI=y
> +CONFIG_SPI_FSL_DSPI=y
> +CONFIG_SPI_SPIDEV=y
> +
> +#GPIO
> +CONFIG_GPIO_CDEV=y
> +CONFIG_GPIO_S32CC=y
> +CONFIG_GPIO_PCA953X=y
> +
> +#PCIE
> +CONFIG_PCI=y
> +CONFIG_PCIE_DW=y
> +CONFIG_PCIE_DW_PLAT_HOST=y
> +CONFIG_PCI_ENDPOINT=y
> +CONFIG_PCIE_DW_PLAT_EP=y
> +CONFIG_PCIEAER=y
> +CONFIG_PCI_S32CC=y
> +
> +#USB
> +CONFIG_USB=y
> +CONFIG_USB_OTG=y
> +CONFIG_USB_OTG_FSM=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_CHIPIDEA=y
> +CONFIG_USB_CHIPIDEA_UDC=y
> +CONFIG_USB_CHIPIDEA_HOST=y
> +CONFIG_USB_CHIPIDEA_IMX=m
> +CONFIG_USB_ULPI_GENERIC=y
> +CONFIG_USB_ULPI=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_CONFIGFS=y
> +CONFIG_USB_CONFIGFS_MASS_STORAGE=y
> +
> +CONFIG_USB_ACM=y
> +CONFIG_USB_WDM=y
> +
> +CONFIG_USB_SERIAL=y
> +CONFIG_USB_SERIAL_FTDI_SIO=y
> +CONFIG_USB_SERIAL_CP210X=m
> +CONFIG_USB_SERIAL_PL2303=m
> +CONFIG_USB_SERIAL_WWAN=y
> +CONFIG_USB_SERIAL_OPTION=y
> +
> +#MMC
> +CONFIG_MMC=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_PLTFM=y
> +CONFIG_MMC_SDHCI_ESDHC_IMX=y
> +CONFIG_DMADEVICES=y
> +CONFIG_FSL_EDMA=y
> +CONFIG_CMA=y
> +CONFIG_DMA_CMA=y
> +CONFIG_CMA_SIZE_MBYTES=128
> +
> +CONFIG_MTD=y
> +CONFIG_MTD_CMDLINE_PARTS=y
> +CONFIG_MTD_BLOCK=y
> +CONFIG_MTD_CFI=y
> +CONFIG_MTD_PHYSMAP=y
> +CONFIG_MTD_PHYSMAP_OF=y
> +CONFIG_MTD_DATAFLASH=y
> +CONFIG_MTD_SPI_NOR=y
> +
> +CONFIG_INPUT_EVDEV=y
> +CONFIG_INPUT_MISC=y
> +CONFIG_INPUT_UINPUT=y
> +
> +# Thermal
> +CONFIG_THERMAL=y
> +CONFIG_S32CC_THERMAL=y
> +
> +# ADC
> +CONFIG_IIO=y
> +CONFIG_S32CC_ADC=m
> +
> +# PWM
> +CONFIG_PWM=y
> +CONFIG_PWM_FSL_FTM=m
> +
> +CONFIG_S32CC_FCCU=y
> +CONFIG_GPIOLIB=y
> +CONFIG_OF_GPIO=y
> +
> +CONFIG_MDIO_DEVICE=y
> +CONFIG_PHYLIB=y
> +
> +#QSPI
> +CONFIG_SPI_FSL_QUADSPI=y
> +
> +#RTC
> +CONFIG_RTC_CLASS=y
> +CONFIG_RTC_DRV_S32CC=y
> +CONFIG_RTC_DRV_PCF85063=y
> +
> +#I2C
> +CONFIG_I2C=y
> +CONFIG_I2C_CHARDEV=y
> +CONFIG_I2C_IMX=m
> +
> +#Watchdog
> +# We need keep this driver built-in since rmmod will trigger reboot
> +CONFIG_S32CC_WDT=y
> +
> 

Re: [linux-yocto] [linux-yocto std/rt kernel v6.1]: nxp-s32g: update kernel to v6.1 based on SDK BSP36 v5.15 release kernel

2023-05-10 Thread Bruce Ashfield
In message: [linux-yocto] [linux-yocto std/rt kernel v6.1]: nxp-s32g: update 
kernel to v6.1 based on SDK BSP36 v5.15 release kernel
on 09/05/2023 Zhantao Tang wrote:

> Hi Bruce,
> 
> The following patches are to update kernel to v6.1 based on SDK BSP36 v5.15
> release kernel. 
> 
> Would you please help to create branches:
>   v6.1/standard/nxp-sdk-5.15/nxp-s32g
>   v6.1/standard/preempt-rt/nxp-sdk-5.15/nxp-s32g

Created and merged.

Bruce

> 
> based on v6.1/standard/base and v6.1/standard/preempt-rt/base, and merge the
> following patches into the new branches?
> 
> The patches info as following:
> 
> The following changes since commit 5595b9b98df96b1ef27dc5879d19b9b512cc5c14:
> 
>   Merge tag 'v6.1.27' into v6.1/standard/base (2023-05-02 21:39:51 -0400)
> 
> are available in the Git repository at:
> 
>   https://github.com/zhantaotang/linux-yocto-std 
> v6.1/standard/nxp-sdk-5.15/nxp-s32g
> 
> for you to fetch changes up to c003347331cdd516939224989cc6a45cd578c4f4:
> 
>   nxp-s32g: usb: chipedea: add ulpi usb phy support (2023-05-09 15:47:54 
> +0800)
> 
> 
> Thanks,
> Zhantao
> 

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Re: [linux-yocto] [yocto-kernel-cache v6.1]: nxp-s32g: add scc and cfg files for S32G platform

2023-05-10 Thread Bruce Ashfield
In message: [yocto-kernel-cache v6.1]: nxp-s32g: add scc and cfg files for S32G 
platform
on 09/05/2023 Zhantao Tang wrote:

> Hi Bruce,
> 
> The following patch is to add scc and cfg files for S32G platform,
> would you please help to merge it into yocto-6.1 branch?

merged.

Bruce

> 
> Thanks,
> Zhantao

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Re: [linux-yocto] [yocto-kernel-cache][yocto-6.1][PATCH 0/2] add preempt-rt for

2023-05-10 Thread Bruce Ashfield
In message: [yocto-kernel-cache][yocto-6.1][PATCH 0/2] add preempt-rt for
on 09/05/2023 quanyang.w...@windriver.com wrote:

> From: Quanyang Wang 
> 
> Hi Bruce,
> Would you please help merge these 2 patches to the branch:
>   yocto-6.1

merged.

Bruce

> Thanks,
> Quanyang
> 
> 
> Quanyang Wang (2):
>   bsp: xilinx-zynq: add preempt-rt support
>   bsp: xilinx-zynqmp: add preempt-rt support
> 
>  bsp/xilinx-zynq/xilinx-zynq-preempt-rt.scc | 8 
>  bsp/xilinx-zynqmp/xilinx-zynqmp-preempt-rt.scc | 8 
>  2 files changed, 16 insertions(+)
>  create mode 100644 bsp/xilinx-zynq/xilinx-zynq-preempt-rt.scc
>  create mode 100644 bsp/xilinx-zynqmp/xilinx-zynqmp-preempt-rt.scc
> 
> -- 
> 2.36.1
> 

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[linux-yocto][v6.1/standard/preempt-rt/nxp-sdk-5.15/nxp-s32g][PATCH 2/5] dts: Aptiv-FL: disable unsupported device nodes

2023-05-10 Thread quanyang.wang via lists.yoctoproject.org
From: Quanyang Wang 

The device nodes of "qspi" and "gmac0" are not supported in linux, so we
need to disable them to eliminate error log while booting.

Signed-off-by: Quanyang Wang 
Signed-off-by: Bruce Ashfield 
---
 arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi 
b/arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi
index a91e466dbc272..1a868eec29b7d 100644
--- a/arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi
@@ -31,11 +31,13 @@  {
 };
 
  {
-   status = "okay";
+   /* We don't support HyperFlash in linux */
+   status = "disabled";
 };
 
  {
-   status = "okay";
+   /* Before enabling SJA1110, set it to be "disabled" */
+   status = "disabled";
phy-mode = "rgmii";
phy-handle = <_mdio_c_phy19>;
pinctrl-names = "default";
-- 
2.36.1


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[linux-yocto][v6.1/standard/preempt-rt/nxp-sdk-5.15/nxp-s32g][PATCH 5/5] dts: Aptiv-FL: refactor Aptiv CVC FL s32g399a dts files

2023-05-10 Thread quanyang.wang via lists.yoctoproject.org
From: Quanyang Wang 

For now, dts files for NXP rdb/evb boards are following the naming
rules as s32gXXX.dtsi/s32gXXX.dts/s32gXXX-pfems.dts. Let's switch
Aptiv dts files to the same rule.

Rename original s32g399a-cvc-fl.dts to be s32g399a-cvc-fl.dtsi and make
new s32g399a-cvc-fl.dts and s32g399a-cvc-fl-pfems.dts to include this dtsi
file.

Signed-off-by: Quanyang Wang 
Signed-off-by: Bruce Ashfield 
---
 arch/arm64/boot/dts/freescale/Makefile|  3 +-
 .../dts/freescale/s32g399a-cvc-fl-pfems.dts   | 23 +
 .../boot/dts/freescale/s32g399a-cvc-fl.dts| 32 ++-
 .../boot/dts/freescale/s32g399a-cvc-fl.dtsi   | 28 
 4 files changed, 62 insertions(+), 24 deletions(-)
 create mode 100644 arch/arm64/boot/dts/freescale/s32g399a-cvc-fl-pfems.dts
 create mode 100644 arch/arm64/boot/dts/freescale/s32g399a-cvc-fl.dtsi

diff --git a/arch/arm64/boot/dts/freescale/Makefile 
b/arch/arm64/boot/dts/freescale/Makefile
index 16feaade66cb0..e3a7662e40d85 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -135,6 +135,8 @@ dtb-$(CONFIG_ARCH_MXC) += 
imx8mm-venice-gw73xx-0x-rs232-rts.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb
 
+dtb-$(CONFIG_ARCH_S32) += s32g399a-cvc-fl.dtb
+dtb-$(CONFIG_ARCH_S32) += s32g399a-cvc-fl-pfems.dtb
 dtb-$(CONFIG_ARCH_S32) += s32g274a-bluebox3.dtb
 dtb-$(CONFIG_ARCH_S32) += s32g2xxa-evb.dtb
 dtb-$(CONFIG_ARCH_S32) += s32g2xxa-evb-pfems.dtb
@@ -154,4 +156,3 @@ dtb-$(CONFIG_ARCH_S32) += s32g399a-emu.dtb
 dtb-$(CONFIG_ARCH_S32) += s32r45-evb.dtb
 dtb-$(CONFIG_ARCH_S32) += s32r45-emu.dtb
 dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb
-dtb-$(CONFIG_ARCH_S32) += s32g399a-cvc-fl.dtb
diff --git a/arch/arm64/boot/dts/freescale/s32g399a-cvc-fl-pfems.dts 
b/arch/arm64/boot/dts/freescale/s32g399a-cvc-fl-pfems.dts
new file mode 100644
index 0..661f8f8efb6cf
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32g399a-cvc-fl-pfems.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2023 Wind River Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Based on s32g399a-rdb3-pfems.dts
+ */
+
+/dts-v1/;
+#include "s32g399a-cvc-fl.dtsi"
+#include "s32g-pfe-slave.dtsi"
+
+_aux0 {
+   status = "okay";
+};
+
+_aux0 {
+   status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/s32g399a-cvc-fl.dts 
b/arch/arm64/boot/dts/freescale/s32g399a-cvc-fl.dts
index 994f80a736ee4..bee72e0eeed1e 100644
--- a/arch/arm64/boot/dts/freescale/s32g399a-cvc-fl.dts
+++ b/arch/arm64/boot/dts/freescale/s32g399a-cvc-fl.dts
@@ -1,28 +1,14 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /*
- * Copyright 2021 NXP
+ * Copyright (C) 2023 Wind River Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Based on s32g399a-rdb3.dts
  */
 
 /dts-v1/;
-#include "s32g3.dtsi"
-#include "s32gxxxa-cvc-fl.dtsi"
-/ {
-   model = "Freescale S32G399A";
-   compatible = "fsl,s32g399", "arm,vexpress";
-};
-
- {
-   status = "okay";
-};
-
- {
-   status = "okay";
-};
-
- {
-   status = "okay";
-};
-
- {
-   status = "okay";
-};
+#include "s32g399a-cvc-fl.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/s32g399a-cvc-fl.dtsi 
b/arch/arm64/boot/dts/freescale/s32g399a-cvc-fl.dtsi
new file mode 100644
index 0..994f80a736ee4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32g399a-cvc-fl.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2021 NXP
+ */
+
+/dts-v1/;
+#include "s32g3.dtsi"
+#include "s32gxxxa-cvc-fl.dtsi"
+/ {
+   model = "Freescale S32G399A";
+   compatible = "fsl,s32g399", "arm,vexpress";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
-- 
2.36.1


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[linux-yocto][v6.1/standard/preempt-rt/nxp-sdk-5.15/nxp-s32g][PATCH 4/5] dts: Aptiv-FL: disable flexcan3

2023-05-10 Thread quanyang.wang via lists.yoctoproject.org
From: Quanyang Wang 

The flexcan3 is used by Autosar running at M7 core. So disable it in
linux for Aptiv FL board.

Signed-off-by: Quanyang Wang 
Signed-off-by: Bruce Ashfield 
---
 arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi 
b/arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi
index 02cf6074262e4..961ba2ec13581 100644
--- a/arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi
@@ -213,7 +213,7 @@  {
  {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
-   status = "okay";
+   status = "disabled";
 };
 
  {
-- 
2.36.1


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[linux-yocto][v6.1/standard/preempt-rt/nxp-sdk-5.15/nxp-s32g][PATCH 3/5] dts: Aptiv-FL: add correct pinctrls for pfe interfaces for Aptiv-FL board

2023-05-10 Thread quanyang.wang via lists.yoctoproject.org
From: Quanyang Wang 

Add pinctrls for pfe0/1/2 interfaces for Aptiv-FL board. Note that
RTL9010 phys need to be configured at u-boot.

This patch comes from:
meta-cvc-fl/recipes-kernel/linux/linux-s32/0001-ESL-427-Linux-S32-cvc-support+cleanup.patch

Signed-off-by: Quanyang Wang 
Signed-off-by: Bruce Ashfield 
---
 .../boot/dts/freescale/s32gxxxa-cvc-fl.dtsi   | 136 +-
 1 file changed, 38 insertions(+), 98 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi 
b/arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi
index 1a868eec29b7d..02cf6074262e4 100644
--- a/arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi
@@ -59,6 +59,7 @@  {
 
 _netif0 {
status = "okay";
+   phy-mode = "sgmii";
phy-handle = <_phy8>;
fixed-link {
speed = <1000>;
@@ -68,6 +69,7 @@ fixed-link {
 
 _netif1 {
status = "okay";
+   phy-mode = "sgmii";
phy-handle = <_rtl_sw>;
fixed-link {
speed = <1000>;
@@ -102,6 +104,9 @@ can0-en-hog {
 
 _mdio0 {
status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+
/* RTL9010 */
mdio0_phy8: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
@@ -109,11 +114,13 @@ mdio0_phy8: ethernet-phy@1 {
#size-cells = <0>;
reg = <1>;
};
-
 };
 
 _mdio1 {
status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+
/* RTL9075 */
mdio1_rtl_sw: ethernet-phy@24 {
compatible = "ethernet-phy-ieee802.3-c22";
@@ -125,6 +132,9 @@ mdio1_rtl_sw: ethernet-phy@24 {
 
 _mdio2 {
status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+
/* RTL9010 */
mdio2_phy7: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
@@ -530,67 +540,6 @@ usbotg_grp3 {
 
};
 
-   pfe2mdioa_pins: pfe2mdioa {
-   pfe2mdioa_grp0 {
-   pinmux = ;
-   output-enable;
-   slew-rate = ;
-   };
-
-   pfe2mdioa_grp1 {
-   pinmux = ;
-   output-enable;
-   input-enable;
-   slew-rate = ;
-   };
-
-   pfe2mdioa_grp2 {
-   pinmux = ;
-   };
-
-   };
-
-   pfe2rgmiia_pins: pfe2rgmiia {
-   pfe2rgmiia_grp0 {
-   pinmux = ,
-,
-,
-,
-;
-   output-enable;
-   slew-rate = ;
-   };
-
-   pfe2rgmiia_grp1 {
-   pinmux = ,
-,
-,
-,
-,
-;
-   input-enable;
-   slew-rate = ;
-   };
-
-   pfe2rgmiia_grp2 {
-   pinmux = ,
-,
-,
-,
-,
-,
-;
-   };
-
-   pfe2rgmiia_grp3 {
-   pinmux = ;
-   output-enable;
-   slew-rate = ;
-   bias-pull-up;
-   };
-
-   };
-
gmac0mdioc_pins: gmac0mdioc {
gmac0mdioc_grp0 {
pinmux = ;
@@ -652,70 +601,61 @@ gmac0rgmiic_grp3 {
 
};
 
-   pfe1mdioc_pins: pfe1mdioc {
-   pfe1mdioc_grp0 {
-   pinmux = ;
+   pfe0mdio_pins: pfe0mdio {
+   pfe0mdio_grp0 {
+   pinmux = ;
output-enable;
slew-rate = ;
};
 
-   pfe1mdioc_grp1 {
-   pinmux = ;
+   pfe0mdio_grp1 {
+   pinmux = ;
output-enable;
input-enable;
slew-rate = ;
};
 
-   pfe1mdioc_grp2 {
-   pinmux = ;
+   pfe0mdio_grp2 {
+   pinmux = ;
};
-
};
 
-   pfe1rgmiic_pins: pfe1rgmiic {
-   pfe1rgmiic_grp0 {
-   pinmux = ;
+   pfe1mdio_pins: pfe1mdio {
+   pfe1mdio_grp0 {
+   pinmux = ;
output-enable;
slew-rate = ;
-   bias-pull-up;
};
 
-   pfe1rgmiic_grp1 {
-   

[linux-yocto][v6.1/standard/preempt-rt/nxp-sdk-5.15/nxp-s32g][PATCH 1/5] dts: Aptiv-FL: add dts file for Aptiv CVC-FL board

2023-05-10 Thread quanyang.wang via lists.yoctoproject.org
From: Quanyang Wang 

This patch comes from the patch:
meta-cvc-fl/recipes-kernel/linux/linux-s32/0001-ESL-427-Linux-S32-cvc-support+cleanup.patch

Modifications as below:
1. Change usb phy from "usb-nop-xceiv" to "usb-phy-ulpi-generic".
2. Add "can17_19_en-hog" to enable can17~19.
3. Add "can0-stb-hog" and "can0-en-hog" to enable can0.

Signed-off-by: Quanyang Wang 
Signed-off-by: Bruce Ashfield 
---
 arch/arm64/boot/dts/freescale/Makefile|   1 +
 .../boot/dts/freescale/s32g399a-cvc-fl.dts|  28 +
 .../boot/dts/freescale/s32gxxxa-cvc-fl.dtsi   | 912 ++
 3 files changed, 941 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/s32g399a-cvc-fl.dts
 create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi

diff --git a/arch/arm64/boot/dts/freescale/Makefile 
b/arch/arm64/boot/dts/freescale/Makefile
index fe5b4d93db559..16feaade66cb0 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -154,3 +154,4 @@ dtb-$(CONFIG_ARCH_S32) += s32g399a-emu.dtb
 dtb-$(CONFIG_ARCH_S32) += s32r45-evb.dtb
 dtb-$(CONFIG_ARCH_S32) += s32r45-emu.dtb
 dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb
+dtb-$(CONFIG_ARCH_S32) += s32g399a-cvc-fl.dtb
diff --git a/arch/arm64/boot/dts/freescale/s32g399a-cvc-fl.dts 
b/arch/arm64/boot/dts/freescale/s32g399a-cvc-fl.dts
new file mode 100644
index 0..994f80a736ee4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32g399a-cvc-fl.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2021 NXP
+ */
+
+/dts-v1/;
+#include "s32g3.dtsi"
+#include "s32gxxxa-cvc-fl.dtsi"
+/ {
+   model = "Freescale S32G399A";
+   compatible = "fsl,s32g399", "arm,vexpress";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi 
b/arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi
new file mode 100644
index 0..a91e466dbc272
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi
@@ -0,0 +1,912 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2019-2021 NXP
+ */
+#include 
+
+/ {
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   usbphyulpi: usbphyulpi {
+   compatible = "nxp,saf1508", "usb-phy-ulpi-generic";
+   /* ULPI_OTG_ID_PULLUP | ULPI_OTG_DRVVBUS_EXT | 
ULPI_OTG_EXTVBUSIND |
+* ULPI_IC_IND_PASSTHRU | ULPI_IC_EXTVBUS_INDINV
+*/
+   usb-ulpi-flags = <0x60C1>;
+   #phy-cells = <0>;
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   fsl,usbphy = <>;
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   phy-mode = "rgmii";
+   phy-handle = <_mdio_c_phy19>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>, <_pins>;
+};
+
+_mdio {
+   /* SJA SW */
+   gmac0_mdio_c_phy19: ethernet-phy@19 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <19>;
+   };
+};
+
+ {
+   status = "okay";
+};
+
+_netif0 {
+   status = "okay";
+   phy-handle = <_phy8>;
+   fixed-link {
+   speed = <1000>;
+   full-duplex;
+   };
+};
+
+_netif1 {
+   status = "okay";
+   phy-handle = <_rtl_sw>;
+   fixed-link {
+   speed = <1000>;
+   full-duplex;
+   };
+};
+
+_netif2 {
+   status = "okay";
+   phy-mode = "sgmii";
+   phy-handle = <_phy7>;
+   fixed-link {
+   speed = <1000>;
+   full-duplex;
+   };
+};
+
+ {
+   can0-stb-hog {
+   gpio-hog;
+   gpios = <24 GPIO_ACTIVE_HIGH>;
+   output-high;
+   line-name = "can0_stb";
+   };
+   can0-en-hog {
+   gpio-hog;
+   gpios = <9 GPIO_ACTIVE_HIGH>;
+   output-high;
+   line-name = "can0_en";
+   };
+};
+
+_mdio0 {
+   status = "okay";
+   /* RTL9010 */
+   mdio0_phy8: ethernet-phy@1 {
+   compatible = "ethernet-phy-ieee802.3-c22";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+   };
+
+};
+
+_mdio1 {
+   status = "okay";
+   /* RTL9075 */
+   mdio1_rtl_sw: ethernet-phy@24 {
+   compatible = "ethernet-phy-ieee802.3-c22";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <24>;
+   };
+};
+
+_mdio2 {
+   status = "okay";
+   /* RTL9010 */
+   mdio2_phy7: ethernet-phy@1 {
+   compatible = "ethernet-phy-ieee802.3-c22";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+   };
+};
+
+_timer {
+   

[linux-yocto][v6.1] nxp-s32g: aptiv dts files

2023-05-10 Thread quanyang.wang via lists.yoctoproject.org
From: Quanyang Wang 

Hi Bruce,
Would you please help merge these 5 patches to the branches:
v6.1/standard/preempt-rt/nxp-sdk-5.15/nxp-s32g
v6.1/standard/nxp-sdk-5.15/nxp-s32g
Thanks,
Quanyang

Quanyang Wang (5):
  dts: Aptiv-FL: add dts file for Aptiv CVC-FL board
  dts: Aptiv-FL: disable unsupported device nodes
  dts: Aptiv-FL: add correct pinctrls for pfe interfaces for Aptiv-FL
board
  dts: Aptiv-FL: disable flexcan3
  dts: Aptiv-FL: refactor Aptiv CVC FL s32g399a dts files

 arch/arm64/boot/dts/freescale/Makefile|   2 +
 .../dts/freescale/s32g399a-cvc-fl-pfems.dts   |  23 +
 .../boot/dts/freescale/s32g399a-cvc-fl.dts|  14 +
 .../boot/dts/freescale/s32g399a-cvc-fl.dtsi   |  28 +
 .../boot/dts/freescale/s32gxxxa-cvc-fl.dtsi   | 854 ++
 5 files changed, 921 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/s32g399a-cvc-fl-pfems.dts
 create mode 100644 arch/arm64/boot/dts/freescale/s32g399a-cvc-fl.dts
 create mode 100644 arch/arm64/boot/dts/freescale/s32g399a-cvc-fl.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi

-- 
2.36.1


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[linux-yocto] [yocto-kernel-cache][yocto-6.1][PATCH] bsp: aptiv-s32g: add support for Aptiv FL board

2023-05-10 Thread quanyang.wang via lists.yoctoproject.org
From: Quanyang Wang 

Add scc and cfg files for Aptiv FL board.

Signed-off-by: Quanyang Wang 
---
Hi Bruce,
Would you please help merge this patch to the branch:
yocto-6.1
Thanks,
Quanyang
---
 bsp/aptiv-s32g/aptiv-cvc-fl-preempt-rt.scc |   7 +
 bsp/aptiv-s32g/aptiv-cvc.cfg   | 177 +
 bsp/aptiv-s32g/aptiv-cvc.scc   |   7 +
 3 files changed, 191 insertions(+)
 create mode 100644 bsp/aptiv-s32g/aptiv-cvc-fl-preempt-rt.scc
 create mode 100644 bsp/aptiv-s32g/aptiv-cvc.cfg
 create mode 100644 bsp/aptiv-s32g/aptiv-cvc.scc

diff --git a/bsp/aptiv-s32g/aptiv-cvc-fl-preempt-rt.scc 
b/bsp/aptiv-s32g/aptiv-cvc-fl-preempt-rt.scc
new file mode 100644
index 00..d8a0c51af0
--- /dev/null
+++ b/bsp/aptiv-s32g/aptiv-cvc-fl-preempt-rt.scc
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: MIT
+define KMACHINE aptiv-cvc-fl
+define KTYPE preempt-rt
+define KARCH arm64
+
+include ktypes/preempt-rt
+include aptiv-cvc.scc
diff --git a/bsp/aptiv-s32g/aptiv-cvc.cfg b/bsp/aptiv-s32g/aptiv-cvc.cfg
new file mode 100644
index 00..5714cb9c74
--- /dev/null
+++ b/bsp/aptiv-s32g/aptiv-cvc.cfg
@@ -0,0 +1,177 @@
+# SPDX-License-Identifier: MIT
+..
+.WARNING
+.
+. This file is a kernel configuration fragment, and not a full kernel
+. configuration file.  The final kernel configuration is made up of
+. an assembly of processed fragments, each of which is designed to
+. capture a specific part of the final configuration (e.g. platform
+. configuration, feature configuration, and board specific hardware
+. configuration).  For more information on kernel configuration, please
+. consult the product documentation.
+.
+..
+
+CONFIG_ARM64=y
+CONFIG_ARCH_NXP=y
+CONFIG_ARCH_S32=y
+CONFIG_SOC_S32CC=y
+CONFIG_SCHED_MC=y
+CONFIG_ARM_SMMU=y
+
+CONFIG_PINCTRL_S32CC=y
+
+CONFIG_CPU_IDLE=y
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+
+CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y
+#To keep align with SDK, unset the ARM_SCMI_POWER_DOMAIN config
+# CONFIG_ARM_SCMI_POWER_DOMAIN is not set
+
+#CAN
+CONFIG_CAN=y
+CONFIG_CAN_VCAN=y
+CONFIG_CAN_SLCAN=y
+CONFIG_CAN_FLEXCAN=m
+
+#Ethernet
+CONFIG_STMMAC_ETH=y
+CONFIG_DWMAC_DWC_QOS_ETH=y
+
+#Serial
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_FSL_LINFLEXUART=y
+CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
+
+#SPI
+CONFIG_SPI=y
+CONFIG_SPI_FSL_DSPI=y
+CONFIG_SPI_SPIDEV=y
+
+#GPIO
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_S32CC=y
+CONFIG_GPIO_PCA953X=y
+
+#PCIE
+CONFIG_PCI=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_PLAT_HOST=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCIE_DW_PLAT_EP=y
+CONFIG_PCIEAER=y
+CONFIG_PCI_S32CC=y
+
+#USB
+CONFIG_USB=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_FSM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_IMX=m
+CONFIG_USB_ULPI_GENERIC=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+
+CONFIG_USB_ACM=y
+CONFIG_USB_WDM=y
+
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_WWAN=y
+CONFIG_USB_SERIAL_OPTION=y
+
+#MMC
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_DMADEVICES=y
+CONFIG_FSL_EDMA=y
+CONFIG_CMA=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=128
+
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_SPI_NOR=y
+
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+
+# Thermal
+CONFIG_THERMAL=y
+CONFIG_S32CC_THERMAL=y
+
+# ADC
+CONFIG_IIO=y
+CONFIG_S32CC_ADC=m
+
+# PWM
+CONFIG_PWM=y
+CONFIG_PWM_FSL_FTM=m
+
+CONFIG_S32CC_FCCU=y
+CONFIG_GPIOLIB=y
+CONFIG_OF_GPIO=y
+
+CONFIG_MDIO_DEVICE=y
+CONFIG_PHYLIB=y
+
+#QSPI
+CONFIG_SPI_FSL_QUADSPI=y
+
+#RTC
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_S32CC=y
+CONFIG_RTC_DRV_PCF85063=y
+
+#I2C
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_IMX=m
+
+#Watchdog
+# We need keep this driver built-in since rmmod will trigger reboot
+CONFIG_S32CC_WDT=y
+
+#NVME
+CONFIG_BLK_DEV_NVME=y
+CONFIG_NVME_TARGET=y
+CONFIG_NVMEM_S32CC_SIUL2=y
+
+#LLCE
+CONFIG_CAN_LLCE=y
+CONFIG_CAN_LLCE_CONTROLLER=m
+
+# Regulator configuration
+CONFIG_REGULATOR=y
+
+#HSE UIO
+CONFIG_UIO=y
+CONFIG_CRYPTO_DEV_NXP_HSE=y
+CONFIG_UIO_NXP_HSE=y
+CONFIG_UIO_NXP_HSE_MU0=y
+CONFIG_CRYPTO_DEV_NXP_HSE_MU1=y
+
+#RANDOM
+CONFIG_HW_RANDOM=y
diff --git a/bsp/aptiv-s32g/aptiv-cvc.scc b/bsp/aptiv-s32g/aptiv-cvc.scc
new file mode 100644
index 00..30fa80132f
--- /dev/null
+++ b/bsp/aptiv-s32g/aptiv-cvc.scc
@@ -0,0 +1,7 @@
+#