From: Meng Li <meng...@windriver.com>
This dts file is created by referring to Xilix SDK petalinux.
Signed-off-by: Meng Li <meng...@windriver.com>
Signed-off-by: Bruce Ashfield <bruce.ashfi...@gmail.com>
---
arch/arm64/boot/dts/xilinx/Makefile | 1 +
.../dts/xilinx/zynqmp-zcu102-rev1.0-canfd.dts | 82 +++++++++++++++++++
2 files changed, 83 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0-canfd.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile
b/arch/arm64/boot/dts/xilinx/Makefile
index 1398b0e21e78c..25dfafe085ab2 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0-canfd.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.1.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revC.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0-canfd.dts
b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0-canfd.dts
new file mode 100644
index 0000000000000..73ba3abd7aa89
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0-canfd.dts
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU102 Rev1.0 CANFD
+ *
+ * Copyright (C) 2016 - 2023 Wind River Systems, Inc.
+ *
+ * Meng Li <meng...@windriver.com>
+ */
+
+#include "zynqmp-zcu102-rev1.0.dts"
+
+/ {
+ amba_pl: amba_pl {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges ;
+ axi_iic_0: i2c@80003000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "s_axi_aclk";
+ clocks = <&zynqmp_clk 71>;
+ compatible = "xlnx,axi-iic-2.0", "xlnx,xps-iic-2.00.a";
+ reg = <0x0 0x80003000 0x0 0x1000>;
+ };
+ axi_timer_0: timer@80000000 {
+ clock-frequency = <187481262>;
+ clock-names = "s_axi_aclk";
+ clocks = <&zynqmp_clk 71>;
+ compatible = "xlnx,axi-timer-2.0",
"xlnx,xps-timer-1.00.a";
+ interrupt-names = "interrupt";
+ interrupt-parent = <&gic>;
+ interrupts = <0 91 4>;
+ reg = <0x0 0x80000000 0x0 0x1000>;
+ xlnx,count-width = <0x20>;
+ xlnx,gen0-assert = <0x1>;
+ xlnx,gen1-assert = <0x1>;
+ xlnx,one-timer-only = <0x0>;
+ xlnx,trig0-assert = <0x1>;
+ xlnx,trig1-assert = <0x1>;
+ };
+ canfd_0: canfd@81000000 {
+ clock-names = "can_clk", "can_clk_x2", "s_axi_aclk";
+ clocks = <&clk_wiz_0 1>, <&clk_wiz_0 0>, <&zynqmp_clk
71>;
+ compatible = "xlnx,canfd-2.0";
+ interrupt-names = "ip2bus_intrevent";
+ interrupt-parent = <&gic>;
+ interrupts = <0 89 4>;
+ reg = <0x0 0x81000000 0x0 0x8000>;
+ rx-fifo-depth = <0x20>;
+ tx-mailbox-count = <0x20>;
+ };
+ canfd_1: canfd@82000000 {
+ clock-names = "can_clk", "can_clk_x2", "s_axi_aclk";
+ clocks = <&clk_wiz_0 1>, <&clk_wiz_0 0>, <&zynqmp_clk
71>;
+ compatible = "xlnx,canfd-2.0";
+ interrupt-names = "ip2bus_intrevent";
+ interrupt-parent = <&gic>;
+ interrupts = <0 90 4>;
+ reg = <0x0 0x82000000 0x0 0x8000>;
+ rx-fifo-depth = <0x20>;
+ tx-mailbox-count = <0x20>;
+ };
+ clk_wiz_0: clk_wiz@80010000 {
+ #clock-cells = <1>;
+ clock-names = "s_axi_aclk", "clk_in1";
+ clock-output-names = "clk_out1", "clk_out2",
"clk_out3", "clk_out4", "clk_out5", "clk_out6", "clk_out7";
+ clocks = <&zynqmp_clk 71>, <&zynqmp_clk 71>;
+ compatible = "xlnx,clk-wiz-6.0", "xlnx,clocking-wizard";
+ reg = <0x0 0x80010000 0x0 0x10000>;
+ speed-grade = <2>;
+ };
+ psu_ctrl_ipi: PERIPHERAL@ff380000 {
+ compatible = "xlnx,PERIPHERAL-1.0";
+ reg = <0x0 0xff380000 0x0 0x80000>;
+ };
+ psu_message_buffers: PERIPHERAL@ff990000 {
+ compatible = "xlnx,PERIPHERAL-1.0";
+ reg = <0x0 0xff990000 0x0 0x10000>;
+ };
+ };
+};
--
2.36.1
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