[linux-yocto] [PATCH 2/2] pinctrl: intel: fix offset calculation issue of register PAD_OWN

[Tan Jui Nee]

From: Qipeng Zha <qipeng@intel.com>

The calculation equation of PAD_OWN register offset is not
correct for Broxton, verified this fix will get right
offset for Broxton.

Signed-off-by: Qi Zheng <qi.zh...@intel.com>
Signed-off-by: Qipeng Zha <qipeng@intel.com>
Acked-by: Mika Westerberg <mika.westerb...@linux.intel.com>
Signed-off-by: Linus Walleij <linus.wall...@linaro.org>
(cherry picked from commit 99a735b3c287b70aa67952b1ff3d85cd924d85f9)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/pinctrl/intel/pinctrl-intel.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/intel/pinctrl-intel.c 
b/drivers/pinctrl/intel/pinctrl-intel.c
index f5595f1..7d3cb1b 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -34,6 +34,7 @@
 #define PADOWN_BITS4
 #define PADOWN_SHIFT(p)((p) % 8 * PADOWN_BITS)
 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
+#define PADOWN_GPP(p)  ((p) / 8)
 
 /* Offset from pad_regs */
 #define PADCFG00x000
@@ -139,7 +140,7 @@ static void __iomem *intel_get_padcfg(struct intel_pinctrl 
*pctrl, unsigned pin,
 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
 {
const struct intel_community *community;
-   unsigned padno, gpp, gpp_offset, offset;
+   unsigned padno, gpp, offset, group;
void __iomem *padown;
 
community = intel_get_community(pctrl, pin);
@@ -149,9 +150,9 @@ static bool intel_pad_owned_by_host(struct intel_pinctrl 
*pctrl, unsigned pin)
return true;
 
padno = pin_to_padno(community, pin);
-   gpp = padno / NPADS_IN_GPP;
-   gpp_offset = padno % NPADS_IN_GPP;
-   offset = community->padown_offset + gpp * 16 + (gpp_offset / 8) * 4;
+   group = padno / community->gpp_size;
+   gpp = PADOWN_GPP(padno % community->gpp_size);
+   offset = community->padown_offset + 0x10 * group + gpp * 4;
padown = community->regs + offset;
 
return !(readl(padown) & PADOWN_MASK(padno));
-- 
1.9.1

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[linux-yocto] [PATCH 0/2] Backport pinctrl/intel patches from mainline kernel into linux-yocto-4.1

[Tan Jui Nee]

Hi Bruce,

The patches are to backport Intel Broxton / Apollo Lake patches
that are available in the mainline Linux kernel, upstreamed by
Qipeng Zha.

The patches are to fix GPIO register offset calculation for Intel
Broxton / Apollo Lake.

The patches are targetted to merge into linux-yocto-4.1 on
standard/base branch.

Please review and provide feedback if any.

Thanks and best regards,
Juinee

Qipeng Zha (2):
  pinctrl: intel: fix bug of register offset calculation
  pinctrl: intel: fix offset calculation issue of register PAD_OWN

 drivers/pinctrl/intel/pinctrl-broxton.c  |  1 +
 drivers/pinctrl/intel/pinctrl-intel.c| 41 ++--
 drivers/pinctrl/intel/pinctrl-intel.h|  3 ++
 drivers/pinctrl/intel/pinctrl-sunrisepoint.c |  1 +
 4 files changed, 25 insertions(+), 21 deletions(-)

-- 
1.9.1

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[linux-yocto] [PATCH 18/18] serial: 8250_dw: Do not use readl/writel before checking port iotype

[Tan Jui Nee]

From: Noam Camus <no...@ezchip.com>

Direct call to readl()/writel() is checked against iotype
and in case of UPIO_MEM32BE we use ioread32be()/iowrite32be()
instead of them.

Signed-off-by: Noam Camus <no...@ezchip.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
(cherry picked from commit 5a43140cc4a59eda4549cc3b74989efa77973158)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c 
b/drivers/tty/serial/8250/8250_dw.c
index 92c4a9b..30810ac 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -114,6 +114,8 @@ static void dw8250_check_lcr(struct uart_port *p, int value)
 #else
if (p->iotype == UPIO_MEM32)
writel(value, offset);
+   else if (p->iotype == UPIO_MEM32BE)
+   iowrite32be(value, offset);
else
writeb(value, offset);
 #endif
@@ -327,14 +329,20 @@ static void dw8250_setup_port(struct uart_port *p)
 * If the Component Version Register returns zero, we know that
 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
 */
-   reg = readl(p->membase + DW_UART_UCV);
+   if (p->iotype == UPIO_MEM32BE)
+   reg = ioread32be(p->membase + DW_UART_UCV);
+   else
+   reg = readl(p->membase + DW_UART_UCV);
if (!reg)
return;
 
dev_dbg(p->dev, "Designware UART version %c.%c%c\n",
(reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
 
-   reg = readl(p->membase + DW_UART_CPR);
+   if (p->iotype == UPIO_MEM32BE)
+   reg = ioread32be(p->membase + DW_UART_CPR);
+   else
+   reg = readl(p->membase + DW_UART_CPR);
if (!reg)
return;
 
-- 
1.9.1

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[linux-yocto] [PATCH 13/18] serial: 8250_dw: cleanup dw8250_idma_filter

[Tan Jui Nee]

From: Heikki Krogerus <heikki.kroge...@linux.intel.com>

Remove the extra return.

Signed-off-by: Heikki Krogerus <heikki.kroge...@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
(cherry picked from commit 83ce95ef5efba06e5201c31064d11069bfdb87a0)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c 
b/drivers/tty/serial/8250/8250_dw.c
index a16579e..dbc88e2 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -290,12 +290,7 @@ static void dw8250_setup_port(struct uart_8250_port *up)
 
 static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
 {
-   struct device *dev = param;
-
-   if (dev != chan->device->dev->parent)
-   return false;
-
-   return true;
+   return param == chan->device->dev->parent;
 }
 
 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
-- 
1.9.1

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[linux-yocto] [PATCH 12/18] serial: 8250_dw: rename and comment the fallback dma filter

[Tan Jui Nee]

From: Heikki Krogerus <heikki.kroge...@linux.intel.com>

Adding comment where the purpose of the function is
explained.

The dma parameters are not used, so removing them, and also
moving the assignment of the function to the same place
where the other dw8250_data structures members are being set
in dw8250_probe.

Signed-off-by: Heikki Krogerus <heikki.kroge...@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
(cherry picked from commit 1edb3cf21f4b0be2a5d9577d4913eb9a3131cd16)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c 
b/drivers/tty/serial/8250/8250_dw.c
index a4aa671..a16579e 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -243,7 +243,15 @@ out:
serial8250_do_set_termios(p, termios, old);
 }
 
-static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
+/*
+ * dw8250_fallback_dma_filter will prevent the UART from getting just any free
+ * channel on platforms that have DMA engines, but don't have any channels
+ * assigned to the UART.
+ *
+ * REVISIT: This is a work around for limitation in the DMA Engine API. Once 
the
+ * core problem is fixed, this function is no longer needed.
+ */
+static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
 {
return false;
 }
@@ -370,6 +378,7 @@ static int dw8250_probe(struct platform_device *pdev)
if (!data)
return -ENOMEM;
 
+   data->dma.fn = dw8250_fallback_dma_filter;
data->usr_reg = DW_UART_USR;
p->private_data = data;
 
@@ -456,10 +465,6 @@ static int dw8250_probe(struct platform_device *pdev)
if (!IS_ERR(data->rst))
reset_control_deassert(data->rst);
 
-   data->dma.rx_param = data;
-   data->dma.tx_param = data;
-   data->dma.fn = dw8250_dma_filter;
-
dw8250_quirks(p, data);
 
/* If the Busy Functionality is not implemented, don't handle it */
-- 
1.9.1

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[linux-yocto] [PATCH 16/18] serial: 8250_dw: Avoid serial_outx code duplicate with new dw8250_check_lcr()

[Tan Jui Nee]

From: Noam Camus <no...@ezchip.com>

With the help of Heikki we take common code that
makes sure LCR write wasn't ignored and put it in new function called
dw8250_check_lcr(). This function serves 3 serial_out routines:
dw8250_serial_out(), dw8250_serial_out32(), and dw8250_serial_outq().

This patch only brings better code reuse.

Signed-off-by: Noam Camus <no...@ezchip.com>
Cc: Heikki Krogerus <heikki.kroge...@linux.intel.com>
Cc: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
(cherry picked from commit cdcea058e51008479545f29201b4fa577c59733c)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 91 ++-
 1 file changed, 42 insertions(+), 49 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c 
b/drivers/tty/serial/8250/8250_dw.c
index a5d319e..ffe5e0c 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -95,25 +95,43 @@ static void dw8250_force_idle(struct uart_port *p)
(void)p->serial_in(p, UART_RX);
 }
 
-static void dw8250_serial_out(struct uart_port *p, int offset, int value)
+static void dw8250_check_lcr(struct uart_port *p, int value)
 {
-   writeb(value, p->membase + (offset << p->regshift));
+   void __iomem *offset = p->membase + (UART_LCR << p->regshift);
+   int tries = 1000;
 
/* Make sure LCR write wasn't ignored */
-   if (offset == UART_LCR) {
-   int tries = 1000;
-   while (tries--) {
-   unsigned int lcr = p->serial_in(p, UART_LCR);
-   if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
-   return;
-   dw8250_force_idle(p);
-   writeb(value, p->membase + (UART_LCR << p->regshift));
-   }
-   /*
-* FIXME: this deadlocks if port->lock is already held
-* dev_err(p->dev, "Couldn't set LCR to %d\n", value);
-*/
+   while (tries--) {
+   unsigned int lcr = p->serial_in(p, UART_LCR);
+
+   if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
+   return;
+
+   dw8250_force_idle(p);
+
+#ifdef CONFIG_64BIT
+   __raw_writeq(value & 0xff, offset);
+#else
+   if (p->iotype == UPIO_MEM32)
+   writel(value, offset);
+   else
+   writeb(value, offset);
+#endif
}
+   /*
+* FIXME: this deadlocks if port->lock is already held
+* dev_err(p->dev, "Couldn't set LCR to %d\n", value);
+*/
+}
+
+static void dw8250_serial_out(struct uart_port *p, int offset, int value)
+{
+   struct dw8250_data *d = p->private_data;
+
+   writeb(value, p->membase + (offset << p->regshift));
+
+   if (offset == UART_LCR && !d->uart_16550_compatible)
+   dw8250_check_lcr(p, value);
 }
 
 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
@@ -135,49 +153,26 @@ static unsigned int dw8250_serial_inq(struct uart_port 
*p, int offset)
 
 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
 {
+   struct dw8250_data *d = p->private_data;
+
value &= 0xff;
__raw_writeq(value, p->membase + (offset << p->regshift));
/* Read back to ensure register write ordering. */
__raw_readq(p->membase + (UART_LCR << p->regshift));
 
-   /* Make sure LCR write wasn't ignored */
-   if (offset == UART_LCR) {
-   int tries = 1000;
-   while (tries--) {
-   unsigned int lcr = p->serial_in(p, UART_LCR);
-   if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
-   return;
-   dw8250_force_idle(p);
-   __raw_writeq(value & 0xff,
-p->membase + (UART_LCR << p->regshift));
-   }
-   /*
-* FIXME: this deadlocks if port->lock is already held
-* dev_err(p->dev, "Couldn't set LCR to %d\n", value);
-*/
-   }
+   if (offset == UART_LCR && !d->uart_16550_compatible)
+   dw8250_check_lcr(p, value);
 }
 #endif /* CONFIG_64BIT */
 
 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
 {
+   struct dw8250_data *d = p->private_data;
+
writel(value, p->membase + (offset << p->regshift));
 
-   /* Make sure LCR write wasn't ignored */
-   if (offset == UART_LCR) {
-   int tries = 1000;
-

[linux-yocto] [PATCH 15/18] serial: 8250_dw: don't set UPF_BOOT_AUTOCONF flag

[Tan Jui Nee]

From: Heikki Krogerus <heikki.kroge...@linux.intel.com>

serial8250_register_8250_port adds it to all ports it
registers. No need to set it separately.

Signed-off-by: Heikki Krogerus <heikki.kroge...@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
(cherry picked from commit 7693c79ce0779e9f3ebeaee747592da42294bc5f)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c 
b/drivers/tty/serial/8250/8250_dw.c
index 937174b..a5d319e 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -359,7 +359,7 @@ static int dw8250_probe(struct platform_device *pdev)
p->handle_irq   = dw8250_handle_irq;
p->pm   = dw8250_do_pm;
p->type = PORT_8250;
-   p->flags= UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
+   p->flags= UPF_SHARE_IRQ | UPF_FIXED_PORT;
p->dev  = >dev;
p->iotype   = UPIO_MEM;
p->serial_in= dw8250_serial_in;
-- 
1.9.1

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[linux-yocto] [PATCH 14/18] serial: 8250_dw: cleanup dw8250_setup_port

[Tan Jui Nee]

From: Heikki Krogerus <heikki.kroge...@linux.intel.com>

Using the same style of declaring variables as used in the
other functions of the driver. Passing uart_port to the
function instead of uart_8250_port, as it is the one mostly
needed.

Signed-off-by: Heikki Krogerus <heikki.kroge...@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
(cherry picked from commit 2338a75e0fe7195a615e66941a183b3286ee2fcd)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 66 +++
 1 file changed, 33 insertions(+), 33 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c 
b/drivers/tty/serial/8250/8250_dw.c
index dbc88e2..937174b 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -256,38 +256,6 @@ static bool dw8250_fallback_dma_filter(struct dma_chan 
*chan, void *param)
return false;
 }
 
-static void dw8250_setup_port(struct uart_8250_port *up)
-{
-   struct uart_port*p = >port;
-   u32 reg = readl(p->membase + DW_UART_UCV);
-
-   /*
-* If the Component Version Register returns zero, we know that
-* ADDITIONAL_FEATURES are not enabled. No need to go any further.
-*/
-   if (!reg)
-   return;
-
-   dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
-   (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
-
-   reg = readl(p->membase + DW_UART_CPR);
-   if (!reg)
-   return;
-
-   /* Select the type based on fifo */
-   if (reg & DW_UART_CPR_FIFO_MODE) {
-   p->type = PORT_16550A;
-   p->flags |= UPF_FIXED_TYPE;
-   p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
-   up->tx_loadsz = p->fifosize;
-   up->capabilities = UART_CAP_FIFO;
-   }
-
-   if (reg & DW_UART_CPR_AFCE_MODE)
-   up->capabilities |= UART_CAP_AFE;
-}
-
 static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
 {
return param == chan->device->dev->parent;
@@ -332,6 +300,38 @@ static void dw8250_quirks(struct uart_port *p, struct 
dw8250_data *data)
}
 }
 
+static void dw8250_setup_port(struct uart_port *p)
+{
+   struct uart_8250_port *up = up_to_u8250p(p);
+   u32 reg;
+
+   /*
+* If the Component Version Register returns zero, we know that
+* ADDITIONAL_FEATURES are not enabled. No need to go any further.
+*/
+   reg = readl(p->membase + DW_UART_UCV);
+   if (!reg)
+   return;
+
+   dev_dbg(p->dev, "Designware UART version %c.%c%c\n",
+   (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
+
+   reg = readl(p->membase + DW_UART_CPR);
+   if (!reg)
+   return;
+
+   /* Select the type based on fifo */
+   if (reg & DW_UART_CPR_FIFO_MODE) {
+   p->type = PORT_16550A;
+   p->flags |= UPF_FIXED_TYPE;
+   p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
+   up->capabilities = UART_CAP_FIFO;
+   }
+
+   if (reg & DW_UART_CPR_AFCE_MODE)
+   up->capabilities |= UART_CAP_AFE;
+}
+
 static int dw8250_probe(struct platform_device *pdev)
 {
struct uart_8250_port uart = {};
@@ -469,7 +469,7 @@ static int dw8250_probe(struct platform_device *pdev)
}
 
if (!data->skip_autocfg)
-   dw8250_setup_port();
+   dw8250_setup_port(p);
 
/* If we have a valid fifosize, try hooking up DMA */
if (p->fifosize) {
-- 
1.9.1

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[linux-yocto] [PATCH 11/18] serial: 8250_dw: proper support for UARTs without busy functionality

[Tan Jui Nee]

From: Heikki Krogerus <heikki.kroge...@linux.intel.com>

If the DW_apb_uart is configured with UART_16550_COMPATIBLE
configuration parameter set, then the Busy Functionality is
not available. These UARTs will never generate the Busy
detect indication interrupt, and therefore don't need
handling for it.

This creates a small optimization for the DW_apb_uarts
configured without the busy functionality, but more
importantly, it removes the small but real risk of hitting
potential issues caused by busy functionality handling when
no busy functionality exist.

Signed-off-by: Heikki Krogerus <heikki.kroge...@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
(cherry picked from commit c73942e22aa4a3d910f9be8d48de4080c3a52086)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 .../devicetree/bindings/serial/snps-dw-apb-uart.txt |  3 +++
 drivers/tty/serial/8250/8250_dw.c   | 13 -
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt 
b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
index 289c40e..12bbe9f 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
@@ -15,6 +15,9 @@ The supplying peripheral clock can also be handled, needing a 
second property
Required elements: "baudclk", "apb_pclk"
 
 Optional properties:
+- snps,uart-16550-compatible : reflects the value of UART_16550_COMPATIBLE
+  configuration parameter. Define this if your UART does not implement the busy
+  functionality.
 - resets : phandle to the parent reset controller.
 - reg-shift : quantity to shift the register offsets by.  If this property is
   not present then the register offsets are not shifted.
diff --git a/drivers/tty/serial/8250/8250_dw.c 
b/drivers/tty/serial/8250/8250_dw.c
index c5907a7..a4aa671 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -65,6 +65,7 @@ struct dw8250_data {
struct uart_8250_dmadma;
 
unsigned intskip_autocfg:1;
+   unsigned intuart_16550_compatible:1;
 };
 
 #define BYT_PRV_CLK0x800
@@ -313,8 +314,9 @@ static void dw8250_quirks(struct uart_port *p, struct 
dw8250_data *data)
p->iotype = UPIO_MEM32;
p->regshift = 2;
p->serial_in = dw8250_serial_in32;
-   p->serial_out = dw8250_serial_out32;
p->set_termios = dw8250_set_termios;
+   /* So far none of there implement the Busy Functionality */
+   data->uart_16550_compatible = true;
}
 
/* Platforms with iDMA */
@@ -371,6 +373,9 @@ static int dw8250_probe(struct platform_device *pdev)
data->usr_reg = DW_UART_USR;
p->private_data = data;
 
+   data->uart_16550_compatible = device_property_read_bool(p->dev,
+   "snps,uart-16550-compatible");
+
err = device_property_read_u32(p->dev, "reg-shift", );
if (!err)
p->regshift = val;
@@ -457,6 +462,12 @@ static int dw8250_probe(struct platform_device *pdev)
 
dw8250_quirks(p, data);
 
+   /* If the Busy Functionality is not implemented, don't handle it */
+   if (data->uart_16550_compatible) {
+   p->serial_out = NULL;
+   p->handle_irq = NULL;
+   }
+
if (!data->skip_autocfg)
dw8250_setup_port();
 
-- 
1.9.1

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[linux-yocto] [PATCH 17/18] serial: 8250_dw: Add support for big-endian MMIO accesses

[Tan Jui Nee]

From: Noam Camus <no...@ezchip.com>

Add support for UPIO_MEM32BE in addition to UPIO_MEM32.

For big endian we use 2 new accessors similar to little endian,
called dw8250_serial_out32be() and dw8250_serial_in32be().

Signed-off-by: Noam Camus <no...@ezchip.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
(cherry picked from commit 4625090187768bc776d69dfaa6a1f79b1125debe)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_dw.c 
b/drivers/tty/serial/8250/8250_dw.c
index ffe5e0c..92c4a9b 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -182,6 +182,24 @@ static unsigned int dw8250_serial_in32(struct uart_port 
*p, int offset)
return dw8250_modify_msr(p, offset, value);
 }
 
+static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
+{
+   struct dw8250_data *d = p->private_data;
+
+   iowrite32be(value, p->membase + (offset << p->regshift));
+
+   if (offset == UART_LCR && !d->uart_16550_compatible)
+   dw8250_check_lcr(p, value);
+}
+
+static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
+{
+   unsigned int value = ioread32be(p->membase + (offset << p->regshift));
+
+   return dw8250_modify_msr(p, offset, value);
+}
+
+
 static int dw8250_handle_irq(struct uart_port *p)
 {
struct dw8250_data *d = p->private_data;
@@ -276,6 +294,11 @@ static void dw8250_quirks(struct uart_port *p, struct 
dw8250_data *data)
data->skip_autocfg = true;
}
 #endif
+   if (of_device_is_big_endian(p->dev->of_node)) {
+   p->iotype = UPIO_MEM32BE;
+   p->serial_in = dw8250_serial_in32be;
+   p->serial_out = dw8250_serial_out32be;
+   }
} else if (has_acpi_companion(p->dev)) {
p->iotype = UPIO_MEM32;
p->regshift = 2;
-- 
1.9.1

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[linux-yocto] [PATCH 10/18] serial: 8250_dw: add dw8250_quirks function

[Tan Jui Nee]

From: Heikki Krogerus <heikki.kroge...@linux.intel.com>

Merging the DT and ACPI specific probe functions into
dw8250_quirks. Those functions did not have that much code
any more and some of the quirks need to be shared. This
will also allow platforms without DT or ACPI to use the
driver.

Signed-off-by: Heikki Krogerus <heikki.kroge...@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
(cherry picked from commit 9e08fa50b2f5935a219a323df5380d28f675c585)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 82 +++
 1 file changed, 31 insertions(+), 51 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c 
b/drivers/tty/serial/8250/8250_dw.c
index 6411992..c5907a7 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -279,30 +279,6 @@ static void dw8250_setup_port(struct uart_8250_port *up)
up->capabilities |= UART_CAP_AFE;
 }
 
-static int dw8250_probe_of(struct uart_port *p,
-  struct dw8250_data *data)
-{
-   struct device_node  *np = p->dev->of_node;
-   int id;
-
-#ifdef CONFIG_64BIT
-   if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
-   p->serial_in = dw8250_serial_inq;
-   p->serial_out = dw8250_serial_outq;
-   p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
-   p->type = PORT_OCTEON;
-   data->usr_reg = 0x27;
-   data->skip_autocfg = true;
-   }
-#endif
-   /* get index of serial line, if found in DT aliases */
-   id = of_alias_get_id(np, "serial");
-   if (id >= 0)
-   p->line = id;
-
-   return 0;
-}
-
 static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
 {
struct device *dev = param;
@@ -313,27 +289,42 @@ static bool dw8250_idma_filter(struct dma_chan *chan, 
void *param)
return true;
 }
 
-static int dw8250_probe_acpi(struct uart_8250_port *up,
-struct dw8250_data *data)
+static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
 {
-   struct uart_port *p = >port;
-
-   p->iotype = UPIO_MEM32;
-   p->serial_in = dw8250_serial_in32;
-   p->serial_out = dw8250_serial_out32;
-   p->regshift = 2;
+   if (p->dev->of_node) {
+   struct device_node *np = p->dev->of_node;
+   int id;
+
+   /* get index of serial line, if found in DT aliases */
+   id = of_alias_get_id(np, "serial");
+   if (id >= 0)
+   p->line = id;
+#ifdef CONFIG_64BIT
+   if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
+   p->serial_in = dw8250_serial_inq;
+   p->serial_out = dw8250_serial_outq;
+   p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | 
UPF_FIXED_TYPE;
+   p->type = PORT_OCTEON;
+   data->usr_reg = 0x27;
+   data->skip_autocfg = true;
+   }
+#endif
+   } else if (has_acpi_companion(p->dev)) {
+   p->iotype = UPIO_MEM32;
+   p->regshift = 2;
+   p->serial_in = dw8250_serial_in32;
+   p->serial_out = dw8250_serial_out32;
+   p->set_termios = dw8250_set_termios;
+   }
 
/* Platforms with iDMA */
-   if (platform_get_resource_byname(to_platform_device(up->port.dev),
+   if (platform_get_resource_byname(to_platform_device(p->dev),
 IORESOURCE_MEM, "lpss_priv")) {
-   data->dma.rx_param = up->port.dev->parent;
-   data->dma.tx_param = up->port.dev->parent;
+   p->set_termios = dw8250_set_termios;
+   data->dma.rx_param = p->dev->parent;
+   data->dma.tx_param = p->dev->parent;
data->dma.fn = dw8250_idma_filter;
}
-
-   up->port.set_termios = dw8250_set_termios;
-
-   return 0;
 }
 
 static int dw8250_probe(struct platform_device *pdev)
@@ -464,18 +455,7 @@ static int dw8250_probe(struct platform_device *pdev)
data->dma.tx_param = data;
data->dma.fn = dw8250_dma_filter;
 
-   if (pdev->dev.of_node) {
-   err = dw8250_probe_of(p, data);
-   if (err)
-   goto err_reset;
-   } else if (ACPI_HANDLE(>dev)) {
-   err = dw8250_probe_acpi(, data);
-   if (err)
-   goto err_reset;
-   } else {
-   err = -ENODEV;
-   goto er

[linux-yocto] [PATCH 09/18] serial: 8250_dw: only setup the port from one place

[Tan Jui Nee]

From: Heikki Krogerus <heikki.kroge...@linux.intel.com>

This adds a flag "skip_autocfg" that the platforms that do
not have the ADDITIONAL_FEATURES implemented can use to skip
the port setup. It's then enough to call dw8250_setup_port
just from dw8250_probe based on that flag.

Signed-off-by: Heikki Krogerus <heikki.kroge...@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
(cherry picked from commit 4f042054faa0f40b5801464ef818f28885e5435e)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 14 ++
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c 
b/drivers/tty/serial/8250/8250_dw.c
index a606408..6411992 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -63,6 +63,8 @@ struct dw8250_data {
struct clk  *pclk;
struct reset_control*rst;
struct uart_8250_dmadma;
+
+   unsigned intskip_autocfg:1;
 };
 
 #define BYT_PRV_CLK0x800
@@ -281,8 +283,6 @@ static int dw8250_probe_of(struct uart_port *p,
   struct dw8250_data *data)
 {
struct device_node  *np = p->dev->of_node;
-   struct uart_8250_port *up = up_to_u8250p(p);
-   bool has_ucv = true;
int id;
 
 #ifdef CONFIG_64BIT
@@ -292,12 +292,9 @@ static int dw8250_probe_of(struct uart_port *p,
p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
p->type = PORT_OCTEON;
data->usr_reg = 0x27;
-   has_ucv = false;
+   data->skip_autocfg = true;
}
 #endif
-   if (has_ucv)
-   dw8250_setup_port(up);
-
/* get index of serial line, if found in DT aliases */
id = of_alias_get_id(np, "serial");
if (id >= 0)
@@ -321,8 +318,6 @@ static int dw8250_probe_acpi(struct uart_8250_port *up,
 {
struct uart_port *p = >port;
 
-   dw8250_setup_port(up);
-
p->iotype = UPIO_MEM32;
p->serial_in = dw8250_serial_in32;
p->serial_out = dw8250_serial_out32;
@@ -482,6 +477,9 @@ static int dw8250_probe(struct platform_device *pdev)
goto err_reset;
}
 
+   if (!data->skip_autocfg)
+   dw8250_setup_port();
+
/* If we have a valid fifosize, try hooking up DMA */
if (p->fifosize) {
data->dma.rxconf.src_maxburst = p->fifosize / 4;
-- 
1.9.1

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[linux-yocto] [PATCH 07/18] serial: 8250_dw: adapt to unified device property interface

[Tan Jui Nee]

From: Heikki Krogerus <heikki.kroge...@linux.intel.com>

This makes the properties available for all types of
platforms instead of just the ones using DT.

Signed-off-by: Heikki Krogerus <heikki.kroge...@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
(cherry picked from commit 1bd8edba10e6aa275434a8daa7ddcaf849fe49ad)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 80 ++-
 1 file changed, 37 insertions(+), 43 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c 
b/drivers/tty/serial/8250/8250_dw.c
index 56e5cac..2611ee6 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -282,7 +282,6 @@ static int dw8250_probe_of(struct uart_port *p,
 {
struct device_node  *np = p->dev->of_node;
struct uart_8250_port *up = up_to_u8250p(p);
-   u32 val;
bool has_ucv = true;
int id;
 
@@ -294,22 +293,8 @@ static int dw8250_probe_of(struct uart_port *p,
p->type = PORT_OCTEON;
data->usr_reg = 0x27;
has_ucv = false;
-   } else
-#endif
-   if (!of_property_read_u32(np, "reg-io-width", )) {
-   switch (val) {
-   case 1:
-   break;
-   case 4:
-   p->iotype = UPIO_MEM32;
-   p->serial_in = dw8250_serial_in32;
-   p->serial_out = dw8250_serial_out32;
-   break;
-   default:
-   dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
-   return -EINVAL;
-   }
}
+#endif
if (has_ucv)
dw8250_setup_port(up);
 
@@ -321,38 +306,11 @@ static int dw8250_probe_of(struct uart_port *p,
up->dma->txconf.dst_maxburst = p->fifosize / 4;
}
 
-   if (!of_property_read_u32(np, "reg-shift", ))
-   p->regshift = val;
-
/* get index of serial line, if found in DT aliases */
id = of_alias_get_id(np, "serial");
if (id >= 0)
p->line = id;
 
-   if (of_property_read_bool(np, "dcd-override")) {
-   /* Always report DCD as active */
-   data->msr_mask_on |= UART_MSR_DCD;
-   data->msr_mask_off |= UART_MSR_DDCD;
-   }
-
-   if (of_property_read_bool(np, "dsr-override")) {
-   /* Always report DSR as active */
-   data->msr_mask_on |= UART_MSR_DSR;
-   data->msr_mask_off |= UART_MSR_DDSR;
-   }
-
-   if (of_property_read_bool(np, "cts-override")) {
-   /* Always report CTS as active */
-   data->msr_mask_on |= UART_MSR_CTS;
-   data->msr_mask_off |= UART_MSR_DCTS;
-   }
-
-   if (of_property_read_bool(np, "ri-override")) {
-   /* Always report Ring indicator as inactive */
-   data->msr_mask_off |= UART_MSR_RI;
-   data->msr_mask_off |= UART_MSR_TERI;
-   }
-
return 0;
 }
 
@@ -403,6 +361,7 @@ static int dw8250_probe(struct platform_device *pdev)
struct uart_port *p = 
struct dw8250_data *data;
int err;
+   u32 val;
 
if (!regs) {
dev_err(>dev, "no registers defined\n");
@@ -438,6 +397,41 @@ static int dw8250_probe(struct platform_device *pdev)
data->usr_reg = DW_UART_USR;
p->private_data = data;
 
+   err = device_property_read_u32(p->dev, "reg-shift", );
+   if (!err)
+   p->regshift = val;
+
+   err = device_property_read_u32(p->dev, "reg-io-width", );
+   if (!err && val == 4) {
+   p->iotype = UPIO_MEM32;
+   p->serial_in = dw8250_serial_in32;
+   p->serial_out = dw8250_serial_out32;
+   }
+
+   if (device_property_read_bool(p->dev, "dcd-override")) {
+   /* Always report DCD as active */
+   data->msr_mask_on |= UART_MSR_DCD;
+   data->msr_mask_off |= UART_MSR_DDCD;
+   }
+
+   if (device_property_read_bool(p->dev, "dsr-override")) {
+   /* Always report DSR as active */
+   data->msr_mask_on |= UART_MSR_DSR;
+   data->msr_mask_off |= UART_MSR_DDSR;
+   }
+
+   if (device_property_read_bool(p->dev, "cts-override")) {
+   /* Always report CTS as active */
+   data->msr_mask_on |= UART_MSR_CTS;
+   data->msr_mask_off |= UART_MSR_DCTS;
+   }
+
+  

[linux-yocto] [PATCH 08/18] serial: 8250_dw: hook the DMA in one place

[Tan Jui Nee]

From: Heikki Krogerus <heikki.kroge...@linux.intel.com>

Instead of assigning the dma member in dw8250_probe_of and
dw8250_probe_acpi separately, assigning it in dw8250_probe.

Signed-off-by: Heikki Krogerus <heikki.kroge...@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
(cherry picked from commit 2559318caa76028edc9c0553932a17139e6adc58)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 19 +++
 1 file changed, 7 insertions(+), 12 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c 
b/drivers/tty/serial/8250/8250_dw.c
index 2611ee6..a606408 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -298,14 +298,6 @@ static int dw8250_probe_of(struct uart_port *p,
if (has_ucv)
dw8250_setup_port(up);
 
-   /* if we have a valid fifosize, try hooking up DMA here */
-   if (p->fifosize) {
-   up->dma = >dma;
-
-   up->dma->rxconf.src_maxburst = p->fifosize / 4;
-   up->dma->txconf.dst_maxburst = p->fifosize / 4;
-   }
-
/* get index of serial line, if found in DT aliases */
id = of_alias_get_id(np, "serial");
if (id >= 0)
@@ -344,10 +336,6 @@ static int dw8250_probe_acpi(struct uart_8250_port *up,
data->dma.fn = dw8250_idma_filter;
}
 
-   up->dma = >dma;
-   up->dma->rxconf.src_maxburst = p->fifosize / 4;
-   up->dma->txconf.dst_maxburst = p->fifosize / 4;
-
up->port.set_termios = dw8250_set_termios;
 
return 0;
@@ -494,6 +482,13 @@ static int dw8250_probe(struct platform_device *pdev)
goto err_reset;
}
 
+   /* If we have a valid fifosize, try hooking up DMA */
+   if (p->fifosize) {
+   data->dma.rxconf.src_maxburst = p->fifosize / 4;
+   data->dma.txconf.dst_maxburst = p->fifosize / 4;
+   uart.dma = >dma;
+   }
+
data->line = serial8250_register_8250_port();
if (data->line < 0) {
err = data->line;
-- 
1.9.1

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[linux-yocto] [PATCH 06/18] serial: 8250_dw: add separate pointer for the uart_port to dw8250_probe

[Tan Jui Nee]

From: Heikki Krogerus <heikki.kroge...@linux.intel.com>

For convenience, adding separate pointer for the "port"
member of struct uart_8250_port that is being filled in the
probe function.

Signed-off-by: Heikki Krogerus <heikki.kroge...@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
(cherry picked from commit 78d3da75d54ac7c1984ff19ba6034db2f549df89)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 42 +++
 1 file changed, 20 insertions(+), 22 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c 
b/drivers/tty/serial/8250/8250_dw.c
index df3eddf..56e5cac 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -400,6 +400,7 @@ static int dw8250_probe(struct platform_device *pdev)
struct uart_8250_port uart = {};
struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
int irq = platform_get_irq(pdev, 0);
+   struct uart_port *p = 
struct dw8250_data *data;
int err;
 
@@ -414,18 +415,20 @@ static int dw8250_probe(struct platform_device *pdev)
return irq;
}
 
-   spin_lock_init();
-   uart.port.mapbase = regs->start;
-   uart.port.irq = irq;
-   uart.port.handle_irq = dw8250_handle_irq;
-   uart.port.pm = dw8250_do_pm;
-   uart.port.type = PORT_8250;
-   uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
-   uart.port.dev = >dev;
-
-   uart.port.membase = devm_ioremap(>dev, regs->start,
-resource_size(regs));
-   if (!uart.port.membase)
+   spin_lock_init(>lock);
+   p->mapbase  = regs->start;
+   p->irq  = irq;
+   p->handle_irq   = dw8250_handle_irq;
+   p->pm   = dw8250_do_pm;
+   p->type = PORT_8250;
+   p->flags= UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
+   p->dev  = >dev;
+   p->iotype   = UPIO_MEM;
+   p->serial_in= dw8250_serial_in;
+   p->serial_out   = dw8250_serial_out;
+
+   p->membase = devm_ioremap(>dev, regs->start, resource_size(regs));
+   if (!p->membase)
return -ENOMEM;
 
data = devm_kzalloc(>dev, sizeof(*data), GFP_KERNEL);
@@ -433,10 +436,10 @@ static int dw8250_probe(struct platform_device *pdev)
return -ENOMEM;
 
data->usr_reg = DW_UART_USR;
+   p->private_data = data;
 
/* Always ask for fixed clock rate from a property. */
-   device_property_read_u32(>dev, "clock-frequency",
-);
+   device_property_read_u32(p->dev, "clock-frequency", >uartclk);
 
/* If there is separate baudclk, get the rate from it. */
data->clk = devm_clk_get(>dev, "baudclk");
@@ -450,11 +453,11 @@ static int dw8250_probe(struct platform_device *pdev)
dev_warn(>dev, "could not enable optional 
baudclk: %d\n",
 err);
else
-   uart.port.uartclk = clk_get_rate(data->clk);
+   p->uartclk = clk_get_rate(data->clk);
}
 
/* If no clock rate is defined, fail. */
-   if (!uart.port.uartclk) {
+   if (!p->uartclk) {
dev_err(>dev, "clock rate not defined\n");
return -EINVAL;
}
@@ -484,13 +487,8 @@ static int dw8250_probe(struct platform_device *pdev)
data->dma.tx_param = data;
data->dma.fn = dw8250_dma_filter;
 
-   uart.port.iotype = UPIO_MEM;
-   uart.port.serial_in = dw8250_serial_in;
-   uart.port.serial_out = dw8250_serial_out;
-   uart.port.private_data = data;
-
if (pdev->dev.of_node) {
-   err = dw8250_probe_of(, data);
+   err = dw8250_probe_of(p, data);
if (err)
goto err_reset;
} else if (ACPI_HANDLE(>dev)) {
-- 
1.9.1

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[linux-yocto] [PATCH 05/18] serial: 8250_dw: allow lower reference frequencies

[Tan Jui Nee]

From: Andy Shevchenko <andriy.shevche...@linux.intel.com>

We have couple of standard but rare used baudrates which are not supported by
1,8432MHz reference frequency. Besides that user can potentially ask for any
baudrate (via BOTHER flag) and we currently don't fully support that. Since
clk-fractional-divider is moved to use rational best approximation for
reference frequency we may amend the driver to support whatever user wants.

Acked-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
(cherry picked from commit 3b4261dcf65993f95de80a0d63c5299aab922bd8)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c 
b/drivers/tty/serial/8250/8250_dw.c
index 06324f1..df3eddf 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -224,10 +224,6 @@ static void dw8250_set_termios(struct uart_port *p, struct 
ktermios *termios,
if (IS_ERR(d->clk) || !old)
goto out;
 
-   /* Not requesting clock rates below 1.8432Mhz */
-   if (baud < 115200)
-   baud = 115200;
-
clk_disable_unprepare(d->clk);
rate = clk_round_rate(d->clk, baud * 16);
ret = clk_set_rate(d->clk, rate);
-- 
1.9.1

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[linux-yocto] [PATCH 00/18] Backport serial patches from mainline kernel into linux-yocto-4.1

[Tan Jui Nee]

Hi Bruce,

These patches are the serial backports for Intel Apollo Lake/Broxton, that
are available in mainline Linux kernel.

All the patches are to enable serial driver support for Intel Apollo Lake/
Broxton.

The patches are targeted to merge into linux-yocto-4.1 on standard/base
branch.

Please review and provide feedback if any.

Thanks and best regards,
Juinee

Andy Shevchenko (2):
  serial: 8250_dma: no need to sync RX buffer
  serial: 8250_dw: allow lower reference frequencies

Heikki Krogerus (11):
  serial: 8250_dw: support ACPI platforms with integrated DMA engine
  serial: 8250_dw: add separate pointer for the uart_port to
dw8250_probe
  serial: 8250_dw: adapt to unified device property interface
  serial: 8250_dw: hook the DMA in one place
  serial: 8250_dw: only setup the port from one place
  serial: 8250_dw: add dw8250_quirks function
  serial: 8250_dw: proper support for UARTs without busy functionality
  serial: 8250_dw: rename and comment the fallback dma filter
  serial: 8250_dw: cleanup dw8250_idma_filter
  serial: 8250_dw: cleanup dw8250_setup_port
  serial: 8250_dw: don't set UPF_BOOT_AUTOCONF flag

Noam Camus (3):
  serial: 8250_dw: Avoid serial_outx code duplicate with new
dw8250_check_lcr()
  serial: 8250_dw: Add support for big-endian MMIO accesses
  serial: 8250_dw: Do not use readl/writel before checking port iotype

Qipeng Zha (2):
  serial: 8250: Auto CTS control by HW if AFE enabled
  serial:8250_dw: do not alter CTS and DCTS since AFE is enabled

 .../bindings/serial/snps-dw-apb-uart.txt   |   3 +
 drivers/tty/serial/8250/8250_dma.c |   6 -
 drivers/tty/serial/8250/8250_dw.c  | 408 ++---
 drivers/tty/serial/8250/8250_pci.c |   4 +
 4 files changed, 209 insertions(+), 212 deletions(-)

-- 
1.9.1

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[linux-yocto] [PATCH 01/18] serial: 8250_dma: no need to sync RX buffer

[Tan Jui Nee]

From: Andy Shevchenko <andriy.shevche...@linux.intel.com>

RX buffer is allocated from DMA coherent memory. Thus there is no need to call
DMA sync API for it.

Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
(cherry picked from commit 27c310c5c3129aac9d2f325211df85a82177f274)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/tty/serial/8250/8250_dma.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dma.c 
b/drivers/tty/serial/8250/8250_dma.c
index e508939..78259d3 100644
--- a/drivers/tty/serial/8250/8250_dma.c
+++ b/drivers/tty/serial/8250/8250_dma.c
@@ -54,9 +54,6 @@ static void __dma_rx_complete(void *param)
struct dma_tx_state state;
int count;
 
-   dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr,
-   dma->rx_size, DMA_FROM_DEVICE);
-
dma->rx_running = 0;
dmaengine_tx_status(dma->rxchan, dma->rx_cookie, );
 
@@ -152,9 +149,6 @@ int serial8250_rx_dma(struct uart_8250_port *p, unsigned 
int iir)
 
dma->rx_cookie = dmaengine_submit(desc);
 
-   dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr,
-  dma->rx_size, DMA_FROM_DEVICE);
-
dma_async_issue_pending(dma->rxchan);
 
return 0;
-- 
1.9.1

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[linux-yocto] [PATCH 04/18] serial:8250_dw: do not alter CTS and DCTS since AFE is enabled

[Tan Jui Nee]

From: Qipeng Zha <qipeng@intel.com>

Since the serial core is informed that this device is doing
automatic flow control, it is not necessary to alter CTS and
DCTS of the MSR as the core no longer attempts stop the port
in uart_handle_cts_change().

Signed-off-by: Huiquan Zhong <huiquan.zh...@intel.com>
Signed-off-by: Qipeng Zha <qipeng@intel.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
(cherry picked from commit cbba3e6f7a1eb642cccf520f690d4a58b97a9588)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 22 --
 1 file changed, 22 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c 
b/drivers/tty/serial/8250/8250_dw.c
index 8d04ea7..06324f1 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -56,7 +56,6 @@
 
 struct dw8250_data {
u8  usr_reg;
-   int last_mcr;
int line;
int msr_mask_on;
int msr_mask_off;
@@ -76,12 +75,6 @@ static inline int dw8250_modify_msr(struct uart_port *p, int 
offset, int value)
 {
struct dw8250_data *d = p->private_data;
 
-   /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
-   if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
-   value |= UART_MSR_CTS;
-   value &= ~UART_MSR_DCTS;
-   }
-
/* Override any modem control signals if needed */
if (offset == UART_MSR) {
value |= d->msr_mask_on;
@@ -101,11 +94,6 @@ static void dw8250_force_idle(struct uart_port *p)
 
 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
 {
-   struct dw8250_data *d = p->private_data;
-
-   if (offset == UART_MCR)
-   d->last_mcr = value;
-
writeb(value, p->membase + (offset << p->regshift));
 
/* Make sure LCR write wasn't ignored */
@@ -144,11 +132,6 @@ static unsigned int dw8250_serial_inq(struct uart_port *p, 
int offset)
 
 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
 {
-   struct dw8250_data *d = p->private_data;
-
-   if (offset == UART_MCR)
-   d->last_mcr = value;
-
value &= 0xff;
__raw_writeq(value, p->membase + (offset << p->regshift));
/* Read back to ensure register write ordering. */
@@ -175,11 +158,6 @@ static void dw8250_serial_outq(struct uart_port *p, int 
offset, int value)
 
 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
 {
-   struct dw8250_data *d = p->private_data;
-
-   if (offset == UART_MCR)
-   d->last_mcr = value;
-
writel(value, p->membase + (offset << p->regshift));
 
/* Make sure LCR write wasn't ignored */
-- 
1.9.1

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[linux-yocto] [PATCH 02/18] serial: 8250_dw: support ACPI platforms with integrated DMA engine

[Tan Jui Nee]

From: Heikki Krogerus <heikki.kroge...@linux.intel.com>

On many new Intel SoCs the UART has an integrated DMA engine
(iDMA). In order to use it a special filter function is needed.

Signed-off-by: Heikki Krogerus <heikki.kroge...@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
(cherry picked from commit 0788c39b955151d92711800ce14f41154095bfa6)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c 
b/drivers/tty/serial/8250/8250_dw.c
index 176f18f..d48b506 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -377,6 +377,16 @@ static int dw8250_probe_of(struct uart_port *p,
return 0;
 }
 
+static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
+{
+   struct device *dev = param;
+
+   if (dev != chan->device->dev->parent)
+   return false;
+
+   return true;
+}
+
 static int dw8250_probe_acpi(struct uart_8250_port *up,
 struct dw8250_data *data)
 {
@@ -389,8 +399,15 @@ static int dw8250_probe_acpi(struct uart_8250_port *up,
p->serial_out = dw8250_serial_out32;
p->regshift = 2;
 
-   up->dma = >dma;
+   /* Platforms with iDMA */
+   if (platform_get_resource_byname(to_platform_device(up->port.dev),
+IORESOURCE_MEM, "lpss_priv")) {
+   data->dma.rx_param = up->port.dev->parent;
+   data->dma.tx_param = up->port.dev->parent;
+   data->dma.fn = dw8250_idma_filter;
+   }
 
+   up->dma = >dma;
up->dma->rxconf.src_maxburst = p->fifosize / 4;
up->dma->txconf.dst_maxburst = p->fifosize / 4;
 
-- 
1.9.1

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[linux-yocto] [PATCH 03/18] serial: 8250: Auto CTS control by HW if AFE enabled

[Tan Jui Nee]

From: Qipeng Zha <qipeng@intel.com>

According to DesignWare 8250 spec, if auto flow control
mode is enabled, a change in CTS does not cause an interrupt,
so sw-assisted CTS flow control mode will not work properly.

There reported an GPS firmware download failure issue, and we
verified the root cause is, the default sw-assisted CTS flow
control mode can not work properly since no interrupt when got
CTS signal.

This patch is to enable auto CTS mode by defaut if CRTSCTS
is enable for DesignWare 8250 controller.

Signed-off-by: Huiquan Zhong <huiquan.zh...@intel.com>
Signed-off-by: Qipeng Zha <qipeng@intel.com>
Reviewed-by: Peter Hurley <pe...@hurleysoftware.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
(cherry picked from commit 0a6c301a2db2f9af0478a83c15d8ec5cdac65eb9)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/tty/serial/8250/8250_dw.c  | 5 +
 drivers/tty/serial/8250/8250_pci.c | 4 
 2 files changed, 9 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_dw.c 
b/drivers/tty/serial/8250/8250_dw.c
index d48b506..8d04ea7 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -257,6 +257,11 @@ static void dw8250_set_termios(struct uart_port *p, struct 
ktermios *termios,
 
if (!ret)
p->uartclk = rate;
+
+   p->status &= ~UPSTAT_AUTOCTS;
+   if (termios->c_cflag & CRTSCTS)
+   p->status |= UPSTAT_AUTOCTS;
+
 out:
serial8250_do_set_termios(p, termios, old);
 }
diff --git a/drivers/tty/serial/8250/8250_pci.c 
b/drivers/tty/serial/8250/8250_pci.c
index b82b2a0..d341f30 100644
--- a/drivers/tty/serial/8250/8250_pci.c
+++ b/drivers/tty/serial/8250/8250_pci.c
@@ -1420,6 +1420,10 @@ byt_set_termios(struct uart_port *p, struct ktermios 
*termios,
reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
writel(reg, p->membase + BYT_PRV_CLK);
 
+   p->status &= ~UPSTAT_AUTOCTS;
+   if (termios->c_cflag & CRTSCTS)
+   p->status |= UPSTAT_AUTOCTS;
+
serial8250_do_set_termios(p, termios, old);
 }
 
-- 
1.9.1

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[linux-yocto] [PATCH] dmaengine: idma: rename to INTEL_IDMA64

[Tan Jui Nee]

From: Vinod Koul <vinod.k...@intel.com>

the symbol CONFIG_IDMA64 should rather be CONFIG_INTEL_IDMA64 to conform to
rest of the intel dmaengine drivers. This was found after sorting the
entries and trying to place this odd one

Suggested-by: Linus Torvalds <torva...@linux-foundation.org>
Acked-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.k...@intel.com>
(cherry picked from commit 9ab8b4e7cacfc4a03e4f39fe8a090436ce456720)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>

Conflicts:
drivers/dma/Kconfig
drivers/dma/Makefile
---
 drivers/dma/Kconfig  | 2 +-
 drivers/dma/Makefile | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 2c2e174..703df70 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -85,7 +85,7 @@ config INTEL_IOP_ADMA
help
  Enable support for the Intel(R) IOP Series RAID engines.
 
-config IDMA64
+config INTEL_IDMA64
tristate "Intel integrated DMA 64-bit support"
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index c1fe119..9078963 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -14,7 +14,7 @@ obj-$(CONFIG_HSU_DMA) += hsu/
 obj-$(CONFIG_MPC512X_DMA) += mpc512x_dma.o
 obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
 obj-$(CONFIG_MV_XOR) += mv_xor.o
-obj-$(CONFIG_IDMA64) += idma64.o
+obj-$(CONFIG_INTEL_IDMA64) += idma64.o
 obj-$(CONFIG_DW_DMAC_CORE) += dw/
 obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
 obj-$(CONFIG_AT_XDMAC) += at_xdmac.o
-- 
1.9.1

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[linux-yocto] [PATCH] Backport iDMA64 patches from mainline kernel into linux-yocto-4.1

[Tan Jui Nee]

Hi Bruce,

The patch is to rename symbol CONFIG_IDMA64 to CONFIG_INTEL_IDMA64,
as to conform to rest of the intel dmaengine drivers. 

The patch is targeted to merge into linux-yocto-4.1 on standard/base
branch.

Please review and provide feedback if any.

Thanks and best regards,
Juinee

Vinod Koul (1):
  dmaengine: idma: rename to INTEL_IDMA64

 drivers/dma/Kconfig  | 2 +-
 drivers/dma/Makefile | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

-- 
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[linux-yocto] [PATCH 12/12] dmaengine: idma64: clear LLP_[SD]_EN bits in last descriptor

[Tan Jui Nee]

From: Andy Shevchenko <andriy.shevche...@linux.intel.com>

The datasheet requires that the user must clear LLP_[SD]_EN bits whenever
LLP.LOC is zero, i.e. in the last descriptor of a multi-block chain.

Make the driver do this.

Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.k...@intel.com>
(cherry picked from commit a2826e662eb13a041078260692b4e023ed5cbf62)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/dma/idma64.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c
index 3cb7b2c..1953e57 100644
--- a/drivers/dma/idma64.c
+++ b/drivers/dma/idma64.c
@@ -289,6 +289,9 @@ static void idma64_desc_fill(struct idma64_chan *idma64c,
 
/* Trigger an interrupt after the last block is transfered */
lli->ctllo |= IDMA64C_CTLL_INT_EN;
+
+   /* Disable LLP transfer in the last block */
+   lli->ctllo &= ~(IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
 }
 
 static struct dma_async_tx_descriptor *idma64_prep_slave_sg(
-- 
1.9.1

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[linux-yocto] [PATCH 09/12] dmaengine: idma64: set maximum allowed segment size for DMA

[Tan Jui Nee]

From: Andy Shevchenko <andriy.shevche...@linux.intel.com>

This tells, for example, IOMMU what the maximum size of a segment
the DMA controller can send.

Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.k...@intel.com>
(cherry picked from commit e3fdb1894cfac6dd4a5bb24d3232fd97ddf74c93)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/dma/idma64.c | 2 ++
 drivers/dma/idma64.h | 3 ++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c
index 6bba090..97802be 100644
--- a/drivers/dma/idma64.c
+++ b/drivers/dma/idma64.c
@@ -588,6 +588,8 @@ static int idma64_probe(struct idma64_chip *chip)
 
idma64->dma.dev = chip->dev;
 
+   dma_set_max_seg_size(idma64->dma.dev, IDMA64C_CTLH_BLOCK_TS_MASK);
+
ret = dma_async_device_register(>dma);
if (ret)
return ret;
diff --git a/drivers/dma/idma64.h b/drivers/dma/idma64.h
index f6aeff0..8423f13 100644
--- a/drivers/dma/idma64.h
+++ b/drivers/dma/idma64.h
@@ -54,7 +54,8 @@
 #define IDMA64C_CTLL_LLP_S_EN  (1 << 28)   /* src block chain */
 
 /* Bitfields in CTL_HI */
-#define IDMA64C_CTLH_BLOCK_TS(x)   ((x) & ((1 << 17) - 1))
+#define IDMA64C_CTLH_BLOCK_TS_MASK ((1 << 17) - 1)
+#define IDMA64C_CTLH_BLOCK_TS(x)   ((x) & IDMA64C_CTLH_BLOCK_TS_MASK)
 #define IDMA64C_CTLH_DONE  (1 << 17)
 
 /* Bitfields in CFG_LO */
-- 
1.9.1

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[linux-yocto] [PATCH 10/12] dmaengine: idma64: convert idma64_hw_desc_fill() to return void

[Tan Jui Nee]

From: Andy Shevchenko <andriy.shevche...@linux.intel.com>

Explicitly show in idma64_desc_fill() how we link the hardware
descriptors.

Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.k...@intel.com>
(cherry picked from commit ac02979413e0310f85bbcc2945d65da7071c08fe)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/dma/idma64.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c
index 97802be..b6c13f9 100644
--- a/drivers/dma/idma64.c
+++ b/drivers/dma/idma64.c
@@ -231,7 +231,7 @@ static void idma64_vdesc_free(struct virt_dma_desc *vdesc)
idma64_desc_free(idma64c, to_idma64_desc(vdesc));
 }
 
-static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw,
+static void idma64_hw_desc_fill(struct idma64_hw_desc *hw,
struct dma_slave_config *config,
enum dma_transfer_direction direction, u64 llp)
 {
@@ -268,7 +268,6 @@ static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw,
 IDMA64C_CTLL_SRC_WIDTH(src_width);
 
lli->llp = llp;
-   return hw->llp;
 }
 
 static void idma64_desc_fill(struct idma64_chan *idma64c,
@@ -283,7 +282,8 @@ static void idma64_desc_fill(struct idma64_chan *idma64c,
/* Fill the hardware descriptors and link them to a list */
do {
hw = >hw[--i];
-   llp = idma64_hw_desc_fill(hw, config, desc->direction, llp);
+   idma64_hw_desc_fill(hw, config, desc->direction, llp);
+   llp = hw->llp;
desc->length += hw->len;
} while (i);
 
-- 
1.9.1

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[linux-yocto] [PATCH 04/12] dmaengine: idma64: useless use of min_t()

[Tan Jui Nee]

From: Andy Shevchenko <andriy.shevche...@linux.intel.com>

We use a pattern

x = min_t(u32, , __ffs(expr));

There is no need to use min_t() since we can replace it by

x = __ffs(expr | <2^LOG2_CONST>);

and moreover guarantee that argument of __ffs() will be not zero.

Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.k...@intel.com>
(cherry picked from commit 22b74406c5ac1829cd60f75c8c6a4ed1e0f4da03)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/dma/idma64.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c
index 8aea9f0..c7da43c 100644
--- a/drivers/dma/idma64.c
+++ b/drivers/dma/idma64.c
@@ -257,7 +257,7 @@ static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw,
dar = config->dst_addr;
ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC |
 IDMA64C_CTLL_FC_M2P;
-   src_width = min_t(u32, 2, __ffs(sar | hw->len));
+   src_width = __ffs(sar | hw->len | 4);
dst_width = __ffs(config->dst_addr_width);
} else {/* DMA_DEV_TO_MEM */
sar = config->src_addr;
@@ -265,7 +265,7 @@ static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw,
ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX |
 IDMA64C_CTLL_FC_P2M;
src_width = __ffs(config->src_addr_width);
-   dst_width = min_t(u32, 2, __ffs(dar | hw->len));
+   dst_width = __ffs(dar | hw->len | 4);
}
 
lli->sar = sar;
-- 
1.9.1

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[linux-yocto] [PATCH 06/12] dmaengine: idma64: make better performance on pause / resume

[Tan Jui Nee]

From: Andy Shevchenko <andriy.shevche...@linux.intel.com>

Accordingly to the documentation the CH_DRAIN bit enforses single bursts when
channel is going to be suspended. This, in case when channel will be resumed,
makes data to flow in non-optimal mode until DMA returns to full burst mode.
The fix differentiates pause / resume cycle from pause / terminate and sets
CH_DRAIN bit accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.k...@intel.com>
(cherry picked from commit 2e9b55becc905207eb01e24bc282f8062cc497b5)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/dma/idma64.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c
index c7da43c..7d56b47 100644
--- a/drivers/dma/idma64.c
+++ b/drivers/dma/idma64.c
@@ -65,9 +65,6 @@ static void idma64_chan_init(struct idma64 *idma64, struct 
idma64_chan *idma64c)
u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
u32 cfglo = 0;
 
-   /* Enforce FIFO drain when channel is suspended */
-   cfglo |= IDMA64C_CFGL_CH_DRAIN;
-
/* Set default burst alignment */
cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN;
 
@@ -428,12 +425,17 @@ static int idma64_slave_config(struct dma_chan *chan,
return 0;
 }
 
-static void idma64_chan_deactivate(struct idma64_chan *idma64c)
+static void idma64_chan_deactivate(struct idma64_chan *idma64c, bool drain)
 {
unsigned short count = 100;
u32 cfglo;
 
cfglo = channel_readl(idma64c, CFG_LO);
+   if (drain)
+   cfglo |= IDMA64C_CFGL_CH_DRAIN;
+   else
+   cfglo &= ~IDMA64C_CFGL_CH_DRAIN;
+
channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP);
do {
udelay(1);
@@ -456,7 +458,7 @@ static int idma64_pause(struct dma_chan *chan)
 
spin_lock_irqsave(>vchan.lock, flags);
if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) {
-   idma64_chan_deactivate(idma64c);
+   idma64_chan_deactivate(idma64c, false);
idma64c->desc->status = DMA_PAUSED;
}
spin_unlock_irqrestore(>vchan.lock, flags);
@@ -486,7 +488,7 @@ static int idma64_terminate_all(struct dma_chan *chan)
LIST_HEAD(head);
 
spin_lock_irqsave(>vchan.lock, flags);
-   idma64_chan_deactivate(idma64c);
+   idma64_chan_deactivate(idma64c, true);
idma64_stop_transfer(idma64c);
if (idma64c->desc) {
idma64_vdesc_free(>desc->vdesc);
-- 
1.9.1

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[linux-yocto] [PATCH 01/12] dmaengine: add a driver for Intel integrated DMA 64-bit

[Tan Jui Nee]

From: Andy Shevchenko <andriy.shevche...@linux.intel.com>

Intel integrated DMA (iDMA) 64-bit is a specific IP that is used as a part of
LPSS devices such as HSUART or SPI. The iDMA IP is attached for private
usage on each host controller independently.

While it has similarities with Synopsys DesignWare DMA, the following
distinctions doesn't allow to use the existing driver:
- 64-bit mode with corresponding changes in Hardware Linked List data structure
- many slight differences in the channel registers

Moreover this driver is based on the DMA virtual channels framework that helps
to make the driver cleaner and easy to understand.

Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Acked-by: Vinod Koul <vinod.k...@intel.com>
Signed-off-by: Lee Jones <lee.jo...@linaro.org>
(cherry picked from commit 667dfed98615ae1fc4cc05b0763078435598c0f5)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/dma/Kconfig  |   8 +
 drivers/dma/Makefile |   1 +
 drivers/dma/idma64.c | 710 +++
 drivers/dma/idma64.h | 233 +
 4 files changed, 952 insertions(+)
 create mode 100644 drivers/dma/idma64.c
 create mode 100644 drivers/dma/idma64.h

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index bda2cb0..2c2e174 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -85,6 +85,14 @@ config INTEL_IOP_ADMA
help
  Enable support for the Intel(R) IOP Series RAID engines.
 
+config IDMA64
+   tristate "Intel integrated DMA 64-bit support"
+   select DMA_ENGINE
+   select DMA_VIRTUAL_CHANNELS
+   help
+ Enable DMA support for Intel Low Power Subsystem such as found on
+ Intel Skylake PCH.
+
 source "drivers/dma/dw/Kconfig"
 
 config AT_HDMAC
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 69f77d5..c1fe119 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_HSU_DMA) += hsu/
 obj-$(CONFIG_MPC512X_DMA) += mpc512x_dma.o
 obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
 obj-$(CONFIG_MV_XOR) += mv_xor.o
+obj-$(CONFIG_IDMA64) += idma64.o
 obj-$(CONFIG_DW_DMAC_CORE) += dw/
 obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
 obj-$(CONFIG_AT_XDMAC) += at_xdmac.o
diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c
new file mode 100644
index 000..18c14e1
--- /dev/null
+++ b/drivers/dma/idma64.c
@@ -0,0 +1,710 @@
+/*
+ * Core driver for the Intel integrated DMA 64-bit
+ *
+ * Copyright (C) 2015 Intel Corporation
+ * Author: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "idma64.h"
+
+/* Platform driver name */
+#define DRV_NAME   "idma64"
+
+/* For now we support only two channels */
+#define IDMA64_NR_CHAN 2
+
+/* -- */
+
+static struct device *chan2dev(struct dma_chan *chan)
+{
+   return >dev->device;
+}
+
+/* -- */
+
+static void idma64_off(struct idma64 *idma64)
+{
+   unsigned short count = 100;
+
+   dma_writel(idma64, CFG, 0);
+
+   channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
+   channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask);
+   channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask);
+   channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask);
+   channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
+
+   do {
+   cpu_relax();
+   } while (dma_readl(idma64, CFG) & IDMA64_CFG_DMA_EN && --count);
+}
+
+static void idma64_on(struct idma64 *idma64)
+{
+   dma_writel(idma64, CFG, IDMA64_CFG_DMA_EN);
+}
+
+/* -- */
+
+static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan 
*idma64c)
+{
+   u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
+   u32 cfglo = 0;
+
+   /* Enforce FIFO drain when channel is suspended */
+   cfglo |= IDMA64C_CFGL_CH_DRAIN;
+
+   /* Set default burst alignment */
+   cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN;
+
+   channel_writel(idma64c, CFG_LO, cfglo);
+   channel_writel(idma64c, CFG_HI, cfghi);
+
+   /* Enable interrupts */
+   channel_set_bit(idma64, MASK(XFER), idma64c->mask);
+   channel_set_bit(idma64, MASK(ERROR), idma64c->mask);
+
+   /*
+* Enforce the controller to be turned on.
+*
+* The iDMA is turned off in ->pr

[linux-yocto] [PATCH 08/12] dmaengine: idma64: drop IRQ enable / disable in handler

[Tan Jui Nee]

From: Andy Shevchenko <andriy.shevche...@linux.intel.com>

There is no need to disable interrupts in the IRQ handler. The driver
guarantess that at one time only one descriptor is active, besides the fact
that each call to the same channel will be serialized in idma64_chan_irq()
handler anyway.

Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.k...@intel.com>
(cherry picked from commit 37580559f314bfba0c8bdae002bc5c10088ac457)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/dma/idma64.c | 8 
 1 file changed, 8 deletions(-)

diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c
index 7d56b47..6bba090 100644
--- a/drivers/dma/idma64.c
+++ b/drivers/dma/idma64.c
@@ -178,20 +178,12 @@ static irqreturn_t idma64_irq(int irq, void *dev)
if (!status)
return IRQ_NONE;
 
-   /* Disable interrupts */
-   channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
-   channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
-
status_xfer = dma_readl(idma64, RAW(XFER));
status_err = dma_readl(idma64, RAW(ERROR));
 
for (i = 0; i < idma64->dma.chancnt; i++)
idma64_chan_irq(idma64, i, status_err, status_xfer);
 
-   /* Re-enable interrupts */
-   channel_set_bit(idma64, MASK(XFER), idma64->all_chan_mask);
-   channel_set_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
-
return IRQ_HANDLED;
 }
 
-- 
1.9.1

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[linux-yocto] [PATCH 05/12] dmaengine: idma64: this is not DesignWare

[Tan Jui Nee]

From: Andy Shevchenko <andriy.shevche...@linux.intel.com>

This patch fixes a comment where DesignWare is wrongly mentioned. There is no
functional change.

Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.k...@intel.com>
(cherry picked from commit 581ec089a5476a9ddc8d0707e47315a2609297ad)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/dma/idma64.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/idma64.h b/drivers/dma/idma64.h
index a4d9968..323c3f1 100644
--- a/drivers/dma/idma64.h
+++ b/drivers/dma/idma64.h
@@ -217,7 +217,7 @@ static inline void idma64_writel(struct idma64 *idma64, int 
offset, u32 value)
idma64_writel(idma64, IDMA64_##reg, (value))
 
 /**
- * struct idma64_chip - representation of DesignWare DMA controller hardware
+ * struct idma64_chip - representation of iDMA 64-bit controller hardware
  * @dev:   struct device of the DMA controller
  * @irq:   irq line
  * @regs:  memory mapped I/O space
-- 
1.9.1

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[linux-yocto] [PATCH 02/12] dmaengine: idma64: improve residue estimation

[Tan Jui Nee]

From: Andy Shevchenko <andriy.shevche...@linux.intel.com>

The residue calculation may provide a wrong estimation when the transfer is
started. There are possible scenarios we have to separate:

1) the transfer is not started yet; residue is equal to the total
   length;

2) the transfer is just started (first chunk is ongoing); residue is
   equal to the total length without already transfered bytes;

3) the transfer is ongoing and we already sent few chunks of data;
   residue is equal to the total length without fully transfered chunks
   and already sent bytes.

Mistakenly the calculation in cases 2) and 3) was done in the similar way and
the result is equal to -bytes that have been transfered, i.e. quite big since
size_t type can't keep negative values.

Rewrite the calculation algorithm to be one pass and have a correct result.

Besides above in case user asks for a status of the active DMA descriptor
without pausing an ongoing transfer the residue will be estimated based on the
register value, though it's still racy. Since the transfer is active the value
is continuously being changed. Here we have to read two registers at a time. To
minimize an error make those reads close to each other.

Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.k...@intel.com>
(cherry picked from commit 0b23a1ece9be2c3e04c3b8d3594a1ada1fa1ae50)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/dma/idma64.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c
index 18c14e1..48d6d9e 100644
--- a/drivers/dma/idma64.c
+++ b/drivers/dma/idma64.c
@@ -355,23 +355,23 @@ static size_t idma64_active_desc_size(struct idma64_chan 
*idma64c)
struct idma64_desc *desc = idma64c->desc;
struct idma64_hw_desc *hw;
size_t bytes = desc->length;
-   u64 llp;
-   u32 ctlhi;
+   u64 llp = channel_readq(idma64c, LLP);
+   u32 ctlhi = channel_readl(idma64c, CTL_HI);
unsigned int i = 0;
 
-   llp = channel_readq(idma64c, LLP);
do {
hw = >hw[i];
-   } while ((hw->llp != llp) && (++i < desc->ndesc));
+   if (hw->llp == llp)
+   break;
+   bytes -= hw->len;
+   } while (++i < desc->ndesc);
 
if (!i)
return bytes;
 
-   do {
-   bytes -= desc->hw[--i].len;
-   } while (i);
+   /* The current chunk is not fully transfered yet */
+   bytes += desc->hw[--i].len;
 
-   ctlhi = channel_readl(idma64c, CTL_HI);
return bytes - IDMA64C_CTLH_BLOCK_TS(ctlhi);
 }
 
-- 
1.9.1

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[linux-yocto] [PATCH 00/12] Backport iDMA64 patches from mainline kernel into linux-yocto-4.1

[Tan Jui Nee]

Hi Bruce,

The patches are to enable iDMA64 driver support for Intel
Broxton that are available in the mainline Linux kernel,
upstreamed by Andy Shevchenko.

The patches are targeted to merge into linux-yocto-4.1 on
standard/base branch.

Please review and provide feedback if any.

Thanks and best regards,
Juinee

Andy Shevchenko (12):
  dmaengine: add a driver for Intel integrated DMA 64-bit
  dmaengine: idma64: improve residue estimation
  dmaengine: idma64: convert to __ffs()
  dmaengine: idma64: useless use of min_t()
  dmaengine: idma64: this is not DesignWare
  dmaengine: idma64: make better performance on pause / resume
  dmaengine: idma64: use lo_hi_readq() / lo_hi_writeq()
  dmaengine: idma64: drop IRQ enable / disable in handler
  dmaengine: idma64: set maximum allowed segment size for DMA
  dmaengine: idma64: convert idma64_hw_desc_fill() to return void
  dmaengine: idma64: use local variable to index descriptor
  dmaengine: idma64: clear LLP_[SD]_EN bits in last descriptor

 drivers/dma/Kconfig  |   8 +
 drivers/dma/Makefile |   1 +
 drivers/dma/idma64.c | 709 +++
 drivers/dma/idma64.h | 230 +
 4 files changed, 948 insertions(+)
 create mode 100644 drivers/dma/idma64.c
 create mode 100644 drivers/dma/idma64.h

-- 
1.9.1

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[linux-yocto] [PATCH 01/11] pwm: lpss: Add support for multiple PWMs

[Tan Jui Nee]

From: Mika Westerberg <mika.westerb...@linux.intel.com>

New Intel SoCs such as Broxton will have four PWMs per PCI (or ACPI)
device. Each PWM has 1k of register space allocated from the parent device.
Add support for this.

Signed-off-by: Mika Westerberg <mika.westerb...@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.red...@gmail.com>
(cherry picked from commit 4e11f5acb25b0b8eb937c726ade319b988fe3664)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/pwm/pwm-lpss.c | 48 +++-
 drivers/pwm/pwm-lpss.h |  1 +
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c
index e979825..e7392bd 100644
--- a/drivers/pwm/pwm-lpss.c
+++ b/drivers/pwm/pwm-lpss.c
@@ -29,6 +29,9 @@
 #define PWM_LIMIT  (0x8000 + PWM_DIVISION_CORRECTION)
 #define NSECS_PER_SEC  10UL
 
+/* Size of each PWM register space if multiple */
+#define PWM_SIZE   0x400
+
 struct pwm_lpss_chip {
struct pwm_chip chip;
void __iomem *regs;
@@ -37,13 +40,15 @@ struct pwm_lpss_chip {
 
 /* BayTrail */
 const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
-   .clk_rate = 2500
+   .clk_rate = 2500,
+   .npwm = 1,
 };
 EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
 
 /* Braswell */
 const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
-   .clk_rate = 1920
+   .clk_rate = 1920,
+   .npwm = 1,
 };
 EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
 
@@ -52,6 +57,20 @@ static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip 
*chip)
return container_of(chip, struct pwm_lpss_chip, chip);
 }
 
+static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
+{
+   struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
+
+   return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
+}
+
+static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
+{
+   struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
+
+   writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
+}
+
 static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm,
   int duty_ns, int period_ns)
 {
@@ -79,38 +98,30 @@ static int pwm_lpss_config(struct pwm_chip *chip, struct 
pwm_device *pwm,
duty_ns = 1;
on_time_div = 255 - (255 * duty_ns / period_ns);
 
-   ctrl = readl(lpwm->regs + PWM);
+   ctrl = pwm_lpss_read(pwm);
ctrl &= ~(PWM_BASE_UNIT_MASK | PWM_ON_TIME_DIV_MASK);
ctrl |= (u16) base_unit << PWM_BASE_UNIT_SHIFT;
ctrl |= on_time_div;
/* request PWM to update on next cycle */
ctrl |= PWM_SW_UPDATE;
-   writel(ctrl, lpwm->regs + PWM);
+   pwm_lpss_write(pwm, ctrl);
 
return 0;
 }
 
 static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
-   struct pwm_lpss_chip *lpwm = to_lpwm(chip);
-   u32 ctrl;
-
-   ctrl = readl(lpwm->regs + PWM);
-   writel(ctrl | PWM_ENABLE, lpwm->regs + PWM);
-
+   pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
return 0;
 }
 
 static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
-   struct pwm_lpss_chip *lpwm = to_lpwm(chip);
-   u32 ctrl;
-
-   ctrl = readl(lpwm->regs + PWM);
-   writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM);
+   pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
 }
 
 static const struct pwm_ops pwm_lpss_ops = {
+   .free = pwm_lpss_disable,
.config = pwm_lpss_config,
.enable = pwm_lpss_enable,
.disable = pwm_lpss_disable,
@@ -135,7 +146,7 @@ struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, 
struct resource *r,
lpwm->chip.dev = dev;
lpwm->chip.ops = _lpss_ops;
lpwm->chip.base = -1;
-   lpwm->chip.npwm = 1;
+   lpwm->chip.npwm = info->npwm;
 
ret = pwmchip_add(>chip);
if (ret) {
@@ -149,11 +160,6 @@ EXPORT_SYMBOL_GPL(pwm_lpss_probe);
 
 int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
 {
-   u32 ctrl;
-
-   ctrl = readl(lpwm->regs + PWM);
-   writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM);
-
return pwmchip_remove(>chip);
 }
 EXPORT_SYMBOL_GPL(pwm_lpss_remove);
diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h
index aa041bb..1804383 100644
--- a/drivers/pwm/pwm-lpss.h
+++ b/drivers/pwm/pwm-lpss.h
@@ -20,6 +20,7 @@ struct pwm_lpss_chip;
 
 struct pwm_lpss_boardinfo {
unsigned long clk_rate;
+   unsigned int npwm;
 };
 
 extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info;
-- 
1.9.1

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[linux-yocto] [PATCH 02/11] pwm: lpss: Support all four PWMs on Intel Broxton

[Tan Jui Nee]

From: Mika Westerberg <mika.westerb...@linux.intel.com>

Intel Broxton has similar PWM than Intel Braswell but instead of one it has
four PWMs included in one PCI/ACPI device. This patch adds support for all
the four PWMs and changes the PCI part of the driver to use
'pwm_lpss_bxt_info' instead.

Signed-off-by: Mika Westerberg <mika.westerb...@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.red...@gmail.com>
(cherry picked from commit 87219cb47e5ccfb932177e960c495d475bc16add)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>

Conflicts:
drivers/pwm/pwm-lpss-pci.c - resolve cherry-pick conflicts
manually for not picking below commit:
361c106 pwm: lpss: pci: Add support for Broxton platform
which has typo error.
---
 drivers/pwm/pwm-lpss-pci.c | 2 ++
 drivers/pwm/pwm-lpss.c | 7 +++
 drivers/pwm/pwm-lpss.h | 1 +
 3 files changed, 10 insertions(+)

diff --git a/drivers/pwm/pwm-lpss-pci.c b/drivers/pwm/pwm-lpss-pci.c
index cf20d2b..6432a0b 100644
--- a/drivers/pwm/pwm-lpss-pci.c
+++ b/drivers/pwm/pwm-lpss-pci.c
@@ -44,8 +44,10 @@ static void pwm_lpss_remove_pci(struct pci_dev *pdev)
 }
 
 static const struct pci_device_id pwm_lpss_pci_ids[] = {
+   { PCI_VDEVICE(INTEL, 0x0ac8), (unsigned long)_lpss_bxt_info},
{ PCI_VDEVICE(INTEL, 0x0f08), (unsigned long)_lpss_byt_info},
{ PCI_VDEVICE(INTEL, 0x0f09), (unsigned long)_lpss_byt_info},
+   { PCI_VDEVICE(INTEL, 0x1ac8), (unsigned long)_lpss_bxt_info},
{ PCI_VDEVICE(INTEL, 0x2288), (unsigned long)_lpss_bsw_info},
{ PCI_VDEVICE(INTEL, 0x2289), (unsigned long)_lpss_bsw_info},
{ },
diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c
index e7392bd..df03b50 100644
--- a/drivers/pwm/pwm-lpss.c
+++ b/drivers/pwm/pwm-lpss.c
@@ -52,6 +52,13 @@ const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
 };
 EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
 
+/* Broxton */
+const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
+   .clk_rate = 1920,
+   .npwm = 4,
+};
+EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info);
+
 static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
 {
return container_of(chip, struct pwm_lpss_chip, chip);
diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h
index 1804383..e8cf337 100644
--- a/drivers/pwm/pwm-lpss.h
+++ b/drivers/pwm/pwm-lpss.h
@@ -25,6 +25,7 @@ struct pwm_lpss_boardinfo {
 
 extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info;
 extern const struct pwm_lpss_boardinfo pwm_lpss_bsw_info;
+extern const struct pwm_lpss_boardinfo pwm_lpss_bxt_info;
 
 struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
 const struct pwm_lpss_boardinfo *info);
-- 
1.9.1

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[linux-yocto] [PATCH 00/11] Backport PWM patches from mainline kernel into linux-yocto-4.1

[Tan Jui Nee]

Hi Bruce,

The patches are PWM backport for Intel Broxton that are available in
the mainline Linux kernel.

The following patches are to enable PWM driver support for Intel Broxton.
pwm: lpss: Add support for multiple PWMs
pwm: lpss: Support all four PWMs on Intel Broxton
pwm: lpss: Add more Intel Broxton IDs
pwm: lpss: Add support for runtime PM
pwm: lpss: Remove ->free() callback
pwm: lpss: Update PWM setting for Broxton
pwm: lpss: Select core part automatically
pwm: lpss: Rework the sequence of programming PWM_SW_UPDATE
pwm: Add the pwm_is_enabled() helper

The rest of the patches are dependency patches, to ensure
the above patches applied cleanly to the branch.

The patches are targeted to merge into linux-yocto-4.1 on
standard/base branch.

Please review and provide feedback if any.

Thanks and best regards,
Juinee

Alexandre Belloni (2):
  pwm: atmel: Fix incorrect CDTY value after enabling
  pwm: atmel: Fix incorrect CDTY value after disabling

Andy Shevchenko (1):
  pwm: lpss: Select core part automatically

Boris Brezillon (1):
  pwm: Add the pwm_is_enabled() helper

Mika Westerberg (5):
  pwm: lpss: Add support for multiple PWMs
  pwm: lpss: Support all four PWMs on Intel Broxton
  pwm: lpss: Add more Intel Broxton IDs
  pwm: lpss: Remove ->free() callback
  pwm: lpss: Rework the sequence of programming PWM_SW_UPDATE

Qipeng Zha (1):
  pwm: lpss: Add support for runtime PM

qipeng.zha (1):
  pwm: lpss: Update PWM setting for Broxton

 drivers/pwm/Kconfig |  15 ++
 drivers/pwm/core.c  |   4 +-
 drivers/pwm/pwm-atmel-tcb.c |   2 +-
 drivers/pwm/pwm-atmel.c |  67 ---
 drivers/pwm/pwm-bcm-kona.c  |   4 +-
 drivers/pwm/pwm-ep93xx.c|   4 +-
 drivers/pwm/pwm-imx.c   |   2 +-
 drivers/pwm/pwm-lpss-pci.c  |  35 
 drivers/pwm/pwm-lpss-platform.c |   7 +++
 drivers/pwm/pwm-lpss.c  | 117 +++-
 drivers/pwm/pwm-lpss.h  |   3 ++
 drivers/pwm/pwm-mxs.c   |   4 +-
 drivers/pwm/pwm-renesas-tpu.c   |   2 +-
 drivers/pwm/pwm-tegra.c |   6 +--
 drivers/pwm/pwm-tiecap.c|  10 ++--
 drivers/pwm/pwm-tiehrpwm.c  |   6 +--
 drivers/pwm/sysfs.c |   2 +-
 include/linux/pwm.h |   5 ++
 18 files changed, 206 insertions(+), 89 deletions(-)

-- 
1.9.1

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[linux-yocto] [PATCH 11/11] pwm: Add the pwm_is_enabled() helper

[Tan Jui Nee]

From: Boris Brezillon <boris.brezil...@free-electrons.com>

Some PWM drivers are testing the PWMF_ENABLED flag. Create a helper
function to hide the logic behind enabled test. This will allow us to
smoothly move from the current approach to an atomic PWM update
approach.

Signed-off-by: Boris Brezillon <boris.brezil...@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.red...@gmail.com>
(cherry picked from commit 5c31252c4a86dc591c23f1a951edd52ad791ef0e)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/pwm/core.c|  4 ++--
 drivers/pwm/pwm-atmel-tcb.c   |  2 +-
 drivers/pwm/pwm-atmel.c   |  6 +++---
 drivers/pwm/pwm-bcm-kona.c|  4 ++--
 drivers/pwm/pwm-ep93xx.c  |  4 ++--
 drivers/pwm/pwm-imx.c |  2 +-
 drivers/pwm/pwm-mxs.c |  4 ++--
 drivers/pwm/pwm-renesas-tpu.c |  2 +-
 drivers/pwm/pwm-tegra.c   |  6 +++---
 drivers/pwm/pwm-tiecap.c  | 10 +-
 drivers/pwm/pwm-tiehrpwm.c|  6 +++---
 drivers/pwm/sysfs.c   |  2 +-
 include/linux/pwm.h   |  5 +
 13 files changed, 31 insertions(+), 26 deletions(-)

diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index ba34c7d..049d41d 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -438,7 +438,7 @@ int pwm_set_polarity(struct pwm_device *pwm, enum 
pwm_polarity polarity)
if (!pwm->chip->ops->set_polarity)
return -ENOSYS;
 
-   if (test_bit(PWMF_ENABLED, >flags))
+   if (pwm_is_enabled(pwm))
return -EBUSY;
 
err = pwm->chip->ops->set_polarity(pwm->chip, pwm, polarity);
@@ -819,7 +819,7 @@ static void pwm_dbg_show(struct pwm_chip *chip, struct 
seq_file *s)
if (test_bit(PWMF_REQUESTED, >flags))
seq_puts(s, " requested");
 
-   if (test_bit(PWMF_ENABLED, >flags))
+   if (pwm_is_enabled(pwm))
seq_puts(s, " enabled");
 
seq_puts(s, "\n");
diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c
index d14e067..6da01b3 100644
--- a/drivers/pwm/pwm-atmel-tcb.c
+++ b/drivers/pwm/pwm-atmel-tcb.c
@@ -347,7 +347,7 @@ static int atmel_tcb_pwm_config(struct pwm_chip *chip, 
struct pwm_device *pwm,
tcbpwm->duty = duty;
 
/* If the PWM is enabled, call enable to apply the new conf */
-   if (test_bit(PWMF_ENABLED, >flags))
+   if (pwm_is_enabled(pwm))
atmel_tcb_pwm_enable(chip, pwm);
 
return 0;
diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
index a947c90..b3b294d 100644
--- a/drivers/pwm/pwm-atmel.c
+++ b/drivers/pwm/pwm-atmel.c
@@ -114,7 +114,7 @@ static int atmel_pwm_config(struct pwm_chip *chip, struct 
pwm_device *pwm,
u32 val;
int ret;
 
-   if (test_bit(PWMF_ENABLED, >flags) && (period_ns != pwm->period)) {
+   if (pwm_is_enabled(pwm) && (period_ns != pwm->period)) {
dev_err(chip->dev, "cannot change PWM period while enabled\n");
return -EBUSY;
}
@@ -176,7 +176,7 @@ static void atmel_pwm_config_v1(struct pwm_chip *chip, 
struct pwm_device *pwm,
 * If the PWM channel is enabled, only update CDTY by using the update
 * register, it needs to set bit 10 of CMR to 0
 */
-   if (test_bit(PWMF_ENABLED, >flags))
+   if (pwm_is_enabled(pwm))
return;
/*
 * If the PWM channel is disabled, write value to duty and period
@@ -191,7 +191,7 @@ static void atmel_pwm_config_v2(struct pwm_chip *chip, 
struct pwm_device *pwm,
 {
struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 
-   if (test_bit(PWMF_ENABLED, >flags)) {
+   if (pwm_is_enabled(pwm)) {
/*
 * If the PWM channel is enabled, using the duty update register
 * to update the value.
diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
index 02bc048..2a09fb3 100644
--- a/drivers/pwm/pwm-bcm-kona.c
+++ b/drivers/pwm/pwm-bcm-kona.c
@@ -134,7 +134,7 @@ static int kona_pwmc_config(struct pwm_chip *chip, struct 
pwm_device *pwm,
}
 
/* If the PWM channel is enabled, write the settings to the HW */
-   if (test_bit(PWMF_ENABLED, >flags)) {
+   if (pwm_is_enabled(pwm)) {
value = readl(kp->base + PRESCALE_OFFSET);
value &= ~PRESCALE_MASK(chan);
value |= prescale << PRESCALE_SHIFT(chan);
@@ -290,7 +290,7 @@ static int kona_pwmc_remove(struct platform_device *pdev)
unsigned int chan;
 
for (chan = 0; chan < kp->chip.npwm; chan++)
-   if (test_bit(PWMF_ENABLED, >chip.pwms[chan].flags))
+   if (pwm_is_enabled(>chip.pwms[chan]))
clk_disable_unprepare(kp->clk);
 
return pwmchip_remove

[linux-yocto] [PATCH 10/11] pwm: atmel: Fix incorrect CDTY value after disabling

[Tan Jui Nee]

From: Alexandre Belloni <alexandre.bell...@free-electrons.com>

pwm-leds calls .config() and .disable() in a row. This exhibits that it
may happen that the channel gets disabled before CDTY has been updated
with CUPD. The issue gets quite worse with long periods. So, ensure that
at least one period has past before disabling the channel by polling
ISR.

Signed-off-by: Alexandre Belloni <alexandre.bell...@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.fe...@atmel.com>
Tested-by: Gaël PORTAY <gael.por...@gmail.com>
Signed-off-by: Thierry Reding <thierry.red...@gmail.com>
(cherry picked from commit 472ac3dcac108d6648ee28616c6de1e3b0bb361f)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/pwm/pwm-atmel.c | 28 
 1 file changed, 28 insertions(+)

diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
index 89f9ca4..a947c90 100644
--- a/drivers/pwm/pwm-atmel.c
+++ b/drivers/pwm/pwm-atmel.c
@@ -8,9 +8,11 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -21,6 +23,7 @@
 #define PWM_ENA0x04
 #define PWM_DIS0x08
 #define PWM_SR 0x0C
+#define PWM_ISR0x1C
 /* Bit field in SR */
 #define PWM_SR_ALL_CH_ON   0x0F
 
@@ -60,6 +63,9 @@ struct atmel_pwm_chip {
struct clk *clk;
void __iomem *base;
 
+   unsigned int updated_pwms;
+   struct mutex isr_lock; /* ISR is cleared when read, ensure only one 
thread does that */
+
void (*config)(struct pwm_chip *chip, struct pwm_device *pwm,
   unsigned long dty, unsigned long prd);
 };
@@ -144,6 +150,10 @@ static int atmel_pwm_config(struct pwm_chip *chip, struct 
pwm_device *pwm,
val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
atmel_pwm->config(chip, pwm, dty, prd);
+   mutex_lock(_pwm->isr_lock);
+   atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
+   atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm);
+   mutex_unlock(_pwm->isr_lock);
 
clk_disable(atmel_pwm->clk);
return ret;
@@ -243,7 +253,22 @@ static int atmel_pwm_enable(struct pwm_chip *chip, struct 
pwm_device *pwm)
 static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
+   unsigned long timeout = jiffies + 2 * HZ;
+
+   /*
+* Wait for at least a complete period to have passed before disabling a
+* channel to be sure that CDTY has been updated
+*/
+   mutex_lock(_pwm->isr_lock);
+   atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
+
+   while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) &&
+  time_before(jiffies, timeout)) {
+   usleep_range(10, 100);
+   atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
+   }
 
+   mutex_unlock(_pwm->isr_lock);
atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
 
clk_disable(atmel_pwm->clk);
@@ -358,6 +383,8 @@ static int atmel_pwm_probe(struct platform_device *pdev)
atmel_pwm->chip.npwm = 4;
atmel_pwm->chip.can_sleep = true;
atmel_pwm->config = data->config;
+   atmel_pwm->updated_pwms = 0;
+   mutex_init(_pwm->isr_lock);
 
ret = pwmchip_add(_pwm->chip);
if (ret < 0) {
@@ -379,6 +406,7 @@ static int atmel_pwm_remove(struct platform_device *pdev)
struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
 
clk_unprepare(atmel_pwm->clk);
+   mutex_destroy(_pwm->isr_lock);
 
return pwmchip_remove(_pwm->chip);
 }
-- 
1.9.1

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[linux-yocto] [PATCH 07/11] pwm: lpss: Select core part automatically

[Tan Jui Nee]

From: Andy Shevchenko <andriy.shevche...@linux.intel.com>

We have two users of core part right now. Let them to select core part
automatically.

Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerb...@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.red...@gmail.com>
(cherry picked from commit 6f90a00c6667dce5651341f0629443cf7951b235)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/pwm/Kconfig | 15 +--
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 749198f..91a08a5 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -184,18 +184,12 @@ config PWM_LPC32XX
  will be called pwm-lpc32xx.
 
 config PWM_LPSS
-   tristate "Intel LPSS PWM support"
-   depends on X86
-   help
- Generic PWM framework driver for Intel Low Power Subsystem PWM
- controller.
-
- To compile this driver as a module, choose M here: the module
- will be called pwm-lpss.
+   tristate
 
 config PWM_LPSS_PCI
tristate "Intel LPSS PWM PCI driver"
-   depends on PWM_LPSS && PCI
+   depends on X86 && PCI
+   select PWM_LPSS
help
  The PCI driver for Intel Low Power Subsystem PWM controller.
 
@@ -204,7 +198,8 @@ config PWM_LPSS_PCI
 
 config PWM_LPSS_PLATFORM
tristate "Intel LPSS PWM platform driver"
-   depends on PWM_LPSS && ACPI
+   depends on X86 && ACPI
+   select PWM_LPSS
help
  The platform driver for Intel Low Power Subsystem PWM controller.
 
-- 
1.9.1

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[linux-yocto] [PATCH 06/11] pwm: lpss: Update PWM setting for Broxton

[Tan Jui Nee]

From: "qipeng.zha" <qipeng@intel.com>

For Broxton PWM controller, base unit is defined as 8-bit integer
and 14-bit fraction, so need to update base unit setting to output
wave with right frequency.

Signed-off-by: Qipeng Zha <qipeng@intel.com>
Acked-by: Mika Westerberg <mika.westerb...@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.red...@gmail.com>
(cherry picked from commit 883e4d070fe125028c0579d8666b820aadf458fb)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/pwm/pwm-lpss.c | 33 +++--
 drivers/pwm/pwm-lpss.h |  1 +
 2 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c
index 3f61c50..ebf8450 100644
--- a/drivers/pwm/pwm-lpss.c
+++ b/drivers/pwm/pwm-lpss.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "pwm-lpss.h"
 
@@ -24,11 +25,8 @@
 #define PWM_ENABLE BIT(31)
 #define PWM_SW_UPDATE  BIT(30)
 #define PWM_BASE_UNIT_SHIFT8
-#define PWM_BASE_UNIT_MASK 0x0000
 #define PWM_ON_TIME_DIV_MASK   0x00ff
 #define PWM_DIVISION_CORRECTION0x2
-#define PWM_LIMIT  (0x8000 + PWM_DIVISION_CORRECTION)
-#define NSECS_PER_SEC  10UL
 
 /* Size of each PWM register space if multiple */
 #define PWM_SIZE   0x400
@@ -36,13 +34,14 @@
 struct pwm_lpss_chip {
struct pwm_chip chip;
void __iomem *regs;
-   unsigned long clk_rate;
+   const struct pwm_lpss_boardinfo *info;
 };
 
 /* BayTrail */
 const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
.clk_rate = 2500,
.npwm = 1,
+   .base_unit_bits = 16,
 };
 EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
 
@@ -50,6 +49,7 @@ EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
 const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
.clk_rate = 1920,
.npwm = 1,
+   .base_unit_bits = 16,
 };
 EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
 
@@ -57,6 +57,7 @@ EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
 const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
.clk_rate = 1920,
.npwm = 4,
+   .base_unit_bits = 22,
 };
 EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info);
 
@@ -84,23 +85,25 @@ static int pwm_lpss_config(struct pwm_chip *chip, struct 
pwm_device *pwm,
 {
struct pwm_lpss_chip *lpwm = to_lpwm(chip);
u8 on_time_div;
-   unsigned long c;
-   unsigned long long base_unit, freq = NSECS_PER_SEC;
+   unsigned long c, base_unit_range;
+   unsigned long long base_unit, freq = NSEC_PER_SEC;
u32 ctrl;
 
do_div(freq, period_ns);
 
-   /* The equation is: base_unit = ((freq / c) * 65536) + correction */
-   base_unit = freq * 65536;
+   /*
+* The equation is:
+* base_unit = ((freq / c) * base_unit_range) + correction
+*/
+   base_unit_range = BIT(lpwm->info->base_unit_bits);
+   base_unit = freq * base_unit_range;
 
-   c = lpwm->clk_rate;
+   c = lpwm->info->clk_rate;
if (!c)
return -EINVAL;
 
do_div(base_unit, c);
base_unit += PWM_DIVISION_CORRECTION;
-   if (base_unit > PWM_LIMIT)
-   return -EINVAL;
 
if (duty_ns <= 0)
duty_ns = 1;
@@ -109,8 +112,10 @@ static int pwm_lpss_config(struct pwm_chip *chip, struct 
pwm_device *pwm,
pm_runtime_get_sync(chip->dev);
 
ctrl = pwm_lpss_read(pwm);
-   ctrl &= ~(PWM_BASE_UNIT_MASK | PWM_ON_TIME_DIV_MASK);
-   ctrl |= (u16) base_unit << PWM_BASE_UNIT_SHIFT;
+   ctrl &= ~PWM_ON_TIME_DIV_MASK;
+   ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
+   base_unit &= (base_unit_range - 1);
+   ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
ctrl |= on_time_div;
/* request PWM to update on next cycle */
ctrl |= PWM_SW_UPDATE;
@@ -155,7 +160,7 @@ struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, 
struct resource *r,
if (IS_ERR(lpwm->regs))
return ERR_CAST(lpwm->regs);
 
-   lpwm->clk_rate = info->clk_rate;
+   lpwm->info = info;
lpwm->chip.dev = dev;
lpwm->chip.ops = _lpss_ops;
lpwm->chip.base = -1;
diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h
index e8cf337..04766e0 100644
--- a/drivers/pwm/pwm-lpss.h
+++ b/drivers/pwm/pwm-lpss.h
@@ -21,6 +21,7 @@ struct pwm_lpss_chip;
 struct pwm_lpss_boardinfo {
unsigned long clk_rate;
unsigned int npwm;
+   unsigned long base_unit_bits;
 };
 
 extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info;
-- 
1.9.1

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[linux-yocto] [PATCH 03/11] pwm: lpss: Add more Intel Broxton IDs

[Tan Jui Nee]

From: Mika Westerberg <mika.westerb...@linux.intel.com>

Add more Intel Broxton ACPI and PCI IDs to the driver supported devices
list.

Signed-off-by: Mika Westerberg <mika.westerb...@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.red...@gmail.com>
(cherry picked from commit 03f00e5311d5d0d3ac716121865cb967259980ca)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/pwm/pwm-lpss-pci.c  | 1 +
 drivers/pwm/pwm-lpss-platform.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/pwm/pwm-lpss-pci.c b/drivers/pwm/pwm-lpss-pci.c
index 6432a0b..c15bc6d 100644
--- a/drivers/pwm/pwm-lpss-pci.c
+++ b/drivers/pwm/pwm-lpss-pci.c
@@ -50,6 +50,7 @@ static const struct pci_device_id pwm_lpss_pci_ids[] = {
{ PCI_VDEVICE(INTEL, 0x1ac8), (unsigned long)_lpss_bxt_info},
{ PCI_VDEVICE(INTEL, 0x2288), (unsigned long)_lpss_bsw_info},
{ PCI_VDEVICE(INTEL, 0x2289), (unsigned long)_lpss_bsw_info},
+   { PCI_VDEVICE(INTEL, 0x5ac8), (unsigned long)_lpss_bxt_info},
{ },
 };
 MODULE_DEVICE_TABLE(pci, pwm_lpss_pci_ids);
diff --git a/drivers/pwm/pwm-lpss-platform.c b/drivers/pwm/pwm-lpss-platform.c
index 18a9c88..a914aac 100644
--- a/drivers/pwm/pwm-lpss-platform.c
+++ b/drivers/pwm/pwm-lpss-platform.c
@@ -49,6 +49,7 @@ static int pwm_lpss_remove_platform(struct platform_device 
*pdev)
 static const struct acpi_device_id pwm_lpss_acpi_match[] = {
{ "80860F09", (unsigned long)_lpss_byt_info },
{ "80862288", (unsigned long)_lpss_bsw_info },
+   { "80865AC8", (unsigned long)_lpss_bxt_info },
{ },
 };
 MODULE_DEVICE_TABLE(acpi, pwm_lpss_acpi_match);
-- 
1.9.1

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[linux-yocto] [PATCH 9/9] i2c: i801: Add support for Intel Broxton

[Tan Jui Nee]

From: Jarkko Nikula <jarkko.nik...@linux.intel.com>

This patch adds the SMBUS PCI ID of Intel Broxton.

Signed-off-by: Jarkko Nikula <jarkko.nik...@linux.intel.com>
Signed-off-by: Wolfram Sang <w...@the-dreams.de>
(cherry picked from commit dd77f423e516293c37c2370b44fd700900409c48)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/i2c/busses/i2c-i801.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 47c2ddf..d8219bc 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -61,6 +61,7 @@
  * Sunrise Point-H (PCH)   0xa123  32  hardyes yes yes
  * Sunrise Point-LP (PCH)  0x9d23  32  hardyes yes yes
  * DNV (SOC)   0x19df  32  hardyes yes yes
+ * Broxton (SOC)   0x5ad4  32  hardyes yes yes
  *
  * Features supported by this driver:
  * Software PECno
@@ -204,6 +205,7 @@
 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS   0xa123
 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS  0x9d23
 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS  0x19df
+#define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS  0x5ad4
 
 struct i801_mux_config {
char *gpio_chip;
@@ -866,6 +868,7 @@ static const struct pci_device_id i801_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 
PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 
PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
+   { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
{ 0, }
 };
 
-- 
1.9.1

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[linux-yocto] [PATCH 6/9] mfd: watchdog: iTCO_wdt: Expose watchdog properties using platform data

[Tan Jui Nee]

From: Matt Fleming <matt.flem...@intel.com>

Intel Sunrisepoint (Skylake PCH) has the iTCO watchdog accessible across
the SMBus, unlike previous generations of PCH/ICH where it was on the
LPC bus. Because it's on the SMBus, it doesn't make sense to pass around
a 'struct lpc_ich_info', and leaking the type of bus into the iTCO
watchdog driver is kind of backwards anyway.

This change introduces a new 'struct itco_wdt_platform_data' for use
inside the iTCO watchdog driver and by the upcoming Intel Sunrisepoint
code, which neatly avoids having to include lpc_ich headers in the i801
i2c driver.

This change is overdue because lpc_ich_info has already found its way
into other TCO watchdog users, notably the intel_pmc_ipc driver where
the watchdog actually isn't on the LPC bus as far as I can see.

A simple translation layer is provided for converting from the existing
'struct lpc_ich_info' inside the lpc_ich mfd driver.

Signed-off-by: Matt Fleming <matt.flem...@intel.com>
Acked-by: Darren Hart <dvh...@linux.intel.com> [drivers/x86 refactoring]
Reviewed-by: Guenter Roeck <li...@roeck-us.net>
Signed-off-by: Lee Jones <lee.jo...@linaro.org>
(cherry picked from commit 420b54de25828c45f3fc1f12d52d9657f5e90a53)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/mfd/lpc_ich.c  | 32 +---
 drivers/platform/x86/intel_pmc_ipc.c   |  9 -
 drivers/watchdog/iTCO_wdt.c| 11 +--
 include/linux/mfd/lpc_ich.h|  6 --
 include/linux/platform_data/itco_wdt.h | 19 +++
 5 files changed, 57 insertions(+), 20 deletions(-)
 create mode 100644 include/linux/platform_data/itco_wdt.h

diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c
index 8de3439..c5a9a08 100644
--- a/drivers/mfd/lpc_ich.c
+++ b/drivers/mfd/lpc_ich.c
@@ -66,6 +66,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define ACPIBASE   0x40
 #define ACPIBASE_GPE_OFF   0x28
@@ -835,9 +836,31 @@ static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
priv->actrl_pbase_save = reg_save;
 }
 
-static void lpc_ich_finalize_cell(struct pci_dev *dev, struct mfd_cell *cell)
+static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev)
 {
+   struct itco_wdt_platform_data *pdata;
struct lpc_ich_priv *priv = pci_get_drvdata(dev);
+   struct lpc_ich_info *info;
+   struct mfd_cell *cell = _ich_cells[LPC_WDT];
+
+   pdata = devm_kzalloc(>dev, sizeof(*pdata), GFP_KERNEL);
+   if (!pdata)
+   return -ENOMEM;
+
+   info = _chipset_info[priv->chipset];
+
+   pdata->version = info->iTCO_version;
+   strlcpy(pdata->name, info->name, sizeof(pdata->name));
+
+   cell->platform_data = pdata;
+   cell->pdata_size = sizeof(*pdata);
+   return 0;
+}
+
+static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev)
+{
+   struct lpc_ich_priv *priv = pci_get_drvdata(dev);
+   struct mfd_cell *cell = _ich_cells[LPC_GPIO];
 
cell->platform_data = _chipset_info[priv->chipset];
cell->pdata_size = sizeof(struct lpc_ich_info);
@@ -933,7 +956,7 @@ gpe0_done:
lpc_chipset_info[priv->chipset].use_gpio = ret;
lpc_ich_enable_gpio_space(dev);
 
-   lpc_ich_finalize_cell(dev, _ich_cells[LPC_GPIO]);
+   lpc_ich_finalize_gpio_cell(dev);
ret = mfd_add_devices(>dev, PLATFORM_DEVID_AUTO,
  _ich_cells[LPC_GPIO], 1, NULL, 0, NULL);
 
@@ -1007,7 +1030,10 @@ static int lpc_ich_init_wdt(struct pci_dev *dev)
res->end = base_addr + ACPIBASE_PMC_END;
}
 
-   lpc_ich_finalize_cell(dev, _ich_cells[LPC_WDT]);
+   ret = lpc_ich_finalize_wdt_cell(dev);
+   if (ret)
+   goto wdt_done;
+
ret = mfd_add_devices(>dev, PLATFORM_DEVID_AUTO,
  _ich_cells[LPC_WDT], 1, NULL, 0, NULL);
 
diff --git a/drivers/platform/x86/intel_pmc_ipc.c 
b/drivers/platform/x86/intel_pmc_ipc.c
index 105cfff..28b2a12 100644
--- a/drivers/platform/x86/intel_pmc_ipc.c
+++ b/drivers/platform/x86/intel_pmc_ipc.c
@@ -33,7 +33,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 /*
  * IPC registers
@@ -473,9 +473,9 @@ static struct resource tco_res[] = {
},
 };
 
-static struct lpc_ich_info tco_info = {
+static struct itco_wdt_platform_data tco_info = {
.name = "Apollo Lake SoC",
-   .iTCO_version = 3,
+   .version = 3,
 };
 
 static int ipc_create_punit_device(void)
@@ -552,8 +552,7 @@ static int ipc_create_tco_device(void)
goto err;
}
 
-   ret = platform_device_add_data(pdev, _info,
-  sizeof(struct lpc_ich_info));
+   ret = platform_device_add_data(pdev, _info, sizeof(tco_info));
if (ret) {
dev_err(ipcdev.dev, "Failed to add tco platform data\n");

[linux-yocto] [PATCH 8/9] i2c: i801: Add support for Intel DNV

[Tan Jui Nee]

From: Mika Westerberg <mika.westerb...@linux.intel.com>

Intel DNV SoC has the same legacy SMBus host controller than Intel
Sunrisepoint PCH. It also has same iTCO watchdog on the bus.

Add DNV PCI ID to the list of supported devices.

Signed-off-by: Mika Westerberg <mika.westerb...@linux.intel.com>
Signed-off-by: Wolfram Sang <w...@the-dreams.de>
(cherry picked from commit 84d7f2ebd70d36e9d83e0973d2f4dac56a671f4f)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/i2c/busses/i2c-i801.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index eaef9bc..47c2ddf 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -60,6 +60,7 @@
  * BayTrail (SOC)  0x0f12  32  hardyes yes yes
  * Sunrise Point-H (PCH)   0xa123  32  hardyes yes yes
  * Sunrise Point-LP (PCH)  0x9d23  32  hardyes yes yes
+ * DNV (SOC)   0x19df  32  hardyes yes yes
  *
  * Features supported by this driver:
  * Software PECno
@@ -202,6 +203,7 @@
 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS  0x9ca2
 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS   0xa123
 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS  0x9d23
+#define PCI_DEVICE_ID_INTEL_DNV_SMBUS  0x19df
 
 struct i801_mux_config {
char *gpio_chip;
@@ -863,6 +865,7 @@ static const struct pci_device_id i801_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 
PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 
PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
+   { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
{ 0, }
 };
 
@@ -1256,6 +1259,7 @@ static int i801_probe(struct pci_dev *dev, const struct 
pci_device_id *id)
switch (dev->device) {
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
+   case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
priv->features |= FEATURE_I2C_BLOCK_READ;
priv->features |= FEATURE_IRQ;
priv->features |= FEATURE_SMBUS_PEC;
-- 
1.9.1

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[linux-yocto] [PATCH 5/9] intel_pmc_ipc: Update kerneldoc formatting

[Tan Jui Nee]

From: "qipeng.zha" <qipeng@intel.com>

Update kerneldoc formatting per Documentation/kernel-dec-nano-HOWTO.txt.

Signed-off-by: qipeng.zha <qipeng@intel.com>
Signed-off-by: Darren Hart <dvh...@linux.intel.com>
(cherry picked from commit 02941007f59ce015233d4c0f7047776960bf0c17)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 arch/x86/include/asm/intel_pmc_ipc.h | 27 -
 drivers/platform/x86/intel_pmc_ipc.c | 57 ++--
 2 files changed, 35 insertions(+), 49 deletions(-)

diff --git a/arch/x86/include/asm/intel_pmc_ipc.h 
b/arch/x86/include/asm/intel_pmc_ipc.h
index 200ec2e..cd0310e 100644
--- a/arch/x86/include/asm/intel_pmc_ipc.h
+++ b/arch/x86/include/asm/intel_pmc_ipc.h
@@ -25,36 +25,9 @@
 
 #if IS_ENABLED(CONFIG_INTEL_PMC_IPC)
 
-/*
- * intel_pmc_ipc_simple_command
- * @cmd: command
- * @sub: sub type
- */
 int intel_pmc_ipc_simple_command(int cmd, int sub);
-
-/*
- * intel_pmc_ipc_raw_cmd
- * @cmd: command
- * @sub: sub type
- * @in: input data
- * @inlen: input length in bytes
- * @out: output data
- * @outlen: output length in dwords
- * @sptr: data writing to SPTR register
- * @dptr: data writing to DPTR register
- */
 int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
u32 *out, u32 outlen, u32 dptr, u32 sptr);
-
-/*
- * intel_pmc_ipc_command
- * @cmd: command
- * @sub: sub type
- * @in: input data
- * @inlen: input length in bytes
- * @out: output data
- * @outlen: output length in dwords
- */
 int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
u32 *out, u32 outlen);
 
diff --git a/drivers/platform/x86/intel_pmc_ipc.c 
b/drivers/platform/x86/intel_pmc_ipc.c
index 69d43b8..105cfff 100644
--- a/drivers/platform/x86/intel_pmc_ipc.c
+++ b/drivers/platform/x86/intel_pmc_ipc.c
@@ -210,10 +210,15 @@ static int intel_pmc_ipc_check_status(void)
return ret;
 }
 
-/*
- * intel_pmc_ipc_simple_command
- * @cmd: command
- * @sub: sub type
+/**
+ * intel_pmc_ipc_simple_command() - Simple IPC command
+ * @cmd:   IPC command code.
+ * @sub:   IPC command sub type.
+ *
+ * Send a simple IPC command to PMC when don't need to specify
+ * input/output data and source/dest pointers.
+ *
+ * Return: an IPC error code or 0 on success.
  */
 int intel_pmc_ipc_simple_command(int cmd, int sub)
 {
@@ -232,16 +237,20 @@ int intel_pmc_ipc_simple_command(int cmd, int sub)
 }
 EXPORT_SYMBOL_GPL(intel_pmc_ipc_simple_command);
 
-/*
- * intel_pmc_ipc_raw_cmd
- * @cmd: command
- * @sub: sub type
- * @in: input data
- * @inlen: input length in bytes
- * @out: output data
- * @outlen: output length in dwords
- * @sptr: data writing to SPTR register
- * @dptr: data writing to DPTR register
+/**
+ * intel_pmc_ipc_raw_cmd() - IPC command with data and pointers
+ * @cmd:   IPC command code.
+ * @sub:   IPC command sub type.
+ * @in:input data of this IPC command.
+ * @inlen: input data length in bytes.
+ * @out:   output data of this IPC command.
+ * @outlen:output data length in dwords.
+ * @sptr:  data writing to SPTR register.
+ * @dptr:  data writing to DPTR register.
+ *
+ * Send an IPC command to PMC with input/output data and source/dest pointers.
+ *
+ * Return: an IPC error code or 0 on success.
  */
 int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, u32 *out,
  u32 outlen, u32 dptr, u32 sptr)
@@ -278,14 +287,18 @@ int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 
inlen, u32 *out,
 }
 EXPORT_SYMBOL_GPL(intel_pmc_ipc_raw_cmd);
 
-/*
- * intel_pmc_ipc_command
- * @cmd: command
- * @sub: sub type
- * @in: input data
- * @inlen: input length in bytes
- * @out: output data
- * @outlen: output length in dwords
+/**
+ * intel_pmc_ipc_command() -  IPC command with input/output data
+ * @cmd:   IPC command code.
+ * @sub:   IPC command sub type.
+ * @in:input data of this IPC command.
+ * @inlen: input data length in bytes.
+ * @out:   output data of this IPC command.
+ * @outlen:output data length in dwords.
+ *
+ * Send an IPC command to PMC with input/output data.
+ *
+ * Return: an IPC error code or 0 on success.
  */
 int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
  u32 *out, u32 outlen)
-- 
1.9.1

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[linux-yocto] [PATCH 7/9] watchdog: iTCO_wdt: Add support for TCO on Intel Sunrisepoint

[Tan Jui Nee]

From: Matt Fleming <matt.flem...@intel.com>

The revision of the watchdog hardware in Sunrisepoint necessitates a new
"version" inside the TCO watchdog driver because some of the register
layouts have changed.

Also update the Kconfig entry to select both the LPC and SMBus drivers
since the TCO device is on the SMBus in Sunrisepoint.

Signed-off-by: Matt Fleming <matt.flem...@intel.com>
Reviewed-by: Guenter Roeck <li...@roeck-us.net>
Signed-off-by: Lee Jones <lee.jo...@linaro.org>
(cherry picked from commit 2a7a0e9bf7b32e838d873226808ab8a6c00148f7)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/watchdog/Kconfig|  3 +-
 drivers/watchdog/iTCO_wdt.c | 71 -
 2 files changed, 46 insertions(+), 28 deletions(-)

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index e5e7c55..020fb8a 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -753,7 +753,8 @@ config ITCO_WDT
tristate "Intel TCO Timer/Watchdog"
depends on (X86 || IA64) && PCI
select WATCHDOG_CORE
-   select LPC_ICH
+   select LPC_ICH if !EXPERT
+   select I2C_I801 if !EXPERT
---help---
  Hardware driver for the intel TCO timer based watchdog devices.
  These drivers are included in the Intel 82801 I/O Controller
diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c
index a94401b..0acc6c5 100644
--- a/drivers/watchdog/iTCO_wdt.c
+++ b/drivers/watchdog/iTCO_wdt.c
@@ -145,59 +145,67 @@ static inline unsigned int ticks_to_seconds(int ticks)
return iTCO_wdt_private.iTCO_version == 3 ? ticks : (ticks * 6) / 10;
 }
 
+static inline u32 no_reboot_bit(void)
+{
+   u32 enable_bit;
+
+   switch (iTCO_wdt_private.iTCO_version) {
+   case 3:
+   enable_bit = 0x0010;
+   break;
+   case 2:
+   enable_bit = 0x0020;
+   break;
+   case 4:
+   case 1:
+   default:
+   enable_bit = 0x0002;
+   break;
+   }
+
+   return enable_bit;
+}
+
 static void iTCO_wdt_set_NO_REBOOT_bit(void)
 {
u32 val32;
 
/* Set the NO_REBOOT bit: this disables reboots */
-   if (iTCO_wdt_private.iTCO_version == 3) {
-   val32 = readl(iTCO_wdt_private.gcs_pmc);
-   val32 |= 0x0010;
-   writel(val32, iTCO_wdt_private.gcs_pmc);
-   } else if (iTCO_wdt_private.iTCO_version == 2) {
+   if (iTCO_wdt_private.iTCO_version >= 2) {
val32 = readl(iTCO_wdt_private.gcs_pmc);
-   val32 |= 0x0020;
+   val32 |= no_reboot_bit();
writel(val32, iTCO_wdt_private.gcs_pmc);
} else if (iTCO_wdt_private.iTCO_version == 1) {
pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, );
-   val32 |= 0x0002;
+   val32 |= no_reboot_bit();
pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
}
 }
 
 static int iTCO_wdt_unset_NO_REBOOT_bit(void)
 {
-   int ret = 0;
-   u32 val32;
+   u32 enable_bit = no_reboot_bit();
+   u32 val32 = 0;
 
/* Unset the NO_REBOOT bit: this enables reboots */
-   if (iTCO_wdt_private.iTCO_version == 3) {
-   val32 = readl(iTCO_wdt_private.gcs_pmc);
-   val32 &= 0xffef;
-   writel(val32, iTCO_wdt_private.gcs_pmc);
-
-   val32 = readl(iTCO_wdt_private.gcs_pmc);
-   if (val32 & 0x0010)
-   ret = -EIO;
-   } else if (iTCO_wdt_private.iTCO_version == 2) {
+   if (iTCO_wdt_private.iTCO_version >= 2) {
val32 = readl(iTCO_wdt_private.gcs_pmc);
-   val32 &= 0xffdf;
+   val32 &= ~enable_bit;
writel(val32, iTCO_wdt_private.gcs_pmc);
 
val32 = readl(iTCO_wdt_private.gcs_pmc);
-   if (val32 & 0x0020)
-   ret = -EIO;
} else if (iTCO_wdt_private.iTCO_version == 1) {
pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, );
-   val32 &= 0xfffd;
+   val32 &= ~enable_bit;
pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
 
pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, );
-   if (val32 & 0x0002)
-   ret = -EIO;
}
 
-   return ret; /* returns: 0 = OK, -EIO = Error */
+   if (val32 & enable_bit)
+   return -EIO;
+
+   return 0;
 }
 
 static int iTCO_wdt_start(struct watchdog_device *wd_dev)
@@ -503,12 +511,21 @@ static int iTCO_wdt_probe(struct platform_device *dev)
pdata->name, pdata->version, (u64)TCOBASE);
 
/* Clear out the (probably old) status */
-   if (iTCO_wdt_private.iTCO_version == 3

[linux-yocto] [PATCH 3/9] intel_pmc_ipc: Add Intel Apollo Lake PMC IPC driver

[Tan Jui Nee]

From: "qipeng.zha" <qipeng@intel.com>

This driver provides support for PMC control on Apollo Lake platforms.
The PMC is an ARC processor which defines some IPC commands for
communication with other entities in the CPU.

Signed-off-by: qipeng.zha <qipeng@intel.com>
[fengguang...@intel.com: Fix Sparse and Cocinelle warnings]
Signed-off-by: Fengguang Wu <fengguang...@intel.com>
Signed-off-by: Darren Hart <dvh...@linux.intel.com>

(cherry picked from commit 0a8b83530b6f67b9a50bd7937d57a5deea187b5b)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 MAINTAINERS  |   7 +
 arch/x86/include/asm/intel_pmc_ipc.h |  82 
 drivers/platform/x86/Kconfig |   7 +
 drivers/platform/x86/Makefile|   1 +
 drivers/platform/x86/intel_pmc_ipc.c | 767 +++
 5 files changed, 864 insertions(+)
 create mode 100644 arch/x86/include/asm/intel_pmc_ipc.h
 create mode 100644 drivers/platform/x86/intel_pmc_ipc.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 632e406..ffc0edb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5295,6 +5295,13 @@ F:   include/uapi/linux/mei.h
 F: drivers/misc/mei/*
 F: Documentation/misc-devices/mei/*
 
+INTEL PMC IPC DRIVER
+M: Zha Qipeng<qipeng@intel.com>
+L: platform-driver-...@vger.kernel.org
+S: Maintained
+F: drivers/platform/x86/intel_pmc_ipc.c
+F: arch/x86/include/asm/intel_pmc_ipc.h
+
 IOC3 ETHERNET DRIVER
 M: Ralf Baechle <r...@linux-mips.org>
 L: linux-m...@linux-mips.org
diff --git a/arch/x86/include/asm/intel_pmc_ipc.h 
b/arch/x86/include/asm/intel_pmc_ipc.h
new file mode 100644
index 000..200ec2e
--- /dev/null
+++ b/arch/x86/include/asm/intel_pmc_ipc.h
@@ -0,0 +1,82 @@
+#ifndef _ASM_X86_INTEL_PMC_IPC_H_
+#define  _ASM_X86_INTEL_PMC_IPC_H_
+
+/* Commands */
+#define PMC_IPC_PMIC_ACCESS0xFF
+#definePMC_IPC_PMIC_ACCESS_READ0x0
+#definePMC_IPC_PMIC_ACCESS_WRITE   0x1
+#define PMC_IPC_USB_PWR_CTRL   0xF0
+#define PMC_IPC_PMIC_BLACKLIST_SEL 0xEF
+#define PMC_IPC_PHY_CONFIG 0xEE
+#define PMC_IPC_NORTHPEAK_CTRL 0xED
+#define PMC_IPC_PM_DEBUG   0xEC
+#define PMC_IPC_PMC_TELEMTRY   0xEB
+#define PMC_IPC_PMC_FW_MSG_CTRL0xEA
+
+/* IPC return code */
+#define IPC_ERR_NONE   0
+#define IPC_ERR_CMD_NOT_SUPPORTED  1
+#define IPC_ERR_CMD_NOT_SERVICED   2
+#define IPC_ERR_UNABLE_TO_SERVICE  3
+#define IPC_ERR_CMD_INVALID4
+#define IPC_ERR_CMD_FAILED 5
+#define IPC_ERR_EMSECURITY 6
+#define IPC_ERR_UNSIGNEDKERNEL 7
+
+#if IS_ENABLED(CONFIG_INTEL_PMC_IPC)
+
+/*
+ * intel_pmc_ipc_simple_command
+ * @cmd: command
+ * @sub: sub type
+ */
+int intel_pmc_ipc_simple_command(int cmd, int sub);
+
+/*
+ * intel_pmc_ipc_raw_cmd
+ * @cmd: command
+ * @sub: sub type
+ * @in: input data
+ * @inlen: input length in bytes
+ * @out: output data
+ * @outlen: output length in dwords
+ * @sptr: data writing to SPTR register
+ * @dptr: data writing to DPTR register
+ */
+int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
+   u32 *out, u32 outlen, u32 dptr, u32 sptr);
+
+/*
+ * intel_pmc_ipc_command
+ * @cmd: command
+ * @sub: sub type
+ * @in: input data
+ * @inlen: input length in bytes
+ * @out: output data
+ * @outlen: output length in dwords
+ */
+int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
+   u32 *out, u32 outlen);
+
+#else
+
+static inline int intel_pmc_ipc_simple_command(int cmd, int sub)
+{
+   return -EINVAL;
+}
+
+static inline int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
+   u32 *out, u32 outlen, u32 dptr, u32 sptr)
+{
+   return -EINVAL;
+}
+
+static inline int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
+   u32 *out, u32 outlen)
+{
+   return -EINVAL;
+}
+
+#endif /*CONFIG_INTEL_PMC_IPC*/
+
+#endif
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index f9f205c..a1e048e 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -885,4 +885,11 @@ config PVPANIC
  a paravirtualized device provided by QEMU; it lets a virtual machine
  (guest) communicate panic events to the host.
 
+config INTEL_PMC_IPC
+   tristate "Intel PMC IPC Driver"
+   ---help---
+   This driver provides support for PMC control on some Intel platforms.
+   The PMC is an ARC processor which defines IPC commands for communication
+   with other entities in the CPU.
+
 endif # X86_PLATFORM_DEVICES
diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile
index f82232b..1051372 100644
--- a/drivers/platform/x86/Makefile
+++ b/drivers/platform/x86/Makefile
@@ -58,3 +58,4 @@ obj-$(CONFIG_INTEL_SMARTCONNECT)  += intel-smartconnect.o
 
 obj-$(CONF

[linux-yocto] [PATCH 0/9] Backport SMBus/iTCO patches from mainline kernel into linux-yocto-4.1

[Tan Jui Nee]

Hi Bruce,

The patches are to backport Intel Broxton and Denverton
patches that are available in the mainline Linux kernel.

The following patches are to enable SMBus and iTCO watchdog
drivers support for Intel Broxton and Denverton.
i2c: i801: Create iTCO device on newer Intel PCHs
mfd: watchdog: iTCO_wdt: Expose watchdog properties using platform data
watchdog: iTCO_wdt: Add support for TCO on Intel Sunrisepoint
i2c: i801: Add support for Intel Broxton

The rest of the patches are dependency patches, to ensure
the above patches applied cleanly to the branch.

The patches are targeted to merge into linux-yocto-4.1 on
standard/base branch.

Please review and provide feedback if any.

Thanks and best regards,
Juinee

Jarkko Nikula (1):
  i2c: i801: Add support for Intel Broxton

Matt Fleming (2):
  mfd: watchdog: iTCO_wdt: Expose watchdog properties using platform
data
  watchdog: iTCO_wdt: Add support for TCO on Intel Sunrisepoint

Mika Westerberg (3):
  i2c: i801: Create iTCO device on newer Intel PCHs
  mfd: lpc_ich: Assign subdevice ids automatically
  i2c: i801: Add support for Intel DNV

qipeng.zha (3):
  intel_pmc_ipc: Add Intel Apollo Lake PMC IPC driver
  intel_pmc_ipc: Fix compiler casting warnings
  intel_pmc_ipc: Update kerneldoc formatting

 MAINTAINERS|   7 +
 arch/x86/include/asm/intel_pmc_ipc.h   |  55 +++
 drivers/i2c/busses/i2c-i801.c  | 127 +-
 drivers/mfd/lpc_ich.c  |  40 +-
 drivers/platform/x86/Kconfig   |   7 +
 drivers/platform/x86/Makefile  |   1 +
 drivers/platform/x86/intel_pmc_ipc.c   | 779 +
 drivers/watchdog/Kconfig   |   3 +-
 drivers/watchdog/iTCO_wdt.c|  82 ++--
 include/linux/mfd/lpc_ich.h|   6 -
 include/linux/platform_data/itco_wdt.h |  19 +
 11 files changed, 1078 insertions(+), 48 deletions(-)
 create mode 100644 arch/x86/include/asm/intel_pmc_ipc.h
 create mode 100644 drivers/platform/x86/intel_pmc_ipc.c
 create mode 100644 include/linux/platform_data/itco_wdt.h

-- 
1.9.1

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [PATCH 1/9] i2c: i801: Create iTCO device on newer Intel PCHs

[Tan Jui Nee]

From: Mika Westerberg <mika.westerb...@linux.intel.com>

Starting from Intel Sunrisepoint (Skylake PCH) the iTCO watchdog resources
have been moved to reside under the i801 SMBus host controller whereas
previously they were under the LPC device.

In order to support the iTCO watchdog on newer PCHs we need to create the
platform device here in the SMBus driver and pass all known resources using
platform data.

Signed-off-by: Mika Westerberg <mika.westerb...@linux.intel.com>
Signed-off-by: Matt Fleming <matt.flem...@intel.com>
Reviewed-by: Guenter Roeck <li...@roeck-us.net>
Acked-by: Wolfram Sang <w...@the-dreams.de>
Signed-off-by: Lee Jones <lee.jo...@linaro.org>
(cherry picked from commit 9424693035a57961a8eb09e96aab315a7096535d)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/i2c/busses/i2c-i801.c | 120 +-
 1 file changed, 119 insertions(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 5ecbb3f..eaef9bc 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -88,12 +88,13 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
defined CONFIG_DMI
 #include 
 #include 
-#include 
 #endif
 
 /* I801 SMBus address offsets */
@@ -113,6 +114,16 @@
 #define SMBPCICTL  0x004
 #define SMBPCISTS  0x006
 #define SMBHSTCFG  0x040
+#define TCOBASE0x050
+#define TCOCTL 0x054
+
+#define ACPIBASE   0x040
+#define ACPIBASE_SMI_OFF   0x030
+#define ACPICTRL   0x044
+#define ACPICTRL_EN0x080
+
+#define SBREG_BAR  0x10
+#define SBREG_SMBCTRL  0xc6000c
 
 /* Host status bits for SMBPCISTS */
 #define SMBPCISTS_INTS 0x08
@@ -125,6 +136,9 @@
 #define SMBHSTCFG_SMB_SMI_EN   2
 #define SMBHSTCFG_I2C_EN   4
 
+/* TCO configuration bits for TCOCTL */
+#define TCOCTL_EN  0x0100
+
 /* Auxiliary control register bits, ICH4+ only */
 #define SMBAUXCTL_CRC  1
 #define SMBAUXCTL_E32B 2
@@ -221,6 +235,7 @@ struct i801_priv {
const struct i801_mux_config *mux_drvdata;
struct platform_device *mux_pdev;
 #endif
+   struct platform_device *tco_pdev;
 };
 
 #define FEATURE_SMBUS_PEC  (1 << 0)
@@ -230,6 +245,7 @@ struct i801_priv {
 #define FEATURE_IRQ(1 << 4)
 /* Not really a feature, but it's convenient to handle it as such */
 #define FEATURE_IDF(1 << 15)
+#define FEATURE_TCO(1 << 16)
 
 static const char *i801_feature_names[] = {
"SMBus PEC",
@@ -1132,6 +1148,95 @@ static inline unsigned int i801_get_adapter_class(struct 
i801_priv *priv)
 }
 #endif
 
+static const struct itco_wdt_platform_data tco_platform_data = {
+   .name = "Intel PCH",
+   .version = 4,
+};
+
+static DEFINE_SPINLOCK(p2sb_spinlock);
+
+static void i801_add_tco(struct i801_priv *priv)
+{
+   struct pci_dev *pci_dev = priv->pci_dev;
+   struct resource tco_res[3], *res;
+   struct platform_device *pdev;
+   unsigned int devfn;
+   u32 tco_base, tco_ctl;
+   u32 base_addr, ctrl_val;
+   u64 base64_addr;
+
+   if (!(priv->features & FEATURE_TCO))
+   return;
+
+   pci_read_config_dword(pci_dev, TCOBASE, _base);
+   pci_read_config_dword(pci_dev, TCOCTL, _ctl);
+   if (!(tco_ctl & TCOCTL_EN))
+   return;
+
+   memset(tco_res, 0, sizeof(tco_res));
+
+   res = _res[ICH_RES_IO_TCO];
+   res->start = tco_base & ~1;
+   res->end = res->start + 32 - 1;
+   res->flags = IORESOURCE_IO;
+
+   /*
+* Power Management registers.
+*/
+   devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
+   pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, _addr);
+
+   res = _res[ICH_RES_IO_SMI];
+   res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
+   res->end = res->start + 3;
+   res->flags = IORESOURCE_IO;
+
+   /*
+* Enable the ACPI I/O space.
+*/
+   pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, _val);
+   ctrl_val |= ACPICTRL_EN;
+   pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
+
+   /*
+* We must access the NO_REBOOT bit over the Primary to Sideband
+* bridge (P2SB). The BIOS prevents the P2SB device from being
+* enumerated by the PCI subsystem, so we need to unhide/hide it
+* to lookup the P2SB BAR.
+*/
+   spin_lock(_spinlock);
+
+   devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
+
+   /* Unhide the P2SB device */
+   pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
+
+   pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_

[linux-yocto] [PATCH 2/6] pinctrl: make pinctrl_register() return proper error code

[Tan Jui Nee]

From: Masahiro Yamada <yamada.masah...@socionext.com>

Currently, pinctrl_register() just returns NULL on error, so the
callers can not know the exact reason of the failure.

Some of the pinctrl drivers return -EINVAL, some -ENODEV, and some
-ENOMEM on error of pinctrl_register(), although the error code
might be different from the real cause of the error.

This commit reworks pinctrl_register() to return the appropriate
error code and modifies all of the pinctrl drivers to use IS_ERR()
for the error checking and PTR_ERR() for getting the error code.

Signed-off-by: Masahiro Yamada <yamada.masah...@socionext.com>
Acked-by: Patrice Chotard <patrice.chot...@st.com>
Acked-by: Thierry Reding <tred...@nvidia.com>
Acked-by: Heiko Stuebner <he...@sntech.de>
Tested-by: Mika Westerberg <mika.westerb...@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerb...@linux.intel.com>
Acked-by: Lee Jones <l...@kernel.org>
Acked-by: Sören Brinkmann <soren.brinkm...@xilinx.com>
Acked-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
Acked-by: Ray Jui <r...@broadcom.com>
Acked-by: Antoine Tenart <antoine.ten...@free-electrons.com>
Acked-by: Hongzhou Yang <hongzhou.y...@mediatek.com>
Acked-by: Wei Chen <wei.c...@csr.com>
Signed-off-by: Linus Walleij <linus.wall...@linaro.org>
(cherry picked from commit 323de9efdf3e75d1dfb48003a52e59d6d9d4c7a5)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>

Conflicts:
drivers/pinctrl/pinctrl-lpc18xx.c
drivers/pinctrl/pinctrl-pistachio.c
drivers/pinctrl/sirf/pinctrl-atlas7.c
---
 drivers/pinctrl/bcm/pinctrl-bcm281xx.c|  4 ++--
 drivers/pinctrl/bcm/pinctrl-bcm2835.c |  4 ++--
 drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c |  4 ++--
 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c  |  4 ++--
 drivers/pinctrl/berlin/berlin.c   |  4 ++--
 drivers/pinctrl/core.c| 17 ++---
 drivers/pinctrl/freescale/pinctrl-imx.c   |  4 ++--
 drivers/pinctrl/freescale/pinctrl-imx1-core.c |  4 ++--
 drivers/pinctrl/freescale/pinctrl-mxs.c   |  4 ++--
 drivers/pinctrl/intel/pinctrl-cherryview.c|  4 ++--
 drivers/pinctrl/intel/pinctrl-intel.c |  4 ++--
 drivers/pinctrl/mediatek/pinctrl-mtk-common.c |  4 ++--
 drivers/pinctrl/meson/pinctrl-meson.c |  4 ++--
 drivers/pinctrl/mvebu/pinctrl-mvebu.c |  4 ++--
 drivers/pinctrl/nomadik/pinctrl-abx500.c  |  4 ++--
 drivers/pinctrl/nomadik/pinctrl-nomadik.c |  4 ++--
 drivers/pinctrl/pinctrl-adi2.c|  4 ++--
 drivers/pinctrl/pinctrl-amd.c |  4 ++--
 drivers/pinctrl/pinctrl-as3722.c  |  4 ++--
 drivers/pinctrl/pinctrl-at91.c|  4 ++--
 drivers/pinctrl/pinctrl-lantiq.c  |  4 ++--
 drivers/pinctrl/pinctrl-palmas.c  |  4 ++--
 drivers/pinctrl/pinctrl-rockchip.c|  4 ++--
 drivers/pinctrl/pinctrl-single.c  |  4 ++--
 drivers/pinctrl/pinctrl-st.c  |  4 ++--
 drivers/pinctrl/pinctrl-tb10x.c   |  4 ++--
 drivers/pinctrl/pinctrl-tegra-xusb.c  |  4 ++--
 drivers/pinctrl/pinctrl-tegra.c   |  4 ++--
 drivers/pinctrl/pinctrl-tz1090-pdc.c  |  4 ++--
 drivers/pinctrl/pinctrl-tz1090.c  |  4 ++--
 drivers/pinctrl/pinctrl-u300.c|  4 ++--
 drivers/pinctrl/pinctrl-zynq.c|  4 ++--
 drivers/pinctrl/qcom/pinctrl-msm.c|  4 ++--
 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c  |  4 ++--
 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c   |  4 ++--
 drivers/pinctrl/samsung/pinctrl-exynos5440.c  |  4 ++--
 drivers/pinctrl/samsung/pinctrl-samsung.c |  4 ++--
 drivers/pinctrl/sh-pfc/pinctrl.c  |  4 ++--
 drivers/pinctrl/sirf/pinctrl-sirf.c   |  4 ++--
 drivers/pinctrl/spear/pinctrl-spear.c |  4 ++--
 drivers/pinctrl/sunxi/pinctrl-sunxi.c |  4 ++--
 drivers/pinctrl/vt8500/pinctrl-wmt.c  |  4 ++--
 42 files changed, 92 insertions(+), 89 deletions(-)

diff --git a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c 
b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c
index 9641f1c..c3c692e 100644
--- a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c
@@ -1425,9 +1425,9 @@ static int __init bcm281xx_pinctrl_probe(struct 
platform_device *pdev)
pctl = pinctrl_register(_pinctrl_desc,
>dev,
pdata);
-   if (!pctl) {
+   if (IS_ERR(pctl)) {
dev_err(>dev, "Failed to register pinctrl\n");
-   return -ENODEV;
+   return PTR_ERR(pctl);
}
 
platform_set_drvdata(pdev, pdata);
diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c 
b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
index 8d908e3..efcf2a2 100644
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pi

[linux-yocto] [PATCH 1/6] pinctrl: intel: sunrisepoint: Add Intel Sunrisepoint-H support

[Tan Jui Nee]

From: Mika Westerberg <mika.westerb...@linux.intel.com>

Intel Sunrisepoint-H is a desktop version of the PCH (Platform Controller
Hub). It has slightly different pin configuration compared to the LP
version. This patch adds support for Sunrisepoint-H to the existing
pinctrl-sunrisepoint.c driver.

Signed-off-by: Mika Westerberg <mika.westerb...@linux.intel.com>
Signed-off-by: Linus Walleij <linus.wall...@linaro.org>
(cherry picked from commit 551fa5801ef10298aa1f43e5e95355e2dd5cb3bb)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 263 +++
 1 file changed, 263 insertions(+)

diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c 
b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
index 55d025d..1de9ae5 100644
--- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
+++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
@@ -284,8 +284,271 @@ static const struct intel_pinctrl_soc_data sptlp_soc_data 
= {
.ncommunities = ARRAY_SIZE(sptlp_communities),
 };
 
+/* Sunrisepoint-H */
+static const struct pinctrl_pin_desc spth_pins[] = {
+   /* GPP_A */
+   PINCTRL_PIN(0, "RCINB"),
+   PINCTRL_PIN(1, "LAD_0"),
+   PINCTRL_PIN(2, "LAD_1"),
+   PINCTRL_PIN(3, "LAD_2"),
+   PINCTRL_PIN(4, "LAD_3"),
+   PINCTRL_PIN(5, "LFRAMEB"),
+   PINCTRL_PIN(6, "SERIQ"),
+   PINCTRL_PIN(7, "PIRQAB"),
+   PINCTRL_PIN(8, "CLKRUNB"),
+   PINCTRL_PIN(9, "CLKOUT_LPC_0"),
+   PINCTRL_PIN(10, "CLKOUT_LPC_1"),
+   PINCTRL_PIN(11, "PMEB"),
+   PINCTRL_PIN(12, "BM_BUSYB"),
+   PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
+   PINCTRL_PIN(14, "SUS_STATB"),
+   PINCTRL_PIN(15, "SUSACKB"),
+   PINCTRL_PIN(16, "CLKOUT_48"),
+   PINCTRL_PIN(17, "ISH_GP_7"),
+   PINCTRL_PIN(18, "ISH_GP_0"),
+   PINCTRL_PIN(19, "ISH_GP_1"),
+   PINCTRL_PIN(20, "ISH_GP_2"),
+   PINCTRL_PIN(21, "ISH_GP_3"),
+   PINCTRL_PIN(22, "ISH_GP_4"),
+   PINCTRL_PIN(23, "ISH_GP_5"),
+   /* GPP_B */
+   PINCTRL_PIN(24, "CORE_VID_0"),
+   PINCTRL_PIN(25, "CORE_VID_1"),
+   PINCTRL_PIN(26, "VRALERTB"),
+   PINCTRL_PIN(27, "CPU_GP_2"),
+   PINCTRL_PIN(28, "CPU_GP_3"),
+   PINCTRL_PIN(29, "SRCCLKREQB_0"),
+   PINCTRL_PIN(30, "SRCCLKREQB_1"),
+   PINCTRL_PIN(31, "SRCCLKREQB_2"),
+   PINCTRL_PIN(32, "SRCCLKREQB_3"),
+   PINCTRL_PIN(33, "SRCCLKREQB_4"),
+   PINCTRL_PIN(34, "SRCCLKREQB_5"),
+   PINCTRL_PIN(35, "EXT_PWR_GATEB"),
+   PINCTRL_PIN(36, "SLP_S0B"),
+   PINCTRL_PIN(37, "PLTRSTB"),
+   PINCTRL_PIN(38, "SPKR"),
+   PINCTRL_PIN(39, "GSPI0_CSB"),
+   PINCTRL_PIN(40, "GSPI0_CLK"),
+   PINCTRL_PIN(41, "GSPI0_MISO"),
+   PINCTRL_PIN(42, "GSPI0_MOSI"),
+   PINCTRL_PIN(43, "GSPI1_CSB"),
+   PINCTRL_PIN(44, "GSPI1_CLK"),
+   PINCTRL_PIN(45, "GSPI1_MISO"),
+   PINCTRL_PIN(46, "GSPI1_MOSI"),
+   PINCTRL_PIN(47, "SML1ALERTB"),
+   /* GPP_C */
+   PINCTRL_PIN(48, "SMBCLK"),
+   PINCTRL_PIN(49, "SMBDATA"),
+   PINCTRL_PIN(50, "SMBALERTB"),
+   PINCTRL_PIN(51, "SML0CLK"),
+   PINCTRL_PIN(52, "SML0DATA"),
+   PINCTRL_PIN(53, "SML0ALERTB"),
+   PINCTRL_PIN(54, "SML1CLK"),
+   PINCTRL_PIN(55, "SML1DATA"),
+   PINCTRL_PIN(56, "UART0_RXD"),
+   PINCTRL_PIN(57, "UART0_TXD"),
+   PINCTRL_PIN(58, "UART0_RTSB"),
+   PINCTRL_PIN(59, "UART0_CTSB"),
+   PINCTRL_PIN(60, "UART1_RXD"),
+   PINCTRL_PIN(61, "UART1_TXD"),
+   PINCTRL_PIN(62, "UART1_RTSB"),
+   PINCTRL_PIN(63, "UART1_CTSB"),
+   PINCTRL_PIN(64, "I2C0_SDA"),
+   PINCTRL_PIN(65, "I2C0_SCL"),
+   PINCTRL_PIN(66, "I2C1_SDA"),
+   PINCTRL_PIN(67, "I2C1_SCL"),
+   PINCTRL_PIN(68, "UART2_RXD"),
+   PINCTRL_PIN(69, "UART2_TXD"),
+   PINCTRL_PIN(70, "UART2_RTSB"),
+   PINCTRL_PIN(71, "UART2_CTSB"),
+   /* GPP_D */
+   PINCTRL_PIN(72, "SPI1_CSB"),
+   PINCTRL_PIN(73, "SPI1_CLK"),
+   PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
+   PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
+   PINCTRL_PIN(76, "ISH_I2C2_SDA"),
+   PINCTRL_PIN(77, "SSP0_SFRM"),
+   PINCTRL_PIN(78, "SSP0_TX

[linux-yocto] [PATCH 4/6] pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt

[Tan Jui Nee]

From: Mika Westerberg <mika.westerb...@linux.intel.com>

On Intel Broxton the GPIO hardware consists of several chips that all share
the parent interrupt. It is not possible to handle this by setting chained
handler for each chip (as they will overwrite each other).

To overcome this we need to request the interrupt using devm_request_irq()
and pass IRQF_SHARED with the flags.

Signed-off-by: Mika Westerberg <mika.westerb...@linux.intel.com>
Signed-off-by: Linus Walleij <linus.wall...@linaro.org>
(cherry picked from commit 193b40c8258f781d8dc395909b2971472aad6796)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>

Conflicts:
drivers/pinctrl/intel/pinctrl-intel.c
---
 drivers/pinctrl/intel/pinctrl-intel.c | 52 +--
 1 file changed, 37 insertions(+), 15 deletions(-)

diff --git a/drivers/pinctrl/intel/pinctrl-intel.c 
b/drivers/pinctrl/intel/pinctrl-intel.c
index 834f269..f342c6b 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -12,6 +12,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -803,9 +804,11 @@ static int intel_gpio_irq_wake(struct irq_data *d, 
unsigned int on)
return 0;
 }
 
-static void intel_gpio_community_irq_handler(struct gpio_chip *gc,
+static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl 
*pctrl,
const struct intel_community *community)
 {
+   struct gpio_chip *gc = >chip;
+   irqreturn_t ret = IRQ_NONE;
int gpp;
 
for (gpp = 0; gpp < community->ngpps; gpp++) {
@@ -832,24 +835,28 @@ static void intel_gpio_community_irq_handler(struct 
gpio_chip *gc,
irq = irq_find_mapping(gc->irqdomain,
   community->pin_base + padno);
generic_handle_irq(irq);
+
+   ret |= IRQ_HANDLED;
}
}
+
+   return ret;
 }
 
-static void intel_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
+static irqreturn_t intel_gpio_irq(int irq, void *data)
 {
-   struct gpio_chip *gc = irq_desc_get_handler_data(desc);
-   struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
-   struct irq_chip *chip = irq_get_chip(irq);
+   const struct intel_community *community;
+   struct intel_pinctrl *pctrl = data;
+   irqreturn_t ret = IRQ_NONE;
int i;
 
-   chained_irq_enter(chip, desc);
-
/* Need to check all communities for pending interrupts */
-   for (i = 0; i < pctrl->ncommunities; i++)
-   intel_gpio_community_irq_handler(gc, >communities[i]);
+   for (i = 0; i < pctrl->ncommunities; i++) {
+   community = >communities[i];
+   ret |= intel_gpio_community_irq_handler(pctrl, community);
+   }
 
-   chained_irq_exit(chip, desc);
+   return ret;
 }
 
 static struct irq_chip intel_gpio_irqchip = {
@@ -882,21 +889,36 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, 
int irq)
 0, 0, pctrl->soc->npins);
if (ret) {
dev_err(pctrl->dev, "failed to add GPIO pin range\n");
-   gpiochip_remove(>chip);
-   return ret;
+   goto fail;
+   }
+
+   /*
+* We need to request the interrupt here (instead of providing chip
+* to the irq directly) because on some platforms several GPIO
+* controllers share the same interrupt line.
+*/
+   ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, IRQF_SHARED,
+  dev_name(pctrl->dev), pctrl);
+   if (ret) {
+   dev_err(pctrl->dev, "failed to request interrupt\n");
+   goto fail;
}
 
ret = gpiochip_irqchip_add(>chip, _gpio_irqchip, 0,
   handle_simple_irq, IRQ_TYPE_NONE);
if (ret) {
dev_err(pctrl->dev, "failed to add irqchip\n");
-   gpiochip_remove(>chip);
-   return ret;
+   goto fail;
}
 
gpiochip_set_chained_irqchip(>chip, _gpio_irqchip, irq,
-intel_gpio_irq_handler);
+NULL);
return 0;
+
+fail:
+   gpiochip_remove(>chip);
+
+   return ret;
 }
 
 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
-- 
1.9.1

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[linux-yocto] [PATCH 3/6] pinctrl: intel: Fix compilation warning when !CONFIG_PM_SLEEP

[Tan Jui Nee]

From: Mika Westerberg <mika.westerb...@linux.intel.com>

We get following warning when CONFIG_PM_SLEEP is not set

  warning: ‘intel_gpio_irq_init’ defined but not used [-Wunused-function]

Since the function is only called from intel_pinctrl_resume() move it
inside CONFIG_PM_SLEEP guard as well.

Signed-off-by: Mika Westerberg <mika.westerb...@linux.intel.com>
Signed-off-by: Linus Walleij <linus.wall...@linaro.org>
(cherry picked from commit f487bbf309759153f56bac7d7ba5ee63196ce584)
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/pinctrl/intel/pinctrl-intel.c | 40 +--
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/pinctrl/intel/pinctrl-intel.c 
b/drivers/pinctrl/intel/pinctrl-intel.c
index f9ee0d6..834f269 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -861,26 +861,6 @@ static struct irq_chip intel_gpio_irqchip = {
.irq_set_wake = intel_gpio_irq_wake,
 };
 
-static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
-{
-   size_t i;
-
-   for (i = 0; i < pctrl->ncommunities; i++) {
-   const struct intel_community *community;
-   void __iomem *base;
-   unsigned gpp;
-
-   community = >communities[i];
-   base = community->regs;
-
-   for (gpp = 0; gpp < community->ngpps; gpp++) {
-   /* Mask and clear all interrupts */
-   writel(0, base + community->ie_offset + gpp * 4);
-   writel(0x, base + GPI_IS + gpp * 4);
-   }
-   }
-}
-
 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
 {
int ret;
@@ -1087,6 +1067,26 @@ int intel_pinctrl_suspend(struct device *dev)
 }
 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
 
+static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
+{
+   size_t i;
+
+   for (i = 0; i < pctrl->ncommunities; i++) {
+   const struct intel_community *community;
+   void __iomem *base;
+   unsigned gpp;
+
+   community = >communities[i];
+   base = community->regs;
+
+   for (gpp = 0; gpp < community->ngpps; gpp++) {
+   /* Mask and clear all interrupts */
+   writel(0, base + community->ie_offset + gpp * 4);
+   writel(0x, base + GPI_IS + gpp * 4);
+   }
+   }
+}
+
 int intel_pinctrl_resume(struct device *dev)
 {
struct platform_device *pdev = to_platform_device(dev);
-- 
1.9.1

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[linux-yocto] [PATCH] drm/i915: Fix the VBT child device parsing for BSW

[Tan Jui Nee]

From: Ville Syrjälä <ville.syrj...@linux.intel.com>

Recent BSW VBT has a VBT child device size 37 bytes instead of the 33
bytes our code assumes. This means we fail to parse the VBT and thus
fail to detect eDP ports properly and just register them as DP ports
instead.

Fix it up by using the reported child device size from the VBT instead
of assuming it matches out struct defintions.

The latest spec I have shows that the child device size should be 36
bytes for rev >= 195, however on my BSW the size is actually 37 bytes.
And our current struct definition is 33 bytes.

Feels like the entire VBT parses would need to be rewritten to handle
changes in the layout better, but for now I've decided to do just the
bare minimum to get my eDP port back.

Cc: Vijay Purushothaman <vijay.a.purushotha...@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lesp...@intel.com>
Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
(cherry picked from commit 90e4f1592bb6e82f6690f0e05a8aadcf04d7bce7)
Signed-off-by: abdul arif abdul muttalib <abdul.arif.b.abdul.mutta...@intel.com>
Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c | 26 +-
 drivers/gpu/drm/i915/intel_bios.h |  4 ++--
 2 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index c684085..4cbd325 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -447,6 +447,12 @@ parse_general_definitions(struct drm_i915_private 
*dev_priv,
}
 }
 
+static union child_device_config *
+child_device_ptr(struct bdb_general_definitions *p_defs, int i)
+{
+   return (void *) _defs->devices[i * p_defs->child_dev_size];
+}
+
 static void
 parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
  struct bdb_header *bdb)
@@ -476,10 +482,10 @@ parse_sdvo_device_mapping(struct drm_i915_private 
*dev_priv,
block_size = get_blocksize(p_defs);
/* get the number of child device */
child_device_num = (block_size - sizeof(*p_defs)) /
-   sizeof(*p_child);
+   p_defs->child_dev_size;
count = 0;
for (i = 0; i < child_device_num; i++) {
-   p_child = &(p_defs->devices[i]);
+   p_child = child_device_ptr(p_defs, i);
if (!p_child->old.device_type) {
/* skip the device block if device type is invalid */
continue;
@@ -1067,25 +1073,19 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
DRM_DEBUG_KMS("No general definition block is found, no devices 
defined.\n");
return;
}
-   /* judge whether the size of child device meets the requirements.
-* If the child device size obtained from general definition block
-* is different with sizeof(struct child_device_config), skip the
-* parsing of sdvo device info
-*/
-   if (p_defs->child_dev_size != sizeof(*p_child)) {
-   /* different child dev size . Ignore it */
-   DRM_DEBUG_KMS("different child size is found. Invalid.\n");
+   if (p_defs->child_dev_size < sizeof(*p_child)) {
+   DRM_ERROR("General definiton block child device size is too 
small.\n");
return;
}
/* get the block size of general definitions */
block_size = get_blocksize(p_defs);
/* get the number of child device */
child_device_num = (block_size - sizeof(*p_defs)) /
-   sizeof(*p_child);
+   p_defs->child_dev_size;
count = 0;
/* get the number of child device that is present */
for (i = 0; i < child_device_num; i++) {
-   p_child = &(p_defs->devices[i]);
+   p_child = child_device_ptr(p_defs, i);
if (!p_child->common.device_type) {
/* skip the device block if device type is invalid */
continue;
@@ -1105,7 +1105,7 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
dev_priv->vbt.child_dev_num = count;
count = 0;
for (i = 0; i < child_device_num; i++) {
-   p_child = &(p_defs->devices[i]);
+   p_child = child_device_ptr(p_defs, i);
if (!p_child->common.device_type) {
/* skip the device block if device type is invalid */
continue;
diff --git a/drivers/gpu/drm/i915/intel_bios.h 
b/drivers/gpu/drm/i915/intel_bios.h
index 6afd5be..af0b476 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -277,9 +277,9 @@ struct bdb_ge

[linux-yocto] [PATCH] Backport eDP bug fix for Braswell

[Tan Jui Nee]

Hi,

This patch is targeted for Braswell bug fixes on i915 graphics driver.
We encountered issues which eDP unable to initialize due to changes in
BIOS VBT.
The patch was backported from upstream kernel into linux-yocto-4.1.
The functionality and bug fixed by the patch has been built and tested
on the Cherry Hill platform.

This patchset was targeted to merge into linux-yocto-4.1 on standard/base 
branch.

Please review and provide feedback if any.

Thank you.

Best regards,
Jui Nee

Ville Syrjälä (1):
  drm/i915: Fix the VBT child device parsing for BSW

 drivers/gpu/drm/i915/intel_bios.c | 26 +-
 drivers/gpu/drm/i915/intel_bios.h |  4 ++--
 2 files changed, 15 insertions(+), 15 deletions(-)

-- 
1.9.1

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