Re: [linux-yocto] [PATCH] arm64: dts: r8a7795: Add CPUIdle support for all CPU core

2019-10-22 Thread Bruce Ashfield 
This should already be on the branches:

Author: Takeshi Kihara 
Date:   Tue Oct 15 13:46:44 2019 +0800

arm64: dts: r8a7795: Add CPUIdle support for all CPU core

commit 3c3b44c752c4eef9a29694f4262934445c5f5da9 from
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git

This patch enables CPUIdle (Core shutdown) support for R-Car H3.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Meng Li 
Signed-off-by: Bruce Ashfield 

:100644 100644 097538cc4b1f 7596216409cd M
arch/arm64/boot/dts/renesas/r8a7795.dtsi

On Tue, Oct 22, 2019 at 10:47 PM  wrote:
>
> From: Takeshi Kihara 
>
> commit 3c3b44c752c4eef9a29694f4262934445c5f5da9 from
> git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git
>
> This patch enables CPUIdle (Core shutdown) support for R-Car H3.
>
> Signed-off-by: Takeshi Kihara 
> Signed-off-by: Meng Li 
> ---
>  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32 
> 
>  1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index e8c3d5f..7fe7428 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -123,6 +123,7 @@
> power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
> next-level-cache = <&L2_CA57>;
> enable-method = "psci";
> +   cpu-idle-states = <&CPU_SLEEP_0>;
> clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
> operating-points-v2 = <&cluster0_opp>;
> capacity-dmips-mhz = <1024>;
> @@ -135,6 +136,7 @@
> power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
> next-level-cache = <&L2_CA57>;
> enable-method = "psci";
> +   cpu-idle-states = <&CPU_SLEEP_0>;
> clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
> operating-points-v2 = <&cluster0_opp>;
> capacity-dmips-mhz = <1024>;
> @@ -147,6 +149,7 @@
> power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
> next-level-cache = <&L2_CA57>;
> enable-method = "psci";
> +   cpu-idle-states = <&CPU_SLEEP_0>;
> clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
> operating-points-v2 = <&cluster0_opp>;
> capacity-dmips-mhz = <1024>;
> @@ -159,6 +162,7 @@
> power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
> next-level-cache = <&L2_CA57>;
> enable-method = "psci";
> +   cpu-idle-states = <&CPU_SLEEP_0>;
> clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
> operating-points-v2 = <&cluster0_opp>;
> capacity-dmips-mhz = <1024>;
> @@ -171,6 +175,7 @@
> power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
> next-level-cache = <&L2_CA53>;
> enable-method = "psci";
> +   cpu-idle-states = <&CPU_SLEEP_1>;
> clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
> operating-points-v2 = <&cluster1_opp>;
> capacity-dmips-mhz = <535>;
> @@ -182,6 +187,7 @@
> power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
> next-level-cache = <&L2_CA53>;
> enable-method = "psci";
> +   cpu-idle-states = <&CPU_SLEEP_1>;
> clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
> operating-points-v2 = <&cluster1_opp>;
> capacity-dmips-mhz = <535>;
> @@ -193,6 +199,7 @@
> power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
> next-level-cache = <&L2_CA53>;
> enable-method = "psci";
> +   cpu-idle-states = <&CPU_SLEEP_1>;
> clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
> operating-points-v2 = <&cluster1_opp>;
> capacity-dmips-mhz = <535>;
> @@ -204,6 +211,7 @@
> power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
> next-level-cache = <&L2_CA53>;
> enable-method = "psci";
> +   cpu-idle-states = <&CPU_SLEEP_1>;
> clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
> operating-points-v2 = <&cluster1_opp>;
> capacity-dmips-mhz = <535>;
> @@ -221,6 +229,30 @@
> cache-unified;
> cache-level = <2>;
> };
> +
> +   idle-states {
> +

Re: [linux-yocto] [PATCH] arm64: dts: r8a7795: Add CPUIdle support for all CPU core

2019-10-22 Thread Bruce Ashfield 
On Tue, Oct 22, 2019 at 10:57 PM Bruce Ashfield
 wrote:
>
> This should already be on the branches:
>

.. and I forgot the commit id:

c93bf81feabf89b5ee77838d3bb62825d04dab09

Bruce

> Author: Takeshi Kihara 
> Date:   Tue Oct 15 13:46:44 2019 +0800
>
> arm64: dts: r8a7795: Add CPUIdle support for all CPU core
>
> commit 3c3b44c752c4eef9a29694f4262934445c5f5da9 from
> git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git
>
> This patch enables CPUIdle (Core shutdown) support for R-Car H3.
>
> Signed-off-by: Takeshi Kihara 
> Signed-off-by: Meng Li 
> Signed-off-by: Bruce Ashfield 
>
> :100644 100644 097538cc4b1f 7596216409cd M
> arch/arm64/boot/dts/renesas/r8a7795.dtsi
>
> On Tue, Oct 22, 2019 at 10:47 PM  wrote:
> >
> > From: Takeshi Kihara 
> >
> > commit 3c3b44c752c4eef9a29694f4262934445c5f5da9 from
> > git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git
> >
> > This patch enables CPUIdle (Core shutdown) support for R-Car H3.
> >
> > Signed-off-by: Takeshi Kihara 
> > Signed-off-by: Meng Li 
> > ---
> >  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32 
> > 
> >  1 file changed, 32 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
> > b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> > index e8c3d5f..7fe7428 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> > @@ -123,6 +123,7 @@
> > power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
> > next-level-cache = <&L2_CA57>;
> > enable-method = "psci";
> > +   cpu-idle-states = <&CPU_SLEEP_0>;
> > clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
> > operating-points-v2 = <&cluster0_opp>;
> > capacity-dmips-mhz = <1024>;
> > @@ -135,6 +136,7 @@
> > power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
> > next-level-cache = <&L2_CA57>;
> > enable-method = "psci";
> > +   cpu-idle-states = <&CPU_SLEEP_0>;
> > clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
> > operating-points-v2 = <&cluster0_opp>;
> > capacity-dmips-mhz = <1024>;
> > @@ -147,6 +149,7 @@
> > power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
> > next-level-cache = <&L2_CA57>;
> > enable-method = "psci";
> > +   cpu-idle-states = <&CPU_SLEEP_0>;
> > clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
> > operating-points-v2 = <&cluster0_opp>;
> > capacity-dmips-mhz = <1024>;
> > @@ -159,6 +162,7 @@
> > power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
> > next-level-cache = <&L2_CA57>;
> > enable-method = "psci";
> > +   cpu-idle-states = <&CPU_SLEEP_0>;
> > clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
> > operating-points-v2 = <&cluster0_opp>;
> > capacity-dmips-mhz = <1024>;
> > @@ -171,6 +175,7 @@
> > power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
> > next-level-cache = <&L2_CA53>;
> > enable-method = "psci";
> > +   cpu-idle-states = <&CPU_SLEEP_1>;
> > clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
> > operating-points-v2 = <&cluster1_opp>;
> > capacity-dmips-mhz = <535>;
> > @@ -182,6 +187,7 @@
> > power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
> > next-level-cache = <&L2_CA53>;
> > enable-method = "psci";
> > +   cpu-idle-states = <&CPU_SLEEP_1>;
> > clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
> > operating-points-v2 = <&cluster1_opp>;
> > capacity-dmips-mhz = <535>;
> > @@ -193,6 +199,7 @@
> > power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
> > next-level-cache = <&L2_CA53>;
> > enable-method = "psci";
> > +   cpu-idle-states = <&CPU_SLEEP_1>;
> > clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
> > operating-points-v2 = <&cluster1_opp>;
> > capacity-dmips-mhz = <535>;
> > @@ -204,6 +211,7 @@
> > power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
> > next-level-cache = <&L2_CA53>;
> > enable-method = "psci";
> > +   cpu-idle-states = <&CPU_SLEEP_1>;
> > clocks =

[linux-yocto] [PATCH] arm64: dts: r8a7795: Add CPUIdle support for all CPU core

2019-10-22 Thread Meng.Li 
From: Takeshi Kihara 

commit 3c3b44c752c4eef9a29694f4262934445c5f5da9 from
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git

This patch enables CPUIdle (Core shutdown) support for R-Car H3.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32 
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index e8c3d5f..7fe7428 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -123,6 +123,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
@@ -135,6 +136,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
@@ -147,6 +149,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
@@ -159,6 +162,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
@@ -171,6 +175,7 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@@ -182,6 +187,7 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@@ -193,6 +199,7 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@@ -204,6 +211,7 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@@ -221,6 +229,30 @@
cache-unified;
cache-level = <2>;
};
+
+   idle-states {
+   entry-method = "psci";
+
+   CPU_SLEEP_0: cpu-sleep-0 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+   entry-latency-us = <400>;
+   exit-latency-us = <500>;
+   min-residency-us = <4000>;
+   status = "okay";
+   };
+
+   CPU_SLEEP_1: cpu-sleep-1 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+

[linux-yocto] [PATCH] arm64: dts: r8a7795: Add CPUIdle support for all CPU core

2019-10-14 Thread Meng.Li 
From: Takeshi Kihara 

commit 3c3b44c752c4eef9a29694f4262934445c5f5da9 from
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git

This patch enables CPUIdle (Core shutdown) support for R-Car H3.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32 
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index e8c3d5f..7fe7428 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -123,6 +123,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
@@ -135,6 +136,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
@@ -147,6 +149,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
@@ -159,6 +162,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
@@ -171,6 +175,7 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@@ -182,6 +187,7 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@@ -193,6 +199,7 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@@ -204,6 +211,7 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@@ -221,6 +229,30 @@
cache-unified;
cache-level = <2>;
};
+
+   idle-states {
+   entry-method = "psci";
+
+   CPU_SLEEP_0: cpu-sleep-0 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+   entry-latency-us = <400>;
+   exit-latency-us = <500>;
+   min-residency-us = <4000>;
+   status = "okay";
+   };
+
+   CPU_SLEEP_1: cpu-sleep-1 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+

[linux-yocto] [PATCH] arm64: dts: r8a7795: Add CPUIdle support for all CPU core

2019-10-14 Thread Meng.Li 
From: Takeshi Kihara 

commit 3c3b44c752c4eef9a29694f4262934445c5f5da9 from
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git

This patch enables CPUIdle (Core shutdown) support for R-Car H3.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32 
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index e8c3d5f..7fe7428 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -123,6 +123,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_0>;
dynamic-power-coefficient = <854>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
@@ -135,6 +136,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
@@ -147,6 +149,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
@@ -159,6 +162,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
@@ -171,6 +175,7 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_1>;
#cooling-cells = <2>;
dynamic-power-coefficient = <277>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
@@ -182,6 +187,7 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@@ -193,6 +199,7 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@@ -204,6 +211,7 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+   cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@@ -221,6 +229,30 @@
cache-unified;
cache-level = <2>;
};
+
+   idle-states {
+   entry-method = "psci";
+
+   CPU_SLEEP_0: cpu-sleep-0 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+   entry-latency-us = <400>;
+   exit-latency-us = <500>;
+   min-residency-us = <4000>;
+   status = "okay";
+   };
+
+   CPU_SLEEP_1: cpu-sleep-1 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+