Is anybody checking in new code in tla?
Hi, Are there any recent checkins made to the arch tree? I'm mostly interested in the 440BX v2 development. tla update * tree is already up to date No changes since April 2 when it was checked out ... (I followed the instructions at the website) ___ Linuxbios mailing list Linuxbios@clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: Is 440BX ported to Linuxbios v2?
On Fri, 2005-01-14 at 02:57 +0100, Peter Stuge wrote: On Thu, Jan 13, 2005 at 10:54:59PM +0100, Svante Signell wrote: I found the BIOS chip brand and version: Its a Winbond W290C020-90 (84400M282325601VA). Any suppliers available somehere? Farnell has an equivalent part in stock at the very fair price of 46,43 SEK (USD 7) for single quantities. Thanks a lot everybody, your response is overwhelming. I found where to try to purchase the flash ROM chips due to Peter Stuge. I'll be back when I've succeeded to purchase these flash BIOSes and found out where to find a flash programmer. Maybe we even have one at school. I'll be back in one week (Business trip). I can't seem to reproduce a working direct link, but go to http://se.farnell.com/ and search for 4376146, it should come up with the AT29C020-90PI from Atmel. It has some extra bells and whistles compared to the Winbond, but it will do the job just fine. //Peter ___ -- Svante Signell [EMAIL PROTECTED] ___ Linuxbios mailing list Linuxbios@clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: Is 440BX ported to Linuxbios v2?
On Wed, 2005-01-12 at 07:53 -0800, Richard Smith wrote: --- Svante Signell [EMAIL PROTECTED] wrote: dual CPU board MSI-6120. The current MSI/AMI BIOS V2.0 does not support newer CPUs than Coppermine. Porting 440bx to V2 is on my TODO list but it's currently blocked by a few other priorities. The V1 code should work for you fine. All you need to do is find out what superIO you have and change the serial port setup accordingly so you can get debug messages. The super IO chip is a Winbond W83977TF-AW (AM.MEGA.87-96, 845AC2830694028a) Is is supported by V1? in V1 look at the ./mainboard/bitworks/IMS I think thats the most complete 440bx port. -- Svante Signell [EMAIL PROTECTED] ___ Linuxbios mailing list Linuxbios@clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: Is 440BX ported to Linuxbios v2?
On Wed, 2005-01-12 at 18:12 +0100, Peter Stuge wrote: On Wed, Jan 12, 2005 at 10:38:57AM +0100, Svante Signell wrote: Where can I purchase a replacement BIOS chip? Placed in a socket on the main board is a 2x16 pin DIL labeled: 686 AMI BIOS 1995 CS 9. Please remove the shiny sticker and check how the actual package is marked. You're looking for thin letters and numbers engraved on top of the black plastic. Look for 29F020 or something similar. I found the BIOS chip brand and version: Its a Winbond W290C020-90 (84400M282325601VA). Any suppliers available somehere? Is it large enough to host LinuxBIOS? My dual-CPU MSI-6120 MOBO has on-board dual channel Adaptec 7895 SCSI support. Does V1 support this? What about the FSB settings avalaible in the MSI/AMI BIOS v2.0: 100MHz, 103MHz, 112MHz, 133MHz? It would be nice to run the board at 133MHz, eqipped with an 1.4GHz Tualatin Celeron 2 or dual PIIIs. (Or VIA C3 1.0-1.4GHz, currently single CPU, and hopefully soon dual CPU) -- Svante Signell [EMAIL PROTECTED] ___ Linuxbios mailing list Linuxbios@clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: Is 440BX ported to Linuxbios v2?
On Thu, 2005-01-13 at 16:23 -0600, Richard Smith wrote: On Thu, 13 Jan 2005 14:59:08 -0700 (MST), Ronald G. Minnich rminnich@lanl.gov wrote: On Thu, 13 Jan 2005, Svante Signell wrote: I found the BIOS chip brand and version: Its a Winbond W290C020-90 a nice common safe part. Try hamilton-avnet or arrow. WARNING: when you call them, use the EXACT part #. Their databases are not able to do fuzzy logic. http://www.digikey.com is your friend. Well really almost any JDEC part 2MBits and larger will work. If you use a larger part you might have to ground the unused address lines if they left them floating on the pcb. Thanks for the links. No luck with any of the links given, however. How to find a replacement part? no idea on the FSB settings -- I think linuxbios always goes with the fastest :-) The FSB is set via the clock chip. The clock chip we have is set via straps. I'm not sure what your commercial bios is doing but the 440bx is not rated for over 100Mhz. So those other settings are overclockings. And they will change the speed of your PCI bus as well. I know about the 100MHz rating for 440BX. However, on the board you can select 66/100 MHz FSB and the BIOS supports the higher FSB speeds. Also the board has multiplier settings (3-5) x (66,100) MHz = 200-500 MHz for CPUs with changable clock multipliers. The board runs today with dual Celeron (Mendocino, 300MHz, before Intel disabled dual on Celerons) at 103/66*300MHz = 466MHz stably for many years now. BTW: The memories I have installed are all PC133 parts. I suspect your board has a small microcontroller on it with eeprom that sets the strap settings on boot and then de-asserts reset. That or it boots in 66Mhz and then sets the clock chip after that. Anybody know what clock chip is on that board? Where to look for that chip? The board also has a system manager jumper: Selectable between the SuperIO chip (default) vs. the PIIX4E (southbridge). Wht is the meaning of this choice? I have the board description in pdf-format available if someone is interested. -- Svante Signell [EMAIL PROTECTED] ___ Linuxbios mailing list Linuxbios@clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: Is 440BX ported to Linuxbios v2?
On Thu, 2005-01-13 at 18:14 -0600, Richard Smith wrote: http://www.digikey.com is your friend. Well really almost any JDEC part 2MBits and larger will work. If you use a larger part you might have to ground the unused address lines if they left them floating on the pcb. Thanks for the links. No luck with any of the links given, however. How to find a replacement part? They are there but you just don't know what to look for. *grin* First off you part number is incorrect it should be W29C020 not W290C020. But there are't that many people who sell windbond. But you don need a windbond any 2MBit part will work as long as the footprint is the same... any 29?020 part will work. Oh wait a minute... I bet you don't have a programmer do you? Ick. In that case foget what I said. You will need a part supported by the hot swap trick. Ron. What flash parts are supported by your hotswap trick? I did find out the extra zero in my search, thank you. Now I got a few hits at digikey. No, I don't have a FLASH programmer, but i can purchase one if needed, and the price is not to high. According what you write it does not seem to be possible to program an empy BIOS with a boot floppy similar to re-programming an existing one. Can I copy the content of the old BIOS with a programmer and start from there? How to proceed? -- Svante Signell [EMAIL PROTECTED] ___ Linuxbios mailing list Linuxbios@clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: Is 440BX ported to Linuxbios v2?
On Thu, 2005-01-13 at 18:57 -0600, Richard Smith wrote: I did find out the extra zero in my search, thank you. Now I got a few hits at digikey. No, I don't have a FLASH programmer, but i can purchase one if needed, and the price is not to high. According what you write it Depends on the model.. You can spend anywhere from $200 to $2000. There is a USB one from batronix that is fairly cheap but I can't recommend it since the software sucks and its never worked correctly for me. Others on the list have not had issues with it though. Google for flash programmer or eprom programmer and see if you can find one in your price range. Also unless your chip is a DIP you will have to buy an adapter which will be around $100. One quick check. Your flash chip is socketed right? Thank for your prompt replies. Yes, I have a socketed chip. Unfortunately it is a 32 PIN DIP package and the chips found at digikey are using an PLCC package. Atmel seem to have replacement chips, but they are packaged in either PLCC or TSOP... Things get complicated. Are socket converters available on the market? -- Svante Signell [EMAIL PROTECTED] ___ Linuxbios mailing list Linuxbios@clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios
Is 440BX ported to Linuxbios v2?
Hello, I have been communicating with the Linuxbios mailing list on and off (mostly off lately). I'm interested to try out the linuxBIOS on my old dual CPU board MSI-6120. The current MSI/AMI BIOS V2.0 does not support newer CPUs than Coppermine. Currently I have two old PII processors (Mendocino) installed and would like to upgrade to one Celeron 2 or dual PIIIs (Tualatin) using one or two SLOT-T slot 1 to socket 370 adapters. A 1.3GHz Celeron 2 boots with this new CPU but runs _extremely_ slow, at aronund 8MHz compared to expected 1.3GHz. This has been reported before in the thread 'Level 2 cache activation code' in late 2003. Where can I purchase a replacement BIOS chip? Placed in a socket on the main board is a 2x16 pin DIL labeled: 686 AMI BIOS 1995 CS 9. lspci shows: :00:00.0 Host bridge: Intel Corp. 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (rev 03) :00:01.0 PCI bridge: Intel Corp. 440BX/ZX/DX - 82443BX/ZX/DX AGP bridge (rev 03) :00:07.0 ISA bridge: Intel Corp. 82371AB/EB/MB PIIX4 ISA (rev 02) :00:07.1 IDE interface: Intel Corp. 82371AB/EB/MB PIIX4 IDE (rev 01) :00:07.2 USB Controller: Intel Corp. 82371AB/EB/MB PIIX4 USB (rev 01) :00:07.3 Bridge: Intel Corp. 82371AB/EB/MB PIIX4 ACPI (rev 02) :00:0f.0 Ethernet controller: 3Com Corporation 3c905B 100BaseTX [Cyclone] (rev 30) :00:10.0 Multimedia audio controller: Creative Labs SB Live! EMU10k1 (rev 05) :00:10.1 Input device controller: Creative Labs SB Live! MIDI/Game Port (rev 05) :01:00.0 VGA compatible controller: Matrox Graphics, Inc. MGA G400 AGP (rev 04) -- Svante Signell [EMAIL PROTECTED] ___ Linuxbios mailing list Linuxbios@clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: Can I execute a linuxbios image from linux?
On Fri, 2004-04-02 at 20:08, ron minnich wrote: On Fri, 2 Apr 2004, Svante Signell wrote: Thank you for the information. I'll check if this equipment is usable for my hardware. The crucial thing is whether the BIOS chip is socketed or not. We'll see, at least I know the size is 2Mbit, since the latest BIOS binary (A6120IMS.200) supported by MSI is 261144kbyte. Does anybody Sorry my mistake: 261.144 kbyte = 256 Kibyte = 2 Mibit = 2.097152 Mbit. 2 Mbit == 256K, too small for a kernel. I thought the LinuxBIOS was parts from of a kernel. What size is needed? It seems that the flash sizes are 1,2 and 4 Mibit, at least for older boards. Have I missed something here? I think Bari Ari will tell us if you can get that part off :-) Is he on this list? However, according to the answers obtained so far there seems to be no interest at all to make LinuxBIOS(V2) work with older motherboards, such as the widely spread 440BX-based ones. As mentioned in earlier postings, I'm willing to be a test pilot for this port, but I cannot do it without help from the LinuxBIOS developers. LinuxBIOS generally works fine with 440BX boards. Do you mean the target for 440BX in freebios version1, freebios/util/config/l440bx-test12.config? Do the latest kernels,e.g. 2.4.25 still have to be patched with the 2.4.13 patch, freebios/src/kernel_patches/linux-2.4.13-l440gx.diff? Is the onboard SCSI and dual CPU supported? ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: Can I execute a linuxbios image from linux?
Kevin, Thank you for the information. I'll check if this equipment is usable for my hardware. The crucial thing is whether the BIOS chip is socketed or not. We'll see, at least I know the size is 2Mbit, since the latest BIOS binary (A6120IMS.200) supported by MSI is 261144kbyte. Does anybody have experience with removing a soldered chip on a motherboard without destroying anything? I sent in an update enquiry about my BIOS version (AMI) to www.esupport.com and they offered me to purchase a new one, supporting modern CPUs and up to Windows XP, for around the same price as the BIOS saviour board costs. Since I'm only running Linux on this computer, I'm not interested in booting other OSes. I'm mostly interested to be able to upgrade the box with faster (dual) processors. However, according to the answers obtained so far there seems to be no interest at all to make LinuxBIOS(V2) work with older motherboards, such as the widely spread 440BX-based ones. As mentioned in earlier postings, I'm willing to be a test pilot for this port, but I cannot do it without help from the LinuxBIOS developers. Thanks, Svante On Thu, 2004-04-01 at 02:46, Kevin O'Connor wrote: On Wed, Mar 31, 2004 at 09:30:16PM +0200, Svante Signell wrote: Is there a way to try out a new BIOS without risking to end up with an unbootable main-board, ethernet, serial port, some special card connected to the south-bridge (PIIX4) e.g. a special PCI/ISA card, etc? Other solutions including soldering, EEPROM programming devices, etc? A number of people are using the BIOS Savior product with success. See: http://www.ioss.com.tw/eg/rd1/index.html Depending on which part you need, you can mail order it from mwave.com, pcmods.com, or probably a bunch of other places. -Kevin ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Can I execute a linuxbios image from linux?
Hello, I'm trying to upgrade the CPU on a 440BX dual board MSI-6210 from dual Celerons (Mendocino) to a single Celeron2 (Tualatin) using a socket 370 to slot 1 adapter, SLOT-T from Upgradeware. On other 440BX based motherboards, this works perfectly. Two computers I have upgraded are a QDI BrillianX 1 based box and the Compaq 5670. The lates BIOS for the 6120 does not support Coppermine or Tualatin processors. With the 6120, I get a successful boot too, but the effective speed is 7 MHz as compared to expected 1.3GHz (measured with lmbench). I have made a small kernel module testing the level 2 cache activation code, without any improvements. Also mtrr seems to be set up correctly. Now I would like to execute a full linuxbios image after boot to linux, in order to avoid the problem of re-flashing the BIOS. Is this possible? The Upgradeware support pages mentions that the IO chips have to be of correct type for a similar single CPU board, the MSI-6119 to uork with the SLOT-T adapter. What function does the IO chip have, and how can in be tested? Thanks, Svante ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: Can I execute a linuxbios image from linux?
OK, maybe my question is OT, but not completely OT. Maybe I can try to move the L440BX stuff from V1 to V2, and when it compiles get help from the list after that? Is there a way to try out a new BIOS without risking to end up with an unbootable main-board, ethernet, serial port, some special card connected to the south-bridge (PIIX4) e.g. a special PCI/ISA card, etc? Other solutions including soldering, EEPROM programming devices, etc? What is the function of th IO chip? Thanks, Svante On Wed, 2004-03-31 at 16:39, ron minnich wrote: I'm not sure you're going to get much help here, as your question is kind of off topic for this list, but we'll see. ron ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: Level 2 cache activation code?
On Mon, 2003-12-01 at 00:47, Denis Dowling wrote:
Hi Svante,
- Original Message -
From: Svante Signell [EMAIL PROTECTED]
To: ron minnich [EMAIL PROTECTED]
Cc: Takeshi Sone [EMAIL PROTECTED]; [EMAIL PROTECTED]
Sent: Monday, December 01, 2003 10:14 AM
Subject: Re: Level 2 cache activation code?
The processor is an 1.3GHz Celeron Tualatin, with CPUID: 6b0. According
to the code in l2_cache.c newer CPUs than Coppermine (680) does not need
the L2 setup code. Is this the case?
This was based on the assumption that all CPU from the coppermine forward
had the cache integrated onto the CPU die. Is this the case with your CPU.
Is it just a single large CPU on the slot1 pcb or does there look to be
cache chips mounted on the board as well?
The CPU is placed on a socket 370 to slot 1 adapter (SLOT-T) from Upgradeware.
No, there are no external cache chips on the MOBO. BTW, the MOBO is a dual CPU 82443BX
board (MSI-6120). It runs perfectly well with dual Celerons (Mendocino). Also, the CPU
placed on the SLOT-T adapter works perfectly well with other (single CPU) boards.
if (signature 0x630 || signature = 0x680) {
printk_debug(CPU signature of %x so no L2 cache configuration\n,
signature);
goto done;
You could always just drop this test and see what happens later. If the CPU
does have external cache chips then this code might just work in
initiallising the cache.
I have disabled the test and it seems the cache activation seem to work,
see below. The slowness remains however :-(
Dec 4 14:39:56 cl-dual kernel: Configuring L2 cache...Disable Cache
Dec 4 14:39:56 cl-dual kernel: rdmsr(0x17) = 0, 8432
Dec 4 14:39:56 cl-dual kernel: L2 Cache latency is 1
Dec 4 14:39:56 cl-dual kernel: Sending 0 to set_l2_register4
Dec 4 14:39:56 cl-dual kernel: L2 ECC Checking is enabled
Dec 4 14:39:56 cl-dual kernel: L2 Physical Address Range is 512M
Dec 4 14:39:56 cl-dual kernel: Maximum cache mask is 2000
Dec 4 14:39:56 cl-dual kernel: L2 Cache Mask is 0
Dec 4 14:39:56 cl-dual kernel: read_l2(2) = 0
Dec 4 14:39:56 cl-dual kernel: write_l2(2) = 0
Dec 4 14:39:56 cl-dual kernel: Enable Cache
Dec 4 14:39:56 cl-dual kernel: L2 Cache size is 256K
Dec 4 14:39:56 cl-dual kernel: L2 Cache lines initialized
Dec 4 14:39:56 cl-dual kernel: Disable Cache
Dec 4 14:39:56 cl-dual kernel: Enable Cache
Dec 4 14:39:56 cl-dual kernel: done.
Dec 4 14:39:56 cl-dual kernel: cache_on installed
Looks fine. Turn on as much debugging in the l2_cache code as possible and
post to me and I will decode. Need to be able to see all of the printk_debug
messages.
Regards,
Denis
What is wrong here:
Not caches
Not mtrr
microcode??
anything else??
HW fault, i.e. the VRM does not work as expected, even though lm-sensors
are reporting correct voltages.
The BIOS is not supporting Coppermine and later CPUs. AMI BIOS V2.0 from
(MSI)
Soon giving up...
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Re: Level 2 cache activation code?
I have now made a small kernel module based on l2_cache.c giving the
following output:
Nov 30 17:46:56 cl-dual kernel: Configuring L2 cache...CPU signature of
6b0 so no L2 cache configuration
Nov 30 17:46:56 cl-dual kernel: Enable Cache
Nov 30 17:46:56 cl-dual kernel: done.
Nov 30 17:46:56 cl-dual kernel: cache_on installed
No speed-up seen. Extremely slow as before. Any hints? mtrr is OK, I
believe. Is it the microcode??
The processor is an 1.3GHz Celeron Tualatin, with CPUID: 6b0. According
to the code in l2_cache.c newer CPUs than Coppermine (680) does not need
the L2 setup code. Is this the case?
if (signature 0x630 || signature = 0x680) {
printk_debug(CPU signature of %x so no L2 cache configuration\n,
signature);
goto done;
I few questions:
1. Does a kernel module have to be a standalone object without linking
stage?
2. How to add libraries to link with, if unresolved externals show up.
3. How to create a kernel module consisting of more than one object
file. Now I include the needed source files into the main one.
4. The cflags used are:
CFLAGS = -D__KERNEL__ -DMODULE -I ./include -I$/usr/src/linux/include -I
/usr/src/kernel-headers-2.4.22-1 -O2 -Wall -g
5. My module code looks like:
cat cache_on.c
#include linux/module.h
#include linux/kernel.h
(#include source files and other header files)
#define PFX cache_on
int init_module(void)
{
p6_configure_l2_cache();
printk(KERN_INFO PFX installed \n);
return 0;
}
void cleanup_module(void)
{
printk(KERN_INFO PFX removed\n);
}
On Tue, 2003-11-25 at 22:56, Svante Signell wrote:
Ron and Takeshi,
Thanks for the tip. I'll try that next. Any pointers how to create a
kernel module? So far I have only been writing code for user space.
On Tue, 2003-11-25 at 22:06, ron minnich wrote:
what I did to test this code was to build a kernel module for my linux,
with this code inside, and insmod the kernel module.
ron
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Re: Level 2 cache activation code?
Do I need to use gcc-2.95.x instead of gcc-3.3.2 to make the inline
assembly run OK? Or is there something about 16bit mode versus 32bit
mode?
On Sun, 2003-11-16 at 11:14, Svante Signell wrote:
I did boot another kernel and for that kernel there was one entry for
mtrr, so this seems to work. However, now I have tried executing both
the mtrr and cache activation code, and when coming to any inline
assembly code the program exits with a segfault :( All commented out
calls have been tried one after the other by single-stepping with gdb.
Below is the main progam I used:
#include mem.h
main()
{
struct mem_range mem;
int res = iopl(3);
if(res) {error();exit(-1);}
// cache_enable();
// p6_configure_l2_cache();
cache_on(mem);
}
On Sat, 2003-11-15 at 20:54, ron minnich wrote:
On Sun, 16 Nov 2003, Takeshi Sone wrote:
On Fri, Nov 14, 2003 at 10:46:00PM +0100, Svante Signell wrote:
# Faulty system:
cat /proc/mtrr
cat: /proc/mtrr: No such file or directory
I guess the BIOS does not initialize the MTRR, and all RAM is uncached.
(MTRR is the registers that tell CPU where to cache)
no, even if bios does not set mtrr, those registers exist, and are
readable. Something weird is going on here!
ron
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Re: Level 2 cache activation code?
I did boot another kernel and for that kernel there was one entry for
mtrr, so this seems to work. However, now I have tried executing both
the mtrr and cache activation code, and when coming to any inline
assembly code the program exits with a segfault :( All commented out
calls have been tried one after the other by single-stepping with gdb.
Below is the main progam I used:
#include mem.h
main()
{
struct mem_range mem;
int res = iopl(3);
if(res) {error();exit(-1);}
// cache_enable();
// p6_configure_l2_cache();
cache_on(mem);
}
On Sat, 2003-11-15 at 20:54, ron minnich wrote:
On Sun, 16 Nov 2003, Takeshi Sone wrote:
On Fri, Nov 14, 2003 at 10:46:00PM +0100, Svante Signell wrote:
# Faulty system:
cat /proc/mtrr
cat: /proc/mtrr: No such file or directory
I guess the BIOS does not initialize the MTRR, and all RAM is uncached.
(MTRR is the registers that tell CPU where to cache)
no, even if bios does not set mtrr, those registers exist, and are
readable. Something weird is going on here!
ron
is going on here.
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Re: Level 2 cache activation code?
Hi, I have now run the lmbench3-0-a3 tests. For the correctly working 1.4 GHz Tualatin CPU the latency numbers shows jumps from 2ns to 6ns at 16k array size and from 6ns to 120ns at 265k array size. I assume this indicates correctly working level 1 and 2 caches. For the erroneous motherboard with a 1.3GHz Tualatin CPU the numbers are around 400ns independent of array size. The only thing changig is that the latency numbers increase to 440-460ns for large values of the stride. My interpretation is that not even the L1 cache is working properly. All other tests indicate a _very_ slow CPU, around 7MHz is measured by lmbench (BTW how good is this value?) compared to the expected 1.3GHz. Two questions immediately arise. 1. Is this slowness reasonable if _no- caches are working properly? 2. If there is a problem with the on-chip voltage regulator and the CPU clock speed is really 7MHz, as measured by lmbench, can the CPU operate properly at this low speed. I thought there was a _lower_ limit as well as an upper limit for the operating frequency? Svante On Fri, 2003-11-07 at 06:04, ron minnich wrote: Those lm bench memory tests with the plots of memory access times will show you l1, l2, and memory boundaries. ron ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: Level 2 cache activation code?
On Fri, 2003-11-14 at 08:41, Takeshi Sone wrote: On Fri, Nov 14, 2003 at 08:26:55AM +0100, Svante Signell wrote: For the erroneous motherboard with a 1.3GHz Tualatin CPU the numbers are around 400ns independent of array size. The only thing changig is that the latency numbers increase to 440-460ns for large values of the stride. My interpretation is that not even the L1 cache is working properly. All other tests indicate a _very_ slow CPU, around 7MHz is measured by lmbench (BTW how good is this value?) compared to the expected 1.3GHz. Two questions immediately arise. 1. Is this slowness reasonable if _no- caches are working properly? 2. If there is a problem with the on-chip voltage regulator and the CPU clock speed is really 7MHz, as measured by lmbench, can the CPU operate properly at this low speed. I thought there was a _lower_ limit as well as an upper limit for the operating frequency? What do these commands say? cat /proc/mtrr cat /proc/cpuinfo Normal output: 1.4GHz Tualatin cat/proc/mtrr: reg00: base=0x ( 0MB), size= 256MB: write-back, count=1 reg01: base=0xe400 (3648MB), size= 8MB: write-combining, count=1 # Faulty system: cat /proc/mtrr cat: /proc/mtrr: No such file or directory Faulty system: $ cat /proc/cpuinfo processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 11 model name : Intel(R) Celeron(TM) CPU1300MHz stepping: 4 cpu MHz : 1340.197 cache size : 256 KB fdiv_bug: no hlt_bug : no f00f_bug: no coma_bug: no fpu : yes fpu_exception : yes cpuid level : 2 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 mmx fxsr sse bogomips: 2641.10 ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: Level 2 cache activation code?
I still do get a segfault when trying to activate the L2 cache, in the
cache_enable() inline assembly routine in l2_cache.c Anything else
neeeded to run this program inside GNU/Linux
On Fri, 2003-11-07 at 15:42, steven james wrote:
Greetings,
Yes, anything non 0 is true. Testing that way (or if(res0) when the
function is to return a count) generally helps to catch wierdness (in the
bad old days, some functions returned -errno or even errno on error but
always 0 on success, this catches all of those cases).
G'day,
sjames
On Thu, 2003-11-06 at 14:59, steven james wrote:
Greetings,
To run that code inside linux, you need to add a call to iopl to
allow
direct hardware access like:
res = iopl(3);
if(res) {
report_error();
exit(-1);
}
or something to that effect.
G'day,
sjames
On Fri, 7 Nov 2003, Svante Signell wrote:
Steven,
Thanks for the tip, I'll try adding this in. Preliminary estimations
with lmbench-2.0 shows like the problems are probably due to the missing
L2 cache. I'm currently compiling and running running lmbench-3, but
with an efficient speed of 7MHz instead of 1300MHz, things take time...
...
5. If the slowness is not due to a disabled L2 cache (how to test this
properly btw?), can the problems be solved by tying with the mtrr or
microcode update code?
6. Maybe the problem is still hardware related, like the on-board
voltage regulator for the CPU is not working properly, even if there are
no indications at all from the on board sensors. However, if the
problems are software related and can be solved, do you think it is
feasible to replace the AMI BIOS with LinuxBIOS? The probability of
getting an updated BIOS from MSI supporting Coppermine and Tualatin
processors is probably zero.
Thanks,
Svante
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Re: Level 2 cache activation code?
Hi, Sorry for taking up this thread again but now I have made a test of the l2_cache activation code and have some further questions. The files put together to make things build are l2_cache.c, printk.c, vsprintf.c, subr.c and corresponding header files from the linuxbios CVS tree. For subr.c I had to add an include (#include sys/io.h) to get outb defined for linking. The result so far is a segfault, in the cache_enable() inline assembly routine in l2_cache.c) 0. How to test this code after a _slow_ boot outside the BIOS? Is single user mode sufficient, i.e. init 1? 1. How are these printk statements supposed to work? Is the output directed to some system logfile, like kern.log? How to define this logfile etc. What to change if I want to log debug outputs to the standard out and/or standard err? I don't find any output when running the main program, neither in the system log files or on the screen. 2. Any special compiler and linker switches needed, like -nostdinc, -nostdlib, -nostartfiles, etc? Your build system is Python based, right, so I cannot easily look at Makefiles in the CVS tree. 3. I found where the program halts with gdb and compiling with debug set. One way to trace is single stepping in gdb etc. What is supposed to happen when the DEBUG is defined in l2_cache.c? 4. You state that the L2 cache stuff is only needed for P2 CPUs, not for P3 type CPUs, such as Coppermine or Tualatin. I'm testing with a Celeron 2 CPU (Tualatin), which is of P3 type. What if the BIOS does not recognise the CPU and disables the L2 cache? People claim that AMI BIOSes work this way. It the enabling code sufficient to make things work. 5. If the slowness is not due to a disabled L2 cache (how to test this properly btw?), can the problems be solved by tying with the mtrr or microcode update code? 6. Maybe the problem is still hardware related, like the on-board voltage regulator for the CPU is not working properly, even if there are no indications at all from the on board sensors. However, if the problems are software related and can be solved, do you think it is feasible to replace the AMI BIOS with LinuxBIOS? The probability of getting an updated BIOS from MSI supporting Coppermine and Tualatin processors is probably zero. Thanks, Svante On Wed, 2003-10-01 at 15:40, ron minnich wrote: On Wed, 1 Oct 2003, Svante Signell wrote: i) Does LinuxBIOS work for 440BX-based mother-boards, single and dual? Downloading the code from CVS shows support for Intel L440GX+ and a patch for linux-2.4.13, not 440BX or kernels later than 2.4.13. Also, I did not find anything about MSI mainboards. single are tested. Dual I don't know. ii) Does the cache activation code work for Mendocino, Coppermine, Tualatin and newer Intel processors? Will it work for the VIA C3 Nehemiah? It was only needed for PII. Coppermine and later -- Just works. It is extremely cpu-dependent. iii) How much of the boot process in GNU/Linux the BIOS responsible for? I thought that the kernel was only dependent on the BIOS for a few functions, such as different HW initialisations: CPU, memory, disks, etc compared to Windows 9x etc. Any pointers? that's about right. I will try. Which files do I need in addition to src/cpu/p6/l2_cache.c? none. You have to turn that back into a main() but it should be fine. With risks I meant the chance of being left with a dead motherboard... I'm always nervous when flashing the BIOS that something will happen, for example a sudden power loss, regardless of where the BIOS originates from. never do this kind of work without a spare bios part. Never. BTW: Why is this work called LinuxBIOS (except maybe for historical reasons). Will other OSes (eg GNU/Hurd) boot with LinuxBIOS now or in the future? Maybe then something like FreeBIOS should be used instead. It was called linuxbios for a simple reason: linux was going to be the bios. linux would be in flash, linux would boot the oses. Small flashes have caused changes in course in some cases, but the name has stuck anyway. Now that vendors have joined in, changing the name would be hard. ron ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: Level 2 cache activation code?
Ron, Thank you for your reply. Maybe there is hope after all. On Wed, 2003-10-01 at 01:34, ron minnich wrote: On Tue, 30 Sep 2003, Svante Signell wrote: i) Does this code work for 440BX motherboards? it's processor-dependent, 440bx or not is not an issue. Thanks for the info. To clarify I'll split the question into three: i) Does LinuxBIOS work for 440BX-based mother-boards, single and dual? Downloading the code from CVS shows support for Intel L440GX+ and a patch for linux-2.4.13, not 440BX or kernels later than 2.4.13. Also, I did not find anything about MSI mainboards. ii) Does the cache activation code work for Mendocino, Coppermine, Tualatin and newer Intel processors? Will it work for the VIA C3 Nehemiah? iii) How much of the boot process in GNU/Linux the BIOS responsible for? I thought that the kernel was only dependent on the BIOS for a few functions, such as different HW initialisations: CPU, memory, disks, etc compared to Windows 9x etc. Any pointers? ii) Is it possible to extract this code and try out after the kernel has booted (slowly), to verify my assumption? yes, we tested it that way. You can try it. I will try. Which files do I need in addition to src/cpu/p6/l2_cache.c? iii) Is there some other tool available for cache activation? Not sure. iv) One interesting continuation would be to try to replace the MSI (AMI) BIOS with linuxbios, but as a first step I think this would be a little risky. well, so far, given the track record of many of these BIOSes, I'm not sure how risky that is ... With risks I meant the chance of being left with a dead motherboard... I'm always nervous when flashing the BIOS that something will happen, for example a sudden power loss, regardless of where the BIOS originates from. ron BTW: Why is this work called LinuxBIOS (except maybe for historical reasons). Will other OSes (eg GNU/Hurd) boot with LinuxBIOS now or in the future? Maybe then something like FreeBIOS should be used instead. Thanks, Svante ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Level 2 cache activation code?
Hello, I have recently upgraded my dual MSI-6120 from 2xCeleron (Mendocino) [EMAIL PROTECTED] with 2xMSI-6905 slot 370 to slot 1 adapters to one Celeron2 1.3GHz (Tualatin) using a Slot-T adapter card. The plan is to equip the mobo with 2xPIII or preferably 2xVIA C3 Nehemiah (when SMP capable). The problem is that the latest MSI BIOS (v2.0) for the mobo does not support Coppermine/Tualatin processors. The single GNU/Linux kernels boot without problems but _extremely_ slowly, at least with a speed reduction by a factor 10. hdparm -tT gives around 20/2 compared with 250/25 with the Mendocino CPU(s). For example uncompressing the kernel takes minute(s) compared to seconds. After some trials and web searching I suspect that the problem is with the level 2 cache not activated by the BIOS. I see the you have code in the linuxbios for activating caches. i) Does this code work for 440BX motherboards? ii) Is it possible to extract this code and try out after the kernel has booted (slowly), to verify my assumption? iii) Is there some other tool available for cache activation? iv) One interesting continuation would be to try to replace the MSI (AMI) BIOS with linuxbios, but as a first step I think this would be a little risky. Any ideas? Thanks, Svante ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
