ram init
Does anyone know if the raminit.c under intel/E7501 is stable enough? I am having a problem with the system reseting when it jumps to the first address in the ram. Could the procedures of writing NorthBrige registers have problems? thanks, Gin ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: ram init
Greetings, It's been a while since I've looked at it, but when I last looked, it did sometimes need power cycled to restart. I worked around that by making the kernel reboot by writing 0x0e to port 0xcf9. That causes the southbridge to do a 3 second power off. G'day, sjames On Fri, 5 Nov 2004, Gin Lin wrote: > Does anyone know if the raminit.c under intel/E7501 is stable enough? I am > having a problem with the system reseting when it jumps to the first address > in the ram. Could the procedures of writing NorthBrige registers have > problems? > > thanks, > Gin > ___ > Linuxbios mailing list > [EMAIL PROTECTED] > http://www.clustermatic.org/mailman/listinfo/linuxbios > | | ||| by Linux Labs International, Inc. Steven James, CTO 55 Marietta Street Suite 1830 Atlanta, Ga 30303 866 824 9737 support ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Status AMD64 ram init
Excerpt from current solo build: LinuxBIOS-1.1.6.0-Fallback Fr Mär 19 14:43:18 CET 2004 starting... setting up resource mapdone. ht reset - LinuxBIOS-1.1.6.0-Fallback Fr Mär 19 14:43:18 CET 2004 starting... setting up resource mapdone. Ram1.00 Ram2.00 Bad SPD value Using the default hynix PC2100U 256MB DDR 266MHz CL2.5 modules. I'm building a debug image which dumps the spd roms... Stefan -- Stefan Reinauer, SUSE LINUX AG Head of Architecture Development ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
i845 ddr ram init
(1)I disabled i786/earlymtrr, RAM NOP ok (2)After executing original bios, RAM NOP couldn't pass. Maybe I should set mtrr correctly. zhu ___ Do you Yahoo!? Declare Yourself - Register online to vote today! http://vote.yahoo.com ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: Status AMD64 ram init
* Stefan Reinauer <[EMAIL PROTECTED]> [040319 15:38]: > Ram1.00 > Ram2.00 > Bad SPD value low = spd_read_byte(device, 6); /* (low byte) */ if (low < 0) goto hw_err; value = value | (low & 0xff); if ((value != 72) && (value &= 64)) goto val_err; ^^^ It seems this should be value != 64 as well? Stefan -- Stefan Reinauer, SUSE LINUX AG Head of Architecture Development ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: i845 ddr ram init
On Tue, 28 Sep 2004, zhu shi song wrote: > (1)I disabled i786/earlymtrr, RAM NOP ok > (2)After executing original bios, RAM NOP couldn't > pass. sounds like it, MTRRs should really not be on during DDR init in the DRAM space. What are your current settings? ron ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
EPIA-M DDR ram init progress
As a recap I was trying to get 2 specific DDR modules working with the epia-m. One has ICT chips and the other has GET chips. The ICT module works with the hardcoded dram configuration, but the GET module doesn't. ICT = 1 bank 128M colbits = 10 GET = 2 banks 64M colbits = 9 I had tried hardcoding the dram settings to the ones award bios uses for the GET module, but it wasn't working. I figured out what the problem was. I need to do the ddr setup for each bank on the ddr module, not just the first one. The hardcoded settings correspond to a ddr with just a single bank. SPD contents is very easy to access. The epia-m code is including src/northbridge/via/vt8623/raminit.inc to initialize ram. I found problems with this, the jedec ddr init spec sequence calls for reads of the ddr memory, this source actually does some writes. I'm wondering what the preferred way of implementing spd for epia-m would be. Should instead of including src/northbridge/via/vt8623/raminit.inc I put that code in with the epia-m code, mix it with the smbus SPD read code, and leave the result in the epia-m tree? Or should I modify the src/northbridge/via/vt8623/raminit.inc file directly? I don't see how that can work since the SMBUS/SPD is accessed with the vt8235 registers, but the DDR dram control registers are part of the northbridge. I can rebuild linuxbios to have it work hardcoded for either memory module type and it works fine, and I can probably live with this state until someone else gets SPD working if it might happen within a month or two. Otherwise I'll probably have to tackle it myself. VIA's Bios porting guide for the nortbridge on the epia-m seems very explicit on how to configure the ddr memory based on the SPD settings. Implementing it should just be a matter of grinding through their flow charts. It's simplified because it only has to deal with DDR memory. -Dave ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: Status AMD64 ram init [resolved]
* Stefan Reinauer <[EMAIL PROTECTED]> [040319 16:50]: > low = spd_read_byte(device, 6); /* (low byte) */ > if (low < 0) goto hw_err; > value = value | (low & 0xff); > if ((value != 72) && (value &= 64)) goto val_err; > ^^^ > It seems this should be value != 64 as well? works and commited. Stefan -- Stefan Reinauer, SUSE LINUX AG Head of Architecture Development ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: Status AMD64 ram init [resolved]
Stefan Reinauer <[EMAIL PROTECTED]> writes: > * Stefan Reinauer <[EMAIL PROTECTED]> [040319 16:50]: > > low = spd_read_byte(device, 6); /* (low byte) */ > > if (low < 0) goto hw_err; > > value = value | (low & 0xff); > > if ((value != 72) && (value &= 64)) goto val_err; > > ^^^ > > It seems this should be value != 64 as well? > > works and commited. Thanks. This appears to fix all of Eric's typo's week :) Eric ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: EPIA-M DDR ram init progress
Hi Dave, > As a recap I was trying to get 2 specific DDR modules working with the > epia-m. One has ICT chips and the other has GET chips. The ICT module works > with the hardcoded dram configuration, but the GET module doesn't. > ICT = 1 bank 128M colbits = 10 > GET = 2 banks 64M colbits = 9 Same here, but if I set 0x58 to 0xc0, both works. > I had tried hardcoding the dram settings to the ones award bios uses for the > GET module, but it wasn't working. I figured out what the problem was. > I need to do the ddr setup for each bank on the ddr module, not just the > first one. The hardcoded settings correspond to a ddr with just a single bank. That's right because EPIA-M has only 1 ddr bank. If some custom has more that 1 bank, I can check it. > SPD contents is very easy to access. The epia-m code is including > src/northbridge/via/vt8623/raminit.inc > to initialize ram. I found problems with this, the jedec ddr init spec > sequence calls for reads of the ddr memory, this source actually does some > writes. Thanks for the catch. It has been fixed. The funny thing is writes work, too!!! > I'm wondering what the preferred way of implementing spd for epia-m would > be. Should instead of including src/northbridge/via/vt8623/raminit.inc I put > that code in with the epia-m code, mix it with the smbus SPD read code, > and leave the result in the epia-m tree? Or should I modify the > src/northbridge/via/vt8623/raminit.inc file directly? I don't see how that > can work since the SMBUS/SPD is accessed with the vt8235 registers, but the > DDR dram control registers are part of the northbridge. SMBUS/SPD should be in southbridge like other platforms. Then, mainboard's Config can include those code such that raminit.inc can call later. E7500 is a very nice reference. -Andrew -- Andrew Ip Email: [EMAIL PROTECTED] Tel:(852) 2542 2046 Fax:(852) 2542 2036 Mobile: (852) 9201 9866 Cwlinux Limited Unit 202B 2/F Lai Cheong Factory Building, 479-479A Castle Peak Road, Lai Chi Kok, Kowloon, Hong Kong. Tel: (852)2542 2046 Fax: (852)2542 2036 For public pgp key, please obtain it from http://www.keyserver.net/en. ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: EPIA-M DDR ram init progress
On Tue, 22 Jul 2003, Andrew Ip wrote: > > SPD contents is very easy to access. The epia-m code is including > > src/northbridge/via/vt8623/raminit.inc > > to initialize ram. I found problems with this, the jedec ddr init spec > > sequence calls for reads of the ddr memory, this source actually does some > > writes. > Thanks for the catch. It has been fixed. The funny thing is writes work, > too!!! interesting. The Intel 430TX part specified reads, but would hang unless you did writes. ron ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
V2 EPIA - IDE compat mode, RAM init, and early MTRR
Attached patch fixes IDE compatibility mode (so FILO works),
and RAM initialization, so the DIMM on the second slot works.
SPD is not used by this patch, we have to figure out how to
type MA mapping by SPD (see the comment in the code).
Maybe I will work on SPD-based RAM timing.
earlymtrr.c should go to src/cpu/p6 so the XIP works.
The change in src/cpu/p6/mtrr.c just reverse the change made by
Eric for K8..
--
Takeshi
? src/cpu/p6/earlymtrr.c
? targets/epia
? targets/via/epia/epia
Index: src/cpu/p6/mtrr.c
===
RCS file: /cvsroot/freebios/freebios2/src/cpu/p6/mtrr.c,v
retrieving revision 1.5
diff -u -r1.5 mtrr.c
--- src/cpu/p6/mtrr.c 11 Oct 2003 06:20:17 - 1.5
+++ src/cpu/p6/mtrr.c 19 Oct 2003 19:24:03 -
@@ -92,7 +92,7 @@
base.lo = basek << 10;
if (sizek < 4*1024*1024) {
- mask.hi = 0x0FF;
+ mask.hi = 0x0F;
mask.lo = ~((sizek << 10) -1);
}
else {
Index: src/mainboard/via/epia/Config.lb
===
RCS file: /cvsroot/freebios/freebios2/src/mainboard/via/epia/Config.lb,v
retrieving revision 1.5
diff -u -r1.5 Config.lb
--- src/mainboard/via/epia/Config.lb1 Oct 2003 23:18:14 - 1.5
+++ src/mainboard/via/epia/Config.lb19 Oct 2003 19:24:03 -
@@ -53,8 +53,8 @@
##
## Clean up the motherboard id strings
##
-option MAINBOARD_PART_NUMBER="HDAMA"
-option MAINBOARD_VENDOR="ARIMA"
+option MAINBOARD_PART_NUMBER="EPIA"
+option MAINBOARD_VENDOR="VIA"
###
### LinuxBIOS layout values
@@ -137,7 +137,7 @@
makerule ./failover.inc
depends "./failover.E ./romcc"
- action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+ action "./romcc -O2 -mcpu=c3 -o failover.inc --label-prefix=failover
./failover.E"
end
makerule ./auto.E
@@ -146,7 +146,7 @@
end
makerule ./auto.inc
depends "./auto.E ./romcc"
- action "./romcc -O ./auto.E > auto.inc"
+ action "./romcc -O2 -mcpu=c3 -o auto.inc ./auto.E"
end
##
@@ -220,7 +220,7 @@
# pci 0:11.6
# pci 0:12.0
register "enable_usb" = "0"
- register "enable_native_ide" = "1"
+ register "enable_native_ide" = "0"
register "enable_com_ports" = "1"
register "enable_keyboard" = "0"
register "enable_nvram" = "1"
@@ -236,4 +236,3 @@
##
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
-
Index: src/mainboard/via/epia/auto.c
===
RCS file: /cvsroot/freebios/freebios2/src/mainboard/via/epia/auto.c,v
retrieving revision 1.12
diff -u -r1.12 auto.c
--- src/mainboard/via/epia/auto.c 3 Oct 2003 02:53:01 - 1.12
+++ src/mainboard/via/epia/auto.c 19 Oct 2003 19:24:03 -
@@ -11,6 +11,7 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/via/vt8601/raminit.h"
+#include "cpu/p6/earlymtrr.c"
/*
*/
void udelay(int usecs)
@@ -77,7 +78,7 @@
/* we do this here as in V2, we can not yet do raw operations
* to pci!
*/
- dev++; /* ICKY */
+ dev += 0x100; /* ICKY */
pci_write_config8(dev, 0x42, 0);
}
@@ -99,10 +100,10 @@
outb(5, 0x80);
enable_vt8231_serial();
- enable_mainboard_devices();
uart_init();
console_init();
+ enable_mainboard_devices();
enable_smbus();
enable_shadow_ram();
/*
@@ -134,4 +135,5 @@
ram_check(check_addrs[i].lo, check_addrs[i].hi);
}
#endif
+ early_mtrr_init();
}
Index: src/northbridge/via/vt8601/raminit.c
===
RCS file: /cvsroot/freebios/freebios2/src/northbridge/via/vt8601/raminit.c,v
retrieving revision 1.11
diff -u -r1.11 raminit.c
--- src/northbridge/via/vt8601/raminit.c3 Oct 2003 02:53:01 - 1.11
+++ src/northbridge/via/vt8601/raminit.c19 Oct 2003 19:24:03 -
@@ -121,7 +121,7 @@
uint8_t c, r;
print_err("vt8601 init starting\n");
- north = pci_locate_device(PCI_ID(0x1106, 0x8601), 0);
+ //north = pci_locate_device(PCI_ID(0x1106, 0x8601), 0);
north = 0;
print_err_hex32(north);
print_err(" is the north\n");
@@ -279,6 +279,117 @@
*/
}
+static unsigned long find_size(unsigned long base)
+{
+unsigned long i;
+unsigned long maximum;
+volatile long *p;
+
+/* First, see if there is any RAM. */
+p = (long *) base;
+*p = 0x12345678;
+p = (long *) (base + 8);
+*p = 0x87654321;
+p = (long *) base;
+if (*p != 0x12345678)
+return 0; /* No memory */
+
+maximum = (0xffUL << 23) - base;
+
+/* Write to addresses with only one address bit on,
+ * in increasing orde
Re: V2 EPIA - IDE compat mode, RAM init, and early MTRR
Takeshi, I have put your changes in (earlymtrr.c, etc.) except for raminit. We should talk about that offline, but I want to better understand what you are doing, since two slots was working for me. ron ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: V2 EPIA - IDE compat mode, RAM init, and early MTRR
On Mon, Oct 20, 2003 at 03:48:18PM -0600, ron minnich wrote:
> Takeshi, I have put your changes in (earlymtrr.c, etc.) except for
> raminit. We should talk about that offline, but I want to better
> understand what you are doing, since two slots was working for me.
Besides raminit, some important fixes are still missing in the
current CVS.
src/mainboard/via/epia/Config.lb:
* chooses COMPATIBILITY mode rather than native mode
* more appropriate romcc options
src/southbridge/via/vt8231/vt8231.c:
* proper interpretation of enable_native_ide
src/mainboard/via/epia/auto.c:
* really call early mtrr
Attached patch also includes random minor fixes.
--
Takeshi
? targets/epia
? targets/via/epia/epia
Index: src/cpu/p6/earlymtrr.c
===
RCS file: /cvsroot/freebios/freebios2/src/cpu/p6/earlymtrr.c,v
retrieving revision 1.1
diff -u -r1.1 earlymtrr.c
--- src/cpu/p6/earlymtrr.c 20 Oct 2003 19:57:35 - 1.1
+++ src/cpu/p6/earlymtrr.c 21 Oct 2003 09:28:39 -
@@ -37,7 +37,6 @@
const unsigned long *msr_addr;
unsigned long cr0;
- print_err("Disabling cache\n");
/* Just to be sure, take all the steps to disable the cache.
* This may not be needed, but C3's may...
* Invalidate the cache */
@@ -56,7 +55,6 @@
/* Invalidate the cache again */
asm volatile ("invd");
- print_err("Clearing mtrr\n");
/* Inialize all of the relevant msrs to 0 */
msr.lo = 0;
@@ -81,7 +79,6 @@
wrmsr(0x201, msr);
#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
- print_err("Setting XIP\n");
/* enable write through caching so we can do execute in place
* on the flash rom.
*/
@@ -104,5 +101,5 @@
cr0 = read_cr0();
cr0 &= 0x9fff;
write_cr0(cr0);
- print_err("Enabled the cache\n");
+ print_err("Enabled the cache\r\n");
}
Index: src/mainboard/via/epia/Config.lb
===
RCS file: /cvsroot/freebios/freebios2/src/mainboard/via/epia/Config.lb,v
retrieving revision 1.5
diff -u -r1.5 Config.lb
--- src/mainboard/via/epia/Config.lb1 Oct 2003 23:18:14 - 1.5
+++ src/mainboard/via/epia/Config.lb21 Oct 2003 09:28:39 -
@@ -53,8 +53,8 @@
##
## Clean up the motherboard id strings
##
-option MAINBOARD_PART_NUMBER="HDAMA"
-option MAINBOARD_VENDOR="ARIMA"
+option MAINBOARD_PART_NUMBER="EPIA"
+option MAINBOARD_VENDOR="VIA"
###
### LinuxBIOS layout values
@@ -137,7 +137,7 @@
makerule ./failover.inc
depends "./failover.E ./romcc"
- action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+ action "./romcc -O2 -mcpu=c3 -o failover.inc --label-prefix=failover
./failover.E"
end
makerule ./auto.E
@@ -146,7 +146,7 @@
end
makerule ./auto.inc
depends "./auto.E ./romcc"
- action "./romcc -O ./auto.E > auto.inc"
+ action "./romcc -O2 -mcpu=c3 -o auto.inc ./auto.E"
end
##
@@ -220,7 +220,7 @@
# pci 0:11.6
# pci 0:12.0
register "enable_usb" = "0"
- register "enable_native_ide" = "1"
+ register "enable_native_ide" = "0"
register "enable_com_ports" = "1"
register "enable_keyboard" = "0"
register "enable_nvram" = "1"
@@ -236,4 +236,3 @@
##
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
-
Index: src/mainboard/via/epia/auto.c
===
RCS file: /cvsroot/freebios/freebios2/src/mainboard/via/epia/auto.c,v
retrieving revision 1.14
diff -u -r1.14 auto.c
--- src/mainboard/via/epia/auto.c 17 Oct 2003 22:21:07 - 1.14
+++ src/mainboard/via/epia/auto.c 21 Oct 2003 09:28:39 -
@@ -11,6 +11,7 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/via/vt8601/raminit.h"
+#include "cpu/p6/earlymtrr.c"
/*
*/
void udelay(int usecs)
@@ -100,10 +101,10 @@
outb(5, 0x80);
enable_vt8231_serial();
- enable_mainboard_devices();
uart_init();
console_init();
+ enable_mainboard_devices();
enable_smbus();
enable_shadow_ram();
/*
@@ -135,4 +136,5 @@
ram_check(check_addrs[i].lo, check_addrs[i].hi);
}
#endif
+ early_mtrr_init();
}
Index: src/southbridge/via/vt8231/vt8231.c
===
RCS file: /cvsroot/freebios/freebios2/src/southbridge/via/vt8231/vt8231.c,v
retrieving revision 1.7
diff -u -r1.7 vt8231.c
--- src/southbridge/via/vt8231/vt8231.c 11 Oct 2003 06:20:22 - 1.7
+++ src/southbridge/via/vt8231/vt8231.c 21 Oct 2003 09:28:39 -
@@ -335,11 +335,11 @@
//
// IDE setup
//
- if (conf->enable_native_id
Re: V2 EPIA - IDE compat mode, RAM init, and early MTRR
On Tue, 21 Oct 2003, SONE Takeshi wrote: > > src/mainboard/via/epia/Config.lb: > * chooses COMPATIBILITY mode rather than native mode > * more appropriate romcc options > > src/southbridge/via/vt8231/vt8231.c: > * proper interpretation of enable_native_ide > > src/mainboard/via/epia/auto.c: > * really call early mtrr > > Attached patch also includes random minor fixes. No, these are in CVS AFAIK; the problem is that you are suffering the 24-hour delay again. ron ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: V2 EPIA - IDE compat mode, RAM init, and early MTRR
On Tue, Oct 21, 2003 at 07:55:20AM -0600, ron minnich wrote: > On Tue, 21 Oct 2003, SONE Takeshi wrote: > > > > > src/mainboard/via/epia/Config.lb: > > * chooses COMPATIBILITY mode rather than native mode > > * more appropriate romcc options > > > > src/southbridge/via/vt8231/vt8231.c: > > * proper interpretation of enable_native_ide > > > > src/mainboard/via/epia/auto.c: > > * really call early mtrr > > > > Attached patch also includes random minor fixes. > > > No, these are in CVS AFAIK; the problem is that you are suffering the > 24-hour delay again. Hmm... I don't see them in the snapshots.linuxbios.org either. SF CVS is working very well these days.. no connection resets, less delay, faster updates. -- Takeshi ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: V2 EPIA - IDE compat mode, RAM init, and early MTRR
* ron minnich <[EMAIL PROTECTED]> [031021 15:55]: > No, these are in CVS AFAIK; the problem is that you are suffering the > 24-hour delay again. If so, please use http://snapshots.linuxbios.org/ Stefan -- ARCHITECTURE TEAM SUSE LINUX AG ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
Re: V2 EPIA - IDE compat mode, RAM init, and early MTRR
On Tue, 21 Oct 2003, SONE Takeshi wrote: > SF CVS is working very well these days.. no connection resets, > less delay, faster updates. I'll check later today and see if I forgot to commit ... ron ___ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
