Re: [PATCH v2] [POWERPC] 4xx: Add endpoint support to 4xx PCIe driver
On Mon, 2008-04-21 at 16:54 +0200, Stefan Roese wrote:
> This patch adds basic endpoint support to the 4xx PCIe driver.
>
> This is done by checking the device_type property of the PCIe
> device node ("pci" for root-complex and "pci-endpoint" for endpoint
> configuration).
>
> Note: Currently we map a fixed 64MByte window to PLB address 0 (SDRAM).
> This should probably be configurable via a dts property.
>
> Signed-off-by: Stefan Roese <[EMAIL PROTECTED]>
Acked-by: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
---
Paul, I forgot to send that ack a while ago, this is .26 material, been
around for some time.
Cheers,
Ben.
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Re: [PATCH] Change the default link address for pSeries zImage kernels.
On Fri, 2008-04-25 at 15:39 +1000, Tony Breeds wrote: > Currently we set the start of the .text section to be 4Mb for pSeries. > In situations where the zImage is > 8Mb we'll fail to boot (due to > overlapping with OF). Move .text in a pSeries zImage from 4MB to 64MB > (well past OF). > > Signed-off-by: Tony Breeds <[EMAIL PROTECTED]> > --- > - Compile tested for *_defconfig with only pSeries chaning it's link >address. > - Boot tested on POWER6 Considering how bad OF can be on some machines, I'd like this to be boot-tested on a wider range of machines. Also, it might depend on the OF real-base setting as well... At least, we should be able to test at ozlabs on cell blades, POWER4 bare metal (ie "SMP mode"), POWER5 and POWER5+. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] ibm_newemac: Increase MDIO timeouts
Benjamin Herrenschmidt wrote: This patch doubles the MDIO timeouts in EMAC as there are field cases where they are two short to communicate with some PHYs. Signed-off-by: Benjamin Herrenschmidt <[EMAIL PROTECTED]> applied ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/6] ibm_newemac: Fix problem with jumbo frame support and EMAC V4.patch
Benjamin Herrenschmidt wrote:
From: Stefan Roese <[EMAIL PROTECTED]>
This fixes the jumbo frame support on EMAC V4 systems. Now the correct
bit is set depending on the EMAC version configured.
Tested on Kilauea (405EX) and Canyonlands (460EX).
Signed-off-by: Stefan Roese <[EMAIL PROTECTED]>
Signed-off-by: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
---
drivers/net/ibm_newemac/core.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ibm_newemac/core.c b/drivers/net/ibm_newemac/core.c
index 0789802..486901f 100644
--- a/drivers/net/ibm_newemac/core.c
+++ b/drivers/net/ibm_newemac/core.c
@@ -524,7 +524,10 @@ static int emac_configure(struct emac_instance *dev)
rx_size = dev->rx_fifo_size_gige;
if (dev->ndev->mtu > ETH_DATA_LEN) {
- mr1 |= EMAC_MR1_JPSM;
+ if (emac_has_feature(dev, EMAC_FTR_EMAC4))
+ mr1 |= EMAC4_MR1_JPSM;
+ else
+ mr1 |= EMAC_MR1_JPSM;
dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
} else
dev->stop_timeout = STOP_TIMEOUT_1000;
applied 1-6
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[PATCH] Change the default link address for pSeries zImage kernels.
Currently we set the start of the .text section to be 4Mb for pSeries.
In situations where the zImage is > 8Mb we'll fail to boot (due to
overlapping with OF). Move .text in a pSeries zImage from 4MB to 64MB
(well past OF).
Signed-off-by: Tony Breeds <[EMAIL PROTECTED]>
---
- Compile tested for *_defconfig with only pSeries chaning it's link
address.
- Boot tested on POWER6
arch/powerpc/boot/wrapper | 14 --
arch/powerpc/boot/zImage.coff.lds.S |1 -
arch/powerpc/boot/zImage.lds.S |1 -
3 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index d6c96d9..b5dfc1f 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -138,14 +138,20 @@ objflags=-S
tmp=$tmpdir/zImage.$$.o
ksection=.kernel:vmlinux.strip
isection=.kernel:initrd
+link_address='0x40'
case "$platform" in
-pmac|pseries|chrp)
+pseries)
+platformo=$object/of.o
+link_address='0x400'
+;;
+pmac|chrp)
platformo=$object/of.o
;;
coff)
platformo=$object/of.o
lds=$object/zImage.coff.lds
+link_address='0x50'
;;
miboot|uboot)
# miboot and U-boot want just the bare bits, not an ELF binary
@@ -190,6 +196,7 @@ ps3)
objflags="-O binary --set-section-flags=.bss=contents,alloc,load,data"
ksection=.kernel:vmlinux.bin
isection=.kernel:initrd
+link_address=''
;;
ep88xc|ep405|ep8248e)
platformo="$object/fixed-head.o $object/$platform.o"
@@ -268,7 +275,10 @@ if [ -n "$dtb" ]; then
fi
if [ "$platform" != "miboot" ]; then
-${CROSS}ld -m elf32ppc -T $lds -o "$ofile" \
+if [ -n "$link_address" ] ; then
+text_start="-Ttext $link_address"
+fi
+${CROSS}ld -m elf32ppc -T $lds $text_start -o "$ofile" \
$platformo $tmp $object/wrapper.a
rm $tmp
fi
diff --git a/arch/powerpc/boot/zImage.coff.lds.S
b/arch/powerpc/boot/zImage.coff.lds.S
index fe87a90..856dc78 100644
--- a/arch/powerpc/boot/zImage.coff.lds.S
+++ b/arch/powerpc/boot/zImage.coff.lds.S
@@ -3,7 +3,6 @@ ENTRY(_zimage_start_opd)
EXTERN(_zimage_start_opd)
SECTIONS
{
- . = (5*1024*1024);
_start = .;
.text :
{
diff --git a/arch/powerpc/boot/zImage.lds.S b/arch/powerpc/boot/zImage.lds.S
index f6e380f..0962d62 100644
--- a/arch/powerpc/boot/zImage.lds.S
+++ b/arch/powerpc/boot/zImage.lds.S
@@ -3,7 +3,6 @@ ENTRY(_zimage_start)
EXTERN(_zimage_start)
SECTIONS
{
- . = (4*1024*1024);
_start = .;
.text :
{
--
1.5.5.1
Yours Tony
linux.conf.auhttp://www.marchsouth.org/
Jan 19 - 24 2009 The Australian Linux Technical Conference!
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Re: sysfs cpu entry
On Apr 24, 2008, at 11:08 PM, Kevin Diggs wrote: Hi, Can someone suggest where to add the code for a cpu (/sys/devices/system/cpu/cpu0) entry in sysfs? The 2.6.24 release has a sysfs.c file but it only seems to be used for 64-bit? Anyone know why? What kind of planetary disasters will I create if I allow it to be used in 32-bit as well? kevin There's no huge harm just make sure that you fixup things to only expose registers that exist on a 32-bit part. What 32-bit chip are you looking to enable this for? - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
sysfs cpu entry
Hi, Can someone suggest where to add the code for a cpu (/sys/devices/system/cpu/cpu0) entry in sysfs? The 2.6.24 release has a sysfs.c file but it only seems to be used for 64-bit? Anyone know why? What kind of planetary disasters will I create if I allow it to be used in 32-bit as well? kevin P.S.: On an unrelated note, anyone know where to start looking for problems in pmac_zilog. My 8600 modem which worked fine in 2.4 is now essentially useless. Some problem with handshaking, I think. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] [POWERPC] spufs: add .gitignore for spu_save_dump.h & spu_restore_dump.h
On Apr 24, 2008, at 7:55 PM, Jeremy Kerr wrote: Kumar, Ah, I was mistaking them for the .h_shipped files. Nevermind me, your patch is fine. Applied to my spufs tree. ok. thanks. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] [POWERPC] spufs: add .gitignore for spu_save_dump.h & spu_restore_dump.h
Kumar, Ah, I was mistaking them for the .h_shipped files. Nevermind me, your patch is fine. Applied to my spufs tree. Cheers, Jeremy ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: mpc5200b custom board upstreamable?
On Thu, 2008-04-24 at 18:28 +0200, Sascha Hauer wrote: > > At the moment my compatible entry looks like this: > > compatible = "phytec,pcm030","generic-mpc52xx"; > > What I think would be nice is that "phytec,pcm030" support is used > when available and "generic-mpc52xx" as a fallback. We do not have any > platform specific hacks at the moment, but we may have later. Having > "phytec,pcm030" in the simple machine would prevent us from doing so. No, please avoid that 'generic' stuff for now, for all the good reasons Grant gave. It might be nice but we aren't there yet. It's trivial to add phytec,pcm030 to the list we support and use that for now. If you do a rev tomorrow that is still compatible and in fact is very close to the pcm030 programmatically and call it pcm035, then you could do something like compatible = "phytec,pcm035", "phytec,pcm030". But don't toy with "generic" things, they sound like good ideas but they ultimately come back and bite us. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] [POWERPC] spufs: add .gitignore for spu_save_dump.h & spu_restore_dump.h
On Apr 24, 2008, at 5:26 PM, Jeremy Kerr wrote: Kumar, --- /dev/null +++ b/arch/powerpc/platforms/cell/spufs/.gitignore @@ -0,0 +1,2 @@ +spu_save_dump.h +spu_restore_dump.h nak - these still need to be tracked (and distributed with the tree), as we want to be able to build the kernel without spu-gcc. So they should be added to the tree? - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[git pull] Please pull powerpc.git master branch
Linus, Please do: git pull \ git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc.git master to get another powerpc update. There are fixes for various problems that have arisen plus a few patchsets that were not quite ready to go when I sent the last pull request but now are. Note that there are some generic changes to include/linux/sched.h and init/main.c. They are from a set of 3 patches from Ben H that Andrew Morton acked and asked us to push through the powerpc tree. Thanks, Paul. Documentation/powerpc/booting-without-of.txt | 11 MAINTAINERS| 25 + arch/powerpc/Kconfig | 83 ++ arch/powerpc/boot/.gitignore |1 arch/powerpc/boot/Makefile |2 arch/powerpc/boot/dts/canyonlands.dts | 37 + arch/powerpc/boot/dts/glacier.dts | 37 + arch/powerpc/boot/ns16550.c|5 arch/powerpc/kernel/Makefile |9 arch/powerpc/kernel/asm-offsets.c | 11 arch/powerpc/kernel/cpu_setup_44x.S|1 arch/powerpc/kernel/cpu_setup_6xx.S|8 arch/powerpc/kernel/cputable.c |4 arch/powerpc/kernel/head_fsl_booke.S | 11 arch/powerpc/kernel/misc_32.S |6 arch/powerpc/kernel/misc_64.S | 20 - arch/powerpc/kernel/of_platform.c |2 arch/powerpc/kernel/paca.c | 87 +- arch/powerpc/kernel/ppc32.h|2 arch/powerpc/kernel/process.c | 31 + arch/powerpc/kernel/prom.c |4 arch/powerpc/kernel/prom_init_check.sh | 58 + arch/powerpc/kernel/ptrace32.c | 27 - arch/powerpc/kernel/setup_64.c |5 arch/powerpc/kernel/stacktrace.c |1 arch/powerpc/kernel/udbg.c |4 arch/powerpc/mm/fsl_booke_mmu.c|2 arch/powerpc/mm/hash_low_32.S |4 arch/powerpc/mm/init_32.c | 13 arch/powerpc/mm/init_64.c |3 arch/powerpc/mm/mem.c | 37 + arch/powerpc/mm/numa.c |1 arch/powerpc/mm/pgtable_32.c | 23 + arch/powerpc/platforms/Kconfig |1 arch/powerpc/platforms/Kconfig.cputype |4 arch/powerpc/platforms/Makefile|1 arch/powerpc/platforms/cell/Kconfig| 13 arch/powerpc/platforms/cell/Makefile | 20 - arch/powerpc/platforms/cell/axon_msi.c |6 arch/powerpc/platforms/cell/beat.c |2 arch/powerpc/platforms/cell/beat.h |0 arch/powerpc/platforms/cell/beat_htab.c|0 arch/powerpc/platforms/cell/beat_hvCall.S |0 arch/powerpc/platforms/cell/beat_interrupt.c |2 arch/powerpc/platforms/cell/beat_interrupt.h |0 arch/powerpc/platforms/cell/beat_iommu.c |0 arch/powerpc/platforms/cell/beat_smp.c |2 arch/powerpc/platforms/cell/beat_spu_priv1.c |0 arch/powerpc/platforms/cell/beat_syscall.h |0 arch/powerpc/platforms/cell/beat_udbg.c|0 arch/powerpc/platforms/cell/beat_wrapper.h |0 arch/powerpc/platforms/cell/celleb_pci.c | 50 + arch/powerpc/platforms/cell/celleb_pci.h | 19 arch/powerpc/platforms/cell/celleb_scc.h | 87 ++ arch/powerpc/platforms/cell/celleb_scc_epci.c | 77 -- arch/powerpc/platforms/cell/celleb_scc_pciex.c | 547 ++ arch/powerpc/platforms/cell/celleb_scc_sio.c |0 arch/powerpc/platforms/cell/celleb_scc_uhc.c |2 arch/powerpc/platforms/cell/celleb_setup.c | 12 arch/powerpc/platforms/cell/io-workarounds.c | 358 +++-- arch/powerpc/platforms/cell/io-workarounds.h | 49 + arch/powerpc/platforms/cell/setup.c| 43 + arch/powerpc/platforms/cell/spider-pci.c | 184 + arch/powerpc/platforms/celleb/Kconfig | 12 arch/powerpc/platforms/celleb/Makefile |9 arch/powerpc/platforms/celleb/io-workarounds.c | 280 --- arch/powerpc/platforms/iseries/exception.S | 27 + arch/powerpc/platforms/ps3/os-area.c |1 arch/powerpc/platforms/pseries/Kconfig |5 arch/powerpc/platforms/pseries/Makefile|4 arch/powerpc/platforms/pseries/eeh.c |1 arch/powerpc/platforms/pseries/eeh_cache.c |1 arch/powerpc/platforms/pseries/firmware.c | 10 arch/powerpc/platforms/pseries/iommu.c | 39 - arch/powerpc/platforms/pseries/lpar.c | 36 - arch/powerpc/platforms/pseries/ras.c |4 arch/powerpc/platforms/pseries/rtasd.c | 14 arch/powerpc/platforms/pseries/scanlog.c | 23 - arch/powerpc/platforms/pseries/setup.c | 17 arch/po
Re: [PATCH] [POWERPC] spufs: add .gitignore for spu_save_dump.h & spu_restore_dump.h
Kumar, > --- /dev/null > +++ b/arch/powerpc/platforms/cell/spufs/.gitignore > @@ -0,0 +1,2 @@ > +spu_save_dump.h > +spu_restore_dump.h nak - these still need to be tracked (and distributed with the tree), as we want to be able to build the kernel without spu-gcc. Jeremy ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [Cbe-oss-dev] [PATCH] Reworked Cell OProfile: SPU mutex lock fix
Carl Love wrote:
This is a reworked patch to fix the SPU data storage. Currently, the
SPU escape sequences and program counter data is being added directly
into the kernel buffer without holding the buffer_mutex lock. This
patch changes how the data is stored. A new function,
oprofile_add_value, is added into the oprofile driver to allow adding
generic data to the per cpu buffers. This enables a series of calls
to the oprofile_add_value to enter the needed SPU escape sequences
and SPU program data into the kernel buffer via the per cpu buffers
without any additional processing. The oprofile_add_value function is
generic so it could be used by other architecures as well provided
the needed postprocessing was added to opreport.
Finally, this patch backs out the changes previously added to the
oprofile generic code for handling the architecture specific
ops.sync_start and ops.sync_stop that allowed the architecture
to skip the per CPU buffer creation.
Looks good except for the few minor things noted below . . .
-Maynard
Signed-off-by: Carl Love <[EMAIL PROTECTED]>
Index: Cell_kernel_4_15_2008/arch/powerpc/oprofile/cell/pr_util.h
===
--- Cell_kernel_4_15_2008.orig/arch/powerpc/oprofile/cell/pr_util.h
+++ Cell_kernel_4_15_2008/arch/powerpc/oprofile/cell/pr_util.h
@@ -20,11 +20,6 @@
#include
#include
-/* Defines used for sync_start */
-#define SKIP_GENERIC_SYNC 0
-#define SYNC_START_ERROR -1
-#define DO_GENERIC_SYNC 1
-
struct spu_overlay_info { /* map of sections within an SPU overlay */
unsigned int vma; /* SPU virtual memory address from elf */
unsigned int size; /* size of section from elf */
@@ -85,7 +80,7 @@ void stop_spu_profiling(void);
int spu_sync_start(void);
/* remove the hooks */
-int spu_sync_stop(void);
+void spu_sync_stop(void);
/* Record SPU program counter samples to the oprofile event buffer. */
void spu_sync_buffer(int spu_num, unsigned int *samples,
Index: Cell_kernel_4_15_2008/arch/powerpc/oprofile/cell/spu_task_sync.c
===
--- Cell_kernel_4_15_2008.orig/arch/powerpc/oprofile/cell/spu_task_sync.c
+++ Cell_kernel_4_15_2008/arch/powerpc/oprofile/cell/spu_task_sync.c
@@ -31,11 +31,13 @@
#define RELEASE_ALL
-static DEFINE_SPINLOCK(buffer_lock);
+static DEFINE_SPINLOCK(add_value_lock);
static DEFINE_SPINLOCK(cache_lock);
static int num_spu_nodes;
+int per_cpu_buffers_exist=0;
The per_cpu_buffers_exist variable is not used for anything useful -- a
vestige of something done earlier, I think.
int spu_prof_num_nodes;
int last_guard_val[MAX_NUMNODES * 8];
+static int spu_ctx_sw_seen[MAX_NUMNODES * 8];
[snip]
int spu_sync_start(void)
{
int k;
- int ret = SKIP_GENERIC_SYNC;
+ int ret = 0;
int register_ret;
- unsigned long flags = 0;
+ int cpu;
spu_prof_num_nodes = number_of_online_nodes();
num_spu_nodes = spu_prof_num_nodes * 8;
- spin_lock_irqsave(&buffer_lock, flags);
- add_event_entry(ESCAPE_CODE);
- add_event_entry(SPU_PROFILING_CODE);
- add_event_entry(num_spu_nodes);
- spin_unlock_irqrestore(&buffer_lock, flags);
+ /* At this point, the CPU buffers have been generated so
Suggest you change "generated" to "allocated" for clarity.
+* writes to the per CPU buffers can occur. Need to
+* set the flag that the buffers exist before registering for
+* the SPU context switches or the routine to process the
+* context switches will not write context switch information.
+*/
+ per_cpu_buffers_exist = 1;
delete
+
+ /* The SPU_PROFILING_CODE escape sequence must proceed
+* the SPU context switch info.
+*/
+ for_each_online_cpu(cpu) {
+ oprofile_add_value(ESCAPE_CODE, cpu);
+ oprofile_add_value(SPU_PROFILING_CODE, cpu);
+ oprofile_add_value((unsigned long int)
+ num_spu_nodes, cpu);
+ }
/* Register for SPU events */
register_ret = spu_switch_event_register(&spu_active);
if (register_ret) {
- ret = SYNC_START_ERROR;
+ /* Stop the profile_spus() function from trying
+* to store samples into the per CPU buffer. The
+* buffer will not be there.
+*/
+ per_cpu_buffers_exist = 0;
delete
+ ret = -1;
goto out;
}
- for (k = 0; k < (MAX_NUMNODES * 8); k++)
+ for (k = 0; k < (MAX_NUMNODES * 8); k++) {
last_guard_val[k] = 0;
+ spu_ctx_sw_seen[k] = 0;
+ }
pr_debug("spu_sync_start -- running.\n");
out:
return ret;
+
}
/* Record SPU program counter samples to the oprofile event buffer. */
@@ -432,7 +460,7 @@ void spu_sync_buf
Re: [PATCH] add gpiolib support for mpc5200
On Thu, Apr 24, 2008 at 9:36 AM, Sascha Hauer <[EMAIL PROTECTED]> wrote:
> Hi all,
>
> Feel free to comment on this.
>
> Sascha
>
>
> This patch adds gpiolib support for mpc5200 SOCs. I'm not sure
> whether it's a good idea to make this optional via kconfig.
> The gpt devices only support a single gpio. In the current of_gpio
> implementation each chip consumes 32 GPIOs which leads to huge
> gaps.
>
> Signed-off-by: Sascha Hauer <[EMAIL PROTECTED]>
Looks pretty good. You've saved me the need to go write a driver
myself. Comments below, but I'll pull it into my tree and give it a
spin.
I don't see any mechanism for setting the open drain state of the pin.
That will either need to be done by platform code or encoded into the
device tree. Does the OF gpio infrastructure provide any callback to
the driver when something requests the pin? That would seem to be the
ideal place to set the open drain state.
You'll also need to document the format of the gpio pin specifier for
these devices (ie. first cell is GPIO number, second cell is ).
As for the wide spans caused by gpt gpios, it is probably okay for
now, but we can rework it to do something clever (like have a single
registration for all gpt gpios) at a later date.
Cheers,
g.
>
> ---
> arch/powerpc/platforms/52xx/Kconfig|6
> arch/powerpc/platforms/52xx/Makefile |2
> arch/powerpc/platforms/52xx/mpc52xx_gpio.c | 408
> +
> 3 files changed, 416 insertions(+)
>
> Index: arch/powerpc/platforms/52xx/mpc52xx_gpio.c
> ===
> --- /dev/null
> +++ b/arch/powerpc/platforms/52xx/mpc52xx_gpio.c
> @@ -0,0 +1,408 @@
> +/*
> + * MPC52xx gpio driver
> + *
> + * Copyright (c) 2008 Sascha Hauer <[EMAIL PROTECTED]>, Pengutronix
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2
> + * as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +static DEFINE_SPINLOCK(gpio_lock);
> +
> +/*
> + * GPIO LIB API implementation for wakeup GPIOs.
> + *
> + * There's a maximum of 8 wakeup GPIOs. Which of these are available
> + * for use depends on your board setup.
> + *
> + * 0 -> GPIO_WKUP_7
> + * 1 -> GPIO_WKUP_6
> + * 2 -> PSC6_1
> + * 3 -> PSC6_0
> + * 4 -> ETH_17
> + * 5 -> PSC3_9
> + * 6 -> PSC2_4
> + * 7 -> PSC1_4
> + *
> + */
> +static int mpc52xx_wkup_gpio_get(struct gpio_chip *gc, unsigned int gpio)
> +{
> + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
> + struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
> + unsigned int ret;
> +
> + ret = (in_8(®s->wkup_ival) >> (7 - gpio)) & 1;
> +
> + pr_debug("%s: gpio: %d ret: %d\n", __func__, gpio, ret);
dev_dbg maybe?
> +
> + return ret;
> +}
> +
> +static void mpc52xx_wkup_gpio_set(struct gpio_chip *gc, unsigned int gpio,
> int val)
> +{
> + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
> + struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
> + unsigned int tmp;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&gpio_lock, flags);
> +
> + tmp = in_8(®s->wkup_dvo);
> + if (val)
> + tmp |= 1 << (7 - gpio);
> + else
> + tmp &= ~(1 << (7 - gpio));
> + out_8(®s->wkup_dvo, tmp);
Rather than read/modify/write of the device register; the function
would probably be faster (one fewer barrier) if you used a shadow
register of the pin state and the critical region would be
shorter/simpler. Also, while this device doesn't have the side
effects associated with shared input/output register, it might still
be good form to use a shadow register just for the sake of clarity.
> +
> + spin_unlock_irqrestore(&gpio_lock, flags);
> +
> + pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
> +}
> +
> +static int mpc52xx_wkup_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
> +{
> + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
> + struct mpc52xx_gpio_wkup *regs = mm_gc->regs;
> + unsigned int tmp;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&gpio_lock, flags);
> +
> + tmp = in_8(®s->wkup_ddr);
> +
Re: [PATCH] add gpiolib support for mpc5200
On Thu, Apr 24, 2008 at 9:36 AM, Sascha Hauer <[EMAIL PROTECTED]> wrote:
> Hi all,
>
> Feel free to comment on this.
>
> Sascha
>
>
> This patch adds gpiolib support for mpc5200 SOCs. I'm not sure
> whether it's a good idea to make this optional via kconfig.
> The gpt devices only support a single gpio. In the current of_gpio
> implementation each chip consumes 32 GPIOs which leads to huge
> gaps.
>
> Signed-off-by: Sascha Hauer <[EMAIL PROTECTED]>
Looks pretty good. You've saved me the need to go write a driver
myself. Comments below, but I'll pull it into my tree and give it a
spin.
I don't see any mechanism for setting the open drain state of the pin.
That will either need to be done by platform code or encoded into the
device tree. Does the OF gpio infrastructure provide any callback to
the driver when something requests the pin? That would seem to be the
ideal place to set the open drain state.
You'll also need to document the format of the gpio pin specifier for
these devices (ie. first cell is GPIO number, second cell is ).
As for the wide spans caused by gpt gpios, it is probably okay for
now, but we can rework it to do something clever (like have a single
registration for all gpt gpios) at a later date.
Cheers,
g.
>
> ---
> arch/powerpc/platforms/52xx/Kconfig|6
> arch/powerpc/platforms/52xx/Makefile |2
> arch/powerpc/platforms/52xx/mpc52xx_gpio.c | 408
> +
> 3 files changed, 416 insertions(+)
>
> Index: arch/powerpc/platforms/52xx/mpc52xx_gpio.c
> ===
> --- /dev/null
> +++ b/arch/powerpc/platforms/52xx/mpc52xx_gpio.c
> @@ -0,0 +1,408 @@
> +/*
> + * MPC52xx gpio driver
> + *
> + * Copyright (c) 2008 Sascha Hauer <[EMAIL PROTECTED]>, Pengutronix
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2
> + * as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +static DEFINE_SPINLOCK(gpio_lock);
> +
> +/*
> + * GPIO LIB API implementation for wakeup GPIOs.
> + *
> + * There's a maximum of 8 wakeup GPIOs. Which of these are available
> + * for use depends on your board setup.
> + *
> + * 0 -> GPIO_WKUP_7
> + * 1 -> GPIO_WKUP_6
> + * 2 -> PSC6_1
> + * 3 -> PSC6_0
> + * 4 -> ETH_17
> + * 5 -> PSC3_9
> + * 6 -> PSC2_4
> + * 7 -> PSC1_4
> + *
> + */
> +static int mpc52xx_wkup_gpio_get(struct gpio_chip *gc, unsigned int gpio)
> +{
> + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
> + struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
> + unsigned int ret;
> +
> + ret = (in_8(®s->wkup_ival) >> (7 - gpio)) & 1;
> +
> + pr_debug("%s: gpio: %d ret: %d\n", __func__, gpio, ret);
dev_dbg maybe?
> +
> + return ret;
> +}
> +
> +static void mpc52xx_wkup_gpio_set(struct gpio_chip *gc, unsigned int gpio,
> int val)
> +{
> + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
> + struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
> + unsigned int tmp;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&gpio_lock, flags);
> +
> + tmp = in_8(®s->wkup_dvo);
> + if (val)
> + tmp |= 1 << (7 - gpio);
> + else
> + tmp &= ~(1 << (7 - gpio));
> + out_8(®s->wkup_dvo, tmp);
Rather than read/modify/write of the device register; the function
would probably be faster (one fewer barrier) if you used a shadow
register of the pin state and the critical region would be
shorter/simpler. Also, while this device doesn't have the side
effects associated with shared input/output register, it might still
be good form to use a shadow register just for the sake of clarity.
> +
> + spin_unlock_irqrestore(&gpio_lock, flags);
> +
> + pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
> +}
> +
> +static int mpc52xx_wkup_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
> +{
> + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
> + struct mpc52xx_gpio_wkup *regs = mm_gc->regs;
> + unsigned int tmp;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&gpio_lock, flags);
> +
> + tmp = in_8(®s->wkup_ddr);
> +
Re: [PATCH] [POWERPC] bootwrapper: fix build error on virtex405-head.S
On Thu, 2008-04-24 at 11:33 -0600, Grant Likely wrote: > From: Grant Likely <[EMAIL PROTECTED]> > > virtex405-head.S is an assembler file, not a C file; therefore BOOTAFLAGS > is the correct place to set the needed -mcpu=405 flag. > > Signed-off-by: Grant Likely <[EMAIL PROTECTED]> Applied, pushed to 4xx/next and 4xx/for-2.6.26, and included in my pull request. josh ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[RFCv2 POWERPC] booting-without-of: bindings for FHCI USB, GPIO LEDs, MCU, and NAND on UPM
On Tue, Apr 22, 2008 at 11:41:35PM +0400, Anton Vorontsov wrote:
> Hi all,
>
> Here is purposed bindings draft for the new drivers that I would like to
> send for this or next merge window, depending on results of this RFC. ;-)
> (The new bindings needs to be in-tree or at least Acked before I could
> send the drivers.)
>
> Comments and suggestions are highly appreciated.
Much thanks for the comments on previous version. Here is the new one,
please speak up if there is anything I could improve.
Thanks in advance.
diff --git a/Documentation/powerpc/booting-without-of.txt
b/Documentation/powerpc/booting-without-of.txt
index c350623..b560dc5 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -59,6 +59,10 @@ Table of Contents
p) Freescale Synchronous Serial Interface
q) USB EHCI controllers
r) Freescale General-purpose Timers Module
+ s) Freescale QUICC Engine USB Controller
+ t) LEDs on GPIOs
+ u) Freescale MCU with MPC8349E-mITX compatible firmware
+ v) NAND on UPM-driven Freescale Localbus
VII - Marvell Discovery mv64[345]6x System Controller chips
1) The /system-controller node
@@ -2866,6 +2870,128 @@ platforms are moved over to use the
flattened-device-tree model.
clock-frequency = <0>;
};
+s) Freescale QUICC Engine USB Controller
+
+Required properties:
+ - compatible : should be "fsl,-qe-usb", "fsl,mpc8323-qe-usb";
+ - reg : the first two cells should contain gtm registers location and
+length, the next two two cells should contain PRAM location and
+length.
+ - interrupts : should contain USB interrupt.
+ - interrupt-parent : interrupt source phandle.
+ - fsl,fullspeed-clock : specifies the full speed USB clock source in
+"clk" or "brg" format.
+ - fsl,lowspeed-clock : specifies the low speed USB clock source in
+"clk" or "brg" format.
+ - fsl,usb-mode : should be "host".
+ - linux,hub-power-budget : optional, USB power budget for the root hub
+in mA.
+ - gpios : should specify GPIOs in this order: USBOE, USBTP, USBTN, USBRP,
+USBRN, SPEED (optional), and POWER (optional).
+
+Example:
+
+ [EMAIL PROTECTED] {
+ compatible = "fsl,mpc8360-qe-usb", "fsl,mpc8323-qe-usb";
+ reg = <0x6c0 0x40 0x8b00 0x100>;
+ interrupts = <11>;
+ interrupt-parent = <&qeic>;
+ fsl,fullspeed-clock = "clk21";
+ fsl,usb-mode = "host";
+ gpios = <&qe_pio_b 2 0 /* USBOE */
+&qe_pio_b 3 0 /* USBTP */
+&qe_pio_b 8 0 /* USBTN */
+&qe_pio_b 9 0 /* USBRP */
+&qe_pio_b 11 0 /* USBRN */
+&qe_pio_e 20 0 /* SPEED */
+&qe_pio_e 21 0 /* POWER */>;
+ };
+
+t) LEDs on GPIOs
+
+Required properties:
+ - compatible : should be "linux,gpio-led".
+ - linux,name : LED name.
+ - linux,active-low : property should be present if LED wired as
+active-low.
+ - linux,default-trigger : Linux default trigger for this LED.
+ - linux,brightness : default brightness.
+ - gpios : should specify LED GPIO.
+
+Example:
+
+ [EMAIL PROTECTED] {
+ compatible = "linux,gpio-led";
+ linux,name = "pwr";
+ linux,brightness = <1>;
+ linux,active-low;
+ gpios = <&mcu_pio 0>;
+ };
+
+ [EMAIL PROTECTED] {
+ compatible = "linux,gpio-led";
+ linux,name = "hdd";
+ linux,default-trigger = "ide-disk";
+ linux,active-low;
+ gpios = <&mcu_pio 1>;
+ };
+
+u) Freescale MCU with MPC8349E-mITX compatible firmware
+
+Required properties:
+ - compatible : "fsl,-", "fsl,mcu-mpc8349emitx";
+ - reg : should specify I2C address (0x0a).
+ - #address-cells : should be 0.
+ - #size-cells : should be 0.
+ - #gpio-cells : should be 2.
+ - gpio-controller : should be present;
+
+Example:
+
+ mcu_pio: [EMAIL PROTECTED] {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #gpio-cells = <2>;
+ compatible = "fsl,mc9s08qg8-mpc8349emitx",
+"fsl,mcu-mpc8349emitx";
+ reg = <0x0a>;
+ gpio-controller;
+ };
+
+v) Freescale Localbus UPM programmed to work with NAND flash
+
+ Required properties:
+ - #address-cells : should be 0;
+ - #size-cells : should be 0;
+ - compatible : "fsl,upm-nand".
+ - reg : should specify localbus chip select and size used for the chip.
+ - fsl,upm-addr-offset : UPM pattern offset for the address latch.
+ - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
+ - gpios : may
[PATCH] [POWERPC] bootwrapper: fix build error on virtex405-head.S
From: Grant Likely <[EMAIL PROTECTED]> virtex405-head.S is an assembler file, not a C file; therefore BOOTAFLAGS is the correct place to set the needed -mcpu=405 flag. Signed-off-by: Grant Likely <[EMAIL PROTECTED]> --- Paul, Josh; This is a bug fix required in .26 ASAP. Cheers, g. arch/powerpc/boot/Makefile |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index 5ba50c6..7822d25 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -40,7 +40,7 @@ $(obj)/ebony.o: BOOTCFLAGS += -mcpu=405 $(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405 $(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405 $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405 -$(obj)/virtex405-head.o: BOOTCFLAGS += -mcpu=405 +$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405 zlib := inffast.c inflate.c inftrees.c ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH] [POWERPC] Update .gitignore file
Update .gitignore for zImage.iseries Signed-off-by: Kumar Gala <[EMAIL PROTECTED]> --- arch/powerpc/boot/.gitignore |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/boot/.gitignore b/arch/powerpc/boot/.gitignore index 5ef2bdf..2347294 100644 --- a/arch/powerpc/boot/.gitignore +++ b/arch/powerpc/boot/.gitignore @@ -27,6 +27,7 @@ zImage.chrp zImage.coff zImage.coff.lds zImage.ep* +zImage.iseries zImage.*lds zImage.miboot zImage.pmac -- 1.5.4.1 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH] [POWERPC] spufs: add .gitignore for spu_save_dump.h & spu_restore_dump.h
Signed-off-by: Kumar Gala <[EMAIL PROTECTED]> --- arch/powerpc/platforms/cell/spufs/.gitignore |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/platforms/cell/spufs/.gitignore diff --git a/arch/powerpc/platforms/cell/spufs/.gitignore b/arch/powerpc/platforms/cell/spufs/.gitignore new file mode 100644 index 000..a09ee8d --- /dev/null +++ b/arch/powerpc/platforms/cell/spufs/.gitignore @@ -0,0 +1,2 @@ +spu_save_dump.h +spu_restore_dump.h -- 1.5.4.1 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 00/10] powerpc: Add kexec/kdump support for ppc32
On Apr 24, 2008, at 10:42 AM, Dale Farnsworth wrote: On Thu, Apr 24, 2008 at 07:50:52AM -0500, Kumar Gala wrote: On Nov 22, 2007, at 9:42 AM, Dale Farnsworth wrote: This patch series adds kexec and kdump support for ppc32 in arch/ powerpc. It has been successfully tested on the mpc8548_cds and prpmc2800 platforms. Mark Greer and I are preparing patches to the kexec-tools package as well. Dale, can you look at updating your patchset now that we've made some progress on other patches. Yes. It'll take a couple of weeks for me to fit it in though. no problem. I figure we are aiming for 2.6.27 for this functionality. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: mpc5200b custom board upstreamable?
On Thu, Apr 24, 2008 at 10:07:20AM -0600, Grant Likely wrote: > On Thu, Apr 24, 2008 at 9:53 AM, Sascha Hauer <[EMAIL PROTECTED]> wrote: > > On Thu, Apr 24, 2008 at 09:13:45AM -0600, Grant Likely wrote: > > > On Thu, Apr 24, 2008 at 9:12 AM, Sascha Hauer <[EMAIL PROTECTED]> wrote: > > > > > > > > Hi all, > > > > > > > > I had the intention to push the code for a custom mpc5200b board > > (freely > > > > available, no internal project) upstream. After cleaning up the code I > > > > realized that actually no board specific code is left and our board is > > > > well handled by the mpc5200_simple_platform machine. > > > > > > > > The only issue is that the machine only matches things like > > > > "schindler,cm5200", there's no generic entry. Would it be possible to > > > > add a "generic-mpc52xx" entry to this list? > > > > > > I'm being cautious about this for the time being. I'd like to have a > > > generic match mechanism, but I don't want to do something that isn't > > > easy to recover from if it turns out to be brain dead. For now, just > > > add your board name to the explicit match list. > > > > The board is called "generic". No, just kidding ;) > > /me slaps Sascha > > Seriously though; I do intend to fix this, but I don't think adding a > generic entry to the compatible list is the right way to do it. For > example, what would "mpc5200-generic" really mean anyway? Convention > for usage of 'compatible' would indicate that it means the *entire > board* is compatible (obviously not true). The use-case you're > talking about is simply "the board uses a 5200 and firmware is sane". > On the other hand, I may just be overthinking things and compatible is > the most appropriate place to specify that the board is a mpc5200 > based board. (please feel free to argue with my; my opinion can > probably be swayed... attaching promises of beer to your argument is > probably an effective strategy) At the moment my compatible entry looks like this: compatible = "phytec,pcm030","generic-mpc52xx"; What I think would be nice is that "phytec,pcm030" support is used when available and "generic-mpc52xx" as a fallback. We do not have any platform specific hacks at the moment, but we may have later. Having "phytec,pcm030" in the simple machine would prevent us from doing so. > > This is an issue that probably affects the other embedded platforms > too, so it would be nice to agree on a common method of handling it. > > Regardless, whatever method is chosen, it is also important that it is > always possible for board specific fixups to override the generic > behavior. agreed Sascha -- Pengutronix e.K. - Linux Solutions for Science and Industry --- Kontakt-Informationen finden Sie im Header dieser Mail oder auf der Webseite -> http://www.pengutronix.de/impressum/ <- ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC][WIP][PATCH] Add IRQSTACKS to ppc32
On Apr 24, 2008, at 9:53 AM, Benjamin Herrenschmidt wrote: On Thu, 2008-04-24 at 07:59 -0500, Kumar Gala wrote: I'm going to change it to be just lmb_alloc() so it will be difficult to share with ppc64 (other than w/an ifdef). Unless we change lmb_alloc to just be an lmb_alloc_base with 0 and have the later do the right thing ? don't follow. Look at the "real" patch and comment on that. You don't put highmem in the LMBs ? If you do, we do need to have the max lowmem there no ? we restrict lmb alloc via LMB_REAL_LIMIT in include/asm-powerpc/lmb.h - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: mpc5200b custom board upstreamable?
On Thu, Apr 24, 2008 at 9:53 AM, Sascha Hauer <[EMAIL PROTECTED]> wrote: > On Thu, Apr 24, 2008 at 09:13:45AM -0600, Grant Likely wrote: > > On Thu, Apr 24, 2008 at 9:12 AM, Sascha Hauer <[EMAIL PROTECTED]> wrote: > > > > > > Hi all, > > > > > > I had the intention to push the code for a custom mpc5200b board (freely > > > available, no internal project) upstream. After cleaning up the code I > > > realized that actually no board specific code is left and our board is > > > well handled by the mpc5200_simple_platform machine. > > > > > > The only issue is that the machine only matches things like > > > "schindler,cm5200", there's no generic entry. Would it be possible to > > > add a "generic-mpc52xx" entry to this list? > > > > I'm being cautious about this for the time being. I'd like to have a > > generic match mechanism, but I don't want to do something that isn't > > easy to recover from if it turns out to be brain dead. For now, just > > add your board name to the explicit match list. > > The board is called "generic". No, just kidding ;) /me slaps Sascha Seriously though; I do intend to fix this, but I don't think adding a generic entry to the compatible list is the right way to do it. For example, what would "mpc5200-generic" really mean anyway? Convention for usage of 'compatible' would indicate that it means the *entire board* is compatible (obviously not true). The use-case you're talking about is simply "the board uses a 5200 and firmware is sane". On the other hand, I may just be overthinking things and compatible is the most appropriate place to specify that the board is a mpc5200 based board. (please feel free to argue with my; my opinion can probably be swayed... attaching promises of beer to your argument is probably an effective strategy) This is an issue that probably affects the other embedded platforms too, so it would be nice to agree on a common method of handling it. Regardless, whatever method is chosen, it is also important that it is always possible for board specific fixups to override the generic behavior. Cheers, g. -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: mpc5200b custom board upstreamable?
On Thu, Apr 24, 2008 at 09:13:45AM -0600, Grant Likely wrote: > On Thu, Apr 24, 2008 at 9:12 AM, Sascha Hauer <[EMAIL PROTECTED]> wrote: > > > > Hi all, > > > > I had the intention to push the code for a custom mpc5200b board (freely > > available, no internal project) upstream. After cleaning up the code I > > realized that actually no board specific code is left and our board is > > well handled by the mpc5200_simple_platform machine. > > > > The only issue is that the machine only matches things like > > "schindler,cm5200", there's no generic entry. Would it be possible to > > add a "generic-mpc52xx" entry to this list? > > I'm being cautious about this for the time being. I'd like to have a > generic match mechanism, but I don't want to do something that isn't > easy to recover from if it turns out to be brain dead. For now, just > add your board name to the explicit match list. The board is called "generic". No, just kidding ;) > > > > > Another question: are defconfig and dts files for custom boards acceptable > > for upstream? > > Yes, in the arch/powerpc/configs/52xx/ directory. ok Sascha -- Pengutronix e.K. - Linux Solutions for Science and Industry --- Kontakt-Informationen finden Sie im Header dieser Mail oder auf der Webseite -> http://www.pengutronix.de/impressum/ <- ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 00/10] powerpc: Add kexec/kdump support for ppc32
On Thu, Apr 24, 2008 at 07:50:52AM -0500, Kumar Gala wrote: > On Nov 22, 2007, at 9:42 AM, Dale Farnsworth wrote: >> This patch series adds kexec and kdump support for ppc32 in arch/ >> powerpc. >> It has been successfully tested on the mpc8548_cds and prpmc2800 >> platforms. >> Mark Greer and I are preparing patches to the kexec-tools package as >> well. > > Dale, can you look at updating your patchset now that we've made some > progress on other patches. Yes. It'll take a couple of weeks for me to fit it in though. -Dale ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: missing current-speed property prevents autoconsole on pegasos
Why not just have users who wish to use console serial port autodetection
add 3 lines to their nvramrc?
--
Matt Sealey <[EMAIL PROTECTED]>
Genesi, Manager, Developer Relations
Olaf Hering wrote:
Pegasos2 has no current-speed property in
/[EMAIL PROTECTED]/[EMAIL PROTECTED]/[EMAIL PROTECTED] As a result,
console=ttyS0,115200 is
still required unless the patch below is used.
What is the correct way to restore console detection on pegasos2?
Index: linux-2.6.25-pegasos/arch/powerpc/platforms/chrp/setup.c
===
--- linux-2.6.25-pegasos.orig/arch/powerpc/platforms/chrp/setup.c
+++ linux-2.6.25-pegasos/arch/powerpc/platforms/chrp/setup.c
@@ -302,7 +305,7 @@ static void chrp_init_early(void)
if (!property)
goto out_put;
if (!strcmp(property, "failsafe") || !strcmp(property, "serial"))
- add_preferred_console("ttyS", 0, NULL);
+ add_preferred_console("ttyS", 0, "115200");
out_put:
of_node_put(node);
}
___
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[PATCH] add gpiolib support for mpc5200
Hi all,
Feel free to comment on this.
Sascha
This patch adds gpiolib support for mpc5200 SOCs. I'm not sure
whether it's a good idea to make this optional via kconfig.
The gpt devices only support a single gpio. In the current of_gpio
implementation each chip consumes 32 GPIOs which leads to huge
gaps.
Signed-off-by: Sascha Hauer <[EMAIL PROTECTED]>
---
arch/powerpc/platforms/52xx/Kconfig|6
arch/powerpc/platforms/52xx/Makefile |2
arch/powerpc/platforms/52xx/mpc52xx_gpio.c | 408 +
3 files changed, 416 insertions(+)
Index: arch/powerpc/platforms/52xx/mpc52xx_gpio.c
===
--- /dev/null
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpio.c
@@ -0,0 +1,408 @@
+/*
+ * MPC52xx gpio driver
+ *
+ * Copyright (c) 2008 Sascha Hauer <[EMAIL PROTECTED]>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static DEFINE_SPINLOCK(gpio_lock);
+
+/*
+ * GPIO LIB API implementation for wakeup GPIOs.
+ *
+ * There's a maximum of 8 wakeup GPIOs. Which of these are available
+ * for use depends on your board setup.
+ *
+ * 0 -> GPIO_WKUP_7
+ * 1 -> GPIO_WKUP_6
+ * 2 -> PSC6_1
+ * 3 -> PSC6_0
+ * 4 -> ETH_17
+ * 5 -> PSC3_9
+ * 6 -> PSC2_4
+ * 7 -> PSC1_4
+ *
+ */
+static int mpc52xx_wkup_gpio_get(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
+ unsigned int ret;
+
+ ret = (in_8(®s->wkup_ival) >> (7 - gpio)) & 1;
+
+ pr_debug("%s: gpio: %d ret: %d\n", __func__, gpio, ret);
+
+ return ret;
+}
+
+static void mpc52xx_wkup_gpio_set(struct gpio_chip *gc, unsigned int gpio, int
val)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
+ unsigned int tmp;
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpio_lock, flags);
+
+ tmp = in_8(®s->wkup_dvo);
+ if (val)
+ tmp |= 1 << (7 - gpio);
+ else
+ tmp &= ~(1 << (7 - gpio));
+ out_8(®s->wkup_dvo, tmp);
+
+ spin_unlock_irqrestore(&gpio_lock, flags);
+
+ pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
+}
+
+static int mpc52xx_wkup_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct mpc52xx_gpio_wkup *regs = mm_gc->regs;
+ unsigned int tmp;
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpio_lock, flags);
+
+ tmp = in_8(®s->wkup_ddr);
+ tmp &= ~(1 << (7 - gpio));
+ out_8(®s->wkup_ddr, tmp);
+
+ spin_unlock_irqrestore(&gpio_lock, flags);
+
+ return 0;
+}
+
+static int mpc52xx_wkup_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio,
int val)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct mpc52xx_gpio_wkup *regs = mm_gc->regs;
+ unsigned int tmp;
+ unsigned long flags;
+
+ /* First set initial value */
+ mpc52xx_wkup_gpio_set(gc, gpio, val);
+
+ spin_lock_irqsave(&gpio_lock, flags);
+
+ /* Then set direction */
+ tmp = in_8(®s->wkup_ddr);
+ tmp |= 1 << (7 - gpio);
+ out_8(®s->wkup_ddr, tmp);
+
+ /* Finally enable the pin */
+ tmp = in_8(®s->wkup_gpioe);
+ tmp |= 1 << (7 - gpio);
+ out_8(®s->wkup_gpioe, tmp);
+
+ spin_unlock_irqrestore(&gpio_lock, flags);
+
+ pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
+
+ return 0;
+}
+
+static int __devinit mpc52xx_wkup_gpiochip_probe(struct of_device *ofdev,
+const struct of_device_id *match)
+{
+ struct of_mm_gpio_chip *mmchip;
+ struct of_gpio_chip *chip;
+
+ mmchip = kzalloc(sizeof(*mmchip), GFP_KERNEL);
+ if (!mmchip)
+ return -ENOMEM;
+
+ chip = &mmchip->of_gc;
+
+ chip->gpio_cells = 2;
+ chip->gc.ngpio= 8;
+ chip->gc.direction_input = mpc52xx_wkup_gpio_dir_in;
+ chip->gc.direction_output = mpc52xx_wkup_gpio_dir_out;
+ chip->gc.get = mpc52xx_wkup_gpio_get;
+ chip->gc.set = mpc5
Memory corruption
Hi,
I saw some random lockups on my PS3, so I decided to give the current kernel a
try on the PS3 development tool. It crashes when setting up the network:
| <5>Sending DHCP requests ., OK
| IP-Config: Got DHCP answer from 192.168.106.200, my address is 192.168.106.196
| IP-Config: Complete:
| device=eth0, addr=192.168.106.196, mask=255.255.255.0,
gw=192.168.106.254,
| host=192.168.106.196, domain=sonytel.be, nis-domain=(none),
| bootserver=192.168.106.200, rootserver=192.168.106.200,
rootpath=/disk-02/ps3linux/debian-powerpc
| <5>Looking up port of RPC 13/2 on 192.168.106.200
| <0>Unrecoverable FP Unavailable Exception 800 at c0305220
| Oops: Unrecoverable FP Unavailable Exception, sig: 6 [#1]
| SMP NR_CPUS=2 PS3
| Modules linked in:
| NIP: c0305220 LR: c0304d34 CTR: c03051c0
| REGS: c604aa70 TRAP: 0800 Not tainted (2.6.25-03562-g3dc5063-dirty)
| MSR: 80008032 CR: 24004082 XER:
| TASK = c6046040[1] 'swapper' THREAD: c6048000 CPU: 0
| <6>GPR00: 0800 c604acf0 c0603a88 c6262680
| <6>GPR04: 066216040002 4000 c64a4110 c062eda8
| <6>GPR08: c61a6000 0001 0100 c62bf880
| <6>GPR12: 0011 c0548300
| <6>GPR16: 005c 005c
| <6>GPR20: c63a9db8 c0a86ac8 c63a9d08
| <6>GPR24: 0040 4000 c63a9b80 c6391e00
| <6>GPR28: c64a4020 c6262680 c05ae478 c604acf0
| NIP [c0305220] .ip_output+0x60/0x8c
| LR [c0304d34] .ip_local_out+0x50/0x78
| Call Trace:
| [c604acf0] [c604ada0] 0xc604ada0 (unreliable)
| [c604ad70] [c0304d34] .ip_local_out+0x50/0x78
| [c604ae00] [c03050c0] .ip_push_pending_frames+0x364/0x410
| [c604aeb0] [c0326a60] .udp_push_pending_frames+0x350/0x408
| [c604af70] [c0328048] .udp_sendmsg+0x4c4/0x630
| [c604b0d0] [c03306e4] .inet_sendmsg+0x84/0xb0
| [c604b170] [c02cd430] .sock_sendmsg+0xc4/0x108
| [c604b370] [c02ceed8] .kernel_sendmsg+0x40/0x64
| [c604b400] [c038cc1c] .xs_send_kvec+0xc8/0x100
| [c604b510] [c038cd10] .xs_sendpages+0xbc/0x2f4
| [c604b5e0] [c038ed38] .xs_udp_send_request+0x60/0x148
| [c604b680] [c038b1b8] .xprt_transmit+0x144/0x27c
| [c604b730] [c038776c] .call_transmit+0x248/0x2b0
| [c604b7d0] [c0390a68] .__rpc_execute+0xd8/0x314
| [c604b870] [c0390d18] .rpc_execute+0x40/0x5c
| [c604b900] [c0387fe8] .rpc_run_task+0x84/0xb0
| [c604b9a0] [c038814c] .rpc_call_sync+0x74/0xc0
| [c604ba70] [c039a568] .rpcb_getport_sync+0x110/0x178
| [c604bb80] [c058] .root_nfs_getport+0x8c/0xbc
| [c604bc30] [c05112f0] .nfs_root_data+0x1a8/0x328
| [c604bd70] [c04f66a8] .mount_root+0x40/0x150
| [c604be10] [c04f695c] .prepare_namespace+0x1a4/0x1f4
| [c604bea0] [c04f5a48] .kernel_init+0x388/0x3c8
| [c604bf90] [c00229c8] .kernel_thread+0x4c/0x68
| Instruction dump:
| e9230028 e8fe8018 7c26 54001ffe e9090018 78001f24 7d27002a 38000800
| 7d2948f8 7d6b482a e92b0058 39290001 00546e70 f9030020 4bfff775
should be f92b0058 b003007e
| <4>---[ end trace c7cf3d9b6c787395 ]---
| <0>Kernel panic - not syncing: Attempted to kill init!
| smp_call_function on cpu 0: other cpus not responding (0)
|
|System does not reboot automatically.
|Please press POWER button.
|
| <7>eth0: no IPv6 routers present
Findings:
- Disabling CONFIG_INET fixed the problem.
- I didn't manage to lock up my PS3 afterwards neither.
But... while typing this, I saw an oops accessing address
0xf000f000f0007000 somewhere in the networking code, so it looks like some
corruption is going on after all.
- Upon closer look, 8 bytes in the instruction dump above are not correct
and have been overwritten with 0xc0546e70, which is the address of
init_task.
With kind regards,
Geert Uytterhoeven
Software Architect
Sony Network and Software Technology Center Europe
The Corporate Village · Da Vincilaan 7-D1 · B-1935 Zaventem · Belgium
Phone:+32 (0)2 700 8453
Fax: +32 (0)2 700 8622
E-mail: [EMAIL PROTECTED]
Internet: http://www.sony-europe.com/
Sony Network and Software Technology Center Europe
A division of Sony Service Centre (Europe) N.V.
Registered office: Technologielaan 7 · B-1840 Londerzeel · Belgium
VAT BE 0413.825.160 · RPR Brussels
Fortis Bank Zaventem · BIC GEBABEBB08A · IBAN BE3
Re: mpc5200b custom board upstreamable?
On Thu, Apr 24, 2008 at 9:12 AM, Sascha Hauer <[EMAIL PROTECTED]> wrote: > > Hi all, > > I had the intention to push the code for a custom mpc5200b board (freely > available, no internal project) upstream. After cleaning up the code I > realized that actually no board specific code is left and our board is > well handled by the mpc5200_simple_platform machine. > > The only issue is that the machine only matches things like > "schindler,cm5200", there's no generic entry. Would it be possible to > add a "generic-mpc52xx" entry to this list? I'm being cautious about this for the time being. I'd like to have a generic match mechanism, but I don't want to do something that isn't easy to recover from if it turns out to be brain dead. For now, just add your board name to the explicit match list. > > Another question: are defconfig and dts files for custom boards acceptable > for upstream? Yes, in the arch/powerpc/configs/52xx/ directory. Cheers, g -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
mpc5200b custom board upstreamable?
Hi all, I had the intention to push the code for a custom mpc5200b board (freely available, no internal project) upstream. After cleaning up the code I realized that actually no board specific code is left and our board is well handled by the mpc5200_simple_platform machine. The only issue is that the machine only matches things like "schindler,cm5200", there's no generic entry. Would it be possible to add a "generic-mpc52xx" entry to this list? Another question: are defconfig and dts files for custom boards acceptable for upstream? Sascha -- Pengutronix e.K. - Linux Solutions for Science and Industry --- Kontakt-Informationen finden Sie im Header dieser Mail oder auf der Webseite -> http://www.pengutronix.de/impressum/ <- ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC][WIP][PATCH] Add IRQSTACKS to ppc32
On Thu, 2008-04-24 at 07:59 -0500, Kumar Gala wrote: > I'm going to change it to be just lmb_alloc() so it will be difficult > to share with ppc64 (other than w/an ifdef). Unless we change lmb_alloc to just be an lmb_alloc_base with 0 and have the later do the right thing ? You don't put highmem in the LMBs ? If you do, we do need to have the max lowmem there no ? Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH] [POWERPC] Add IRQSTACKS support on ppc32
* Added allocation and initialization of the irq stacks. We limit the
stacks to be in lowmem for ppc32.
* Implemented ppc32 versions of call_do_softirq() and call_handle_irq()
to switch the stack pointers
* Reworked how we do stack overflow detection. We now keep around the
limit of the stack in the thread_struct and compare against the limit
to see if we've overflowed. We can now use this on ppc64 if desired.
Signed-off-by: Kumar Gala <[EMAIL PROTECTED]>
---
arch/powerpc/Kconfig.debug|1 -
arch/powerpc/kernel/asm-offsets.c |1 +
arch/powerpc/kernel/entry_32.S|4 ++--
arch/powerpc/kernel/irq.c | 10 +-
arch/powerpc/kernel/misc_32.S | 25 +
arch/powerpc/kernel/process.c |2 ++
arch/powerpc/kernel/setup_32.c| 21 +
include/asm-powerpc/processor.h |6 ++
8 files changed, 66 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index a86d8d8..2cf72d2 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -118,7 +118,6 @@ config XMON_DISASSEMBLY
config IRQSTACKS
bool "Use separate kernel stacks when processing interrupts"
- depends on PPC64
help
If you say Y here the kernel will use separate kernel stacks
for handling hard and soft interrupts. This can help avoid
diff --git a/arch/powerpc/kernel/asm-offsets.c
b/arch/powerpc/kernel/asm-offsets.c
index adf1d09..0ef4d41 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -64,6 +64,7 @@ int main(void)
#endif /* CONFIG_PPC64 */
DEFINE(KSP, offsetof(struct thread_struct, ksp));
+ DEFINE(KSP_LIMIT, offsetof(struct thread_struct, ksp_limit));
DEFINE(PT_REGS, offsetof(struct thread_struct, regs));
DEFINE(THREAD_FPEXC_MODE, offsetof(struct thread_struct, fpexc_mode));
DEFINE(THREAD_FPR0, offsetof(struct thread_struct, fpr[0]));
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 84c8686..f33c1fe 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -137,8 +137,8 @@ transfer_to_handler:
2: /* if from kernel, check interrupted DOZE/NAP mode and
* check for stack overflow
*/
- lwz r9,THREAD_INFO-THREAD(r12)
- cmplw r1,r9 /* if r1 <= current->thread_info */
+ lwz r9,KSP_LIMIT(r12)
+ cmplw r1,r9 /* if r1 <= ksp_limit */
ble-stack_ovf /* then the kernel stack overflowed */
5:
#ifdef CONFIG_6xx
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 425616f..7378c98 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -307,6 +307,7 @@ void do_IRQ(struct pt_regs *regs)
if (curtp != irqtp) {
struct irq_desc *desc = irq_desc + irq;
void *handler = desc->handle_irq;
+ unsigned long saved_sp_limit =
current->thread.ksp_limit;
if (handler == NULL)
handler = &__do_IRQ;
irqtp->task = curtp->task;
@@ -319,7 +320,10 @@ void do_IRQ(struct pt_regs *regs)
(irqtp->preempt_count & ~SOFTIRQ_MASK) |
(curtp->preempt_count & SOFTIRQ_MASK);
+ current->thread.ksp_limit = (unsigned long)irqtp +
+ _ALIGN_UP(sizeof(struct thread_info), 16);
call_handle_irq(irq, desc, irqtp, handler);
+ current->thread.ksp_limit = saved_sp_limit;
irqtp->task = NULL;
@@ -352,7 +356,7 @@ void __init init_IRQ(void)
{
if (ppc_md.init_IRQ)
ppc_md.init_IRQ();
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_IRQSTACKS
irq_ctx_init();
#endif
}
@@ -383,11 +387,15 @@ void irq_ctx_init(void)
static inline void do_softirq_onstack(void)
{
struct thread_info *curtp, *irqtp;
+ unsigned long saved_sp_limit = current->thread.ksp_limit;
curtp = current_thread_info();
irqtp = softirq_ctx[smp_processor_id()];
irqtp->task = curtp->task;
+ current->thread.ksp_limit = (unsigned long)irqtp +
+ _ALIGN_UP(sizeof(struct thread_info), 16);
call_do_softirq(irqtp);
+ current->thread.ksp_limit = saved_sp_limit;
irqtp->task = NULL;
}
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 92ccc6f..896 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -32,6 +32,31 @@
.text
+#ifdef CONFIG_IRQSTACKS
+_GLOBAL(call_do_softirq)
+ mflrr0
+ stw r0,4(r1)
+ stwur1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
+ mr r1,r3
+ bl __do_softirq
+
[PATCH v5] create modalias file in sysfs for bus of_platform
Create /sys/bus/of_platform/devices/*/modalias file to allow autoloading
of modules. modalias files are already present for many other bus types.
This adds also a newline to the devspec files.
Also create a devspec file for mac-io devices. They were created as a side
effect. Use correct buffer size for mac-io modalias buffer.
Tested on iBook1 and Efika.
Signed-off-by: Olaf Hering <[EMAIL PROTECTED]>
---
drivers/macintosh/macio_sysfs.c | 12 +++-
drivers/of/device.c | 36
drivers/of/platform.c |3 +++
3 files changed, 34 insertions(+), 17 deletions(-)
--- a/drivers/macintosh/macio_sysfs.c
+++ b/drivers/macintosh/macio_sysfs.c
@@ -44,7 +44,7 @@ static ssize_t modalias_show (struct dev
struct of_device *ofdev = to_of_device(dev);
int len;
- len = of_device_get_modalias(ofdev, buf, PAGE_SIZE);
+ len = of_device_get_modalias(ofdev, buf, PAGE_SIZE - 2);
buf[len] = '\n';
buf[len+1] = 0;
@@ -52,6 +52,15 @@ static ssize_t modalias_show (struct dev
return len+1;
}
+static ssize_t devspec_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct of_device *ofdev;
+
+ ofdev = to_of_device(dev);
+ return sprintf(buf, "%s\n", ofdev->node->full_name);
+}
+
macio_config_of_attr (name, "%s\n");
macio_config_of_attr (type, "%s\n");
@@ -60,5 +69,6 @@ struct device_attribute macio_dev_attrs[
__ATTR_RO(type),
__ATTR_RO(compatible),
__ATTR_RO(modalias),
+ __ATTR_RO(devspec),
__ATTR_NULL
};
--- a/drivers/of/device.c
+++ b/drivers/of/device.c
@@ -48,16 +48,32 @@ void of_dev_put(struct of_device *dev)
}
EXPORT_SYMBOL(of_dev_put);
-static ssize_t dev_show_devspec(struct device *dev,
+static ssize_t devspec_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct of_device *ofdev;
ofdev = to_of_device(dev);
- return sprintf(buf, "%s", ofdev->node->full_name);
+ return sprintf(buf, "%s\n", ofdev->node->full_name);
}
-static DEVICE_ATTR(devspec, S_IRUGO, dev_show_devspec, NULL);
+static ssize_t modalias_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct of_device *ofdev = to_of_device(dev);
+ ssize_t len = 0;
+
+ len = of_device_get_modalias(ofdev, buf, PAGE_SIZE - 2);
+ buf[len] = '\n';
+ buf[len+1] = 0;
+ return len+1;
+}
+
+struct device_attribute of_platform_device_attrs[] = {
+ __ATTR_RO(devspec),
+ __ATTR_RO(modalias),
+ __ATTR_NULL
+};
/**
* of_release_dev - free an of device structure when all users of it are
finished.
@@ -78,25 +94,13 @@ EXPORT_SYMBOL(of_release_dev);
int of_device_register(struct of_device *ofdev)
{
- int rc;
-
BUG_ON(ofdev->node == NULL);
-
- rc = device_register(&ofdev->dev);
- if (rc)
- return rc;
-
- rc = device_create_file(&ofdev->dev, &dev_attr_devspec);
- if (rc)
- device_unregister(&ofdev->dev);
-
- return rc;
+ return device_register(&ofdev->dev);
}
EXPORT_SYMBOL(of_device_register);
void of_device_unregister(struct of_device *ofdev)
{
- device_remove_file(&ofdev->dev, &dev_attr_devspec);
device_unregister(&ofdev->dev);
}
EXPORT_SYMBOL(of_device_unregister);
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -17,6 +17,8 @@
#include
#include
+extern struct device_attribute of_platform_device_attrs[];
+
static int of_platform_bus_match(struct device *dev, struct device_driver *drv)
{
struct of_device *of_dev = to_of_device(dev);
@@ -103,6 +105,7 @@ int of_bus_type_init(struct bus_type *bu
bus->suspend = of_platform_device_suspend;
bus->resume = of_platform_device_resume;
bus->shutdown = of_platform_device_shutdown;
+ bus->dev_attrs = of_platform_device_attrs;
return bus_register(bus);
}
___
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Re: [RFC][WIP][PATCH] Add IRQSTACKS to ppc32
On Apr 24, 2008, at 2:18 AM, Benjamin Herrenschmidt wrote:
On Thu, 2008-04-24 at 00:37 -0500, Kumar Gala wrote:
+ /*
+* interrupt stacks must be under 256MB, we cannot afford to
take
+* SLB misses on them.
+*/
+ for_each_possible_cpu(i) {
+ softirq_ctx[i] = (struct thread_info *)
+ __va(lmb_alloc_base(THREAD_SIZE,
+ THREAD_SIZE,
0x1000));
+ hardirq_ctx[i] = (struct thread_info *)
+ __va(lmb_alloc_base(THREAD_SIZE,
+ THREAD_SIZE,
0x1000));
+ }
+
The comment is a bit bogus :-) (about SLB misses). lowmem is your
limit
I think. Also, why not share the code with ppc64 ?
I'm going to change it to be just lmb_alloc() so it will be difficult
to share with ppc64 (other than w/an ifdef).
- k
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Re: [PATCH 00/10] powerpc: Add kexec/kdump support for ppc32
On Nov 22, 2007, at 9:42 AM, Dale Farnsworth wrote: This patch series adds kexec and kdump support for ppc32 in arch/ powerpc. It has been successfully tested on the mpc8548_cds and prpmc2800 platforms. Mark Greer and I are preparing patches to the kexec-tools package as well. Dale, can you look at updating your patchset now that we've made some progress on other patches. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Patches pushed to powerpc.git master and powerpc-next branches
I have put the following patches in the powerpc.git repository on the master & powerpc-next branches (this includes some pulled from Kumar's tree). I plan to send a pull request to Linus tomorrow morning my time, so if there are any others I've missed, or any that people don't think should go in, let me know within the next 9 hours or so. Paul. Adrian Bunk (2): [POWERPC] drivers/of/of_i2c.c: Add MODULE_LICENSE [POWERPC] char/xilinx_hwicap/ section fix Benjamin Herrenschmidt (3): [POWERPC] Add thread_info_cache_init() weak hook [POWERPC] Fix kernel stack allocation alignment [POWERPC] Use __weak macro for smp_setup_processor_id Christoph Hellwig (1): [POWERPC] Fix new warnings arising from stacktrace patch Geoff Levand (1): [POWERPC] PS3: Fix gelic net module dependency Ishizaki Kou (9): [POWERPC] cell: Generalize io-workarounds code [POWERPC] celleb: Consolidate io-workarounds code [POWERPC] celleb: Move the files for celleb base support [POWERPC] celleb: Move the SCC related code for celleb [POWERPC] celleb: Move files for Beat hvcall interfaces [POWERPC] celleb: Move files for Beat mmu and iommu [POWERPC] celleb: Move a file for SPU on Beat [POWERPC] celleb: Move miscellaneous files for Beat [POWERPC] celleb: Add support for PCI Express Josh Boyer (2): [POWERPC] 4xx: Fix duplicate phys_addr_t definition [POWERPC] Add strncmp to arch/ppc Kay Sievers (1): [POWERPC] macintosh/windfarm: Fix platform driver hotplug/coldplug Kumar Gala (8): [PPC] Remove mpc8272 ads board from arch/ppc [PPC] Remove mpc885ads and mpc86x ads boards from arch/ppc [POWERPC] ppc32: Fix errata for 603 CPUs [POWERPC] 85xx: Add support for relocatable kernel (and booting at non-zero) [POWERPC] Port fixmap from x86 and use for kmap_atomic [POWERPC] Clean up access to thread_info in assembly [POWERPC] Cleanup asm-offsets.c [POWERPC] Clean up misc_64.S Michael Ellerman (9): [POWERPC] Add include of linux/of.h to numa.c [POWERPC] Add include of linux/of.h to os-area.c [POWERPC] Discourage people from fiddling with kernel data from prom_init [POWERPC] Use of_get_next_parent() in platforms/cell/axon_msi.c [POWERPC] Set udbg_console index to 0 [POWERPC] Mark udbg console as CON_ANYTIME, ie. callable early in boot [POWERPC] Register udbg console early on pseries LPAR [POWERPC] Convert from DBG() to pr_debug() in platforms/pseries/ [POWERPC] Add CONFIG_PPC_PSERIES_DEBUG to enable debugging for platforms/pseries Paul Mackerras (1): Revert "[POWERPC] Add compat handler for PTRACE_GETSIGINFO" Remi Machet (3): [POWERPC] Use default values if necessary in mv64x60 I2C initialization [POWERPC] Initialize all mv64x60 devices even if one fails [POWERPC] Fix mv64x60 early console code to use cell-index property Timur Tabi (1): [POWERPC] Add Timur Tabi to the MAINTAINERS file Tony Breeds (2): [POWERPC] Make iSeries spin on __secondary_hold_spinloop, like pSeries [POWERPC] Raise the upper limit of NR_CPUS and move the pacas into the BSS ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 9/9] celleb: add support for PCI Express
On Thu, 2008-04-24 at 19:27 +0900, Ishizaki Kou wrote: > This patch adds support for PCI Express port on Celleb. I/O space > of this PCI Express port is not mapped in memory space. So we use > the io-workaround mechanism to make accesses indirect. > > I send this patch again because it would be lost. > > Signed-off-by: Kou Ishizaki <[EMAIL PROTECTED]> > Acked-by: Arnd Bergmann <[EMAIL PROTECTED]> > --- Looks good. Doesn't affect non-celleb. I have no time to do a proper test tonight but I think it's good to go. Ack. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 9/9] celleb: add support for PCI Express
This patch adds support for PCI Express port on Celleb. I/O space of this PCI Express port is not mapped in memory space. So we use the io-workaround mechanism to make accesses indirect. I send this patch again because it would be lost. Signed-off-by: Kou Ishizaki <[EMAIL PROTECTED]> Acked-by: Arnd Bergmann <[EMAIL PROTECTED]> --- arch/powerpc/platforms/cell/Makefile |1 arch/powerpc/platforms/cell/celleb_pci.c |3 arch/powerpc/platforms/cell/celleb_pci.h |1 arch/powerpc/platforms/cell/celleb_scc.h | 87 +++ arch/powerpc/platforms/cell/celleb_scc_pciex.c | 547 + 5 files changed, 639 insertions(+) Index: b/arch/powerpc/platforms/cell/celleb_scc.h === --- a/arch/powerpc/platforms/cell/celleb_scc.h 2008-04-24 12:21:38.0 +0900 +++ b/arch/powerpc/platforms/cell/celleb_scc.h 2008-04-24 12:21:38.0 +0900 @@ -125,6 +125,93 @@ /* bits for SCC_EPCI_CNTOPT */ #define SCC_EPCI_CNTOPT_O2PMB 0x0002 +/* SCC PCIEXC SMMIO registers */ +#define PEXCADRS 0x000 +#define PEXCWDATA 0x004 +#define PEXCRDATA 0x008 +#define PEXDADRS 0x010 +#define PEXDCMND 0x014 +#define PEXDWDATA 0x018 +#define PEXDRDATA 0x01c +#define PEXREQID 0x020 +#define PEXTIDMAP 0x024 +#define PEXINTMASK 0x028 +#define PEXINTSTS 0x02c +#define PEXAERRMASK0x030 +#define PEXAERRSTS 0x034 +#define PEXPRERRMASK 0x040 +#define PEXPRERRSTS0x044 +#define PEXPRERRID01 0x048 +#define PEXPRERRID23 0x04c +#define PEXVDMASK 0x050 +#define PEXVDSTS 0x054 +#define PEXRCVCPLIDA 0x060 +#define PEXLENERRIDA 0x068 +#define PEXPHYPLLST0x070 +#define PEXDMRDEN0 0x100 +#define PEXDMRDADR00x104 +#define PEXDMRDENX 0x110 +#define PEXDMRDADRX0x114 +#define PEXECMODE 0xf00 +#define PEXMAEA(n) (0xf50 + (8 * n)) +#define PEXMAEC(n) (0xf54 + (8 * n)) +#define PEXCCRCTRL 0xff0 + +/* SCC PCIEXC bits and shifts for PEXCADRS */ +#define PEXCADRS_BYTE_EN_SHIFT 20 +#define PEXCADRS_CMD_SHIFT 16 +#define PEXCADRS_CMD_READ (0xa << PEXCADRS_CMD_SHIFT) +#define PEXCADRS_CMD_WRITE (0xb << PEXCADRS_CMD_SHIFT) + +/* SCC PCIEXC shifts for PEXDADRS */ +#define PEXDADRS_BUSNO_SHIFT 20 +#define PEXDADRS_DEVNO_SHIFT 15 +#define PEXDADRS_FUNCNO_SHIFT 12 + +/* SCC PCIEXC bits and shifts for PEXDCMND */ +#define PEXDCMND_BYTE_EN_SHIFT 4 +#define PEXDCMND_IO_READ 0x2 +#define PEXDCMND_IO_WRITE 0x3 +#define PEXDCMND_CONFIG_READ 0xa +#define PEXDCMND_CONFIG_WRITE 0xb + +/* SCC PCIEXC bits for PEXPHYPLLST */ +#define PEXPHYPLLST_PEXPHYAPLLST 0x0001 + +/* SCC PCIEXC bits for PEXECMODE */ +#define PEXECMODE_ALL_THROUGH 0x +#define PEXECMODE_ALL_8BIT 0x00550155 +#define PEXECMODE_ALL_16BIT0x00aa02aa + +/* SCC PCIEXC bits for PEXCCRCTRL */ +#define PEXCCRCTRL_PEXIPCOREEN 0x0004 +#define PEXCCRCTRL_PEXIPCONTEN 0x0002 +#define PEXCCRCTRL_PEXPHYPLLEN 0x0001 +#define PEXCCRCTRL_PCIEXCAOCKEN0x0100 + +/* SCC PCIEXC port configuration registers */ +#define PEXTCERRCHK0x21c +#define PEXTAMAPB0 0x220 +#define PEXTAMAPL0 0x224 +#define PEXTAMAPB(n) (PEXTAMAPB0 + 8 * (n)) +#define PEXTAMAPL(n) (PEXTAMAPL0 + 8 * (n)) +#define PEXCHVC0P 0x500 +#define PEXCHVC0NP 0x504 +#define PEXCHVC0C 0x508 +#define PEXCDVC0P 0x50c +#define PEXCDVC0NP 0x510 +#define PEXCDVC0C 0x514 +#define PEXCHVCXP 0x518 +#define PEXCHVCXNP 0x51c +#define PEXCHVCXC 0x520 +#define PEXCDVCXP 0x524 +#define PEXCDVCXNP 0x528 +#define PEXCDVCXC 0x52c +#define PEXCTTRG 0x530 +#define PEXTSCTRL 0x700 +#define PEXTSSTS 0x704 +#define PEXSKPCTRL 0x708 + /* UHC registers */ #define SCC_UHC_CKRCTRL 0xff0 #define SCC_UHC_ECMODE 0xf00 Index: b/arch/powerpc/platforms/cell/celleb_scc_pciex.c === --- /dev/null 1970-01-01 00:00:00.0 + +++ b/arch/powerpc/platforms/cell/celleb_scc_pciex.c2008-04-24 12:21:38.0 +0900 @@ -0,0 +1,547 @@ +/* + * Support for Celleb PCI-Express. + * + * (C) Copyright 2007-2008 TOSHIBA CORPORATION + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public Lice
Re: [PATCH 2/9] celleb: consolidate io-workarounds code
On Thu, 2008-04-24 at 18:24 +0900, Ishizaki Kou wrote:
> Now, we can use generic io-workarounds mechanism and the workaround
> code for spider-pci. This patch changes Celleb PCI code to use
> spider-pci code.
>
> Signed-off-by: Kou Ishizaki <[EMAIL PROTECTED]>
> Acked-by: Arnd Bergmann <[EMAIL PROTECTED]>
> ---
> arch/powerpc/platforms/cell/Makefile |6
> arch/powerpc/platforms/celleb/Makefile |3
> arch/powerpc/platforms/celleb/io-workarounds.c | 280
> -
> arch/powerpc/platforms/celleb/pci.c| 41 ++-
> arch/powerpc/platforms/celleb/pci.h| 18 -
> arch/powerpc/platforms/celleb/scc_epci.c | 59 -
> arch/powerpc/platforms/celleb/setup.c |2
> 7 files changed, 52 insertions(+), 357 deletions(-)
>
> Index: b/arch/powerpc/platforms/celleb/pci.c
> ===
> --- a/arch/powerpc/platforms/celleb/pci.c 2008-04-24 12:05:34.0
> +0900
> +++ b/arch/powerpc/platforms/celleb/pci.c 2008-04-24 12:06:12.0
> +0900
> @@ -41,6 +41,7 @@
> #include
> #include
>
> +#include "../cell/io-workarounds.h"
> #include "pci.h"
> #include "interrupt.h"
>
> @@ -457,33 +458,39 @@
> return 0;
> }
>
> -void __init fake_pci_workaround_init(struct pci_controller *phb)
> -{
> - /**
> - * We will add fake pci bus to scc_pci_bus for the purpose to improve
> - * I/O Macro performance. But device-tree and device drivers
> - * are not ready to use address with a token.
> - */
> -
> - /* celleb_pci_add_one(phb, NULL); */
> -}
> +static struct celleb_phb_spec celleb_fake_pci_spec __initdata = {
> + .setup = celleb_setup_fake_pci,
> +};
>
> static struct of_device_id celleb_phb_match[] __initdata = {
> {
> .name = "pci-pseudo",
> - .data = celleb_setup_fake_pci,
> + .data = &celleb_fake_pci_spec,
> }, {
> .name = "epci",
> - .data = celleb_setup_epci,
> + .data = &celleb_epci_spec,
> }, {
> },
> };
>
> +static int __init celleb_io_workaround_init(struct pci_controller *phb,
> + struct celleb_phb_spec *phb_spec)
> +{
> + if (phb_spec->ops) {
> + iowa_register_bus(phb, phb_spec->ops, phb_spec->iowa_init,
> + phb_spec->iowa_data);
> + io_workaround_init();
> + }
> +
> + return 0;
> +}
> +
> int __init celleb_setup_phb(struct pci_controller *phb)
> {
> struct device_node *dev = phb->dn;
> const struct of_device_id *match;
> - int (*setup_func)(struct device_node *, struct pci_controller *);
> + struct celleb_phb_spec *phb_spec;
> + int rc;
>
> match = of_match_node(celleb_phb_match, dev);
> if (!match)
> @@ -492,8 +499,12 @@
> phb_set_bus_ranges(dev, phb);
> phb->buid = 1;
>
> - setup_func = match->data;
> - return (*setup_func)(dev, phb);
> + phb_spec = match->data;
> + rc = (*phb_spec->setup)(dev, phb);
> + if (rc)
> + return 1;
> +
> + return celleb_io_workaround_init(phb, phb_spec);
> }
>
> int celleb_pci_probe_mode(struct pci_bus *bus)
> Index: b/arch/powerpc/platforms/celleb/pci.h
> ===
> --- a/arch/powerpc/platforms/celleb/pci.h 2008-04-24 12:05:34.0
> +0900
> +++ b/arch/powerpc/platforms/celleb/pci.h 2008-04-24 12:06:12.0
> +0900
> @@ -27,16 +27,18 @@
> #include
> #include
>
> +#include "../cell/io-workarounds.h"
> +
> +struct celleb_phb_spec {
> + int (*setup)(struct device_node *, struct pci_controller *);
> + struct ppc_pci_io *ops;
> + int (*iowa_init)(struct iowa_bus *, void *);
> + void *iowa_data;
> +};
> +
> extern int celleb_setup_phb(struct pci_controller *);
> extern int celleb_pci_probe_mode(struct pci_bus *);
>
> -extern int celleb_setup_epci(struct device_node *, struct pci_controller *);
> -
> -extern void *celleb_dummy_page_va;
> -extern int __init celleb_pci_workaround_init(void);
> -extern void __init celleb_pci_add_one(struct pci_controller *,
> - void (*)(struct pci_controller *));
> -extern void fake_pci_workaround_init(struct pci_controller *);
> -extern void epci_workaround_init(struct pci_controller *);
> +extern struct celleb_phb_spec celleb_epci_spec;
>
> #endif /* _CELLEB_PCI_H */
> Index: b/arch/powerpc/platforms/celleb/scc_epci.c
> ===
> --- a/arch/powerpc/platforms/celleb/scc_epci.c2008-04-24
> 12:05:34.0 +0900
> +++ b/arch/powerpc/platforms/celleb/scc_epci.c2008-04-24
> 12:06:39.0 +0900
> @@ -43,10 +43,6 @@
>
> #define iob() __asm__ __volatile__("eieio; sync":::"memory")
>
> -struct epci_private {
> - dma_addr_t
Re: [PATCH 1/9] cell: generalize io-workarounds code
On Thu, 2008-04-24 at 18:21 +0900, Ishizaki Kou wrote:
> This patch splits cell io-workaround code into spider-pci dependent
> code and a generic part, and also moves io-workarounds initialization
> into cell_setup_phb. This patch includes BenH's fix.
>
> Signed-off-by: Kou Ishizaki <[EMAIL PROTECTED]>
> Signed-off-by: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
I tested this (along with the 7 others as I didn't get 9/9) and they
work fine on a QS20 cell blade.
Acked-by: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
> ---
> arch/powerpc/kernel/of_platform.c|2
> arch/powerpc/platforms/cell/Makefile |3
> arch/powerpc/platforms/cell/io-workarounds.c | 360
> +++
> arch/powerpc/platforms/cell/io-workarounds.h | 49 +++
> arch/powerpc/platforms/cell/setup.c | 43 +++
> arch/powerpc/platforms/cell/spider-pci.c | 184 +
> include/asm-powerpc/io-defs.h| 107
> include/asm-powerpc/io.h |8
> 8 files changed, 437 insertions(+), 319 deletions(-)
>
> Index: b/arch/powerpc/platforms/cell/Makefile
> ===
> --- a/arch/powerpc/platforms/cell/Makefile2008-04-24 12:23:23.0
> +0900
> +++ b/arch/powerpc/platforms/cell/Makefile2008-04-24 12:23:25.0
> +0900
> @@ -1,6 +1,7 @@
> obj-$(CONFIG_PPC_CELL_NATIVE)+= interrupt.o iommu.o setup.o \
> cbe_regs.o spider-pic.o \
> -pervasive.o pmu.o io-workarounds.o
> +pervasive.o pmu.o io-workarounds.o \
> +spider-pci.o
> obj-$(CONFIG_CBE_RAS)+= ras.o
>
> obj-$(CONFIG_CBE_THERM) += cbe_thermal.o
> Index: b/arch/powerpc/platforms/cell/io-workarounds.c
> ===
> --- a/arch/powerpc/platforms/cell/io-workarounds.c2008-04-24
> 12:23:23.0 +0900
> +++ b/arch/powerpc/platforms/cell/io-workarounds.c2008-04-24
> 12:23:25.0 +0900
> @@ -1,6 +1,9 @@
> /*
> + * Support PCI IO workaround
> + *
> * Copyright (C) 2006 Benjamin Herrenschmidt <[EMAIL PROTECTED]>
> * IBM, Corp.
> + * (C) Copyright 2007-2008 TOSHIBA CORPORATION
> *
> * This program is free software; you can redistribute it and/or modify
> * it under the terms of the GNU General Public License version 2 as
> @@ -9,335 +12,174 @@
> #undef DEBUG
>
> #include
> -#include
> -#include
> +
> #include
> #include
> -#include
> +#include
> #include
>
> +#include "io-workarounds.h"
>
> -#define SPIDER_PCI_REG_BASE 0xd000
> -#define SPIDER_PCI_VCI_CNTL_STAT 0x0110
> -#define SPIDER_PCI_DUMMY_READ0x0810
> -#define SPIDER_PCI_DUMMY_READ_BASE 0x0814
> -
> -/* Undefine that to re-enable bogus prefetch
> - *
> - * Without that workaround, the chip will do bogus prefetch past
> - * page boundary from system memory. This setting will disable that,
> - * though the documentation is unclear as to the consequences of doing
> - * so, either purely performances, or possible misbehaviour... It's not
> - * clear wether the chip can handle unaligned accesses at all without
> - * prefetching enabled.
> - *
> - * For now, things appear to be behaving properly with that prefetching
> - * disabled and IDE, possibly because IDE isn't doing any unaligned
> - * access.
> - */
> -#define SPIDER_DISABLE_PREFETCH
> -
> -#define MAX_SPIDERS 3
> +#define IOWA_MAX_BUS 8
>
> -static struct spider_pci_bus {
> - void __iomem*regs;
> - unsigned long mmio_start;
> - unsigned long mmio_end;
> - unsigned long pio_vstart;
> - unsigned long pio_vend;
> -} spider_pci_busses[MAX_SPIDERS];
> -static int spider_pci_count;
> +static struct iowa_bus iowa_busses[IOWA_MAX_BUS];
> +static unsigned int iowa_bus_count;
>
> -static struct spider_pci_bus *spider_pci_find(unsigned long vaddr,
> - unsigned long paddr)
> +static struct iowa_bus *iowa_pci_find(unsigned long vaddr, unsigned long
> paddr)
> {
> - int i;
> -
> - for (i = 0; i < spider_pci_count; i++) {
> - struct spider_pci_bus *bus = &spider_pci_busses[i];
> - if (paddr && paddr >= bus->mmio_start && paddr < bus->mmio_end)
> - return bus;
> - if (vaddr && vaddr >= bus->pio_vstart && vaddr < bus->pio_vend)
> - return bus;
> + int i, j;
> + struct resource *res;
> + unsigned long vstart, vend;
> +
> + for (i = 0; i < iowa_bus_count; i++) {
> + struct iowa_bus *bus = &iowa_busses[i];
> + struct pci_controller *phb = bus->phb;
> +
> + if (vaddr) {
> + vstart = (unsigned long)phb->io_base_virt;
> +
[PATCH 8/9] celleb: move miscellaneous files for Beat
This patch moves miscellaneous files for Beat into platforms/cell/.
All files in this patch are used by celleb-beat only.
Signed-off-by: Kou Ishizaki <[EMAIL PROTECTED]>
Acked-by: Arnd Bergmann <[EMAIL PROTECTED]>
---
arch/powerpc/platforms/Makefile |1
arch/powerpc/platforms/cell/Makefile |6
arch/powerpc/platforms/cell/beat.c | 264 +
arch/powerpc/platforms/cell/beat.h | 39 +++
arch/powerpc/platforms/cell/beat_interrupt.c | 283 +++
arch/powerpc/platforms/cell/beat_interrupt.h | 33 +++
arch/powerpc/platforms/cell/beat_smp.c | 124 +++
arch/powerpc/platforms/cell/beat_udbg.c | 98 +
arch/powerpc/platforms/cell/celleb_setup.c |4
arch/powerpc/platforms/celleb/Makefile |5
arch/powerpc/platforms/celleb/beat.c | 264 -
arch/powerpc/platforms/celleb/beat.h | 39 ---
arch/powerpc/platforms/celleb/interrupt.c| 283 ---
arch/powerpc/platforms/celleb/interrupt.h| 33 ---
arch/powerpc/platforms/celleb/smp.c | 124 ---
arch/powerpc/platforms/celleb/udbg_beat.c| 98 -
16 files changed, 847 insertions(+), 851 deletions(-)
Index: b/arch/powerpc/platforms/cell/beat.c
===
--- /dev/null 1970-01-01 00:00:00.0 +
+++ b/arch/powerpc/platforms/cell/beat.c2008-04-23 21:38:50.0
+0900
@@ -0,0 +1,264 @@
+/*
+ * Simple routines for Celleb/Beat
+ *
+ * (C) Copyright 2006-2007 TOSHIBA CORPORATION
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include "beat_wrapper.h"
+#include "beat.h"
+#include "beat_interrupt.h"
+
+static int beat_pm_poweroff_flag;
+
+void beat_restart(char *cmd)
+{
+ beat_shutdown_logical_partition(!beat_pm_poweroff_flag);
+}
+
+void beat_power_off(void)
+{
+ beat_shutdown_logical_partition(0);
+}
+
+u64 beat_halt_code = 0x1000UL;
+EXPORT_SYMBOL(beat_halt_code);
+
+void beat_halt(void)
+{
+ beat_shutdown_logical_partition(beat_halt_code);
+}
+
+int beat_set_rtc_time(struct rtc_time *rtc_time)
+{
+ u64 tim;
+ tim = mktime(rtc_time->tm_year+1900,
+rtc_time->tm_mon+1, rtc_time->tm_mday,
+rtc_time->tm_hour, rtc_time->tm_min, rtc_time->tm_sec);
+ if (beat_rtc_write(tim))
+ return -1;
+ return 0;
+}
+
+void beat_get_rtc_time(struct rtc_time *rtc_time)
+{
+ u64 tim;
+
+ if (beat_rtc_read(&tim))
+ tim = 0;
+ to_tm(tim, rtc_time);
+ rtc_time->tm_year -= 1900;
+ rtc_time->tm_mon -= 1;
+}
+
+#defineBEAT_NVRAM_SIZE 4096
+
+ssize_t beat_nvram_read(char *buf, size_t count, loff_t *index)
+{
+ unsigned int i;
+ unsigned long len;
+ char *p = buf;
+
+ if (*index >= BEAT_NVRAM_SIZE)
+ return -ENODEV;
+ i = *index;
+ if (i + count > BEAT_NVRAM_SIZE)
+ count = BEAT_NVRAM_SIZE - i;
+
+ for (; count != 0; count -= len) {
+ len = count;
+ if (len > BEAT_NVRW_CNT)
+ len = BEAT_NVRW_CNT;
+ if (beat_eeprom_read(i, len, p))
+ return -EIO;
+
+ p += len;
+ i += len;
+ }
+ *index = i;
+ return p - buf;
+}
+
+ssize_t beat_nvram_write(char *buf, size_t count, loff_t *index)
+{
+ unsigned int i;
+ unsigned long len;
+ char *p = buf;
+
+ if (*index >= BEAT_NVRAM_SIZE)
+ return -ENODEV;
+ i = *index;
+ if (i + count > BEAT_NVRAM_SIZE)
+ count = BEAT_NVRAM_SIZE - i;
+
+ for (; count != 0; count -= len) {
+ len = count;
+ if (len > BEAT_NVRW_CNT)
+ len = BEAT_NVRW_CNT;
+ if (beat_eeprom_write(i, len, p))
+ return -EIO;
+
+ p += len;
+ i += len;
+ }
+ *index = i;
+ return p - buf;
+}
+
+ssize_t beat_nvram_get_size(void)
+{
+ retu
[PATCH 7/9] celleb: move a file for SPU on Beat
This patch moves SPU support code on Beat into platforms/cell/.
Signed-off-by: Kou Ishizaki <[EMAIL PROTECTED]>
Acked-by: Arnd Bergmann <[EMAIL PROTECTED]>
---
arch/powerpc/platforms/cell/Makefile |1
arch/powerpc/platforms/cell/beat_spu_priv1.c | 207 +++
arch/powerpc/platforms/celleb/Makefile |1
arch/powerpc/platforms/celleb/spu_priv1.c| 207 ---
4 files changed, 208 insertions(+), 208 deletions(-)
Index: b/arch/powerpc/platforms/cell/beat_spu_priv1.c
===
--- /dev/null 1970-01-01 00:00:00.0 +
+++ b/arch/powerpc/platforms/cell/beat_spu_priv1.c 2008-04-23
21:38:40.0 +0900
@@ -0,0 +1,207 @@
+/*
+ * spu hypervisor abstraction for Beat
+ *
+ * (C) Copyright 2006-2007 TOSHIBA CORPORATION
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include
+
+#include
+#include
+#include
+
+#include "beat_wrapper.h"
+
+static inline void _int_mask_set(struct spu *spu, int class, u64 mask)
+{
+ spu->shadow_int_mask_RW[class] = mask;
+ beat_set_irq_mask_for_spe(spu->spe_id, class, mask);
+}
+
+static inline u64 _int_mask_get(struct spu *spu, int class)
+{
+ return spu->shadow_int_mask_RW[class];
+}
+
+static void int_mask_set(struct spu *spu, int class, u64 mask)
+{
+ _int_mask_set(spu, class, mask);
+}
+
+static u64 int_mask_get(struct spu *spu, int class)
+{
+ return _int_mask_get(spu, class);
+}
+
+static void int_mask_and(struct spu *spu, int class, u64 mask)
+{
+ u64 old_mask;
+ old_mask = _int_mask_get(spu, class);
+ _int_mask_set(spu, class, old_mask & mask);
+}
+
+static void int_mask_or(struct spu *spu, int class, u64 mask)
+{
+ u64 old_mask;
+ old_mask = _int_mask_get(spu, class);
+ _int_mask_set(spu, class, old_mask | mask);
+}
+
+static void int_stat_clear(struct spu *spu, int class, u64 stat)
+{
+ beat_clear_interrupt_status_of_spe(spu->spe_id, class, stat);
+}
+
+static u64 int_stat_get(struct spu *spu, int class)
+{
+ u64 int_stat;
+ beat_get_interrupt_status_of_spe(spu->spe_id, class, &int_stat);
+ return int_stat;
+}
+
+static void cpu_affinity_set(struct spu *spu, int cpu)
+{
+ return;
+}
+
+static u64 mfc_dar_get(struct spu *spu)
+{
+ u64 dar;
+ beat_get_spe_privileged_state_1_registers(
+ spu->spe_id,
+ offsetof(struct spu_priv1, mfc_dar_RW), &dar);
+ return dar;
+}
+
+static u64 mfc_dsisr_get(struct spu *spu)
+{
+ u64 dsisr;
+ beat_get_spe_privileged_state_1_registers(
+ spu->spe_id,
+ offsetof(struct spu_priv1, mfc_dsisr_RW), &dsisr);
+ return dsisr;
+}
+
+static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
+{
+ beat_set_spe_privileged_state_1_registers(
+ spu->spe_id,
+ offsetof(struct spu_priv1, mfc_dsisr_RW), dsisr);
+}
+
+static void mfc_sdr_setup(struct spu *spu)
+{
+ return;
+}
+
+static void mfc_sr1_set(struct spu *spu, u64 sr1)
+{
+ beat_set_spe_privileged_state_1_registers(
+ spu->spe_id,
+ offsetof(struct spu_priv1, mfc_sr1_RW), sr1);
+}
+
+static u64 mfc_sr1_get(struct spu *spu)
+{
+ u64 sr1;
+ beat_get_spe_privileged_state_1_registers(
+ spu->spe_id,
+ offsetof(struct spu_priv1, mfc_sr1_RW), &sr1);
+ return sr1;
+}
+
+static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
+{
+ beat_set_spe_privileged_state_1_registers(
+ spu->spe_id,
+ offsetof(struct spu_priv1, mfc_tclass_id_RW), tclass_id);
+}
+
+static u64 mfc_tclass_id_get(struct spu *spu)
+{
+ u64 tclass_id;
+ beat_get_spe_privileged_state_1_registers(
+ spu->spe_id,
+ offsetof(struct spu_priv1, mfc_tclass_id_RW), &tclass_id);
+ return tclass_id;
+}
+
+static void tlb_invalidate(struct spu *spu)
+{
+ beat_set_spe_privileged_state_1_registers(
+ spu->spe_id,
+ offsetof(struct spu_priv1, tlb_invalidate_entry_W), 0ul);
+}
+
+static void resource_allocation_groupID_set(struct spu *spu, u64 id)
+{
+ beat_set_spe_privileged_state_1_registers(
+
[PATCH 6/9] celleb: move files for Beat mmu and iommu
This patch moves files for mmu and iommu on Beat into platforms/cell/.
All files in this patch are used by celleb-beat only.
Signed-off-by: Kou Ishizaki <[EMAIL PROTECTED]>
Acked-by: Arnd Bergmann <[EMAIL PROTECTED]>
---
arch/powerpc/platforms/cell/Makefile |3
arch/powerpc/platforms/cell/beat_htab.c | 441 +++
arch/powerpc/platforms/cell/beat_iommu.c | 116
arch/powerpc/platforms/celleb/Makefile |4
arch/powerpc/platforms/celleb/htab.c | 441 ---
arch/powerpc/platforms/celleb/iommu.c| 116
6 files changed, 561 insertions(+), 560 deletions(-)
Index: b/arch/powerpc/platforms/cell/beat_htab.c
===
--- /dev/null 1970-01-01 00:00:00.0 +
+++ b/arch/powerpc/platforms/cell/beat_htab.c 2008-04-23 21:38:30.0
+0900
@@ -0,0 +1,441 @@
+/*
+ * "Cell Reference Set" HTAB support.
+ *
+ * (C) Copyright 2006-2007 TOSHIBA CORPORATION
+ *
+ * This code is based on arch/powerpc/platforms/pseries/lpar.c:
+ * Copyright (C) 2001 Todd Inglett, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#undef DEBUG_LOW
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "beat_wrapper.h"
+
+#ifdef DEBUG_LOW
+#define DBG_LOW(fmt...) do { udbg_printf(fmt); } while (0)
+#else
+#define DBG_LOW(fmt...) do { } while (0)
+#endif
+
+static DEFINE_SPINLOCK(beat_htab_lock);
+
+static inline unsigned int beat_read_mask(unsigned hpte_group)
+{
+ unsigned long hpte_v[5];
+ unsigned long rmask = 0;
+
+ beat_read_htab_entries(0, hpte_group + 0, hpte_v);
+ if (!(hpte_v[0] & HPTE_V_BOLTED))
+ rmask |= 0x8000;
+ if (!(hpte_v[1] & HPTE_V_BOLTED))
+ rmask |= 0x4000;
+ if (!(hpte_v[2] & HPTE_V_BOLTED))
+ rmask |= 0x2000;
+ if (!(hpte_v[3] & HPTE_V_BOLTED))
+ rmask |= 0x1000;
+ beat_read_htab_entries(0, hpte_group + 4, hpte_v);
+ if (!(hpte_v[0] & HPTE_V_BOLTED))
+ rmask |= 0x0800;
+ if (!(hpte_v[1] & HPTE_V_BOLTED))
+ rmask |= 0x0400;
+ if (!(hpte_v[2] & HPTE_V_BOLTED))
+ rmask |= 0x0200;
+ if (!(hpte_v[3] & HPTE_V_BOLTED))
+ rmask |= 0x0100;
+ hpte_group = ~hpte_group & (htab_hash_mask * HPTES_PER_GROUP);
+ beat_read_htab_entries(0, hpte_group + 0, hpte_v);
+ if (!(hpte_v[0] & HPTE_V_BOLTED))
+ rmask |= 0x80;
+ if (!(hpte_v[1] & HPTE_V_BOLTED))
+ rmask |= 0x40;
+ if (!(hpte_v[2] & HPTE_V_BOLTED))
+ rmask |= 0x20;
+ if (!(hpte_v[3] & HPTE_V_BOLTED))
+ rmask |= 0x10;
+ beat_read_htab_entries(0, hpte_group + 4, hpte_v);
+ if (!(hpte_v[0] & HPTE_V_BOLTED))
+ rmask |= 0x08;
+ if (!(hpte_v[1] & HPTE_V_BOLTED))
+ rmask |= 0x04;
+ if (!(hpte_v[2] & HPTE_V_BOLTED))
+ rmask |= 0x02;
+ if (!(hpte_v[3] & HPTE_V_BOLTED))
+ rmask |= 0x01;
+ return rmask;
+}
+
+static long beat_lpar_hpte_insert(unsigned long hpte_group,
+ unsigned long va, unsigned long pa,
+ unsigned long rflags, unsigned long vflags,
+ int psize, int ssize)
+{
+ unsigned long lpar_rc;
+ unsigned long slot;
+ unsigned long hpte_v, hpte_r;
+
+ /* same as iseries */
+ if (vflags & HPTE_V_SECONDARY)
+ return -1;
+
+ if (!(vflags & HPTE_V_BOLTED))
+ DBG_LOW("hpte_insert(group=%lx, va=%016lx, pa=%016lx, "
+ "rflags=%lx, vflags=%lx, psize=%d)\n",
+ hpte_group, va, pa, rflags, vflags, psize);
+
+ hpte_v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M) |
+ vflags | HPTE_V_VALID;
+ hpte_r = hpte_encode_r(pa, psize) | rflags;
+
+ if (!(vflags & HPTE_V_BOLTED))
+ DBG_LOW(" hpte_v=%016lx, hpte_r=%016lx\n", hpte_v, hpte_r);
+
+ if (rflags & (_PAGE_GUARDED|_PAGE_NO_CACHE))
+ hpte_r &= ~_PAGE_COHERENT;
+
+ spin_lock(&beat_htab_lock);
+ lpar_rc = beat_read_mask(hpte_group
Re: cpu_clock confusion
On Thu, 2008-04-24 at 02:24 -0700, David Miller wrote: > From: Johannes Berg <[EMAIL PROTECTED]> > Date: Thu, 24 Apr 2008 11:21:52 +0200 > > > Hmm. Why is that whole cpu_clock stuff in place anyway? powerpc has > > perfectly synchronised time across processors with dirt cheap access to > > it as well, so why build all this code that only messes it up on top of > > it? > > Same on sparc64. These changes add more bugs than they fix. I tend to think all this clock business should be done local to those arches that aren't capable of providing cheap, useful synchronised and accurate clocks themselves. Or be a lib that they can link in if needed. As it stands, it seems to me that it all just penalises those architectures that have decent clocks. johannes signature.asc Description: This is a digitally signed message part ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 5/9] celleb: move files for Beat hvcall interfaces
This patch moves files for Beat hvcall interfaces into platforms/cell/. All files in this patch are used by celleb-beat only. Signed-off-by: Kou Ishizaki <[EMAIL PROTECTED]> Acked-by: Arnd Bergmann <[EMAIL PROTECTED]> --- arch/powerpc/platforms/cell/Makefile |3 arch/powerpc/platforms/cell/beat_hvCall.S| 287 ++ arch/powerpc/platforms/cell/beat_syscall.h | 164 +++ arch/powerpc/platforms/cell/beat_wrapper.h | 289 +++ arch/powerpc/platforms/cell/celleb_setup.c |2 arch/powerpc/platforms/celleb/Makefile |2 arch/powerpc/platforms/celleb/beat.c |2 arch/powerpc/platforms/celleb/beat_syscall.h | 164 --- arch/powerpc/platforms/celleb/beat_wrapper.h | 289 --- arch/powerpc/platforms/celleb/htab.c |2 arch/powerpc/platforms/celleb/hvCall.S | 287 -- arch/powerpc/platforms/celleb/interrupt.c|2 arch/powerpc/platforms/celleb/iommu.c|2 arch/powerpc/platforms/celleb/spu_priv1.c|2 14 files changed, 749 insertions(+), 748 deletions(-) Index: b/arch/powerpc/platforms/cell/beat_hvCall.S === --- /dev/null 1970-01-01 00:00:00.0 + +++ b/arch/powerpc/platforms/cell/beat_hvCall.S 2008-04-23 21:38:14.0 +0900 @@ -0,0 +1,287 @@ +/* + * Beat hypervisor call I/F + * + * (C) Copyright 2007 TOSHIBA CORPORATION + * + * This code is based on arch/powerpc/platforms/pseries/hvCall.S. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include + +#defineSTK_PARM(i) (48 + ((i)-3)*8) + +/* Not implemented on Beat, now */ +#defineHCALL_INST_PRECALL +#defineHCALL_INST_POSTCALL + + .text + +#defineHVSC.long 0x4422 + +/* Note: takes only 7 input parameters at maximum */ +_GLOBAL(beat_hcall_norets) + HMT_MEDIUM + + mfcrr0 + stw r0,8(r1) + + HCALL_INST_PRECALL + + mr r11,r3 + mr r3,r4 + mr r4,r5 + mr r5,r6 + mr r6,r7 + mr r7,r8 + mr r8,r9 + + HVSC/* invoke the hypervisor */ + + HCALL_INST_POSTCALL + + lwz r0,8(r1) + mtcrf 0xff,r0 + + blr /* return r3 = status */ + +/* Note: takes 8 input parameters at maximum */ +_GLOBAL(beat_hcall_norets8) + HMT_MEDIUM + + mfcrr0 + stw r0,8(r1) + + HCALL_INST_PRECALL + + mr r11,r3 + mr r3,r4 + mr r4,r5 + mr r5,r6 + mr r6,r7 + mr r7,r8 + mr r8,r9 + ld r10,STK_PARM(r10)(r1) + + HVSC/* invoke the hypervisor */ + + HCALL_INST_POSTCALL + + lwz r0,8(r1) + mtcrf 0xff,r0 + + blr /* return r3 = status */ + +/* Note: takes only 6 input parameters, 1 output parameters at maximum */ +_GLOBAL(beat_hcall1) + HMT_MEDIUM + + mfcrr0 + stw r0,8(r1) + + HCALL_INST_PRECALL + + std r4,STK_PARM(r4)(r1) /* save ret buffer */ + + mr r11,r3 + mr r3,r5 + mr r4,r6 + mr r5,r7 + mr r6,r8 + mr r7,r9 + mr r8,r10 + + HVSC/* invoke the hypervisor */ + + HCALL_INST_POSTCALL + + ld r12,STK_PARM(r4)(r1) + std r4, 0(r12) + + lwz r0,8(r1) + mtcrf 0xff,r0 + + blr /* return r3 = status */ + +/* Note: takes only 6 input parameters, 2 output parameters at maximum */ +_GLOBAL(beat_hcall2) + HMT_MEDIUM + + mfcrr0 + stw r0,8(r1) + + HCALL_INST_PRECALL + + std r4,STK_PARM(r4)(r1) /* save ret buffer */ + + mr r11,r3 + mr r3,r5 + mr r4,r6 + mr r5,r7 + mr r6,r8 + mr r7,r9 + mr r8,r10 + + HVSC/* invoke the hypervisor */ + + HCALL_INST_POSTCALL + + ld r12,STK_PARM(r4)(r1) + std r4, 0(r12) +
[PATCH 4/9] celleb: move the SCC related code for celleb
This patch moves the SCC (Super Companion Chip) related code for celleb into platforms/cell/. All files in this patch are used by celleb-beat and celleb-native commonly. Signed-off-by: Kou Ishizaki <[EMAIL PROTECTED]> Acked-by: Arnd Bergmann <[EMAIL PROTECTED]> --- arch/powerpc/platforms/cell/Makefile |5 arch/powerpc/platforms/cell/celleb_scc.h | 145 arch/powerpc/platforms/cell/celleb_scc_epci.c | 438 + arch/powerpc/platforms/cell/celleb_scc_sio.c | 101 + arch/powerpc/platforms/cell/celleb_scc_uhc.c | 95 + arch/powerpc/platforms/celleb/Makefile|4 arch/powerpc/platforms/celleb/scc.h | 145 arch/powerpc/platforms/celleb/scc_epci.c | 444 -- arch/powerpc/platforms/celleb/scc_sio.c | 101 - arch/powerpc/platforms/celleb/scc_uhc.c | 95 - 10 files changed, 784 insertions(+), 789 deletions(-) Index: b/arch/powerpc/platforms/cell/celleb_scc.h === --- /dev/null 1970-01-01 00:00:00.0 + +++ b/arch/powerpc/platforms/cell/celleb_scc.h 2008-04-24 12:08:15.0 +0900 @@ -0,0 +1,145 @@ +/* + * SCC (Super Companion Chip) definitions + * + * (C) Copyright 2004-2006 TOSHIBA CORPORATION + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef _CELLEB_SCC_H +#define _CELLEB_SCC_H + +#define PCI_VENDOR_ID_TOSHIBA_2 0x102f +#define PCI_DEVICE_ID_TOSHIBA_SCC_PCIEXC_BRIDGE 0x01b0 +#define PCI_DEVICE_ID_TOSHIBA_SCC_EPCI_BRIDGE 0x01b1 +#define PCI_DEVICE_ID_TOSHIBA_SCC_BRIDGE0x01b2 +#define PCI_DEVICE_ID_TOSHIBA_SCC_GBE 0x01b3 +#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4 +#define PCI_DEVICE_ID_TOSHIBA_SCC_USB2 0x01b5 +#define PCI_DEVICE_ID_TOSHIBA_SCC_USB 0x01b6 +#define PCI_DEVICE_ID_TOSHIBA_SCC_ENCDEC0x01b7 + +#define SCC_EPCI_REG0xd000 + +/* EPCI registers */ +#define SCC_EPCI_CNF10_REG 0x010 +#define SCC_EPCI_CNF14_REG 0x014 +#define SCC_EPCI_CNF18_REG 0x018 +#define SCC_EPCI_PVBAT 0x100 +#define SCC_EPCI_VPMBAT 0x104 +#define SCC_EPCI_VPIBAT 0x108 +#define SCC_EPCI_VCSR 0x110 +#define SCC_EPCI_VIENAB 0x114 +#define SCC_EPCI_VISTAT 0x118 +#define SCC_EPCI_VRDCOUNT 0x124 +#define SCC_EPCI_BAM0 0x12c +#define SCC_EPCI_BAM1 0x134 +#define SCC_EPCI_BAM2 0x13c +#define SCC_EPCI_IADR 0x164 +#define SCC_EPCI_CLKRST 0x800 +#define SCC_EPCI_INTSET 0x804 +#define SCC_EPCI_STATUS 0x808 +#define SCC_EPCI_ABTSET 0x80c +#define SCC_EPCI_WATRP 0x810 +#define SCC_EPCI_DUMYRADR 0x814 +#define SCC_EPCI_SWRESP 0x818 +#define SCC_EPCI_CNTOPT 0x81c +#define SCC_EPCI_ECMODE 0xf00 +#define SCC_EPCI_IOM_AC_NUM 5 +#define SCC_EPCI_IOM_ACTE(n)(0xf10 + (n) * 4) +#define SCC_EPCI_IOT_AC_NUM 4 +#define SCC_EPCI_IOT_ACTE(n)(0xf30 + (n) * 4) +#define SCC_EPCI_MAEA 0xf50 +#define SCC_EPCI_MAEC 0xf54 +#define SCC_EPCI_CKCTRL 0xff0 + +/* bits for SCC_EPCI_VCSR */ +#define SCC_EPCI_VCSR_FRE 0x0002 +#define SCC_EPCI_VCSR_FWE 0x0001 +#define SCC_EPCI_VCSR_DR0x0400 +#define SCC_EPCI_VCSR_SR0x0008 +#define SCC_EPCI_VCSR_AT0x0004 + +/* bits for SCC_EPCI_VIENAB/SCC_EPCI_VISTAT */ +#define SCC_EPCI_VISTAT_PMPE0x0008 +#define SCC_EPCI_VISTAT_PMFE0x0004 +#define SCC_EPCI_VISTAT_PRA 0x0002 +#define SCC_EPCI_VISTAT_PRD 0x0001 +#define SCC_EPCI_VISTAT_ALL 0x000f + +#define SCC_EPCI_VIENAB_PMPEE 0x0008 +#define SCC_EPCI_VIENAB_PMFEE 0x0004 +#define SCC_EPCI_VIENAB_PRA 0x0002 +#define SCC_EPCI_VIENAB_PRD 0x0001 +#define SCC_EPCI_VIENAB_ALL 0x000f + +/* bits for SCC_EPCI_CLKRST */ +#define SCC_EPCI_CLKRST_CKS_MASK 0x0003 +#define SCC_EPCI_CLKRST_CKS_2 0x +#define SCC_EPCI_CLKRST_CKS_4 0x0001 +#define SCC_EPCI_CLKRST_CKS_8 0x0002 +#define SCC_EPCI_CLKRST_PCICRST 0x0400 +#define SCC_EPCI_CLKRST_BC 0x0200 +#define SCC_EPCI_CLKRST_PCIRST 0x0100 +#define SCC_EPCI_CLKRST_PCKEN
[PATCH 3/9] celleb: move the base part for celleb support
This patch moves the base code for celleb support into platforms/cell/. All files in this patch are used by celleb-beat and celleb-native commonly. Signed-off-by: Kou Ishizaki <[EMAIL PROTECTED]> --- arch/powerpc/platforms/Kconfig |1 arch/powerpc/platforms/cell/Kconfig| 13 arch/powerpc/platforms/cell/Makefile |4 arch/powerpc/platforms/cell/celleb_pci.c | 511 arch/powerpc/platforms/cell/celleb_pci.h | 44 ++ arch/powerpc/platforms/cell/celleb_setup.c | 256 ++ arch/powerpc/platforms/celleb/Kconfig | 12 arch/powerpc/platforms/celleb/Makefile |4 arch/powerpc/platforms/celleb/pci.c| 513 - arch/powerpc/platforms/celleb/pci.h| 44 -- arch/powerpc/platforms/celleb/scc_epci.c |2 arch/powerpc/platforms/celleb/setup.c | 256 -- 12 files changed, 830 insertions(+), 830 deletions(-) Index: b/arch/powerpc/platforms/Kconfig === --- a/arch/powerpc/platforms/Kconfig2008-04-24 12:05:34.0 +0900 +++ b/arch/powerpc/platforms/Kconfig2008-04-24 12:07:16.0 +0900 @@ -45,7 +45,6 @@ source "arch/powerpc/platforms/prep/Kconfig" source "arch/powerpc/platforms/maple/Kconfig" source "arch/powerpc/platforms/pasemi/Kconfig" -source "arch/powerpc/platforms/celleb/Kconfig" source "arch/powerpc/platforms/ps3/Kconfig" source "arch/powerpc/platforms/cell/Kconfig" source "arch/powerpc/platforms/8xx/Kconfig" Index: b/arch/powerpc/platforms/cell/Kconfig === --- a/arch/powerpc/platforms/cell/Kconfig 2008-04-24 12:05:34.0 +0900 +++ b/arch/powerpc/platforms/cell/Kconfig 2008-04-24 12:07:16.0 +0900 @@ -25,6 +25,19 @@ select PPC_UDBG_16550 select UDBG_RTAS_CONSOLE +config PPC_CELLEB + bool "Toshiba's Cell Reference Set 'Celleb' Architecture" + depends on PPC_MULTIPLATFORM && PPC64 + select PPC_CELL + select PPC_CELL_NATIVE + select PPC_RTAS + select PPC_INDIRECT_IO + select PPC_OF_PLATFORM_PCI + select HAS_TXX9_SERIAL + select PPC_UDBG_BEAT + select USB_OHCI_BIG_ENDIAN_MMIO + select USB_EHCI_BIG_ENDIAN_MMIO + menu "Cell Broadband Engine options" depends on PPC_CELL Index: b/arch/powerpc/platforms/celleb/Makefile === --- a/arch/powerpc/platforms/celleb/Makefile2008-04-24 12:06:12.0 +0900 +++ b/arch/powerpc/platforms/celleb/Makefile2008-04-24 12:07:16.0 +0900 @@ -1,5 +1,5 @@ -obj-y += interrupt.o iommu.o setup.o \ - htab.o beat.o hvCall.o pci.o \ +obj-y += interrupt.o iommu.o \ + htab.o beat.o hvCall.o \ scc_epci.o scc_uhc.o obj-$(CONFIG_SMP) += smp.o Index: b/arch/powerpc/platforms/celleb/scc_epci.c === --- a/arch/powerpc/platforms/celleb/scc_epci.c 2008-04-24 12:06:39.0 +0900 +++ b/arch/powerpc/platforms/celleb/scc_epci.c 2008-04-24 12:07:16.0 +0900 @@ -35,7 +35,7 @@ #include #include "scc.h" -#include "pci.h" +#include "../cell/celleb_pci.h" #include "interrupt.h" #define MAX_PCI_DEVICES 32 Index: b/arch/powerpc/platforms/cell/Makefile === --- a/arch/powerpc/platforms/cell/Makefile 2008-04-24 12:06:12.0 +0900 +++ b/arch/powerpc/platforms/cell/Makefile 2008-04-24 12:07:16.0 +0900 @@ -31,5 +31,7 @@ # celleb stuff ifeq ($(CONFIG_PPC_CELLEB),y) -obj-y += io-workarounds.o spider-pci.o +obj-y += celleb_setup.o \ + celleb_pci.o \ + io-workarounds.o spider-pci.o endif Index: b/arch/powerpc/platforms/celleb/Kconfig === --- a/arch/powerpc/platforms/celleb/Kconfig 2008-04-24 12:05:34.0 +0900 +++ /dev/null 1970-01-01 00:00:00.0 + @@ -1,12 +0,0 @@ -config PPC_CELLEB - bool "Toshiba's Cell Reference Set 'Celleb' Architecture" - depends on PPC_MULTIPLATFORM && PPC64 - select PPC_CELL - select PPC_CELL_NATIVE - select PPC_RTAS - select PPC_INDIRECT_IO - select PPC_OF_PLATFORM_PCI - select HAS_TXX9_SERIAL - select PPC_UDBG_BEAT - select USB_OHCI_BIG_ENDIAN_MMIO - select USB_EHCI_BIG_ENDIAN_MMIO Index: b/arch/powerpc/platforms/cell/celleb_pci.c === --- /dev/null 1970-01-01 00:00:00.0 + +++
[PATCH 2/9] celleb: consolidate io-workarounds code
Now, we can use generic io-workarounds mechanism and the workaround
code for spider-pci. This patch changes Celleb PCI code to use
spider-pci code.
Signed-off-by: Kou Ishizaki <[EMAIL PROTECTED]>
Acked-by: Arnd Bergmann <[EMAIL PROTECTED]>
---
arch/powerpc/platforms/cell/Makefile |6
arch/powerpc/platforms/celleb/Makefile |3
arch/powerpc/platforms/celleb/io-workarounds.c | 280 -
arch/powerpc/platforms/celleb/pci.c| 41 ++-
arch/powerpc/platforms/celleb/pci.h| 18 -
arch/powerpc/platforms/celleb/scc_epci.c | 59 -
arch/powerpc/platforms/celleb/setup.c |2
7 files changed, 52 insertions(+), 357 deletions(-)
Index: b/arch/powerpc/platforms/celleb/pci.c
===
--- a/arch/powerpc/platforms/celleb/pci.c 2008-04-24 12:05:34.0
+0900
+++ b/arch/powerpc/platforms/celleb/pci.c 2008-04-24 12:06:12.0
+0900
@@ -41,6 +41,7 @@
#include
#include
+#include "../cell/io-workarounds.h"
#include "pci.h"
#include "interrupt.h"
@@ -457,33 +458,39 @@
return 0;
}
-void __init fake_pci_workaround_init(struct pci_controller *phb)
-{
- /**
-* We will add fake pci bus to scc_pci_bus for the purpose to improve
-* I/O Macro performance. But device-tree and device drivers
-* are not ready to use address with a token.
-*/
-
- /* celleb_pci_add_one(phb, NULL); */
-}
+static struct celleb_phb_spec celleb_fake_pci_spec __initdata = {
+ .setup = celleb_setup_fake_pci,
+};
static struct of_device_id celleb_phb_match[] __initdata = {
{
.name = "pci-pseudo",
- .data = celleb_setup_fake_pci,
+ .data = &celleb_fake_pci_spec,
}, {
.name = "epci",
- .data = celleb_setup_epci,
+ .data = &celleb_epci_spec,
}, {
},
};
+static int __init celleb_io_workaround_init(struct pci_controller *phb,
+ struct celleb_phb_spec *phb_spec)
+{
+ if (phb_spec->ops) {
+ iowa_register_bus(phb, phb_spec->ops, phb_spec->iowa_init,
+ phb_spec->iowa_data);
+ io_workaround_init();
+ }
+
+ return 0;
+}
+
int __init celleb_setup_phb(struct pci_controller *phb)
{
struct device_node *dev = phb->dn;
const struct of_device_id *match;
- int (*setup_func)(struct device_node *, struct pci_controller *);
+ struct celleb_phb_spec *phb_spec;
+ int rc;
match = of_match_node(celleb_phb_match, dev);
if (!match)
@@ -492,8 +499,12 @@
phb_set_bus_ranges(dev, phb);
phb->buid = 1;
- setup_func = match->data;
- return (*setup_func)(dev, phb);
+ phb_spec = match->data;
+ rc = (*phb_spec->setup)(dev, phb);
+ if (rc)
+ return 1;
+
+ return celleb_io_workaround_init(phb, phb_spec);
}
int celleb_pci_probe_mode(struct pci_bus *bus)
Index: b/arch/powerpc/platforms/celleb/pci.h
===
--- a/arch/powerpc/platforms/celleb/pci.h 2008-04-24 12:05:34.0
+0900
+++ b/arch/powerpc/platforms/celleb/pci.h 2008-04-24 12:06:12.0
+0900
@@ -27,16 +27,18 @@
#include
#include
+#include "../cell/io-workarounds.h"
+
+struct celleb_phb_spec {
+ int (*setup)(struct device_node *, struct pci_controller *);
+ struct ppc_pci_io *ops;
+ int (*iowa_init)(struct iowa_bus *, void *);
+ void *iowa_data;
+};
+
extern int celleb_setup_phb(struct pci_controller *);
extern int celleb_pci_probe_mode(struct pci_bus *);
-extern int celleb_setup_epci(struct device_node *, struct pci_controller *);
-
-extern void *celleb_dummy_page_va;
-extern int __init celleb_pci_workaround_init(void);
-extern void __init celleb_pci_add_one(struct pci_controller *,
- void (*)(struct pci_controller *));
-extern void fake_pci_workaround_init(struct pci_controller *);
-extern void epci_workaround_init(struct pci_controller *);
+extern struct celleb_phb_spec celleb_epci_spec;
#endif /* _CELLEB_PCI_H */
Index: b/arch/powerpc/platforms/celleb/scc_epci.c
===
--- a/arch/powerpc/platforms/celleb/scc_epci.c 2008-04-24 12:05:34.0
+0900
+++ b/arch/powerpc/platforms/celleb/scc_epci.c 2008-04-24 12:06:39.0
+0900
@@ -43,10 +43,6 @@
#define iob() __asm__ __volatile__("eieio; sync":::"memory")
-struct epci_private {
- dma_addr_t dummy_page_da;
-};
-
static inline PCI_IO_ADDR celleb_epci_get_epci_base(
struct pci_controller *hose)
{
@@ -71,42 +67,6 @@
return hose->cfg_data;
}
-static void scc_epci_dummy_read(struct pci_control
Re: cpu_clock confusion
From: Johannes Berg <[EMAIL PROTECTED]> Date: Thu, 24 Apr 2008 11:21:52 +0200 > Hmm. Why is that whole cpu_clock stuff in place anyway? powerpc has > perfectly synchronised time across processors with dirt cheap access to > it as well, so why build all this code that only messes it up on top of > it? Same on sparc64. These changes add more bugs than they fix. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: cpu_clock confusion (was: printk time confusion?)
> > [2.764009 (3/3)] > > [4.272241 (2/2)] > > [4.272322 (2/2)] > > [4.272375 (2/2)] > > [2.948002 (3/3)] > > > > As you can see, I added printk_cpu and smp_processor_id() to the > > printk timestamp output and thus it is obvious that the different > > times come from different CPUs. > > the fixes are queued for v2.6.26. You can pick them up from > sched-devel/latest as well: > > http://people.redhat.com/mingo/sched-devel.git/README Hmm. Why is that whole cpu_clock stuff in place anyway? powerpc has perfectly synchronised time across processors with dirt cheap access to it as well, so why build all this code that only messes it up on top of it? johannes signature.asc Description: This is a digitally signed message part ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 1/9] cell: generalize io-workarounds code
This patch splits cell io-workaround code into spider-pci dependent
code and a generic part, and also moves io-workarounds initialization
into cell_setup_phb. This patch includes BenH's fix.
Signed-off-by: Kou Ishizaki <[EMAIL PROTECTED]>
Signed-off-by: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
---
arch/powerpc/kernel/of_platform.c|2
arch/powerpc/platforms/cell/Makefile |3
arch/powerpc/platforms/cell/io-workarounds.c | 360 +++
arch/powerpc/platforms/cell/io-workarounds.h | 49 +++
arch/powerpc/platforms/cell/setup.c | 43 +++
arch/powerpc/platforms/cell/spider-pci.c | 184 +
include/asm-powerpc/io-defs.h| 107
include/asm-powerpc/io.h |8
8 files changed, 437 insertions(+), 319 deletions(-)
Index: b/arch/powerpc/platforms/cell/Makefile
===
--- a/arch/powerpc/platforms/cell/Makefile 2008-04-24 12:23:23.0
+0900
+++ b/arch/powerpc/platforms/cell/Makefile 2008-04-24 12:23:25.0
+0900
@@ -1,6 +1,7 @@
obj-$(CONFIG_PPC_CELL_NATIVE) += interrupt.o iommu.o setup.o \
cbe_regs.o spider-pic.o \
- pervasive.o pmu.o io-workarounds.o
+ pervasive.o pmu.o io-workarounds.o \
+ spider-pci.o
obj-$(CONFIG_CBE_RAS) += ras.o
obj-$(CONFIG_CBE_THERM)+= cbe_thermal.o
Index: b/arch/powerpc/platforms/cell/io-workarounds.c
===
--- a/arch/powerpc/platforms/cell/io-workarounds.c 2008-04-24
12:23:23.0 +0900
+++ b/arch/powerpc/platforms/cell/io-workarounds.c 2008-04-24
12:23:25.0 +0900
@@ -1,6 +1,9 @@
/*
+ * Support PCI IO workaround
+ *
* Copyright (C) 2006 Benjamin Herrenschmidt <[EMAIL PROTECTED]>
*IBM, Corp.
+ * (C) Copyright 2007-2008 TOSHIBA CORPORATION
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -9,335 +12,174 @@
#undef DEBUG
#include
-#include
-#include
+
#include
#include
-#include
+#include
#include
+#include "io-workarounds.h"
-#define SPIDER_PCI_REG_BASE0xd000
-#define SPIDER_PCI_VCI_CNTL_STAT 0x0110
-#define SPIDER_PCI_DUMMY_READ 0x0810
-#define SPIDER_PCI_DUMMY_READ_BASE 0x0814
-
-/* Undefine that to re-enable bogus prefetch
- *
- * Without that workaround, the chip will do bogus prefetch past
- * page boundary from system memory. This setting will disable that,
- * though the documentation is unclear as to the consequences of doing
- * so, either purely performances, or possible misbehaviour... It's not
- * clear wether the chip can handle unaligned accesses at all without
- * prefetching enabled.
- *
- * For now, things appear to be behaving properly with that prefetching
- * disabled and IDE, possibly because IDE isn't doing any unaligned
- * access.
- */
-#define SPIDER_DISABLE_PREFETCH
-
-#define MAX_SPIDERS3
+#define IOWA_MAX_BUS 8
-static struct spider_pci_bus {
- void __iomem*regs;
- unsigned long mmio_start;
- unsigned long mmio_end;
- unsigned long pio_vstart;
- unsigned long pio_vend;
-} spider_pci_busses[MAX_SPIDERS];
-static int spider_pci_count;
+static struct iowa_bus iowa_busses[IOWA_MAX_BUS];
+static unsigned int iowa_bus_count;
-static struct spider_pci_bus *spider_pci_find(unsigned long vaddr,
- unsigned long paddr)
+static struct iowa_bus *iowa_pci_find(unsigned long vaddr, unsigned long paddr)
{
- int i;
-
- for (i = 0; i < spider_pci_count; i++) {
- struct spider_pci_bus *bus = &spider_pci_busses[i];
- if (paddr && paddr >= bus->mmio_start && paddr < bus->mmio_end)
- return bus;
- if (vaddr && vaddr >= bus->pio_vstart && vaddr < bus->pio_vend)
- return bus;
+ int i, j;
+ struct resource *res;
+ unsigned long vstart, vend;
+
+ for (i = 0; i < iowa_bus_count; i++) {
+ struct iowa_bus *bus = &iowa_busses[i];
+ struct pci_controller *phb = bus->phb;
+
+ if (vaddr) {
+ vstart = (unsigned long)phb->io_base_virt;
+ vend = vstart + phb->pci_io_size - 1;
+ if ((vaddr >= vstart) && (vaddr <= vend))
+ return bus;
+ }
+
+ if (paddr)
+ for (j = 0; j < 3; j++) {
+ res = &phb->mem_resources[j];
+ if (paddr >= res->start && paddr <= res->end)
+
ML405 failed reboot
Now that my Xilinx card is operational with Kernel 2.6.24 and a buildroot/busybox/uClibc config, I'm getting on the application side. First hitch: I can't do a soft reboot of the card: # reboot The system is going down NOW! Sending SIGTERM to all processes Requesting system reboot [ 434.713999] Restarting system. [ 434.7[ 434.718123] Signal: 4 [ 434.718133] Code: 30001 [ 434.718144] Addr: c74cbdc8 And then it just hangs. I also tried the additional -n (no sync) and -f (force) without difference. Design problem ? Any other way to force a reboot ? -- Guillaume Dargaud http://www.gdargaud.net/ ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC][WIP][PATCH] Add IRQSTACKS to ppc32
On Thu, 2008-04-24 at 00:37 -0500, Kumar Gala wrote:
> + /*
> +* interrupt stacks must be under 256MB, we cannot afford to
> take
> +* SLB misses on them.
> +*/
> + for_each_possible_cpu(i) {
> + softirq_ctx[i] = (struct thread_info *)
> + __va(lmb_alloc_base(THREAD_SIZE,
> + THREAD_SIZE, 0x1000));
> + hardirq_ctx[i] = (struct thread_info *)
> + __va(lmb_alloc_base(THREAD_SIZE,
> + THREAD_SIZE, 0x1000));
> + }
> +
The comment is a bit bogus :-) (about SLB misses). lowmem is your limit
I think. Also, why not share the code with ppc64 ?
Ben.
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Re: LMB regression...
From: Paul Mackerras <[EMAIL PROTECTED]> Date: Thu, 24 Apr 2008 16:56:26 +1000 > David Miller writes: > > > Specifically, you removed the aligning of the size argument given to > > lmb_add_region() in the lmb allocators, and that is critical when > > allocating many small chunks, we run out of LMB slots otherwise > > and allocations start failing. > > Sorry. It's still there in lmb_alloc_nid_unreserved but I lost the > one in __lmb_alloc_base. Are you going to send a fix to Linus, or > will I include it in the pull request I'm going to send tomorrow? I've got it, see my other email. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
