[PATCH v2 0/5] Add a cpufreq driver for the IBM PowerPC 750GX
Hi, This patch set adds a cpufreq driver for the IBM PowerPC 750GX processor. It should also work for the 750FX. The patches are: 1) Add low level PLL config register interface module 2) Add cpufreq driver for the 750GX 3) Other PowerPC kernel changes necessary to support the above 4) Add kernel doc for the completion feature, fix split-man.pl in kernel-doc-nano-HOWTO.txt 5) Add pll script to interface with pll_if sysfs attribute These changes are against 2.6.26. Thanks for all who took the time to review v1! kevin ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v2 0/5] Add a cpufreq driver for the IBM PowerPC 750GX
Hi, This patch set adds a cpufreq driver for the IBM PowerPC 750GX processor. It should also work for the 750FX. The patches are: 1) Add low level PLL config register interface module 2) Add cpufreq driver for the 750GX 3) Other PowerPC kernel changes necessary to support the above 4) Add kernel doc for the completion feature, fix split-man.pl in kernel-doc-nano-HOWTO.txt 5) Add pll script to interface with pll_if sysfs attribute These changes are against 2.6.26. Thanks for all who took the time to review v1! Documentation/DocBook/Makefile|2 Documentation/DocBook/cf750gx.tmpl| 441 Documentation/cpu-freq/pll.pl | 773 Documentation/kernel-doc-nano-HOWTO.txt |4 arch/powerpc/kernel/Makefile |1 arch/powerpc/kernel/cpu/Makefile |6 arch/powerpc/kernel/cpu/cpufreq/Kconfig | 33 + arch/powerpc/kernel/cpu/cpufreq/Makefile |1 arch/powerpc/kernel/cpu/cpufreq/cf750gx.c | 741 +++ arch/powerpc/kernel/cpu/pll_if.c | 807 ++ arch/powerpc/kernel/cpu_setup_6xx.S | 13 arch/powerpc/kernel/cputable.c| 32 + arch/powerpc/kernel/idle_6xx.S| 28 - arch/powerpc/platforms/Kconfig|2 arch/powerpc/platforms/Kconfig.cputype| 30 + arch/powerpc/platforms/powermac/feature.c |9 include/asm-powerpc/cputable.h|3 include/asm-powerpc/pll.h | 209 +++ include/asm-powerpc/pll_if.h | 117 include/linux/completion.h| 41 + kernel/sched.c| 56 ++ 21 files changed, 3305 insertions(+), 44 deletions(-) Ooops, left out the diffstat. kevin ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v2 1/5] Add low level PLL config register interface module
This adds a small module to handle the low level details of dealing with the
PLL config register (HID1) found in the IBM 750GX. It provides 2 possible
interfaces, both selectable via kernel config options. One is a sysfs attribute
and the other is a normal function API. It is called pll_if.
The determination of the bus frequency is what worked on a PowerMac 8600. Any
suggestions on a more general solution are welcome.
After receiving comments, I added an argument for the data item to the
notifier register functions exported for the cpufreq API.
I also fixed a deadlock if the module is unloaded before _modify_PLL() is ever
called.
My name is Kevin Diggs and I approve this patch.
Signed-off-by: Kevin Diggs [EMAIL PROTECTED]
Index: arch/powerpc/kernel/cpu/pll_if.c
===
--- /dev/null 2004-08-10 18:55:00.0 -0700
+++ arch/powerpc/kernel/cpu/pll_if.c2008-08-29 13:42:35.0 -0700
@@ -0,0 +1,807 @@
+/*
+ * pll_if.c - low level interface to HID1 (PLL config) in the PowerPC 750GX
+ *
+ * Copyright (C) 2008 kevin Diggs
+ *
+ * ~~
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~
+ */
+#include linux/init.h
+#include linux/module.h
+#include linux/autoconf.h
+#include linux/kernel.h
+#include linux/errno.h
+#include linux/cpu.h
+#include linux/of.h
+#include linux/notifier.h
+#include linux/delay.h
+#include linux/completion.h
+
+#ifdef CONFIG_PPC_750GX_DUAL_PLL_IF_SYSFS
+#include linux/sysdev.h
+#endif
+#ifdef CONFIG_PPC_750GX_DUAL_PLL_IF_HRTIMER
+#include linux/hrtimer.h
+#endif
+
+#include asm/time.h
+#include asm/mmu.h
+#include asm/processor.h
+#include asm/pgtable.h
+#include asm/cputable.h
+#include asm/system.h
+#include asm/pll_if.h
+#include asm/pll.h
+#include asm/smp.h
+
+MODULE_LICENSE(GPL);
+
+static DECLARE_COMPLETION(pllif_exit_completion);
+
+static unsigned int boot_ratio;
+
+static unsigned int busclock = 0;
+module_param(busclock, uint, 0);
+MODULE_PARM_DESC(busclock,
+ Bus clock frequency in KHz used to compute core clock frequency from
+bus ratios.);
+
+static unsigned int pllif_bus_clock;
+
+#ifdef CONFIG_PPC_750GX_DUAL_PLL_IF_HRTIMER
+static enum hrtimer_restart pllif_i_timer_f(struct hrtimer *hrt);
+static struct hrtimer pll_timer;
+static unsigned long hrtimers_got_no_freakin_callback_data;
+#ifdef DEBUG
+cycles_t pll_time_stamp;
+#endif
+#else
+static void pllif_i_timer_f(unsigned long newPLL);
+static struct timer_list pll_timer;
+cycles_t pll_time_stamp;
+#endif
+
+#ifdef CONFIG_PPC_750GX_DUAL_PLL_IF_SYSFS
+
+unsigned long boot_loops;
+static struct sys_device *sysdev_cpu;
+
+static ssize_t show_ppc750gxpll(struct sys_device *dev, char *buf)
+{
+ return sprintf(buf, %x\n, get_PLL());
+}
+
+static ssize_t __used store_ppc750gxpll(struct sys_device *dev,
+ const char *buf, size_t count)
+{
+ unsigned long pll_ul;
+ int ret;
+
+ pr_debug(__FILE__%s()-%d: buf=%s, count=%d\n, __func__, __LINE__,
+ buf, count);
+
+ ret = strict_strtoul(buf, 16, pll_ul);
+
+ pr_debug(__FILE__%s()-%d: strict_strtoul() returns %d\n, __func__,
+ __LINE__, ret);
+ pr_debug(__FILE__%s()-%d: %lx (%lu)\n, __func__, __LINE__, pll_ul,
+ pll_ul);
+
+ if (!ret) {
+ ret = count;
+
+ /* pllif_modify_PLL((unsigned int)pll_ul,!0); */
+ pllif_modify_PLL((unsigned int)pll_ul, 0);
+ }
+
+ return ret;
+}
+
+static SYSDEV_ATTR(ppc750gxpll, 0600, show_ppc750gxpll, store_ppc750gxpll);
+#endif
+
+#ifdef CONFIG_PPC_750GX_DUAL_PLL_IF_CPU_FREQ
+struct pllif_call_data_t {
+ void *data;
+ int scalar;
+};
+
+static struct pllif_call_data_t pllif_switch_call_data;
+static struct pllif_call_data_t pllif_lock_call_data;
+static RAW_NOTIFIER_HEAD(pllif_pll_switch_chain);
+static RAW_NOTIFIER_HEAD(pllif_pll_lock_chain);
+#endif
+
+/*
+ * This initializes the code for the PLL control:
+ * boot_ratio is used to scale the loops_per_jiffy value from its boot value
+ * boot_loops is the boot value of loops_per_jiffy and is used to compute new
+ * values
[PATCH v2 2/5] Add cpufreq driver for the IBM PowerPC 750GX
This adds the actual cpufreq driver for the 750GX. It supports all integer ratios that are valid for the processor model and bus frequency. It is called cf750gx. It has two modes of operation. Normal mode uses all valid frequencies. In minmaxmode, only the minimum and maximum are used. This provides the ability for very low latency frequency switches. There is also a sysfs attribute to have it switch off the unused PLL for additional power savings. This does NOT support SMP. I fixed a deadlock if the module is unloaded before _target() is ever called. My name is Kevin Diggs and I approve this patch. Signed-off-by: Kevin Diggs [EMAIL PROTECTED] Index: Documentation/DocBook/cf750gx.tmpl === --- /dev/null 2004-08-10 18:55:00.0 -0700 +++ Documentation/DocBook/cf750gx.tmpl 2008-08-27 13:59:45.0 -0700 @@ -0,0 +1,441 @@ +?xml version=1.0 encoding=UTF-8? +!DOCTYPE book PUBLIC -//OASIS//DTD DocBook XML V4.1.2//EN + http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd; [] + +book id=ppc750gx-cpufreq-guide + bookinfo + titlePowerPC 750GX (and FX?) cpufreq driver guide/title + + authorgroup + author +firstnameKevin/firstname +surnameDiggs/surname + /author + /authorgroup + +revhistory + revision + revnumber1.0nbsp;/revnumber + dateAugust 12, 2008/date + revremarkInitial revision posted to linuxppc-dev/revremark + /revision +/revhistory + + copyright + year2008/year + holderKevin Diggs/holder + /copyright + + legalnotice + para +This documentation is free software; you can redistribute +it and/or modify it under the terms of the GNU General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later +version. + /para + + para +This program is distributed in the hope that it will be +useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +See the GNU General Public License for more details. + /para + + para +You should have received a copy of the GNU General Public +License along with this program; if not, write to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, +MA 02111-1307 USA + /para + + para +For more details see the file COPYING in the source +distribution of Linux. + /para + /legalnotice + + releaseinfo + This is the first release of this document coincident with submission of the + driver for inclusion in the kernel. + /releaseinfo + + /bookinfo + + toc/toc + + chapter id=introduction + titleIntroduction/title + para + This guide documents the cpufreq driver for the IBM PowerPC 750GX processor. + It should also work with the 750FX but has not been tested. + /para + para + The driver is split into two main parts. The first provides the low level + interface to the PLL configuration register (HID1 - SPR 1009). It is called + pll_if. The second is the actual cpufreq driver, called cf750gx. The pll_if + component handles the details of dealing with the PLL like PLL lock delay + requirements and preventing illegal operations. The cf750gx driver provides + the interface to the cpufreq subsystem. Under control of the specified + governor it will generate the required commands to switch the processor + frequency as requested and send them to pll_if to carry them out. + /para + /chapter + + chapter id=MajorComponents + titleMajor Components/title + + para + The IBM 750GX (and FX) processor has a pair of PLLs that can be programmed to + operate at a number of different frequencies. The frequencies are specified + as ratios to the system bus and range from 2 to 20. From 2 to 10 it also + supports half ratios (i.e. 2.5, 3.5) though they are not supported in the + cpufreq driver due to a limitation of not being able to switch from one half + ratio directly to another. It takes 100 usec for a PLL to relock to a + new frequency before it can be used [750GX_ds2-17-05.pdf, Table 3-7, + page 18]. It takes 3 bus clocks for the cpu to switch from one PLL to + another [750GX_ds2-17-05.pdf, paragraph 3, page 44]. + /para + + para + The cpufreq driver consists of two main parts: + /para + + itemizedlist + listitem +para + cf750gx - the cpufreq driver module +/para + /listitem + + listitem +para + pll_if - a low level interface that encapsulates the details of dealing + with the PLL register +/para + /listitem + /itemizedlist + + sect1 id=cf750gx + titlecf750gx - The CPUFreq 750GX driver/title + + para +cf750gx provides the standard entry points required of a cpufreq driver. They +are: + + itemizedlist +listitem + para + cf750gx_verify - verify + /para +/listitem + +listitem + para + cf750gx_target -
[PATCH v2 3/5] Various arch/powerpc changes to support the 750GX cpufreq driver
This patch includes various changes necessary to support the cpufreq driver for
the PowerPC 750GX. Highlights include adding entries to recognize the 750GX to
the cputable (This includes the ... unfortunate pvr that the 750GX used in the
PowerLogix PowerForce 750GX = 0x0008 0203). The PLL switch in idle_6xx.S
during sleep (or nap) was also removed (I tried to add ability to disable this
but the result would not boot?).
My name is Kevin Diggs and I approve this patch.
Signed-off-by: Kevin Diggs [EMAIL PROTECTED]
Index: arch/powerpc/kernel/Makefile
===
--- arch/powerpc/kernel/Makefile.orig 2008-08-13 02:19:18.0 -0700
+++ arch/powerpc/kernel/Makefile2008-08-14 02:50:18.0 -0700
@@ -17,6 +17,7 @@ obj-y := cputable.o ptrace.o syscalls
init_task.o process.o systbl.o idle.o \
signal.o
obj-y += vdso32/
+obj-y += cpu/
obj-$(CONFIG_PPC64)+= setup_64.o sys_ppc32.o \
signal_64.o ptrace32.o \
paca.o cpu_setup_ppc970.o \
Index: arch/powerpc/kernel/cputable.c
===
--- arch/powerpc/kernel/cputable.c.orig 2008-08-13 02:19:19.0 -0700
+++ arch/powerpc/kernel/cputable.c 2008-08-14 03:00:51.0 -0700
@@ -42,9 +42,11 @@ extern void __setup_cpu_604(unsigned lon
extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
+extern void __setup_cpu_750gx(unsigned long offset, struct cpu_spec* spec);
extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
+
#endif /* CONFIG_PPC32 */
#ifdef CONFIG_PPC64
extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
@@ -660,7 +662,7 @@ static struct cpu_spec __initdata cpu_sp
.machine_check = machine_check_generic,
.platform = ppc750,
},
- { /* 750GX */
+ { /* 750GX rev 1.x */
.pvr_mask = 0x,
.pvr_value = 0x7002,
.cpu_name = 750GX,
@@ -669,7 +671,33 @@ static struct cpu_spec __initdata cpu_sp
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
- .cpu_setup = __setup_cpu_750fx,
+ .cpu_setup = __setup_cpu_750gx,
+ .machine_check = machine_check_generic,
+ .platform = ppc750,
+ },
+ { /* 750GX (rev 2.3, as used on PowerLogix 750GX upgrade card */
+ .pvr_mask = 0x,
+ .pvr_value = 0x00080203,
+ .cpu_name = 750GX,
+ .cpu_features = CPU_FTRS_750GX,
+ .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+ .num_pmcs = 4,
+ .cpu_setup = __setup_cpu_750gx,
+ .machine_check = machine_check_generic,
+ .platform = ppc750,
+ },
+ { /* 750GX (All revs = 2.0) */
+ .pvr_mask = 0xff00,
+ .pvr_value = 0x70020200,
+ .cpu_name = 750GX,
+ .cpu_features = CPU_FTRS_750GX,
+ .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+ .num_pmcs = 4,
+ .cpu_setup = __setup_cpu_750gx,
.machine_check = machine_check_generic,
.platform = ppc750,
},
Index: arch/powerpc/kernel/cpu_setup_6xx.S
===
--- arch/powerpc/kernel/cpu_setup_6xx.S.orig2008-08-13 02:19:19.0
-0700
+++ arch/powerpc/kernel/cpu_setup_6xx.S 2008-08-14 02:44:30.0 -0700
@@ -53,6 +53,14 @@ _GLOBAL(__setup_cpu_750fx)
bl setup_750fx
mtlrr4
blr
+_GLOBAL(__setup_cpu_750gx)
+ mflrr4
+ bl __init_fpu_registers
+ bl setup_common_caches
+ bl setup_750_7400_hid0
+ bl setup_750gx
+
[PATCH v2 4/5] Add kernel doc for the completion, fix kernel-doc-nano-HOWTO.txt
This patch adds kernel doc for the completion feature. It is in kernel/sched.c
and include/linux/completion.h.
An error in the split-man.pl PERL snippet in kernel-doc-nano-HOWTO.txt is
also fixed.
My name is Kevin Diggs and I approve this patch.
Signed-off-by: Kevin Diggs [EMAIL PROTECTED]
Index: Documentation/kernel-doc-nano-HOWTO.txt
===
--- Documentation/kernel-doc-nano-HOWTO.txt.orig2008-08-13
02:18:53.0 -0700
+++ Documentation/kernel-doc-nano-HOWTO.txt 2008-08-19 14:21:43.0
-0700
@@ -168,10 +168,10 @@ if ($#ARGV 0) {
mkdir $ARGV[0],0777;
$state = 0;
while (STDIN) {
-if (/^\.TH \[^\]*\ 4 \([^\]*)\/) {
+if (/^\.TH \[^\]*\ 9 \([^\]*)\/) {
if ($state == 1) { close OUT }
$state = 1;
- $fn = $ARGV[0]/$1.4;
+ $fn = $ARGV[0]/$1.9;
print STDERR Creating $fn\n;
open OUT, $fn or die can't open $fn: $!\n;
print OUT $_;
Index: include/linux/completion.h
===
--- include/linux/completion.h.orig 2008-08-13 00:56:52.0 -0700
+++ include/linux/completion.h 2008-08-20 01:47:21.0 -0700
@@ -10,6 +10,18 @@
#include linux/wait.h
+/**
+ * struct completion - structure used to maintain state for a completion
+ *
+ * This is the opaque structure used to maintain the state for a completion.
+ * Completions currently use a FIFO to queue threads that have to wait for
+ * the completion event.
+ *
+ * See also: complete(), wait_for_completion() (and friends _timeout,
+ * _interruptible, _interruptible_timeout, and _killable), init_completion(),
+ * and macros DECLARE_COMPLETION(), DECLARE_COMPLETION_ONSTACK(), and
+ * INIT_COMPLETION().
+ */
struct completion {
unsigned int done;
wait_queue_head_t wait;
@@ -21,6 +33,14 @@ struct completion {
#define COMPLETION_INITIALIZER_ONSTACK(work) \
({ init_completion(work); work; })
+/**
+ * DECLARE_COMPLETION: - declare and initialize a completion structure
+ * @work: identifier for the completion structure
+ *
+ * This macro declares and initializes a completion structure. Generally used
+ * for static declarations. You should use the _ONSTACK variant for automatic
+ * variables.
+ */
#define DECLARE_COMPLETION(work) \
struct completion work = COMPLETION_INITIALIZER(work)
@@ -29,6 +49,13 @@ struct completion {
* completions - so we use the _ONSTACK() variant for those that
* are on the kernel stack:
*/
+/**
+ * DECLARE_COMPLETION_ONSTACK: - declare and initialize a completion structure
+ * @work: identifier for the completion structure
+ *
+ * This macro declares and initializes a completion structure on the kernel
+ * stack.
+ */
#ifdef CONFIG_LOCKDEP
# define DECLARE_COMPLETION_ONSTACK(work) \
struct completion work = COMPLETION_INITIALIZER_ONSTACK(work)
@@ -36,6 +63,13 @@ struct completion {
# define DECLARE_COMPLETION_ONSTACK(work) DECLARE_COMPLETION(work)
#endif
+/**
+ * init_completion: - Initialize a dynamically allocated completion
+ * @x: completion structure that is to be initialized
+ *
+ * This inline function will initialize a dynamically created completion
+ * structure.
+ */
static inline void init_completion(struct completion *x)
{
x-done = 0;
@@ -53,6 +87,13 @@ extern unsigned long wait_for_completion
extern void complete(struct completion *);
extern void complete_all(struct completion *);
+/**
+ * INIT_COMPLETION: - reinitialize a completion structure
+ * @x: completion structure to be reinitialized
+ *
+ * This macro should be used to reinitialize a completion structure so it can
+ * be reused. This is especially important after complete_all() is used.
+ */
#define INIT_COMPLETION(x) ((x).done = 0)
#endif
Index: kernel/sched.c
===
--- kernel/sched.c.orig 2008-08-13 02:22:42.0 -0700
+++ kernel/sched.c 2008-08-20 12:36:01.0 -0700
@@ -4363,6 +4363,15 @@ __wake_up_sync(wait_queue_head_t *q, uns
}
EXPORT_SYMBOL_GPL(__wake_up_sync); /* For internal use only */
+/**
+ * complete: - signals a single thread waiting on this completion
+ * @x: holds the state of this particular completion
+ *
+ * This will wake up a single thread waiting on this completion. Threads will
be
+ * awakened in the same order in which they were queued.
+ *
+ * See also complete_all(), wait_for_completion() and related routines.
+ */
void complete(struct completion *x)
{
unsigned long flags;
@@ -4374,6 +4383,12 @@ void complete(struct completion *x)
}
EXPORT_SYMBOL(complete);
+/**
+ * complete_all: - signals all threads waiting on this completion
+ * @x: holds the state of this particular completion
+ *
+ * This will wake up all threads waiting on this particular completion event.
+ */
void complete_all(struct completion *x)
{
unsigned long flags;
@@ -4425,12
[PATCH v2 5/5] Add PERL script to conrol the PLL via the sysfs attribute
This patch adds a PERL script that can be used to manipulate the sysfs
attribute provided by pll_if. It can query the current state, change the
state of the inactive PLL, and switch PLLs (assumming that the inactive PLL is
locked to a valid frequency).
My name is Kevin Diggs and I approve this patch.
Signed-off-by: Kevin Diggs [EMAIL PROTECTED]
Index: Documentation/cpu-freq/pll.pl
===
--- /dev/null 2004-08-10 18:55:00.0 -0700
+++ Documentation/cpu-freq/pll.pl 2008-08-29 13:34:36.0 -0700
@@ -0,0 +1,773 @@
+#!/usr/bin/perl -w
+
+=head1 NAME
+
+pll.pl - Provide user friendly interface to sysfs attribute for the 750GX PLL.
+This uses the pll_if module.
+
+=head1 SYSNOPSIS
+
+ pll.pl [ -bdhtv ] [ -f { clk | ratio }]
+ b:print bus frequency
+ d:dump current pll configuration
+ h:print simple usage information
+ f:set frequency to specified clk (MHz) or ratio (r suffix)
+ t:toggle selected pll. Use with -f to cause a switch to the newly
+ modified PLL on lock.
+ v:enable verbose
+
+=head1 DESCRIPTION
+
+This utility provides a user friendly interface to the sysfs attribute that is
+provided by the pll_if module to control the PLL configuration register (HID1)
+in the IBM PowerPC 750FX and 750GX processors.
+
+=over 4
+
+=item -b
+
+print the bus frequency which is used along with the ratios to compute the
+processor clock frequency.
+
+=pod
+
+The method used to get the bus frequency is to use the value of the
+clock-frequency property from the root of the OF tree.
+
+=item -d
+
+prints the current value of the PLL configuration register in a human readable
+form (well ... more or less).
+
+=item -h
+
+print a simple help message.
+
+=item -t
+
+Toggles the selected PLL that is driving the cpu clock. When used with -f
causes
+a switch to the new PLL upon lock (when the lock timeout expires).
+
+=item -v
+
+Enable verbose mode. Mostly just prints the file paths that stuff is pulled
+from.
+
+=item -f
+
+Sets the INACTIVE PLL to the selected clock frequency in MHz. If the value has
+an r suffix, it is taken as a ratio. This also recognizes the special value
+off (-foff) to turn off the INACTIVE PLL.
+
+=back
+
+=head1 AUTHOR
+
+kevin diggs
+
+=cut
+
+use warnings;
+use Getopt::Std;
+
+#
+# The layout of the PLL register (HID1) is:
+#
+# 0 4|5 6|7|8| 9 11|12 13|14| 15 |16 20|21 22|23|24 28|29 30| 31
+# PCE |PRE|v|v| Res | Res |v | PS | PC0 | PR0 |v | PC1 | PR1 |Res
+#| | | |
+# PSTAT1 -| | | |
+#ECLK -| | |
+#PI0 | |
+# Res |
+#
+# PCE PLL0 read-only external config
+# PRE PLL0 read-only external range
+# PSTAT1 PLL status (0 - PLL0, 1 - PLL1)
+# ECLK1 - enable clkout pin
+# PI0 PLL0 control: 0 - external
+# PS PLL select: 0 - PLL0, 1 - PLL1
+# PC0 PLL0 configuration
+# PR0 PLL0 range
+# PC1 PLL1 configuration
+# PR1 PLL1 range
+#
+# PLL_CFG bus ratio PLL_CFG bus ratio
+# 0 off 1 8
+# 1 off 10001 8.5
+# 00010 bypass 10010 9
+# 00011 bypass 10011 9.5
+# 00100 210100 10
+# 00101 2.5 10101 11
+# 00110 310110 12
+# 00111 3.5 10111 13
+# 01000 411000 14
+# 01001 4.5 11001 15
+# 01010 511010 16
+# 01011 5.5 11011 17
+# 01100 611100 18
+# 01101 6.5 11101 19
+# 01110 70 20
+# 0 7.5 1 off
+#
+# PLL_RNG range
+#00600 - 900
+#01900 - 1000
+#10500 - 600
+#
+# IBM bit numbering:
+# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
+#
+# 26 27 28 29 30 31
+# 5 4 3 2 1 0
+#
+*pllcBusFreqFile=\/proc/device-tree/clock-frequency;
+#*pllcCPUPVR=\/proc/device-tree/PowerPC,*/cpu-version;
+*pllcSysFS=\/sys/devices/system/cpu/cpu0/*pll;
+
+#
+# Update the value of the PLL configuration register based on the crap passed
+# in. The upper 8 bits (0 - 7) are read only and will be used as flags to con-
+# trol what we
Re: [PATCH v2] POWERPC: Allow 32-bit pgtable code to support 36-bit physical
On Fri, Aug 29, 2008 at 08:42:01AM +1000, Benjamin Herrenschmidt wrote: For the non-SMP case, I think it should be possible to optimize it. The only thing that can happen at interrupt time is hashing of kernel or vmalloc/ioremap pages, which shouldn't compete with set_pte on those pages, so there would be no access races there, but I may be missing something as it's the morning and I about just woke up :-) Is that still true with preemptible kernels? -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH] ibm_newemac: MAL[12]_IER_EVENTS definition: 2x *_OTE - *_DE
MAL[12]_IER_EVENTS definitions have MAL_IER_OTE twice but lack MAL_IER_DE Signed-off-by: Roel Kluin [EMAIL PROTECTED] --- drivers/net/ibm_newemac/mal.h |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ibm_newemac/mal.h b/drivers/net/ibm_newemac/mal.h index eaa7262..717dc38 100644 --- a/drivers/net/ibm_newemac/mal.h +++ b/drivers/net/ibm_newemac/mal.h @@ -102,7 +102,7 @@ /* MAL V1 IER bits */ #define MAL1_IER_NWE 0x0008 #define MAL1_IER_SOC_EVENTS MAL1_IER_NWE -#define MAL1_IER_EVENTS (MAL1_IER_SOC_EVENTS | MAL_IER_OTE | \ +#define MAL1_IER_EVENTS (MAL1_IER_SOC_EVENTS | MAL_IER_DE | \ MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE) /* MAL V2 IER bits */ @@ -110,7 +110,7 @@ #define MAL2_IER_PRE 0x0040 #define MAL2_IER_PWE 0x0020 #define MAL2_IER_SOC_EVENTS (MAL2_IER_PT | MAL2_IER_PRE | MAL2_IER_PWE) -#define MAL2_IER_EVENTS (MAL2_IER_SOC_EVENTS | MAL_IER_OTE | \ +#define MAL2_IER_EVENTS (MAL2_IER_SOC_EVENTS | MAL_IER_DE | \ MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE) ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: nfsd, v4: oops in find_acceptable_alias, ppc32 Linux, post-2.6.27-rc1
Paul Collins wrote: Michael Ellerman [EMAIL PROTECTED] writes: Also, how old is the machine? Any chance you're just seeing random memory corruption? It's about four years old. It was in storage for about six months and I got it repaired a few weeks ago (display cable and inverter). The sort of crazy crap I've been reporting certainly smacks of memory corruption. But on the other hand, 2.6.25 (Debian's) and 2.6.26 (my own) have been trouble-free. While it is possible that the new kernel tickles a hardware bug and all the old ones don't, I would put my $ on the kernel being the issue. -- Bill Davidsen [EMAIL PROTECTED] We have more to fear from the bungling of the incompetent than from the machinations of the wicked. - from Slashdot ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
