Re: MPC5121e, MBX driver, pvr.ko ...
Hi David I'm also run on a custom board, and using the MBX. You need to get the device tree file right. You will see the MBX reserved the irq 66 in the boot printout. Instead of using insmod use modprobe. The are 2 versions of rc.pvr. Best Regard Klaus Pedersen I a early thread about memcpy for G2/G3 cores, you mentioned that you will have a look at the init. of the dram controller and the prio-manager, did that give you anything?? David Jander david.jan...@protonic.nl Sent by: linuxppc-dev-bounces+kau=bang-olufsen...@ozlabs.org 06-02-2009 08:53 To Linuxppc-dev Linuxppc-dev@ozlabs.org cc John Rigby jri...@freescale.com Subject MPC5121e, MBX driver, pvr.ko ... Hi all, I have a custom board with a MPC5121e (rev 1.5) on it. It is the latest git kernel from denx ads5121 head with our BSP mixed in. I decided to try out Application Note AN3793 from Freescale (3D Graphics on the ADS512101 Board Using OpenGL ES). I started trying to load the provided (binary!) kernel modules into our kernel, but I am geeting errors inserting the modules using insmod: 'clcdc.ko' complains about not being able to register de device major number, and 'dbgdrv.ko' oopses with a BUG() in percpu_modfree()! This function should never be called in a non-SMP kernel, so I suspect there are some important differences between the kernel I have and the one the binary-only drivers where built against :-( In another approach I managed to load the provided kernel binary (which is built for the ADS512101 evaluation board) on our platform, by tweaking our device-tree until it booted without crashing. In the end I was able to load all the modules and run the OpenGL-ES demo programs. I can't believe this is the intended way of doing this, so I'd like to know if there is someone else who has managed to get the MBX running OpenGL-ES on a custom board with a custom build of the kernel. Note: the kernel version number is still the same: 2.6.24.6, only difference AFAIK is some minor unrelated patches to drivers for other MPC5121 SoC devices, and probably some different configuration options. Apparently this is enough to break binary compatibility for the drivers :-( Any hint is appreciated... Best regards, -- David Jander Protonic Holland. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: MPC5200 PCI Issues
Ok, I have had a breakthrough. I was trying to find out where the
resources were supposed to be allocated and that was when i found this
section of code in pbus_assign_resources_sorted() in
drivers/pci/setup-bus.c:
/* Don't touch classless devices or host bridges or ioapics. */
if (class == PCI_CLASS_NOT_DEFINED ||
class == PCI_CLASS_BRIDGE_HOST)
continue;
After that i took a quick look at the PCI-info reported by u-boot.
Sure enough, all boards were reported having class 0. At first i tried
to write a different class type, but as i suspected, the register
seems to be read-only. Therefore I simply commented out the first part
of the if-statement and now the resources seems to get allocated
properly.
However, I do realize that this is not the proper way of solving this
issue. Any ideas on how to fix it without modifying any kernel code?
On Thu, Feb 5, 2009 at 21:03, Tobias Knutsson tobias.knuts...@gmail.com wrote:
Hi,
That is exactly what the bootlog shows. Debug output on in both
mpc52xx_pci.c and in pci-common.c. And the discussed code section enabled.
Hälsningar / Regards
Tobias Knutsson
On 5 feb 2009, at 17.44, Grant Likely grant.lik...@secretlab.ca wrote:
On Thu, Feb 5, 2009 at 12:06 AM, Tobias Knutsson
tobias.knuts...@gmail.com wrote:
When enabling the debug-printouts, it came to me that I forgot to
mention something kind of important. Using the standard mpc52xx_pci.c,
even the memory resources are mapped to zero.
After disabling this code block, the memory regions are mapped out
fine (but still no IO):
Reenable this code, enable debug in arch/powerpc/kernel/pci-common.c,
and post the results.
When this code is disabled then you're just getting the leftovers from
U-Boot's scan of the PCI bus. For MPC5200 support Linux does its own
scan and its own allocation of memory/IO address space and this code
is needed to make sure that happens.
g.
static void
mpc52xx_pci_fixup_resources(struct pci_dev *dev)
{
int i;
pr_debug(mpc52xx_pci_fixup_resources() %.4x:%.4x\n,
dev-vendor, dev-device);
/* We don't rely on boot loader for PCI and resets all
devices */
for (i = 0; i DEVICE_COUNT_RESOURCE; i++) {
struct resource *res = dev-resource[i];
if (res-end res-start) {/* Only valid resources */
res-end -= res-start;
res-start = 0;
res-flags |= IORESOURCE_UNSET;
}
}
What is the purpose of this code? Since all resources are reset here,
where are they inteded to be re-allocated?
Here is the bootlog with the aforementioned code enabled:
reading cuImage.lite5200b
1833699 bytes read
## Booting kernel from Legacy Image at 00201400 ...
Image Name: Linux-2.6.28
Created: 2009-02-05 6:54:20 UTC
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size:1833635 Bytes = 1.7 MB
Load Address: 0040
Entry Point: 004005a0
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
[0.00] Using lite5200 machine description
[0.00] Linux version 2.6.28 (tknuts...@ztn-ubuntu) (gcc
version 4.3.2 (Sourcery G++ Lite 4.3-50) ) #66 Thu Feb 5 07:51:46 CET
2009
[0.00] Adding MPC52xx PCI host bridge /p...@fd00
[0.00] PCI host bridge /p...@fd00 (primary) ranges:
[0.00] MEM 0x5000..0x5fff -
0x5000
[0.00] IO 0x6000..0x60ff -
0x
[0.00] mpc52xx_pci_setup(hose=c03ec000, pci_regs=fdffad00)
[0.00] mem_resource[0] = {.start=5000, .end=5fff,
.flags=200}
[0.00] .io_resource={.start=0,.end=ff,.flags=100}
.io_base_phys=0x6000
[0.00] Zone PFN ranges:
[0.00] DMA 0x - 0x4000
[0.00] Normal 0x4000 - 0x4000
[0.00] Movable zone start PFN for each node
[0.00] early_node_map[1] active PFN ranges
[0.00] 0: 0x - 0x4000
[0.00] Built 1 zonelists in Zone order, mobility grouping on.
Total pages: 16256
[0.00] Kernel command line: console=ttyPSC0,115200 root=/dev/sda2
rw
[0.00] MPC52xx PIC is up and running!
[0.00] PID hash table entries: 256 (order: 8, 1024 bytes)
[0.00] clocksource: timebase mult[7d0] shift[22] registered
[0.000263] console [ttyPSC0] enabled
[0.121690] Dentry cache hash table entries: 8192 (order: 3, 32768
bytes)
[0.129012] Inode-cache hash table entries: 4096 (order: 2, 16384
bytes)
[0.147433] Memory: 60844k/65536k available (3704k kernel code,
4624k reserved, 156k data, 117k bss, 180k init)
[0.157672] SLUB: Genslabs=12, HWalign=32, Order=0-3, MinObjects=0,
CPUs=1, Nodes=1
[0.165373] Calibrating delay loop... 63.87 BogoMIPS (lpj=127744)
[
[PATCH] Don't emulate mr. instructions
Currently emulate_step() emulates mr. instructions without updating cr0
and this can be disastrous. Don't emulate mr.
This bug has been around for a while, but I am not sure if its a worthy
-stable candidate. I'll leave it to Ben do decide.
Signed-off-by: Ananth N Mavinakayanahalli ana...@in.ibm.com
---
arch/powerpc/lib/sstep.c |2 ++
1 file changed, 2 insertions(+)
Index: linux-2.6.29-rc3/arch/powerpc/lib/sstep.c
===
--- linux-2.6.29-rc3.orig/arch/powerpc/lib/sstep.c
+++ linux-2.6.29-rc3/arch/powerpc/lib/sstep.c
@@ -172,6 +172,8 @@ int __kprobes emulate_step(struct pt_reg
}
break;
case 0x378: /* orx */
+ if (instr 1)
+ break;
rs = (instr 21) 0x1f;
rb = (instr 11) 0x1f;
if (rs == rb) { /* mr */
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Re: MPC5200 PCI Issues
I have now found drivers/pci/quirks.c which seems to be the place for
these types of things. However, since this code is unlikely to ever
make it to mainline, is it possible to register a fixup hook in a
platform setup file (lite5200.c and friends)?
On Fri, Feb 6, 2009 at 12:46, Tobias Knutsson tobias.knuts...@gmail.com wrote:
Ok, I have had a breakthrough. I was trying to find out where the
resources were supposed to be allocated and that was when i found this
section of code in pbus_assign_resources_sorted() in
drivers/pci/setup-bus.c:
/* Don't touch classless devices or host bridges or ioapics.
*/
if (class == PCI_CLASS_NOT_DEFINED ||
class == PCI_CLASS_BRIDGE_HOST)
continue;
After that i took a quick look at the PCI-info reported by u-boot.
Sure enough, all boards were reported having class 0. At first i tried
to write a different class type, but as i suspected, the register
seems to be read-only. Therefore I simply commented out the first part
of the if-statement and now the resources seems to get allocated
properly.
However, I do realize that this is not the proper way of solving this
issue. Any ideas on how to fix it without modifying any kernel code?
On Thu, Feb 5, 2009 at 21:03, Tobias Knutsson tobias.knuts...@gmail.com
wrote:
Hi,
That is exactly what the bootlog shows. Debug output on in both
mpc52xx_pci.c and in pci-common.c. And the discussed code section enabled.
Hälsningar / Regards
Tobias Knutsson
On 5 feb 2009, at 17.44, Grant Likely grant.lik...@secretlab.ca wrote:
On Thu, Feb 5, 2009 at 12:06 AM, Tobias Knutsson
tobias.knuts...@gmail.com wrote:
When enabling the debug-printouts, it came to me that I forgot to
mention something kind of important. Using the standard mpc52xx_pci.c,
even the memory resources are mapped to zero.
After disabling this code block, the memory regions are mapped out
fine (but still no IO):
Reenable this code, enable debug in arch/powerpc/kernel/pci-common.c,
and post the results.
When this code is disabled then you're just getting the leftovers from
U-Boot's scan of the PCI bus. For MPC5200 support Linux does its own
scan and its own allocation of memory/IO address space and this code
is needed to make sure that happens.
g.
static void
mpc52xx_pci_fixup_resources(struct pci_dev *dev)
{
int i;
pr_debug(mpc52xx_pci_fixup_resources() %.4x:%.4x\n,
dev-vendor, dev-device);
/* We don't rely on boot loader for PCI and resets all
devices */
for (i = 0; i DEVICE_COUNT_RESOURCE; i++) {
struct resource *res = dev-resource[i];
if (res-end res-start) {/* Only valid resources */
res-end -= res-start;
res-start = 0;
res-flags |= IORESOURCE_UNSET;
}
}
What is the purpose of this code? Since all resources are reset here,
where are they inteded to be re-allocated?
Here is the bootlog with the aforementioned code enabled:
reading cuImage.lite5200b
1833699 bytes read
## Booting kernel from Legacy Image at 00201400 ...
Image Name: Linux-2.6.28
Created: 2009-02-05 6:54:20 UTC
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size:1833635 Bytes = 1.7 MB
Load Address: 0040
Entry Point: 004005a0
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
[0.00] Using lite5200 machine description
[0.00] Linux version 2.6.28 (tknuts...@ztn-ubuntu) (gcc
version 4.3.2 (Sourcery G++ Lite 4.3-50) ) #66 Thu Feb 5 07:51:46 CET
2009
[0.00] Adding MPC52xx PCI host bridge /p...@fd00
[0.00] PCI host bridge /p...@fd00 (primary) ranges:
[0.00] MEM 0x5000..0x5fff -
0x5000
[0.00] IO 0x6000..0x60ff -
0x
[0.00] mpc52xx_pci_setup(hose=c03ec000, pci_regs=fdffad00)
[0.00] mem_resource[0] = {.start=5000, .end=5fff,
.flags=200}
[0.00] .io_resource={.start=0,.end=ff,.flags=100}
.io_base_phys=0x6000
[0.00] Zone PFN ranges:
[0.00] DMA 0x - 0x4000
[0.00] Normal 0x4000 - 0x4000
[0.00] Movable zone start PFN for each node
[0.00] early_node_map[1] active PFN ranges
[0.00] 0: 0x - 0x4000
[0.00] Built 1 zonelists in Zone order, mobility grouping on.
Total pages: 16256
[0.00] Kernel command line: console=ttyPSC0,115200 root=/dev/sda2
rw
[0.00] MPC52xx PIC is up and running!
[0.00] PID hash table entries: 256 (order: 8, 1024 bytes)
[0.00] clocksource: timebase mult[7d0] shift[22] registered
[0.000263] console [ttyPSC0] enabled
[0.121690] Dentry cache hash table entries: 8192 (order: 3, 32768
bytes)
[0.129012]
Re: MPC5200 PCI Issues
Tobias,
are you starting with 2.6.28 or are you upgrading ?
My system runs very fine with 2.6.27
Tobias Knutsson wrote:
I am currently trying to get an MPC5200-based board to run Linux
2.6.28. Most of the devices are working, however i have some issues
with the PCI-bus. More precisely, the issue is that all of
the cards' IO-regions are mapped to address 0x0.
In my device tree I have the following:
p...@fd00 {
#interrupt-cells = 1;
#size-cells = 2;
#address-cells = 3;
device_type = pci;
compatible = fsl,mpc5200b-pci,fsl,mpc5200-pci;
reg = 0xfd00 0x100;
interrupt-map-mask = 0xf800 0 0 7;
interrupt-map = 0xb000 0 0 1 mpc5200_pic 0 0 3 // MPC5200
0xb000 0 0 2 mpc5200_pic 0 0 3
0xb000 0 0 3 mpc5200_pic 0 0 3
0xb000 0 0 4 mpc5200_pic 0 0 3
What's this ? Is the MPC5200 interrupting itself ?
0xb800 0 0 1 mpc5200_pic 1 1 3 // c64x0
0xb800 0 0 2 mpc5200_pic 1 1 3
0xb800 0 0 3 mpc5200_pic 1 1 3
0xb800 0 0 4 mpc5200_pic 1 1 3
Have you connected 4 IRQ lines to each c64x device ?
0xc000 0 0 1 mpc5200_pic 1 1 3 // c64x1
0xc000 0 0 2 mpc5200_pic 1 1 3
0xc000 0 0 3 mpc5200_pic 1 1 3
0xc000 0 0 4 mpc5200_pic 1 1 3
0xc800 0 0 1 mpc5200_pic 1 1 3 // c64x2
0xc800 0 0 2 mpc5200_pic 1 1 3
0xc800 0 0 3 mpc5200_pic 1 1 3
0xc800 0 0 4 mpc5200_pic 1 1 3
0xd000 0 0 1 mpc5200_pic 1 1 3 // c64x3
0xd000 0 0 2 mpc5200_pic 1 1 3
0xd000 0 0 3 mpc5200_pic 1 1 3
0xd000 0 0 4 mpc5200_pic 1 1 3
0xd800 0 0 1 mpc5200_pic 1 1 3 // c64x4
0xd800 0 0 2 mpc5200_pic 1 1 3
0xd800 0 0 3 mpc5200_pic 1 1 3
0xd800 0 0 4 mpc5200_pic 1 1 3;
I'm using an external FPGA and an e1000 NIC connectedt to IRQ2 and IRQ3 :
interrupt-map = 0x5800 0 0 1 mpc5200_pic 1 2 3
0x5000 0 0 1
mpc5200_pic 1 3 3;
clock-frequency = 0x1e84800; //0; // From boot loader
interrupts = 2 8 0 2 9 0 2 10 0;
interrupt-parent = mpc5200_pic;
bus-range = 0 0;
ranges = 0x0200 0 0x5000 0x5000 0 0x1000
0x0100 0 0x 0x6000 0 0x0100;
};
I'm using a 3 liner :
ranges = 0x4200 0 0x8000 0x8000 0 0x2000
0x0200 0 0xa000 0xa000 0 0x1000
0x0100 0 0x 0xb000 0 0x0100;
The cards' memory regions are mapped out fine to different addresses
in the 0x5000-0x6000 range. However, the IO regions are all mapped
to zero.
Are you c64x devices responding properly ? Is IO access enabled in the
PCI command register ?
Are they announcing a reasonable window ? How man KBytes ?
Do you have any idea on what could be wrong or in which direction I
should be looking?
Hopefully something is useful to you.
regards,
Andre
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Hans-Joachim
Reich
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[PATCH] i2c-mpc: do not allow interruptions when waiting for I2C to complete
The i2c_wait() function is using wait_event_interruptible_timeout() to wait for
the I2C controller to signal that it has completed an I2C bus operation. If
the process that causes the I2C operation terminated abruptly, the wait will
be interrupted, returning an error. It is better to let the I2C operation
finished before the process exits.
It is safe to use wait_event_timeout() instead, because the timeout will allow
the process to exit if the I2C bus hangs. It's also better to allow the
I2C operation to finish, because unacknowledged I2C operations can cause the
I2C bus to hang.
Signed-off-by: Timur Tabi ti...@freescale.com
---
A similar change should probably be done to i2c-cpm.c, and maybe all other
I2C drivers. Not many use wait_event_interruptible_timeout().
drivers/i2c/busses/i2c-mpc.c |9 +++--
1 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index a9a45fc..c0ace48 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -70,7 +70,7 @@ static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
/* Read again to allow register to stabilise */
i2c-interrupt = readb(i2c-base + MPC_I2C_SR);
writeb(0, i2c-base + MPC_I2C_SR);
- wake_up_interruptible(i2c-queue);
+ wake_up(i2c-queue);
}
return IRQ_HANDLED;
}
@@ -115,13 +115,10 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned
timeout, int writing)
writeb(0, i2c-base + MPC_I2C_SR);
} else {
/* Interrupt mode */
- result = wait_event_interruptible_timeout(i2c-queue,
+ result = wait_event_timeout(i2c-queue,
(i2c-interrupt CSR_MIF), timeout * HZ);
- if (unlikely(result 0)) {
- pr_debug(I2C: wait interrupted\n);
- writeccr(i2c, 0);
- } else if (unlikely(!(i2c-interrupt CSR_MIF))) {
+ if (unlikely(!(i2c-interrupt CSR_MIF))) {
pr_debug(I2C: wait timeout\n);
writeccr(i2c, 0);
result = -ETIMEDOUT;
--
1.5.5
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Re: [PATCH 2/2] powerpc/83xx: Fix TSEC0 workability on MPC8313E-RDB boards
On Feb 5, 2009, at 2:10 PM, Anton Vorontsov wrote: TSEC0 is connected to Vitesse 7385 5-port switch. The switch isn't connected to any mdio bus, the link to the switch is fixed to Full-duplex 1000 Mb/s (no pause). This patch fixes following failure during bootup: m...@24520:01 not found eth0: Could not attach to PHY IP-Config: Failed to open eth0 Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com --- arch/powerpc/boot/dts/mpc8313erdb.dts |9 ++--- arch/powerpc/configs/83xx/mpc8313_rdb_defconfig |2 +- 2 files changed, 3 insertions(+), 8 deletions(-) applied to merge - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] arch/powerpc: Eliminate double sizeof
On Feb 4, 2009, at 3:43 PM, Julia Lawall wrote: From: Julia Lawall ju...@diku.dk Taking sizeof the result of sizeof is quite strange and does not seem to be what is wanted here. This was fixed using the following semantic patch. (http://www.emn.fr/x-info/coccinelle/) // smpl @@ expression E; @@ - sizeof ( sizeof (E) - ) @@ type T; @@ - sizeof ( sizeof (T) - ) // /smpl Signed-off-by: Julia Lawall ju...@diku.dk --- arch/powerpc/platforms/82xx/pq2ads-pci-pic.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) applied - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] powerpc/cpm2 Fix set interrupt type
On Jan 27, 2009, at 2:44 AM, paulfax wrote: This is a simple change to correct problems when using set_irq_type on platforms using CPM2. This code correct the problem on most platform but still fails on 8272 derived platforms for some interrupts. On 8272 PC2 3 are missing and PC 23 29 are added, which this patch does not address. Signed-off-by: Paul Bilke paul at conspiracy.net --- diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/ cpm2_pic.c index b16ca3e..78f1f7c 100644 --- a/arch/powerpc/sysdev/cpm2_pic.c +++ b/arch/powerpc/sysdev/cpm2_pic.c @@ -165,7 +165,7 @@ static int cpm2_set_irq_type(unsigned int virq, unsigned int flow_type) edibit = (14 - (src - CPM2_IRQ_EXT1)); else if (src = CPM2_IRQ_PORTC15 src = CPM2_IRQ_PORTC0) - edibit = (31 - (src - CPM2_IRQ_PORTC15)); + edibit = (31 - (CPM2_IRQ_PORTC0 - src)); else return (flow_type IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL; applied - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: Maple PPC970 kexec crash-dump problems
On Feb 4, 2009, at 12:48 PM, Benjamin Walsh wrote: Hi Milton, I've tracked it down to the device tree passed to the second kernel being screwed-up when patched by kexec-tools. Namely, it was creating linux,usable-memory entries that were wrong, and the MMU initialization hung when it failed allocating for the page tables. I hacked the tool, and got passed that point in the init sequence, but the very first IO mapped access fails, so the MMU doesn't seem to be set up correctly. I would need more details exactly what you think is wrong. How does it fail? If the first IO mapped access fails, then I would ask if you are using IOMMU. It is quite possible that the dart iommu code needs to be modified to use the existing mapping table instead of allocating a new table, otherwise any existing mappings being used by inflight dma would fail and the that might cause mmio loads to wait for uncompletable dma writes. Just a theory with the lack of information you gave me. Anyway, up to my question: is the crash dump (kdump) kernel supposed to use the memory reserved for it by the first kernel for its working memory ? e.g. On that board, I have 0-2GB and 4-6GB for a total of 4GB of RAM. Let's say I reserve 1...@32m, that's 0x200-0xa00. Is the second kernel supposed to use (0x200+kernel size) - 0xa00 for its memory pool and leave everything else: 0-0x200, 0xa00 - 8000, 0x1 - 0x18000 as memory that is from the first kernel, used to debug it ? Yes, but that is not quite how the device tree is formed. The second kernel will also use the interrupt vector area at address 0. Therefore that is saved as the backup region in purgatory to the address allocated in the kdump region. The device tree is then created with linux,usable-memory regions extending the kdump region back to 0, and a reserve entry marking the area as reserved. In addition, the device tree gets the memory backing tce tables for pseries smp mode. It may need the page with the dart table, marked reserved, so that the table gets added to the linear map -- except it should be mapped cache inhibited so that may not work either. Basically, I am trying to figure out if I patched the tool correctly. Thanks, Ben On Sat, Jan 24, 2009 at 2:52 AM, Milton Miller milt...@bga.com wrote: On Sat Jan 24 at 07:59:47 EST in 2009, Benjamin Walsh wrote: I am trying to use kexec with a crash dump kernel on a Maple board (Motorola ATCA6101 to be precise). This board is running a two-CPU PPC970FX. I am running a 2.6.27-10 kernel and have tried both older kexec-tools and the newest ones. I have tried SMP and non-SMP kernels. Once you start the second cpu it is likly executing instructions somewhere. Priory to 2.6.27 you had to compile a fixxed offset kerenl to run kdump. With 2.6.27 that option was removed and replaced with teh relocatable kerenl. However, becasue of the way linux interacts with open firmware, the kernel will still move itself to 0 unless a specific flag is set. The location of the flag was changed twice during the merge process, and the patches for kexec-tools were not made until early this year. Using kexec -l to fast boot works correctly. However, loading a crash dump kernel and triggering a crash via echo c /proc/sysrq-trigger simply hangs the board. I have traced the sequence down to after the call to kexec_copy_flush(), when the CPU returns to real-address mode (bl real_mode). At this point I have no further debugging information. Two things could help me: - Getting the fix if this is a known issue and a fix exists. I have looked at recent patches and nothing lept to mind, mostly relocatable kernel support. That is a major change. That said, I don't know if anyone has tested kexec panic beyond pseries for 64 bit powerpc. I know Paul originally prototyped the relocatable patch on a powermac, but I dont' know what if any smp testing he performed. And you said you are actualy on maple not a powermac, so the startup issues are different. - Obtaining the address of the serial port @3f8 in real mode. The init sequence with udbg ON says that the physical address of the port is 0xf40003f8; however, setting it up in poll mode and trying to stuff characters in the tx buffer doesn't produce anything. Ah yes. In real mode you can only talk to cacheable memory without implementation specific assistance. However, if you look in the kernel for the maple early udbg support, you will find the code you need to talk to that serial port in real mode. Has anyone recently tried to use the serial port in real mode ? Thanks for any help. Ben Hope this gets you started. I wrote a lot of the kernel code, but I had the advantage of external jtag access to the processor to see where it when ended up when it went astray. milton ___ Linuxppc-dev mailing
Re: [PATCH 1/3] powerpc: Document FSL eSDHC bindings
On Feb 5, 2009, at 1:04 PM, Anton Vorontsov wrote: This patch documents OF bindings for the Freescale Enhanced Secure Digital Host Controller. Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com --- Documentation/powerpc/dts-bindings/fsl/esdhc.txt | 24 + + 1 files changed, 24 insertions(+), 0 deletions(-) create mode 100644 Documentation/powerpc/dts-bindings/fsl/esdhc.txt applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 2/3] powerpc/83xx: Convert existing sdhc nodes to new bindings
On Feb 5, 2009, at 1:04 PM, Anton Vorontsov wrote: - sdhc node renamed to sdhci (sdhc name is confusing since SDHC is used to name Secure Digital High Capacity cards, while SDHCI is an interface). - Get rid of fsl,esdhc compatible entry, it's replaced by the fsl,chip-esdhc scheme; - Get rid of `model' property. Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com --- arch/powerpc/boot/dts/mpc8377_mds.dts |7 --- arch/powerpc/boot/dts/mpc8378_mds.dts |7 --- arch/powerpc/boot/dts/mpc8379_mds.dts |7 --- 3 files changed, 12 insertions(+), 9 deletions(-) applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 3/3] powerpc/83xx: Add FSL eSDHC support for MPC837x-RDB boards
On Feb 5, 2009, at 1:04 PM, Anton Vorontsov wrote: Simply add appropriate sdhci nodes. Note that U-Boot should configure pin multiplexing for eSDHC prior to Linux could use it. U-Boot should also fill-in the clock-frequency property (eSDHC clock depends on board-specific SCCR[ESDHCCM] bits). Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com --- arch/powerpc/boot/dts/mpc8377_rdb.dts |9 + arch/powerpc/boot/dts/mpc8378_rdb.dts |9 + arch/powerpc/boot/dts/mpc8379_rdb.dts |9 + 3 files changed, 27 insertions(+), 0 deletions(-) applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Please pull from 'merge' branch (for 2.6.29)
Please pull from 'merge' branch of
master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc.git merge
to receive the following updates:
arch/powerpc/boot/dts/mpc8313erdb.dts | 11 ---
arch/powerpc/configs/83xx/mpc8313_rdb_defconfig |2 +-
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c|2 +-
arch/powerpc/sysdev/cpm2_pic.c |2 +-
arch/powerpc/sysdev/ipic.c |2 +-
5 files changed, 8 insertions(+), 11 deletions(-)
Anton Vorontsov (2):
powerpc/83xx: Fix missing #{address,size}-cells in mpc8313erdb.dts
powerpc/83xx: Fix TSEC0 workability on MPC8313E-RDB boards
Julia Lawall (1):
arch/powerpc: Eliminate double sizeof
Michael Neuling (1):
powerpc/83xx: Build breakage for CONFIG_PM but no CONFIG_SUSPEND
paulfax (1):
powerpc/cpm2: Fix set interrupt type
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Re: [PATCH] powerpc: use common cpu_die
On Feb 3, 2009, at 10:07 PM, Benjamin Herrenschmidt wrote:
--- work.git.orig/arch/powerpc/platforms/powermac/setup.c-static void
pmac_cpu_die(void)
+static void pmac64_cpu_die(void)
...
--- work.git.orig/arch/powerpc/platforms/powermac/smp.c 2009-01-05
02:09:08.0 -0600
-void cpu_die(void)
+void pmac32_cpu_die(void)
{
local_irq_disable();
cpu_dead[smp_processor_id()] = 1;
Hi Milton ! Any chance you can move both pmac32 and pmac64 variants
into
the same file ?
I'm sure I could, but (1) it should be an incremental patch, (2) it
would only be compile tested again, and (3) I didn't look to see how
it would fit. I was doing the minimal patch that left the code intact;
it's possible that more consolidation could be done.
milton
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2.6.29-rc3-git9 build break : arch/powerpc/platforms/ps3/setup.o
2.6.29-rc3-git9 randconfig build fails with CALLarch/powerpc/kernel/prom_init_check.sh CC arch/powerpc/platforms/ps3/setup.o In file included from include/scsi/scsi.h:12, from arch/powerpc/platforms/ps3/platform.h:25, from arch/powerpc/platforms/ps3/setup.c:36: include/scsi/scsi_cmnd.h:27:25: warning: BLK_MAX_CDB is not defined include/scsi/scsi_cmnd.h:28:3: error: #error MAX_COMMAND_SIZE can not be bigger than BLK_MAX_CDB In file included from include/scsi/scsi.h:12, from arch/powerpc/platforms/ps3/platform.h:25, from arch/powerpc/platforms/ps3/setup.c:36: include/scsi/scsi_cmnd.h: In function scsi_bidi_cmnd: include/scsi/scsi_cmnd.h:184: error: implicit declaration of function blk_bidi_rq include/scsi/scsi_cmnd.h:185: error: dereferencing pointer to incomplete type include/scsi/scsi_cmnd.h: In function scsi_in: include/scsi/scsi_cmnd.h:191: error: dereferencing pointer to incomplete type include/scsi/scsi_cmnd.h: In function scsi_get_lba: include/scsi/scsi_cmnd.h:273: error: dereferencing pointer to incomplete type make[2]: *** [arch/powerpc/platforms/ps3/setup.o] Error 1 make[1]: *** [arch/powerpc/platforms/ps3] Error 2 make: *** [arch/powerpc/platforms] Error 2 .config attached here. Thanks -Sachin -- - Sachin Sant IBM Linux Technology Center India Systems and Technology Labs Bangalore, India - # # Automatically generated make config: don't edit # Linux kernel version: 2.6.29-rc3-git9 # Fri Feb 6 22:09:59 2009 # CONFIG_PPC64=y # # Processor support # CONFIG_POWER4_ONLY=y CONFIG_POWER4=y CONFIG_TUNE_CELL=y CONFIG_PPC_FPU=y # CONFIG_ALTIVEC is not set CONFIG_PPC_STD_MMU=y CONFIG_PPC_STD_MMU_64=y CONFIG_PPC_MM_SLICES=y CONFIG_VIRT_CPU_ACCOUNTING=y CONFIG_SMP=y CONFIG_NR_CPUS=32 CONFIG_64BIT=y CONFIG_WORD_SIZE=64 CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_HAVE_LATENCYTOP_SUPPORT=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_ARCH_HAS_ILOG2_U32=y CONFIG_ARCH_HAS_ILOG2_U64=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_GPIO=y CONFIG_ARCH_NO_VIRT_TO_BUS=y CONFIG_PPC=y CONFIG_EARLY_PRINTK=y CONFIG_COMPAT=y CONFIG_SYSVIPC_COMPAT=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_PPC_OF=y CONFIG_OF=y CONFIG_PPC_UDBG_16550=y CONFIG_GENERIC_TBSYNC=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y # CONFIG_DEFAULT_UIMAGE is not set CONFIG_HIBERNATE_64=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set CONFIG_PPC_DCR_MMIO=y CONFIG_PPC_DCR=y CONFIG_PPC_OF_PLATFORM_PCI=y CONFIG_DEFCONFIG_LIST=/lib/modules/$UNAME_RELEASE/.config # # General setup # CONFIG_EXPERIMENTAL=y CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION= CONFIG_LOCALVERSION_AUTO=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TASKSTATS=y # CONFIG_TASK_DELAY_ACCT is not set CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y # CONFIG_AUDIT is not set # # RCU Subsystem # CONFIG_CLASSIC_RCU=y # CONFIG_TREE_RCU is not set # CONFIG_PREEMPT_RCU is not set # CONFIG_TREE_RCU_TRACE is not set # CONFIG_PREEMPT_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=17 # CONFIG_GROUP_SCHED is not set CONFIG_CGROUPS=y CONFIG_CGROUP_DEBUG=y # CONFIG_CGROUP_NS is not set CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_DEVICE=y CONFIG_CPUSETS=y # CONFIG_PROC_PID_CPUSET is not set CONFIG_CGROUP_CPUACCT=y CONFIG_RESOURCE_COUNTERS=y CONFIG_CGROUP_MEM_RES_CTLR=y CONFIG_MM_OWNER=y # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE= CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_EMBEDDED=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_HOTPLUG=y # CONFIG_PRINTK is not set CONFIG_BUG=y CONFIG_ELF_CORE=y # CONFIG_COMPAT_BRK is not set CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_ANON_INODES=y # CONFIG_EPOLL is not set CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y # CONFIG_SHMEM is not set CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set CONFIG_PROFILING=y CONFIG_TRACEPOINTS=y # CONFIG_MARKERS is not set CONFIG_OPROFILE=y CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y CONFIG_HAVE_SYSCALL_WRAPPERS=y CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_ATTRS=y CONFIG_USE_GENERIC_SMP_HELPERS=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 # CONFIG_MODULES is not set # CONFIG_BLOCK is not set
[PATCH RFC 0/11] FSL eSDHC support: second call for comments
Hi all, There were only a few comments on the previous version. So, here is the second call for comments. Changes since the first RFC: - Use of_iomap() in sdhci-of.c (suggested by Arnd Bergmann). Also added Arnd's Acked-by: line for the sdhci-of patch. - Kconfig help text improved (thanks to Matt Sealey and M. Warner Losh). - In sdhci: Add quirk to suppress PIO interrupts during DMA transfers patch: sdhci_init() now clears SDHCI_PIO_DISABLED flag, otherwise we won't disable PIO interrupts after suspend. - New patch: sdhci: Add type checking for IO memory accessors That's all, for now. Pierre, what do you think about memory accessors, what is your preference regarding mem ops? Some options were discussed here: http://lkml.org/lkml/2009/1/22/261 Thanks! -- Anton Vorontsov email: cbouatmai...@gmail.com irc://irc.freenode.net/bd2 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 01/11] sdhci: Add quirk for controllers with no end-of-busy IRQ
From: Ben Dooks ben-li...@fluff.org
The Samsung SDHCI (and FSL eSDHC) controller block seems to fail
to generate an INT_DATA_END after the transfer has completed and
the bus busy state finished.
Changes in e809517f6fa5803a5a1cd56026f0e2190fc13d5c to use the
new busy method are the cause of the behaviour change.
Signed-off-by: Ben Dooks ben-li...@fluff.org
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c |5 -
drivers/mmc/host/sdhci.h |2 ++
2 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 6b2d1f9..0a1f5c5 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1291,8 +1291,11 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32
intmask)
if (host-cmd-data)
DBG(Cannot wait for busy signal when also
doing a data transfer);
- else
+ else if (!(host-quirks SDHCI_QUIRK_NO_BUSY_IRQ))
return;
+
+ /* The controller does not support the end-of-busy IRQ,
+* fall through and take the SDHCI_INT_RESPONSE */
}
if (intmask SDHCI_INT_RESPONSE)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 3efba23..2d08dd4 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -210,6 +210,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_BROKEN_SMALL_PIO (113)
/* Controller supports high speed but doesn't have the caps bit set */
#define SDHCI_QUIRK_FORCE_HIGHSPEED(114)
+/* Controller does not provide transfer-complete interrupt when not busy */
+#define SDHCI_QUIRK_NO_BUSY_IRQ(115)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
--
1.5.6.5
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[PATCH 02/11] sdhci: Add support for bus-specific IO memory accessors
Currently the SDHCI driver works with PCI accessors (write{l,b,w} and
read{l,b,w}).
With this patch drivers may change memory accessors, so that we can
support hosts with weird IO memory access requirments.
For example, in FSL eSDHC SDHCI hardware all registers are 32 bit
width, with big-endian addressing. That is, readb(0x2f) should turn
into readb(0x2c), and readw(0x2c) should be translated to
le16_to_cpu(readw(0x2e)).
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci-pci.c |4 +-
drivers/mmc/host/sdhci.c | 205 +-
drivers/mmc/host/sdhci.h | 48 ++
3 files changed, 174 insertions(+), 83 deletions(-)
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index f07255c..a3ced4d 100644
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -212,7 +212,7 @@ static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
if (slot-chip-pdev-revision == 0) {
u16 version;
- version = readl(slot-host-ioaddr + SDHCI_HOST_VERSION);
+ version = sdhci_readl(slot-host, SDHCI_HOST_VERSION);
version = (version SDHCI_VENDOR_VER_MASK)
SDHCI_VENDOR_VER_SHIFT;
@@ -583,7 +583,7 @@ static void sdhci_pci_remove_slot(struct sdhci_pci_slot
*slot)
u32 scratch;
dead = 0;
- scratch = readl(slot-host-ioaddr + SDHCI_INT_STATUS);
+ scratch = sdhci_readl(slot-host, SDHCI_INT_STATUS);
if (scratch == (u32)-1)
dead = 1;
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 0a1f5c5..8557521 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -48,35 +48,35 @@ static void sdhci_dumpregs(struct sdhci_host *host)
printk(KERN_DEBUG DRIVER_NAME : == REGISTER DUMP
==\n);
printk(KERN_DEBUG DRIVER_NAME : Sys addr: 0x%08x | Version: 0x%08x\n,
- readl(host-ioaddr + SDHCI_DMA_ADDRESS),
- readw(host-ioaddr + SDHCI_HOST_VERSION));
+ sdhci_readl(host, SDHCI_DMA_ADDRESS),
+ sdhci_readw(host, SDHCI_HOST_VERSION));
printk(KERN_DEBUG DRIVER_NAME : Blk size: 0x%08x | Blk cnt: 0x%08x\n,
- readw(host-ioaddr + SDHCI_BLOCK_SIZE),
- readw(host-ioaddr + SDHCI_BLOCK_COUNT));
+ sdhci_readw(host, SDHCI_BLOCK_SIZE),
+ sdhci_readw(host, SDHCI_BLOCK_COUNT));
printk(KERN_DEBUG DRIVER_NAME : Argument: 0x%08x | Trn mode: 0x%08x\n,
- readl(host-ioaddr + SDHCI_ARGUMENT),
- readw(host-ioaddr + SDHCI_TRANSFER_MODE));
+ sdhci_readl(host, SDHCI_ARGUMENT),
+ sdhci_readw(host, SDHCI_TRANSFER_MODE));
printk(KERN_DEBUG DRIVER_NAME : Present: 0x%08x | Host ctl: 0x%08x\n,
- readl(host-ioaddr + SDHCI_PRESENT_STATE),
- readb(host-ioaddr + SDHCI_HOST_CONTROL));
+ sdhci_readl(host, SDHCI_PRESENT_STATE),
+ sdhci_readb(host, SDHCI_HOST_CONTROL));
printk(KERN_DEBUG DRIVER_NAME : Power:0x%08x | Blk gap: 0x%08x\n,
- readb(host-ioaddr + SDHCI_POWER_CONTROL),
- readb(host-ioaddr + SDHCI_BLOCK_GAP_CONTROL));
+ sdhci_readb(host, SDHCI_POWER_CONTROL),
+ sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
printk(KERN_DEBUG DRIVER_NAME : Wake-up: 0x%08x | Clock:0x%08x\n,
- readb(host-ioaddr + SDHCI_WAKE_UP_CONTROL),
- readw(host-ioaddr + SDHCI_CLOCK_CONTROL));
+ sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
+ sdhci_readw(host, SDHCI_CLOCK_CONTROL));
printk(KERN_DEBUG DRIVER_NAME : Timeout: 0x%08x | Int stat: 0x%08x\n,
- readb(host-ioaddr + SDHCI_TIMEOUT_CONTROL),
- readl(host-ioaddr + SDHCI_INT_STATUS));
+ sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
+ sdhci_readl(host, SDHCI_INT_STATUS));
printk(KERN_DEBUG DRIVER_NAME : Int enab: 0x%08x | Sig enab: 0x%08x\n,
- readl(host-ioaddr + SDHCI_INT_ENABLE),
- readl(host-ioaddr + SDHCI_SIGNAL_ENABLE));
+ sdhci_readl(host, SDHCI_INT_ENABLE),
+ sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
printk(KERN_DEBUG DRIVER_NAME : AC12 err: 0x%08x | Slot int: 0x%08x\n,
- readw(host-ioaddr + SDHCI_ACMD12_ERR),
- readw(host-ioaddr + SDHCI_SLOT_INT_STATUS));
+ sdhci_readw(host, SDHCI_ACMD12_ERR),
+ sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
printk(KERN_DEBUG DRIVER_NAME : Caps: 0x%08x | Max curr: 0x%08x\n,
- readl(host-ioaddr + SDHCI_CAPABILITIES),
- readl(host-ioaddr + SDHCI_MAX_CURRENT));
+ sdhci_readl(host, SDHCI_CAPABILITIES),
+ sdhci_readl(host, SDHCI_MAX_CURRENT));
[PATCH 03/11] sdhci: Add type checking for IO memory accessors
A new restricted integer type introduced: sdhci_reg_t.
Header file now specifies registers via sdhci_reg() inline function.
Only one place (not counting sdhci_def_*() accessors) need to cast
a register back to an offset, i.e. sdhci_finish_command().
From now on sparse tool will warn about IO memory accessors misuses,
for exampple:
sdhci_writeb(host, SDHCI_TIMEOUT_CONTROL, count);
CHECK sdhci.c
sdhci.c:614:21: warning: incorrect type in argument 2 (different base types)
sdhci.c:614:21:expected unsigned char [unsigned] [usertype] val
sdhci.c:614:21:got restricted int
sdhci.c:614:44: warning: incorrect type in argument 3 (different base types)
sdhci.c:614:44:expected restricted int [usertype] reg
sdhci.c:614:44:got unsigned char [unsigned] [assigned] [usertype] count
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c | 32 +++--
drivers/mmc/host/sdhci.h | 113 ++---
2 files changed, 82 insertions(+), 63 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 8557521..b7a79a0 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -87,34 +87,34 @@ static void sdhci_dumpregs(struct sdhci_host *host)
* *
\*/
-static u32 sdhci_def_readl(struct sdhci_host *host, int reg)
+static u32 sdhci_def_readl(struct sdhci_host *host, sdhci_reg_t reg)
{
- return readl(host-ioaddr + reg);
+ return readl(host-ioaddr + sdhci_off(reg));
}
-static u16 sdhci_def_readw(struct sdhci_host *host, int reg)
+static u16 sdhci_def_readw(struct sdhci_host *host, sdhci_reg_t reg)
{
- return readw(host-ioaddr + reg);
+ return readw(host-ioaddr + sdhci_off(reg));
}
-static u8 sdhci_def_readb(struct sdhci_host *host, int reg)
+static u8 sdhci_def_readb(struct sdhci_host *host, sdhci_reg_t reg)
{
- return readb(host-ioaddr + reg);
+ return readb(host-ioaddr + sdhci_off(reg));
}
-static void sdhci_def_writel(struct sdhci_host *host, u32 val, int reg)
+static void sdhci_def_writel(struct sdhci_host *host, u32 val, sdhci_reg_t reg)
{
- writel(val, host-ioaddr + reg);
+ writel(val, host-ioaddr + sdhci_off(reg));
}
-static void sdhci_def_writew(struct sdhci_host *host, u16 val, int reg)
+static void sdhci_def_writew(struct sdhci_host *host, u16 val, sdhci_reg_t reg)
{
- writew(val, host-ioaddr + reg);
+ writew(val, host-ioaddr + sdhci_off(reg));
}
-static void sdhci_def_writeb(struct sdhci_host *host, u8 val, int reg)
+static void sdhci_def_writeb(struct sdhci_host *host, u8 val, sdhci_reg_t reg)
{
- writeb(val, host-ioaddr + reg);
+ writeb(val, host-ioaddr + sdhci_off(reg));
}
static void sdhci_reset(struct sdhci_host *host, u8 mask)
@@ -891,12 +891,14 @@ static void sdhci_finish_command(struct sdhci_host *host)
if (host-cmd-flags MMC_RSP_136) {
/* CRC is stripped so we need to do some shifting. */
for (i = 0;i 4;i++) {
+ int resp = sdhci_off(SDHCI_RESPONSE);
+
host-cmd-resp[i] = sdhci_readl(host,
- SDHCI_RESPONSE + (3-i)*4) 8;
+ sdhci_reg(resp + (3-i)*4)) 8;
if (i != 3)
host-cmd-resp[i] |=
- sdhci_readb(host,
- SDHCI_RESPONSE + (3-i)*4-1);
+ sdhci_readb(host, sdhci_reg(
+ resp + (3-i)*4-1));
}
} else {
host-cmd-resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 8e4c4a6..5a5c119 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -12,27 +12,41 @@
#include linux/types.h
#include linux/scatterlist.h
+typedef int __bitwise__ sdhci_reg_t;
+
+/* Cast pure integer to register. */
+static inline sdhci_reg_t sdhci_reg(int off)
+{
+ return (sdhci_reg_t __force)off;
+}
+
+/* Cast register to integer (for use with arithmetics). */
+static inline int sdhci_off(sdhci_reg_t reg)
+{
+ return (int __force)reg;
+}
+
/*
* Controller registers
*/
-#define SDHCI_DMA_ADDRESS 0x00
+#define SDHCI_DMA_ADDRESS sdhci_reg(0x00)
-#define SDHCI_BLOCK_SIZE 0x04
+#define SDHCI_BLOCK_SIZE sdhci_reg(0x04)
#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma 0x7) 12) | (blksz 0xFFF))
-#define SDHCI_BLOCK_COUNT 0x06
+#define SDHCI_BLOCK_COUNT sdhci_reg(0x06)
-#define SDHCI_ARGUMENT 0x08
+#define SDHCI_ARGUMENT
[PATCH 04/11] sdhci: Add support for card-detection polling
This patch adds SDHCI_QUIRK_BROKEN_CARD_DETECTION quirk. When specified,
sdhci driver will set MMC_CAP_NEEDS_POLL MMC host capability, and won't
enable card insert/remove interrupts.
This is needed for hosts with unreliable card detection, such as FSL
eSDHC. The original eSDHC driver was tring to debounce card-detection
IRQs by reading present state and disabling particular interrupts. But
with this debouncing scheme I noticed that sometimes we miss card
insertion/removal events.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c |6 ++
drivers/mmc/host/sdhci.h |2 ++
2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index b7a79a0..45c5f1f 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -162,6 +162,9 @@ static void sdhci_init(struct sdhci_host *host)
SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
SDHCI_INT_ADMA_ERROR;
+ if (host-quirks SDHCI_QUIRK_BROKEN_CARD_DETECTION)
+ intmask = ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
+
sdhci_writel(host, intmask, SDHCI_INT_ENABLE);
sdhci_writel(host, intmask, SDHCI_SIGNAL_ENABLE);
}
@@ -1684,6 +1687,9 @@ int sdhci_add_host(struct sdhci_host *host)
mmc-f_max = host-max_clk;
mmc-caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
+ if (host-quirks SDHCI_QUIRK_BROKEN_CARD_DETECTION)
+ mmc-caps |= MMC_CAP_NEEDS_POLL;
+
if ((caps SDHCI_CAN_DO_HISPD) ||
(host-quirks SDHCI_QUIRK_FORCE_HIGHSPEED))
mmc-caps |= MMC_CAP_SD_HIGHSPEED;
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 5a5c119..03f035e 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -227,6 +227,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_FORCE_HIGHSPEED(114)
/* Controller does not provide transfer-complete interrupt when not busy */
#define SDHCI_QUIRK_NO_BUSY_IRQ(115)
+/* Controller has unreliable card detection */
+#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (116)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
--
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[PATCH 05/11] sdhci: Add support for hosts reporting inverted write-protect state
This patch adds SDHCI_QUIRK_INVERTED_WRITE_PROTECT quirk. When
specified, the sdhci driver will invert WP state.
p.s. Actually, the quirk is more board-specific than
controller-specific.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c |2 ++
drivers/mmc/host/sdhci.h |2 ++
2 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 45c5f1f..85f3780 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1121,6 +1121,8 @@ static int sdhci_get_ro(struct mmc_host *mmc)
spin_unlock_irqrestore(host-lock, flags);
+ if (host-quirks SDHCI_QUIRK_INVERTED_WRITE_PROTECT)
+ return !!(present SDHCI_WRITE_PROTECT);
return !(present SDHCI_WRITE_PROTECT);
}
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 03f035e..fd151a1 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -229,6 +229,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_NO_BUSY_IRQ(115)
/* Controller has unreliable card detection */
#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (116)
+/* Controller reports inverted write-protect state */
+#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (117)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
--
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[PATCH 06/11] sdhci: Add support for hosts with strict 32 bit addressing
SDHCI driver must take special care when working with triggering
registers on hosts with strict 32 bit addressing.
In FSL eSDHC hosts all registers are 32 bit width, writing to the
first half of any register will cause [undefined?] write the second
half of the register. That is, 16 bit write to the TRANSFER_MODE
register, makes hardware see a bogus write to the COMMAND register
(these two registers are adjacent).
This patch adds SDHCI_QUIRK_32BIT_REGISTERS quirk. When specified,
the sdhci driver will try to pack all dangerous writes into single
32 bit write transaction.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c | 19 ++-
drivers/mmc/host/sdhci.h |4
2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 85f3780..9b43588 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -747,13 +747,13 @@ static void sdhci_prepare_data(struct sdhci_host *host,
struct mmc_data *data)
sdhci_writew(host, data-blocks, SDHCI_BLOCK_COUNT);
}
-static void sdhci_set_transfer_mode(struct sdhci_host *host,
+static u16 sdhci_get_transfer_mode(struct sdhci_host *host,
struct mmc_data *data)
{
u16 mode;
if (data == NULL)
- return;
+ return 0;
WARN_ON(!host-data);
@@ -765,7 +765,7 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host,
if (host-flags SDHCI_REQ_USE_DMA)
mode |= SDHCI_TRNS_DMA;
- sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
+ return mode;
}
static void sdhci_finish_data(struct sdhci_host *host)
@@ -817,6 +817,7 @@ static void sdhci_finish_data(struct sdhci_host *host)
static void sdhci_send_command(struct sdhci_host *host, struct mmc_command
*cmd)
{
int flags;
+ u16 xfer_mode;
u32 mask;
unsigned long timeout;
@@ -855,7 +856,7 @@ static void sdhci_send_command(struct sdhci_host *host,
struct mmc_command *cmd)
sdhci_writel(host, cmd-arg, SDHCI_ARGUMENT);
- sdhci_set_transfer_mode(host, cmd-data);
+ xfer_mode = sdhci_get_transfer_mode(host, cmd-data);
if ((cmd-flags MMC_RSP_136) (cmd-flags MMC_RSP_BUSY)) {
printk(KERN_ERR %s: Unsupported response type!\n,
@@ -881,7 +882,15 @@ static void sdhci_send_command(struct sdhci_host *host,
struct mmc_command *cmd)
if (cmd-data)
flags |= SDHCI_CMD_DATA;
- sdhci_writew(host, SDHCI_MAKE_CMD(cmd-opcode, flags), SDHCI_COMMAND);
+ if (host-quirks SDHCI_QUIRK_32BIT_REGISTERS) {
+ sdhci_writel(host,
+ SDHCI_MAKE_CMD_32BIT(cmd-opcode, flags, xfer_mode),
+ SDHCI_TRANSFER_MODE);
+ } else {
+ sdhci_writew(host, xfer_mode, SDHCI_TRANSFER_MODE);
+ sdhci_writew(host, SDHCI_MAKE_CMD(cmd-opcode, flags),
+ SDHCI_COMMAND);
+ }
}
static void sdhci_finish_command(struct sdhci_host *host)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index fd151a1..c4edd52 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -58,6 +58,8 @@ static inline int sdhci_off(sdhci_reg_t reg)
#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
#define SDHCI_MAKE_CMD(c, f) (((c 0xff) 8) | (f 0xff))
+#define SDHCI_MAKE_CMD_32BIT(c, f, m) \
+ c) 0xff) 24) | (((f) 0xff) 16) | ((m) 0x37))
#define SDHCI_RESPONSE sdhci_reg(0x10)
@@ -231,6 +233,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (116)
/* Controller reports inverted write-protect state */
#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (117)
+/* Controller has all registers of 32 bit width */
+#define SDHCI_QUIRK_32BIT_REGISTERS(118)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
--
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[PATCH 07/11] sdhci: Add quirk to suppress PIO interrupts during DMA transfers
Some hosts (that is, FSL eSDHC) throw PIO interrupts during DMA
transfers, this causes tons of unneeded interrupts, and thus highly
degraded speed.
This patch adds SDHCI_QUIRK_PIO_IRQS_DURING_DMA quirk. When specified,
the sdhci driver will disable PIO interrupts during DMA transfers.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c | 32
drivers/mmc/host/sdhci.h |3 +++
2 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 9b43588..ede3790 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -167,6 +167,8 @@ static void sdhci_init(struct sdhci_host *host)
sdhci_writel(host, intmask, SDHCI_INT_ENABLE);
sdhci_writel(host, intmask, SDHCI_SIGNAL_ENABLE);
+
+ host-flags = ~SDHCI_PIO_DISABLED;
}
static void sdhci_activate_led(struct sdhci_host *host)
@@ -594,6 +596,33 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host,
struct mmc_data *data)
return count;
}
+static void sdhci_set_pio_irqs(struct sdhci_host *host, bool state)
+{
+ bool current_state = !(host-flags SDHCI_PIO_DISABLED);
+ u32 ier;
+
+ /*
+* We only care about PIO IRQs if the host issues PIO IRQs during
+* DMA transfers. Otherwise we can keep the irqs always enabled.
+*/
+ if (!(host-quirks SDHCI_QUIRK_PIO_IRQS_DURING_DMA))
+ return;
+
+ if (current_state == state)
+ return;
+
+ ier = sdhci_readl(host, SDHCI_INT_ENABLE);
+ if (state) {
+ ier |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
+ host-flags = ~SDHCI_PIO_DISABLED;
+ } else {
+ ier = ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL);
+ host-flags |= SDHCI_PIO_DISABLED;
+ }
+ sdhci_writel(host, ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
+}
+
static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
{
u8 count;
@@ -740,6 +769,9 @@ static void sdhci_prepare_data(struct sdhci_host *host,
struct mmc_data *data)
sg_miter_start(host-sg_miter,
data-sg, data-sg_len, SG_MITER_ATOMIC);
host-blocks = data-blocks;
+ sdhci_set_pio_irqs(host, true);
+ } else {
+ sdhci_set_pio_irqs(host, false);
}
/* We do not handle DMA boundaries, so set it to max (512 KiB) */
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index c4edd52..2e8dfd1 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -235,6 +235,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (117)
/* Controller has all registers of 32 bit width */
#define SDHCI_QUIRK_32BIT_REGISTERS(118)
+/* Controller issues PIO interrupts during DMA transfers */
+#define SDHCI_QUIRK_PIO_IRQS_DURING_DMA(119)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
@@ -256,6 +258,7 @@ struct sdhci_host {
#define SDHCI_USE_ADMA (11) /* Host is ADMA capable */
#define SDHCI_REQ_USE_DMA (12) /* Use DMA for this req. */
#define SDHCI_DEVICE_DEAD (13) /* Device unresponsive */
+#define SDHCI_PIO_DISABLED (14) /* PIO IRQs disabled */
unsigned intversion;/* SDHCI spec. version */
--
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[PATCH 09/11] sdhci: Add set_clock callback
FSL eSDHC hosts have incompatible register map to manage the SDCLK.
This patch adds set_clock callback so that drivers could overwrite
set_clock behaviour.
Similar patch[1] was posted by Ben Dooks, though in Ben's version the
callback is named change_clock, plus the patch has some unrelated bits
that makes the patch difficult to reuse.
[1] http://lkml.org/lkml/2008/12/2/160
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c |5 +
drivers/mmc/host/sdhci.h |2 ++
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 0293368..3c1f1d5 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -969,6 +969,11 @@ static void sdhci_set_clock(struct sdhci_host *host,
unsigned int clock)
if (clock == host-clock)
return;
+ if (host-ops-set_clock) {
+ host-ops-set_clock(host, clock);
+ return;
+ }
+
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
if (clock == 0)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 2e8dfd1..497276b 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -312,6 +312,8 @@ struct sdhci_ops {
void(*writew)(struct sdhci_host *host, u16 val, sdhci_reg_t reg);
void(*writeb)(struct sdhci_host *host, u8 val, sdhci_reg_t reg);
+ void(*set_clock)(struct sdhci_host *host, unsigned int clock);
+
int (*enable_dma)(struct sdhci_host *host);
};
--
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[PATCH 08/11] sdhci: Add support for hosts that don't specify clocks in the cap. register
FSL eSDHC hosts don't provide clocks bits in the capabilities register,
instead we're getting clocks values from the device tree.
There is somewhat similar change[1] from Ben Dooks, the change adds
callbacks for getting the clocks. But for eSDHC the callbacks are
superfluous, since the clocks are static.
[1] http://lkml.org/lkml/2008/12/2/157
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c | 31 +++
1 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index ede3790..0293368 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1703,24 +1703,23 @@ int sdhci_add_host(struct sdhci_host *host)
mmc_dev(host-mmc)-dma_mask = host-dma_mask;
}
- host-max_clk =
- (caps SDHCI_CLOCK_BASE_MASK) SDHCI_CLOCK_BASE_SHIFT;
- if (host-max_clk == 0) {
- printk(KERN_ERR %s: Hardware doesn't specify base clock
- frequency.\n, mmc_hostname(mmc));
- return -ENODEV;
+ if (!host-max_clk) {
+ host-max_clk = (caps SDHCI_CLOCK_BASE_MASK)
+ SDHCI_CLOCK_BASE_SHIFT;
+ if (host-max_clk == 0) {
+ printk(KERN_ERR %s: Hardware doesn't specify base
+ clock frequency.\n, mmc_hostname(mmc));
+ return -ENODEV;
+ }
+ host-max_clk *= 100;
}
- host-max_clk *= 100;
- host-timeout_clk =
- (caps SDHCI_TIMEOUT_CLK_MASK) SDHCI_TIMEOUT_CLK_SHIFT;
- if (host-timeout_clk == 0) {
- printk(KERN_ERR %s: Hardware doesn't specify timeout clock
- frequency.\n, mmc_hostname(mmc));
- return -ENODEV;
+ if (!host-timeout_clk) {
+ host-timeout_clk = (caps SDHCI_TIMEOUT_CLK_MASK)
+ SDHCI_TIMEOUT_CLK_SHIFT;
+ if (caps SDHCI_TIMEOUT_CLK_UNIT)
+ host-timeout_clk *= 1000;
}
- if (caps SDHCI_TIMEOUT_CLK_UNIT)
- host-timeout_clk *= 1000;
/*
* Set host parameters.
--
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[PATCH 10/11] sdhci: Add quirk for Freescale eSDHC controllers
This patch adds SDHCI_QUIRK_FSL quirk. The quirk is used to instruct
the sdhci driver about various FSL eSDHC host incompatibilities:
1) FSL eSDHC controllers can support maximum block size up to 4096
bytes. The MBL (Maximum Block Length) field in the capabilities
register extended by one bit.
(Should we implement a dedicated quirk for this? I.e.
SDHCI_QUIRK_MAX_BLK_SZ_4096?)
2) sdhci_init() is needed after error conditions.
(Can we safely do this for all controllers?)
3) Small udelay is needed to make eSDHC work in PIO mode. Without
the delay reading causes endless interrupt storm, and writing
corrupts data. The first guess would be that we must wait for
some bit in some register, but I didn't find any reliable bits
that changes before and after the delay. Though, more investigation
on this is in my todo list.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c | 36 ++--
drivers/mmc/host/sdhci.h |3 +++
2 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 3c1f1d5..87ba0ed 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -328,6 +328,10 @@ static void sdhci_transfer_pio(struct sdhci_host *host)
mask = ~0;
while (sdhci_readl(host, SDHCI_PRESENT_STATE) mask) {
+ /* FIXME */
+ if (host-quirks SDHCI_QUIRK_FSL)
+ udelay(100);
+
if (host-data-flags MMC_DATA_READ)
sdhci_read_block_pio(host);
else
@@ -625,6 +629,7 @@ static void sdhci_set_pio_irqs(struct sdhci_host *host,
bool state)
static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
{
+ u16 blksz;
u8 count;
u8 ctrl;
int ret;
@@ -775,7 +780,12 @@ static void sdhci_prepare_data(struct sdhci_host *host,
struct mmc_data *data)
}
/* We do not handle DMA boundaries, so set it to max (512 KiB) */
- sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data-blksz), SDHCI_BLOCK_SIZE);
+ if (host-quirks SDHCI_QUIRK_FSL)
+ blksz = data-blksz;
+ else
+ blksz = SDHCI_MAKE_BLKSZ(7, data-blksz);
+
+ sdhci_writew(host, blksz, SDHCI_BLOCK_SIZE);
sdhci_writew(host, data-blocks, SDHCI_BLOCK_COUNT);
}
@@ -1280,6 +1290,9 @@ static void sdhci_tasklet_finish(unsigned long param)
controllers do not like that. */
sdhci_reset(host, SDHCI_RESET_CMD);
sdhci_reset(host, SDHCI_RESET_DATA);
+ /* FSL controllers need this. */
+ if (host-quirks SDHCI_QUIRK_FSL)
+ sdhci_init(host);
}
host-mrq = NULL;
@@ -1789,13 +1802,24 @@ int sdhci_add_host(struct sdhci_host *host)
* Maximum block size. This varies from controller to controller and
* is specified in the capabilities register.
*/
- mmc-max_blk_size = (caps SDHCI_MAX_BLOCK_MASK)
SDHCI_MAX_BLOCK_SHIFT;
- if (mmc-max_blk_size = 3) {
+ if (host-quirks SDHCI_QUIRK_FSL) {
+ mmc-max_blk_size = (caps SDHCI_FSL_MAX_BLOCK_MASK)
+ SDHCI_MAX_BLOCK_SHIFT;
+ if (mmc-max_blk_size = 4)
+ mmc-max_blk_size = ~0;
+ } else {
+ mmc-max_blk_size = (caps SDHCI_MAX_BLOCK_MASK)
+ SDHCI_MAX_BLOCK_SHIFT;
+ if (mmc-max_blk_size = 3)
+ mmc-max_blk_size = ~0;
+ }
+
+ if (mmc-max_blk_size == ~0) {
printk(KERN_WARNING %s: Invalid maximum block size,
assuming 512 bytes\n, mmc_hostname(mmc));
- mmc-max_blk_size = 512;
- } else
- mmc-max_blk_size = 512 mmc-max_blk_size;
+ mmc-max_blk_size = 0;
+ }
+ mmc-max_blk_size = 512 mmc-max_blk_size;
/*
* Maximum block count.
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 497276b..cb575f3 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -152,6 +152,7 @@ static inline int sdhci_off(sdhci_reg_t reg)
#define SDHCI_CLOCK_BASE_MASK 0x3F00
#define SDHCI_CLOCK_BASE_SHIFT8
#define SDHCI_MAX_BLOCK_MASK 0x0003
+#define SDHCI_FSL_MAX_BLOCK_MASK 0x0007
#define SDHCI_MAX_BLOCK_SHIFT 16
#define SDHCI_CAN_DO_ADMA20x0008
#define SDHCI_CAN_DO_ADMA10x0010
@@ -237,6 +238,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_32BIT_REGISTERS(118)
/* Controller issues PIO interrupts during DMA transfers */
#define SDHCI_QUIRK_PIO_IRQS_DURING_DMA(119)
+/* Controller is Freescale eSDHC */
+#define SDHCI_QUIRK_FSL(120)
int irq;
[PATCH 11/11] mmc: Add OpenFirmware bindings for SDHCI driver
This patch adds a new driver: sdhci-of. The driver is similar to
the sdhci-pci, it contains common probe code, and controller-specific
ops and quirks.
So far there are only Freescale eSDHC ops and quirks.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
Acked-by: Arnd Bergmann a...@arndb.de
---
drivers/mmc/host/Kconfig| 10 ++
drivers/mmc/host/Makefile |1 +
drivers/mmc/host/sdhci-of.c | 264 +++
3 files changed, 275 insertions(+), 0 deletions(-)
create mode 100644 drivers/mmc/host/sdhci-of.c
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 99d4b28..73b79e1 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -65,6 +65,16 @@ config MMC_RICOH_MMC
If unsure, say Y.
+config MMC_SDHCI_OF
+ tristate SDHCI support on OpenFirmware platforms
+ depends on MMC_SDHCI PPC_OF
+ help
+ This selects the OF support for Secure Digital Host Controller
+ Interfaces. So far, only the Freescale eSDHC controller is known
+ to exist on OF platforms.
+
+ If unsure, say N.
+
config MMC_OMAP
tristate TI OMAP Multimedia Card Interface support
depends on ARCH_OMAP
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index dedec55..dd512d9 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_MMC_MXC) += mxcmmc.o
obj-$(CONFIG_MMC_SDHCI)+= sdhci.o
obj-$(CONFIG_MMC_SDHCI_PCI)+= sdhci-pci.o
obj-$(CONFIG_MMC_RICOH_MMC)+= ricoh_mmc.o
+obj-$(CONFIG_MMC_SDHCI_OF) += sdhci-of.o
obj-$(CONFIG_MMC_WBSD) += wbsd.o
obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
obj-$(CONFIG_MMC_OMAP) += omap.o
diff --git a/drivers/mmc/host/sdhci-of.c b/drivers/mmc/host/sdhci-of.c
new file mode 100644
index 000..734e751
--- /dev/null
+++ b/drivers/mmc/host/sdhci-of.c
@@ -0,0 +1,264 @@
+/*
+ * OpenFirmware bindings for Secure Digital Host Controller Interface.
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ * Copyright (c) 2009 MontaVista Software, Inc.
+ *
+ * Authors: Xiaobo Xie x@freescale.com
+ * Anton Vorontsov avoront...@ru.mvista.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+#include linux/module.h
+#include linux/init.h
+#include linux/io.h
+#include linux/interrupt.h
+#include linux/delay.h
+#include linux/of.h
+#include linux/of_platform.h
+#include linux/mmc/host.h
+#include sdhci.h
+
+struct sdhci_of_data {
+ unsigned int quirks;
+ struct sdhci_ops ops;
+};
+
+/*
+ * Ops and quirks for the Freescale eSDHC controller.
+ */
+
+#define ESDHC_DMA_SYSCTL 0x40c
+#define ESDHC_DMA_SNOOP0x0040
+
+#define ESDHC_SYSTEM_CONTROL 0x2c
+#define ESDHC_CLOCK_MASK 0xfff0
+#define ESDHC_PREDIV_SHIFT 8
+#define ESDHC_DIVIDER_SHIFT4
+#define ESDHC_CLOCK_PEREN 0x0004
+#define ESDHC_CLOCK_HCKEN 0x0002
+#define ESDHC_CLOCK_IPGEN 0x0001
+
+static u32 esdhc_readl(struct sdhci_host *host, sdhci_reg_t reg)
+{
+ return in_be32(host-ioaddr + sdhci_off(reg));
+}
+
+static u16 esdhc_readw(struct sdhci_host *host, sdhci_reg_t reg)
+{
+ return in_be16(host-ioaddr + (sdhci_off(reg) ^ 0x2));
+}
+
+static u8 esdhc_readb(struct sdhci_host *host, sdhci_reg_t reg)
+{
+ return in_8(host-ioaddr + (sdhci_off(reg) ^ 0x3));
+}
+
+static void esdhc_writel(struct sdhci_host *host, u32 val, sdhci_reg_t reg)
+{
+ out_be32(host-ioaddr + sdhci_off(reg), val);
+}
+
+static void esdhc_writew(struct sdhci_host *host, u16 val, sdhci_reg_t reg)
+{
+ int base = sdhci_off(reg) ~0x3;
+ int shift = (sdhci_off(reg) 0x2) * 8;
+
+ clrsetbits_be32(host-ioaddr + base, 0x shift, val shift);
+}
+
+static void esdhc_writeb(struct sdhci_host *host, u8 val, sdhci_reg_t reg)
+{
+ int base = sdhci_off(reg) ~0x3;
+ int shift = (sdhci_off(reg) 0x3) * 8;
+
+ clrsetbits_be32(host-ioaddr + base , 0xff shift, val shift);
+}
+
+static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+ int div;
+ int pre_div = 1;
+
+ setbits32(host-ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
+ ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN);
+
+ clrbits32(host-ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_MASK);
+
+ if (clock == 0)
+ goto out;
+
+ if (host-max_clk / 16 clock) {
+ for (; pre_div 256; pre_div *= 2) {
+ if (host-max_clk / pre_div clock * 16)
+ break;
+ }
+ }
+
+ for (div = 1; div = 16; div++) {
+ if (host-max_clk / (div * pre_div) = clock)
+
Re: [ANN] Introducing new test branch in powerpc.git tree
On Thu, 2009-02-05 at 15:58 -0500, Josh Boyer wrote: On Fri, Feb 06, 2009 at 07:56:22AM +1100, Benjamin Herrenschmidt wrote: Which begs the question of what master is for. So far, it's just been a mirror of next from what I can tell. Maybe it should just track Linus' tree? I've been wondering myself what to do with it ... I may just leave it to track linus indeed. Or maybe just delete it. I don't think you can delete it without hosing people who try to clone it. The branch to check out by git clone can be overridden via a special file in the .git directory in the shared repository. Unfortunately though, I don't remember what it's called... -- Earthling Michel Dänzer |http://www.vmware.com Libre software enthusiast | Debian, X and DRI developer ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: MPC5121e, MBX driver, pvr.ko ...
Dear David, In message 200902060824.06851.david.jan...@protonic.nl you wrote: I decided to try out Application Note AN3793 from Freescale (3D Graphics on the ADS512101 Board Using OpenGL ES). I started trying to load the provided (binary!) kernel modules into our kernel, but I am geeting errors inserting the modules using The binary kernel modules are a mess. Not only they are a pretty clear GPL license violation (and I wonder what Freescale is going to do to sort this out), but it effectively always locks you down to the specific LTIB kernel version (and probably even to a specific DTS) they were built against. Open source? Forget it. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Send lawyers, guns and money... - Lyrics from a Warren Zevon song ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/1] edac: new ppc4xx driver module
On 1/30/09 2:05 PM, Andrew Morton wrote:
On Fri, 30 Jan 2009 09:54:42 -0700 dougthomp...@xmission.com wrote:
From: Grant Erickson gerick...@nuovations.com
Perhaps a powerpc mailing list should have been cc'ed?
The first round patch went to Doug, the BlueSmoke (EDAC) mailing list and
the Linux/PowerPC mailing list. However, because the original patch was
split in two, subsequent revisions of just the EDAC piece went to Doug and
BlueSmoke. Doug then forwarded it to linux-kernel.
What's the preferred sign-off, ACK chain for this subsystem? Through
PowerPC/4xx or PowerPC GIT upstream or through you and -mm upstream?
These comments try really hard to be in kerneldoc form, but don't quite
succeed.
And I don't think that kerneldoc understands `...@return'? It should :(
Aye. I was mistakenly under the impression that Doxygen == kernel-doc;
however, that's clearly not the case. The next revision of the patch will
have these rectified.
+static int
+ppc4xx_edac_generate_bank_message(const struct mem_ctl_info *mci,
+ const struct ppc4xx_ecc_status *status,
+ char *buffer,
+ size_t size)
+{
+ int n, total = 0;
+ size_t row, rows;
It seems strange to use a size_t here.
Stylistically, I tend to use 'size_t' for 'unsigned type where I am counting
things'. However, I can see where this usage might be confusing and
surprising for some.
The next revision of the patch will use 'unsigned int'.
+static void
+ppc4xx_edac_handle_ce(struct mem_ctl_info *mci,
+const struct ppc4xx_ecc_status *status)
+{
+ int row;
+ char message[PPC4XX_EDAC_MESSAGE_SIZE];
256 bytes on the stack is getting a bit large.
Would you characterize this as a getting a bit large, but still OK or
getting a bit large, this MUST be changed?
I took my guidance from drivers/edac/i5[04]000_edac.c which allocate around
200 bytes on the stack for a similar use.
However, Josh Boyer had suggested that given all the snprintf going on in
the interrupt handler, a work queue might be a better way to go. ISR timings
for a sample population of 300 events are/were:
Ticks Time / us
Minimum 4150 10.38
Maximum 9075 22.69
Mean8024 20.06
Median 8297 20.74
Mode8869 22.17
Std. Dev.8642.16
In short, if this is a MUST rather than a SHOULD, reworking the driver to
pull the message buffers off the stack and implementing a work loop might be
a two-for-one rework opportunity.
+static void
+ppc4xx_edac_handle_ue(struct mem_ctl_info *mci,
+const struct ppc4xx_ecc_status *status)
+{
+ const u64 bear = ((u64)status-bearh 32 | status-bearl);
+ const unsigned long pfn = bear PAGE_SHIFT;
The term `pfn' has a specific meaining in-kernel, and I have a
suspicion that this variable doesn't match it.
I changed 'pfn' and 'poff' to 'page' and 'offset' respectively, in the next
revision of the patch.
Thanks for your feedback!
Regards,
Grant
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Re: [PATCH 1/1] edac: new ppc4xx driver module
On Fri, 06 Feb 2009 11:40:41 -0800
Grant Erickson gerick...@nuovations.com wrote:
On 1/30/09 2:05 PM, Andrew Morton wrote:
On Fri, 30 Jan 2009 09:54:42 -0700 dougthomp...@xmission.com wrote:
From: Grant Erickson gerick...@nuovations.com
Perhaps a powerpc mailing list should have been cc'ed?
The first round patch went to Doug, the BlueSmoke (EDAC) mailing list and
the Linux/PowerPC mailing list. However, because the original patch was
split in two, subsequent revisions of just the EDAC piece went to Doug and
BlueSmoke. Doug then forwarded it to linux-kernel.
What's the preferred sign-off, ACK chain for this subsystem? Through
PowerPC/4xx or PowerPC GIT upstream or through you and -mm upstream?
I don't trust those guys ;)
I'd merge it via -mm, while cc'ing various random powerpc personalities.
+static void
+ppc4xx_edac_handle_ce(struct mem_ctl_info *mci,
+const struct ppc4xx_ecc_status *status)
+{
+ int row;
+ char message[PPC4XX_EDAC_MESSAGE_SIZE];
256 bytes on the stack is getting a bit large.
Would you characterize this as a getting a bit large, but still OK or
getting a bit large, this MUST be changed?
The former.
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Re: MPC5200 PCI Issues
Hi Andre,
I started the development with 2.6.28. Thanks for all of your
suggestions but I managed to find the solution today. The problem was
that the PCI-cards did not have class specified. Adding a fixup hook
to the cards in quirks.c resolved the issue.
On Fri, Feb 6, 2009 at 14:34, Andre Schwarz
andre.schw...@matrix-vision.de wrote:
Tobias,
are you starting with 2.6.28 or are you upgrading ?
My system runs very fine with 2.6.27
Tobias Knutsson wrote:
I am currently trying to get an MPC5200-based board to run Linux
2.6.28. Most of the devices are working, however i have some issues
with the PCI-bus. More precisely, the issue is that all of
the cards' IO-regions are mapped to address 0x0.
In my device tree I have the following:
p...@fd00 {
#interrupt-cells = 1;
#size-cells = 2;
#address-cells = 3;
device_type = pci;
compatible = fsl,mpc5200b-pci,fsl,mpc5200-pci;
reg = 0xfd00 0x100;
interrupt-map-mask = 0xf800 0 0 7;
interrupt-map = 0xb000 0 0 1 mpc5200_pic 0 0 3 // MPC5200
0xb000 0 0 2 mpc5200_pic 0 0 3
0xb000 0 0 3 mpc5200_pic 0 0 3
0xb000 0 0 4 mpc5200_pic 0 0 3
What's this ? Is the MPC5200 interrupting itself ?
No, the PCI-bridge is connected to IRQ0
0xb800 0 0 1 mpc5200_pic 1 1 3 // c64x0
0xb800 0 0 2 mpc5200_pic 1 1 3
0xb800 0 0 3 mpc5200_pic 1 1 3
0xb800 0 0 4 mpc5200_pic 1 1 3
Have you connected 4 IRQ lines to each c64x device ?
No, this is just some copy-paste leftovers that should be trimmed down
after some examination of the schematics.
0xc000 0 0 1 mpc5200_pic 1 1 3 // c64x1
0xc000 0 0 2 mpc5200_pic 1 1 3
0xc000 0 0 3 mpc5200_pic 1 1 3
0xc000 0 0 4 mpc5200_pic 1 1 3
0xc800 0 0 1 mpc5200_pic 1 1 3 // c64x2
0xc800 0 0 2 mpc5200_pic 1 1 3
0xc800 0 0 3 mpc5200_pic 1 1 3
0xc800 0 0 4 mpc5200_pic 1 1 3
0xd000 0 0 1 mpc5200_pic 1 1 3 // c64x3
0xd000 0 0 2 mpc5200_pic 1 1 3
0xd000 0 0 3 mpc5200_pic 1 1 3
0xd000 0 0 4 mpc5200_pic 1 1 3
0xd800 0 0 1 mpc5200_pic 1 1 3 // c64x4
0xd800 0 0 2 mpc5200_pic 1 1 3
0xd800 0 0 3 mpc5200_pic 1 1 3
0xd800 0 0 4 mpc5200_pic 1 1 3;
I'm using an external FPGA and an e1000 NIC connectedt to IRQ2 and IRQ3 :
interrupt-map = 0x5800 0 0 1 mpc5200_pic 1 2 3
0x5000 0 0 1 mpc5200_pic 1 3
3;
clock-frequency = 0x1e84800; //0; // From boot loader
interrupts = 2 8 0 2 9 0 2 10 0;
interrupt-parent = mpc5200_pic;
bus-range = 0 0;
ranges = 0x0200 0 0x5000 0x5000 0 0x1000
0x0100 0 0x 0x6000 0 0x0100;
};
I'm using a 3 liner :
ranges = 0x4200 0 0x8000 0x8000 0 0x2000
0x0200 0 0xa000 0xa000 0 0x1000
0x0100 0 0x 0xb000 0 0x0100;
The cards' memory regions are mapped out fine to different addresses
in the 0x5000-0x6000 range. However, the IO regions are all mapped
to zero.
Are you c64x devices responding properly ? Is IO access enabled in the PCI
command register ?
Are they announcing a reasonable window ? How man KBytes ?
Do you have any idea on what could be wrong or in which direction I
should be looking?
Hopefully something is useful to you.
regards,
Andre
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner,
Hans-Joachim Reich
--
Hälsningar/Regards
Tobias Knutsson
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[PATCH v5] Add PPC/4xx ibm,sdram-4xx-ddr2 EDAC MC Driver
This adds support for an EDAC memory controller adaptation driver for the ibm,sdram-4xx-ddr2 ECC controller realized in the AMCC PowerPC 405EX[r]. Signed-off-by: Grant Erickson gerick...@nuovations.com --- At present, this driver has been developed and tested against the controller realization in the AMCC PPC405EX[r] on the AMCC Kilauea and Haleakala boards (256 MiB w/o ECC memory soldered onto the board) and a proprietary board based on those designs (128 MiB ECC memory, also soldered onto the board). In the future, dynamic feature detection and handling needs to be added for the other realizations of this controller found in the 440SP, 440SPe, 460EX, 460GT and 460SX. Eventually, this driver will likely be evolved and adapted to the above variant realizations of this controller as well as broken apart to handle the other known ECC-capable controllers prevalent in other PPC4xx processors: - IBM SDRAM (405GP, 405CR and 405EP) ibm,sdram-4xx - IBM DDR1 (440GP, 440GX, 440EP and 440GR) ibm,sdram-4xx-ddr - Denali DDR1/DDR2 (440EPX and 440GRX) denali,sdram-4xx-ddr2 Patch v2 removes the 'type' field from the of_device_id match structure to reflect the corresponding removal of the 'device_type' field from the device tree node. Patch v3 incorporates feedback from Josh Boyer regarding compliance of switch statements with Linux coding style, removing gratuitous printk wrappers, and using the DCR mapping from the device tree rather than using a fixed mapping. Patch v4 resync's the patch against the top-of-tree as 'git apply' was reporting fatal: new file drivers/edac/ppc4xx_edac.h depends on old contents. Patch v5 incorporates feedback from Andrew Morton, including changing the comment style from Doxygen to kernel-doc, reducing gratuitous parameter checking in ppc4xx_edac_mc_init, eliminated an unneeded void * cast in the ISR, changed pfn/poff to page/offset and use unsigned int rather than size_t for loop counters with associated printf format specifier changes. drivers/edac/Kconfig |9 + drivers/edac/Makefile |2 +- drivers/edac/ppc4xx_edac.c | 1448 drivers/edac/ppc4xx_edac.h | 172 ++ 4 files changed, 1630 insertions(+), 1 deletions(-) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index eee47fd..ad3e753 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -174,4 +174,13 @@ config EDAC_CELL Cell Broadband Engine internal memory controller on platform without a hypervisor +config EDAC_PPC4XX + tristate PPC4xx IBM DDR2 Memory Controller + depends on EDAC_MM_EDAC 4xx + help + This enables support for EDAC on the ECC memory used + with the IBM DDR2 memory controller found in various + PowerPC 4xx embedded processors such as the 405EX[r], + 440SP, 440SPe, 460EX, 460GT and 460SX. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index b751969..a5fdcf0 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -34,4 +34,4 @@ obj-$(CONFIG_EDAC_PASEMI) += pasemi_edac.o obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac.o obj-$(CONFIG_EDAC_MV64X60) += mv64x60_edac.o obj-$(CONFIG_EDAC_CELL)+= cell_edac.o - +obj-$(CONFIG_EDAC_PPC4XX) += ppc4xx_edac.o diff --git a/drivers/edac/ppc4xx_edac.c b/drivers/edac/ppc4xx_edac.c new file mode 100644 index 000..d244f24 --- /dev/null +++ b/drivers/edac/ppc4xx_edac.c @@ -0,0 +1,1448 @@ +/* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson gerick...@nuovations.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the + * License. + * + */ + +#include linux/edac.h +#include linux/interrupt.h +#include linux/irq.h +#include linux/kernel.h +#include linux/mm.h +#include linux/module.h +#include linux/of_device.h +#include linux/of_platform.h +#include linux/types.h + +#include asm/dcr.h + +#include edac_core.h +#include ppc4xx_edac.h + +/* + * This file implements a driver for monitoring and handling events + * associated with the IMB DDR2 ECC controller found in the AMCC/IBM + * 405EX[r], 440SP, 440SPe, 460EX, 460GT and 460SX. + * + * As realized in the 405EX[r], this controller features: + * + * - Support for registered- and non-registered DDR1 and DDR2 memory. + * - 32-bit or 16-bit memory interface with optional ECC. + * + * o ECC support includes: + * + * - 4-bit SEC/DED + * - Aligned-nibble error detect + * - Bypass mode + * + * - Two (2) memory banks/ranks. + * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per + * bank/rank in 16-bit mode. + * + * As realized in the 440SP and 440SPe, this controller changes/adds: + * + * - 64-bit or 32-bit memory interface with optional ECC. + * + * o
hash-table creation...
Hello, I wanted algorithm for creating hash tables used in paging mechanism.. In the manual that i read i got algorithm to convert Effective Address to Real Address using these hash tables that are created..but i could not find how these hash tables are created in first place using the Real addresses. Is there any document available for the same? Regards, Sumedh ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
