[PATCH] powerpc/44x: Update Glacier dts
Sync Glacier dts with latest Canyonlands version:
- Add l2 cache support
- Add NDFC support
- Add RTC support
- Add AD7414 hwmon support
- Change EMAC compatible node from emac4 to emac4sync and correct the
register size
- Add support for ISA holes on 4xx PCI/X/E
(as done in Benjamin Herrenschmidt's patch for Canyonlands)
- Add Crypto device node
Signed-off-by: Stefan Roese s...@denx.de
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
---
arch/powerpc/boot/dts/glacier.dts | 76
1 files changed, 67 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/boot/dts/glacier.dts
b/arch/powerpc/boot/dts/glacier.dts
index f6f6189..d62a4fb 100644
--- a/arch/powerpc/boot/dts/glacier.dts
+++ b/arch/powerpc/boot/dts/glacier.dts
@@ -1,7 +1,7 @@
/*
* Device Tree Source for AMCC Glacier (460GT)
*
- * Copyright 2008 DENX Software Engineering, Stefan Roese s...@denx.de
+ * Copyright 2008-2010 DENX Software Engineering, Stefan Roese s...@denx.de
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed as is without
@@ -42,6 +42,7 @@
d-cache-size = 32768;
dcr-controller;
dcr-access-method = native;
+ next-level-cache = L2C0;
};
};
@@ -106,6 +107,16 @@
dcr-reg = 0x00c 0x002;
};
+ L2C0: l2c {
+ compatible = ibm,l2-cache-460gt, ibm,l2-cache;
+ dcr-reg = 0x020 0x008 /* Internal SRAM DCR's */
+ 0x030 0x008;/* L2 cache DCR's */
+ cache-line-size = 32; /* 32 bytes */
+ cache-size = 262144; /* L2, 256K */
+ interrupt-parent = UIC1;
+ interrupts = 11 1;
+ };
+
plb {
compatible = ibm,plb-460gt, ibm,plb4;
#address-cells = 2;
@@ -118,6 +129,13 @@
dcr-reg = 0x010 0x002;
};
+ CRYPTO: cry...@18 {
+ compatible = amcc,ppc460gt-crypto,
amcc,ppc4xx-crypto;
+ reg = 4 0x0018 0x80400;
+ interrupt-parent = UIC0;
+ interrupts = 0x1d 0x4;
+ };
+
MAL0: mcmal {
compatible = ibm,mcmal-460gt, ibm,mcmal2;
dcr-reg = 0x180 0x062;
@@ -186,6 +204,29 @@
reg = 0x03fa 0x0006;
};
};
+
+ n...@3,0 {
+ compatible = ibm,ndfc;
+ reg = 0x0003 0x
0x2000;
+ ccr = 0x1000;
+ bank-settings = 0x8000;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ nand {
+ #address-cells = 1;
+ #size-cells = 1;
+
+ partit...@0 {
+ label = u-boot;
+ reg = 0x
0x0010;
+ };
+ partit...@10 {
+ label = user;
+ reg = 0x
0x03f0;
+ };
+ };
+ };
};
UART0: ser...@ef600300 {
@@ -237,6 +278,20 @@
reg = 0xef600700 0x0014;
interrupt-parent = UIC0;
interrupts = 0x2 0x4;
+ #address-cells = 1;
+ #size-cells = 0;
+ r...@68 {
+ compatible = stm,m41t80;
+ reg = 0x68;
+ interrupt-parent = UIC2;
+ interrupts = 0x19 0x8;
+ };
+ s...@48 {
+ compatible = ad,ad7414;
+ reg = 0x48;
+ interrupt-parent = UIC1;
+ interrupts = 0x14 0x8;
+ };
};
IIC1: i...@ef600800 {
[PATCH] powerpc/44x: Fix L2-cache support for 460GT
Also set L2C_CFG_RDBW on 460GT platforms and not only on 460EX. Signed-off-by: Stefan Roese s...@denx.de Cc: Josh Boyer jwbo...@linux.vnet.ibm.com --- arch/powerpc/sysdev/ppc4xx_soc.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/sysdev/ppc4xx_soc.c b/arch/powerpc/sysdev/ppc4xx_soc.c index 5b32adc..5c01435 100644 --- a/arch/powerpc/sysdev/ppc4xx_soc.c +++ b/arch/powerpc/sysdev/ppc4xx_soc.c @@ -174,7 +174,8 @@ static int __init ppc4xx_l2c_probe(void) | L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | L2C_CFG_SMCM; /* Check for 460EX/GT special handling */ - if (of_device_is_compatible(np, ibm,l2-cache-460ex)) + if (of_device_is_compatible(np, ibm,l2-cache-460ex) || + of_device_is_compatible(np, ibm,l2-cache-460gt)) r |= L2C_CFG_RDBW; mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r); -- 1.6.6.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/44x: Update Arches dts
Sync Arches dts with latest Canyonlands version:
- Add 16k FIFO size to supported EMAC nodes
- Add next-level-cache property
- Add Crypto device node
Signed-off-by: Stefan Roese s...@denx.de
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
---
arch/powerpc/boot/dts/arches.dts | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/arches.dts b/arch/powerpc/boot/dts/arches.dts
index 414ef8b..30f4120 100644
--- a/arch/powerpc/boot/dts/arches.dts
+++ b/arch/powerpc/boot/dts/arches.dts
@@ -60,6 +60,7 @@
d-cache-size = 32768;
dcr-controller;
dcr-access-method = native;
+ next-level-cache = L2C0;
};
};
@@ -146,6 +147,13 @@
dcr-reg = 0x010 0x002;
};
+ CRYPTO: cry...@18 {
+ compatible = amcc,ppc460gt-crypto,
amcc,ppc4xx-crypto;
+ reg = 4 0x0018 0x80400;
+ interrupt-parent = UIC0;
+ interrupts = 0x1d 0x4;
+ };
+
MAL0: mcmal {
compatible = ibm,mcmal-460gt, ibm,mcmal2;
dcr-reg = 0x180 0x062;
@@ -274,6 +282,7 @@
max-frame-size = 9000;
rx-fifo-size = 4096;
tx-fifo-size = 2048;
+ rx-fifo-size-gige = 16384;
phy-mode = sgmii;
phy-map = 0x;
gpcs-address = 0x000a;
@@ -302,6 +311,7 @@
max-frame-size = 9000;
rx-fifo-size = 4096;
tx-fifo-size = 2048;
+ rx-fifo-size-gige = 16384;
phy-mode = sgmii;
phy-map = 0x;
gpcs-address = 0x000b;
@@ -331,6 +341,8 @@
max-frame-size = 9000;
rx-fifo-size = 4096;
tx-fifo-size = 2048;
+ rx-fifo-size-gige = 16384;
+ tx-fifo-size-gige = 16384; /* emac23 only */
phy-mode = sgmii;
phy-map = 0x0001;
gpcs-address = 0x000C;
--
1.6.6.1
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [net-next-2.6 PATCH 2/3] fs_enet: Add support for MPC512x to fs_enet driver
Hi David,
David Miller wrote:
From: Anatolij Gustschin ag...@denx.de
Date: Tue, 9 Feb 2010 15:23:17 +0100
In my understanding, in the ESP scsi driver the set of defines for
the register offsets is common for all chip drivers. The chip driver
methods for register access translate the offsets because the
registers on some chips are at different intervals (4-byte, 1-byte,
16-byte for mac_esp.c). But the register order is the same for
different chips.
In our case non only the register order is not the same for 8xx
FEC and 5121 FEC, but there are also other differences, different
reserved areas between several registers, some registers are
available only on 8xx and some only on 5121.
That only means you would need to use a table based register address
translation scheme, rather than a simple calculation. Something
like:
static unsigned int chip_xxx_table[] =
{
[GENERIC_REG_FOO]= CHIP_XXX_FOO,
...
};
static u32 chip_xxx_read_reg(struct chip *p, unsigned int reg)
{
unsigned int reg_off = chip_xxx_table[reg];
return readl(p-regs + reg_off);
}
And this table can have special tokens in entries for
registers which do not exist on a chip, so you can trap
attempted access to them in these read/write handlers.
Yes, that could be done, but to honest, I do not see any improvement in
respect to the previous patch where the register offset were defined via
pointers within a structure.
Please stop looking for excuses to fork this driver, a
unified driver I think can be done cleanly.
Other people suggested to fork the driver because it's getting too ugly.
Wolfgang.
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v6 4/4] powerpc: doc/dts-bindings: update doc of FSL I2C bindings
From: Wolfgang Grandegger w...@denx.de
This patch adds the MPC5121 to the list of supported devices,
enhances the doc of the clock-frequency property and removes
the obsolete cell-index, device_type and fsl-i2c property.
Furthermore an example for the MPC5121 has been added.
Signed-off-by: Wolfgang Grandegger w...@denx.de
Reviewed-by: Wolfram Sang w.s...@pengutronix.de
---
Documentation/powerpc/dts-bindings/fsl/i2c.txt | 30 +--
1 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/fsl/i2c.txt
b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
index b6d2e21..50da203 100644
--- a/Documentation/powerpc/dts-bindings/fsl/i2c.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
@@ -2,15 +2,14 @@
Required properties :
- - device_type : Should be i2c
- reg : Offset and length of the register set for the device
+ - compatible : should be fsl,CHIP-i2c where CHIP is the name of a
+ compatible processor, e.g. mpc8313, mpc8543, mpc8544, mpc5121,
+ mpc5200 or mpc5200b. For the mpc5121, an additional node
+ fsl,mpc5121-i2c-ctrl is required as shown in the example below.
Recommended properties :
- - compatible : compatibility list with 2 entries, the first should
- be fsl,CHIP-i2c where CHIP is the name of a compatible processor,
- e.g. mpc8313, mpc8543, mpc8544, mpc5200 or mpc5200b. The second one
- should be fsl-i2c.
- interrupts : a b where a is the interrupt number and b is a
field that represents an encoding of the sense and level
information for the interrupt. This should be encoded based on
@@ -24,25 +23,40 @@ Recommended properties :
Examples :
+ /* MPC5121 based board */
+ i...@1740 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,mpc5121-i2c, fsl-i2c;
+ reg = 0x1740 0x20;
+ interrupts = 11 0x8;
+ interrupt-parent = ipic;
+ clock-frequency = 10;
+ };
+
+ i2ccont...@1760 {
+ compatible = fsl,mpc5121-i2c-ctrl;
+ reg = 0x1760 0x8;
+ };
+
+ /* MPC5200B based board */
i...@3d00 {
#address-cells = 1;
#size-cells = 0;
compatible = fsl,mpc5200b-i2c,fsl,mpc5200-i2c,fsl-i2c;
- cell-index = 0;
reg = 0x3d00 0x40;
interrupts = 2 15 0;
interrupt-parent = mpc5200_pic;
fsl,preserve-clocking;
};
+ /* MPC8544 base board */
i...@3100 {
#address-cells = 1;
#size-cells = 0;
- cell-index = 1;
compatible = fsl,mpc8544-i2c, fsl-i2c;
reg = 0x3100 0x100;
interrupts = 43 2;
interrupt-parent = mpic;
clock-frequency = 40;
};
-
--
1.6.2.5
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v6 2/4] i2c-mpc: rename setclock initialization functions to setup
From: Wolfgang Grandegger w...@denx.de
To prepare support for the MPC512x processors from Freescale the
setclock initialization functions have been renamed to setup
because I2C interrupts must be enabled for the MPC512x by this
function as well.
Signed-off-by: Wolfgang Grandegger w...@denx.de
---
drivers/i2c/busses/i2c-mpc.c | 34 --
1 files changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index ba4e7af..51d5280 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -67,9 +67,8 @@ struct mpc_i2c_divider {
};
struct mpc_i2c_data {
- void (*setclock)(struct device_node *node,
-struct mpc_i2c *i2c,
-u32 clock, u32 prescaler);
+ void (*setup)(struct device_node *node, struct mpc_i2c *i2c,
+ u32 clock, u32 prescaler);
u32 prescaler;
};
@@ -216,9 +215,9 @@ static int __devinit mpc_i2c_get_fdr_52xx(struct
device_node *node, u32 clock,
return div ? (int)div-fdr : -EINVAL;
}
-static void __devinit mpc_i2c_setclock_52xx(struct device_node *node,
- struct mpc_i2c *i2c,
- u32 clock, u32 prescaler)
+static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
+struct mpc_i2c *i2c,
+u32 clock, u32 prescaler)
{
int ret, fdr;
@@ -231,9 +230,9 @@ static void __devinit mpc_i2c_setclock_52xx(struct
device_node *node,
dev_info(i2c-dev, clock %d Hz (fdr=%d)\n, clock, fdr);
}
#else /* !CONFIG_PPC_MPC52xx */
-static void __devinit mpc_i2c_setclock_52xx(struct device_node *node,
- struct mpc_i2c *i2c,
- u32 clock, u32 prescaler)
+static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
+struct mpc_i2c *i2c,
+u32 clock, u32 prescaler)
{
}
#endif /* CONFIG_PPC_MPC52xx*/
@@ -322,9 +321,9 @@ static int __devinit mpc_i2c_get_fdr_8xxx(struct
device_node *node, u32 clock,
return div ? (int)div-fdr : -EINVAL;
}
-static void __devinit mpc_i2c_setclock_8xxx(struct device_node *node,
- struct mpc_i2c *i2c,
- u32 clock, u32 prescaler)
+static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
+struct mpc_i2c *i2c,
+u32 clock, u32 prescaler)
{
int ret, fdr;
@@ -340,9 +339,9 @@ static void __devinit mpc_i2c_setclock_8xxx(struct
device_node *node,
}
#else /* !CONFIG_FSL_SOC */
-static void __devinit mpc_i2c_setclock_8xxx(struct device_node *node,
- struct mpc_i2c *i2c,
- u32 clock, u32 prescaler)
+static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
+struct mpc_i2c *i2c,
+u32 clock, u32 prescaler)
{
}
#endif /* CONFIG_FSL_SOC */
@@ -533,12 +532,11 @@ static int __devinit fsl_i2c_probe(struct of_device *op,
if (match-data) {
struct mpc_i2c_data *data =
(struct mpc_i2c_data *)match-data;
- data-setclock(op-node, i2c, clock, data-prescaler);
+ data-setup(op-node, i2c, clock, data-prescaler);
} else {
/* Backwards compatibility */
if (of_get_property(op-node, dfsrr, NULL))
- mpc_i2c_setclock_8xxx(op-node, i2c,
- clock, 0);
+ mpc_i2c_setup_8xxx(op-node, i2c, clock, 0);
}
}
--
1.6.2.5
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v6 1/4] i2c-mpc: use __devinit[data] for initialization functions and data
From: Wolfgang Grandegger w...@denx.de
__devinit[data] has not yet been used for all initialization functions
and data. To avoid truncating lines, the struct mpc_i2c_match_data has
been renamed to mpc_i2c_data, which is even the better name.
Signed-off-by: Wolfgang Grandegger w...@denx.de
Tested-by: Wolfram Sang w.s...@pengutronix.de
---
drivers/i2c/busses/i2c-mpc.c | 99 +++--
1 files changed, 46 insertions(+), 53 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index f627001..ba4e7af 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -66,7 +66,7 @@ struct mpc_i2c_divider {
u16 fdr;/* including dfsrr */
};
-struct mpc_i2c_match_data {
+struct mpc_i2c_data {
void (*setclock)(struct device_node *node,
struct mpc_i2c *i2c,
u32 clock, u32 prescaler);
@@ -165,7 +165,7 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout,
int writing)
}
#ifdef CONFIG_PPC_MPC52xx
-static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
+static struct mpc_i2c_divider mpc_i2c_dividers_52xx[] __devinitdata = {
{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
{28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
{36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
@@ -186,7 +186,8 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[]
= {
{10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
};
-int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler)
+static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
+ int prescaler)
{
const struct mpc_i2c_divider *div = NULL;
unsigned int pvr = mfspr(SPRN_PVR);
@@ -215,9 +216,9 @@ int mpc_i2c_get_fdr_52xx(struct device_node *node, u32
clock, int prescaler)
return div ? (int)div-fdr : -EINVAL;
}
-static void mpc_i2c_setclock_52xx(struct device_node *node,
- struct mpc_i2c *i2c,
- u32 clock, u32 prescaler)
+static void __devinit mpc_i2c_setclock_52xx(struct device_node *node,
+ struct mpc_i2c *i2c,
+ u32 clock, u32 prescaler)
{
int ret, fdr;
@@ -230,15 +231,15 @@ static void mpc_i2c_setclock_52xx(struct device_node
*node,
dev_info(i2c-dev, clock %d Hz (fdr=%d)\n, clock, fdr);
}
#else /* !CONFIG_PPC_MPC52xx */
-static void mpc_i2c_setclock_52xx(struct device_node *node,
- struct mpc_i2c *i2c,
- u32 clock, u32 prescaler)
+static void __devinit mpc_i2c_setclock_52xx(struct device_node *node,
+ struct mpc_i2c *i2c,
+ u32 clock, u32 prescaler)
{
}
#endif /* CONFIG_PPC_MPC52xx*/
#ifdef CONFIG_FSL_SOC
-static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
+static struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] __devinitdata = {
{160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
{288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
{416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
@@ -258,7 +259,7 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[]
= {
{49152, 0x011e}, {61440, 0x011f}
};
-u32 mpc_i2c_get_sec_cfg_8xxx(void)
+static u32 __devinit mpc_i2c_get_sec_cfg_8xxx(void)
{
struct device_node *node = NULL;
u32 __iomem *reg;
@@ -287,7 +288,8 @@ u32 mpc_i2c_get_sec_cfg_8xxx(void)
return val;
}
-int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler)
+static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
+ u32 prescaler)
{
const struct mpc_i2c_divider *div = NULL;
u32 divider;
@@ -320,9 +322,9 @@ int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32
clock, u32 prescaler)
return div ? (int)div-fdr : -EINVAL;
}
-static void mpc_i2c_setclock_8xxx(struct device_node *node,
- struct mpc_i2c *i2c,
- u32 clock, u32 prescaler)
+static void __devinit mpc_i2c_setclock_8xxx(struct device_node *node,
+ struct mpc_i2c *i2c,
+ u32 clock, u32 prescaler)
{
int ret, fdr;
@@ -338,9 +340,9 @@ static void mpc_i2c_setclock_8xxx(struct device_node *node,
}
#else /* !CONFIG_FSL_SOC */
-static void mpc_i2c_setclock_8xxx(struct device_node *node,
- struct mpc_i2c *i2c,
- u32 clock, u32 prescaler)
+static void __devinit mpc_i2c_setclock_8xxx(struct device_node *node,
+ struct
[PATCH v6 3/4] i2c-mpc: add support for the MPC512x processors from Freescale
From: Wolfgang Grandegger w...@denx.de
As I2C interrupts must be enabled for the MPC512x by the setup function
as well, fsl,preserve-clocking is handled in a slighly different way.
Also, the old settings are now reported calling dev_dbg(). For the
MPC512x the clock setup function of the MPC52xx can be re-used.
Furthermore, the Kconfig help has been updated and corrected.
Signed-off-by: Wolfgang Grandegger w...@denx.de
Reviewed-by: Wolfram Sang w.s...@pengutronix.de
---
drivers/i2c/busses/Kconfig |7 +--
drivers/i2c/busses/i2c-mpc.c | 93 +
2 files changed, 78 insertions(+), 22 deletions(-)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 5f318ce..5477e41 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -418,13 +418,12 @@ config I2C_IXP2000
instead.
config I2C_MPC
- tristate MPC107/824x/85xx/52xx/86xx
+ tristate MPC107/824x/85xx/512x/52xx/83xx/86xx
depends on PPC32
help
If you say yes to this option, support will be included for the
- built-in I2C interface on the MPC107/Tsi107/MPC8240/MPC8245 and
- MPC85xx/MPC8641 family processors. The driver may also work on 52xx
- family processors, though interrupts are known not to work.
+ built-in I2C interface on the MPC107, Tsi107, MPC512x, MPC52xx,
+ MPC8240, MPC8245, MPC83xx, MPC85xx and MPC8641 family processors.
This driver can also be built as a module. If so, the module
will be called i2c-mpc.
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index 51d5280..106bf90 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -31,6 +31,9 @@
#define DRV_NAME mpc-i2c
+#define MPC_I2C_CLOCK_LEGACY 0
+#define MPC_I2C_CLOCK_PRESERVE (~0U)
+
#define MPC_I2C_FDR 0x04
#define MPC_I2C_CR0x08
#define MPC_I2C_SR0x0c
@@ -163,7 +166,7 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout,
int writing)
return 0;
}
-#ifdef CONFIG_PPC_MPC52xx
+#if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
static struct mpc_i2c_divider mpc_i2c_dividers_52xx[] __devinitdata = {
{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
{28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
@@ -193,7 +196,7 @@ static int __devinit mpc_i2c_get_fdr_52xx(struct
device_node *node, u32 clock,
u32 divider;
int i;
- if (!clock)
+ if (clock == MPC_I2C_CLOCK_LEGACY)
return -EINVAL;
/* Determine divider value */
@@ -221,6 +224,12 @@ static void __devinit mpc_i2c_setup_52xx(struct
device_node *node,
{
int ret, fdr;
+ if (clock == MPC_I2C_CLOCK_PRESERVE) {
+ dev_dbg(i2c-dev, using fdr %d\n,
+ readb(i2c-base + MPC_I2C_FDR));
+ return;
+ }
+
ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler);
fdr = (ret = 0) ? ret : 0x3f; /* backward compatibility */
@@ -229,13 +238,49 @@ static void __devinit mpc_i2c_setup_52xx(struct
device_node *node,
if (ret = 0)
dev_info(i2c-dev, clock %d Hz (fdr=%d)\n, clock, fdr);
}
-#else /* !CONFIG_PPC_MPC52xx */
+#else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
struct mpc_i2c *i2c,
u32 clock, u32 prescaler)
{
}
-#endif /* CONFIG_PPC_MPC52xx*/
+#endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
+
+#ifdef CONFIG_PPC_MPC512x
+static void __devinit mpc_i2c_setup_512x(struct device_node *node,
+struct mpc_i2c *i2c,
+u32 clock, u32 prescaler)
+{
+ struct device_node *node_ctrl;
+ void __iomem *ctrl;
+ const u32 *pval;
+ u32 idx;
+
+ /* Enable I2C interrupts for mpc5121 */
+ node_ctrl = of_find_compatible_node(NULL, NULL,
+ fsl,mpc5121-i2c-ctrl);
+ if (node_ctrl) {
+ ctrl = of_iomap(node_ctrl, 0);
+ if (ctrl) {
+ /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
+ pval = of_get_property(node, reg, NULL);
+ idx = (*pval 0xff) / 0x20;
+ setbits32(ctrl, 1 (24 + idx * 2));
+ iounmap(ctrl);
+ }
+ of_node_put(node_ctrl);
+ }
+
+ /* The clock setup for the 52xx works also fine for the 512x */
+ mpc_i2c_setup_52xx(node, i2c, clock, prescaler);
+}
+#else /* CONFIG_PPC_MPC512x */
+static void __devinit mpc_i2c_setup_512x(struct device_node *node,
+struct mpc_i2c *i2c,
+u32 clock, u32 prescaler)
+{
+}
+#endif /*
[PATCH v6 0/4] i2c-mpc: add support for the Freescale MPC512x and other fixes
From: Wolfgang Grandegger w...@denx.de This patch series adds support for the MPC512x from Freescale to the i2c-mpc driver. At that occasion, issues with __devinit[data] have been fixed and the doc of the FSL I2C dts bindings updated. It has been tested on a MPC5121ADS, TQM5200 and TQM8560 board Changes since v1: - use macro MPC_I2C_CLOCK_PRESERVE/SAFE for the special clock settings. - document the special DTS node fsl,mpc5121-i2c-ctrl. - update and correct the Kconfig help. - some other minor fixes as suggested by Wolfram. Changes since v2: - use __init[data] instead of __devinit[data] for this driver. Changes since v3: - switch back to __devinit[data] as pointed out by Ben. Changes since v4: - check MPC_I2C_CLOCK_SAFE instead of !clock as suggested by Wolfram. - update MODULE_DESCRIPTION(). Changes since v5 (suggested by Grant Likely): - various correctings for labling initialization functions and data (this is tricky because section mismatches are not always obvious). - add a separate patch for renaming the setclock into setup functions. - correct the doc of the I2C bindings, e.g. don't mention the legacy clock setting and remove obsolte parts. Wolfgang Wolfgang Grandegger (4): i2c-mpc: use __devinit[data] for initialization functions and data i2c-mpc: rename setclock initialization functions to setup i2c-mpc: add support for the MPC512x processors from Freescale powerpc: doc/dts-bindings: update doc of FSL I2C bindings Documentation/powerpc/dts-bindings/fsl/i2c.txt | 30 +++- drivers/i2c/busses/Kconfig |7 +- drivers/i2c/busses/i2c-mpc.c | 194 +++- 3 files changed, 146 insertions(+), 85 deletions(-) ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v4 1/3] i2c-mpc: use __devinit[data] for initialization functions and data
Grant Likely wrote:
On Thu, Jan 28, 2010 at 6:25 AM, Wolfgang Grandegger w...@grandegger.com
wrote:
From: Wolfgang Grandegger w...@denx.de
__devinit[data] has not yet been used for all initialization functions
and data. To avoid truncating lines, the struct mpc_i2c_match_data has
been renamed to mpc_i2c_data, which is even the better name.
Signed-off-by: Wolfgang Grandegger w...@denx.de
Several comments below.
---
drivers/i2c/busses/i2c-mpc.c | 103
+++--
1 files changed, 48 insertions(+), 55 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index f627001..275ebe6 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -66,7 +66,7 @@ struct mpc_i2c_divider {
u16 fdr;/* including dfsrr */
};
-struct mpc_i2c_match_data {
+struct mpc_i2c_data {
void (*setclock)(struct device_node *node,
struct mpc_i2c *i2c,
u32 clock, u32 prescaler);
@@ -165,7 +165,7 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned
timeout, int writing)
}
#ifdef CONFIG_PPC_MPC52xx
-static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
+static const struct __devinitdata mpc_i2c_divider mpc_i2c_dividers_52xx[] =
{
__devinitdata goes at the end, immediately before the '='. Ditto
throughout the file.
This made a difference and revealed section mismatches. const seems to
be incompatible with __devinitdata.
{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
{28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
{36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
@@ -582,44 +584,35 @@ static int __devexit fsl_i2c_remove(struct of_device
*op)
return 0;
};
+static struct mpc_i2c_data __devinitdata mpc_i2c_data_52xx = {
+ .setclock = mpc_i2c_setclock_52xx,
+};
+
+static struct mpc_i2c_data __devinitdata mpc_i2c_data_8313 = {
+ .setclock = mpc_i2c_setclock_8xxx,
+};
+
+static struct mpc_i2c_data __devinitdata mpc_i2c_data_8543 = {
+ .setclock = mpc_i2c_setclock_8xxx,
+ .prescaler = 2,
+};
+
+static struct mpc_i2c_data __devinitdata mpc_i2c_data_8544 = {
+ .setclock = mpc_i2c_setclock_8xxx,
+ .prescaler = 3,
+};
+
static const struct of_device_id mpc_i2c_of_match[] = {
You can make this __devinitdata too.
This results in a section mismatch as it's referenced by fsl_i2c_init().
I just sent out v6. Hope it's OK now.
Thanks,
Wolfgang.
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v6 2/4] i2c-mpc: rename setclock initialization functions to setup
On Wed, Feb 10, 2010 at 11:05:28AM +0100, Wolfgang Grandegger wrote: From: Wolfgang Grandegger w...@denx.de To prepare support for the MPC512x processors from Freescale the setclock initialization functions have been renamed to setup because I2C interrupts must be enabled for the MPC512x by this function as well. Signed-off-by: Wolfgang Grandegger w...@denx.de Acked-by: Wolfram Sang w.s...@pengutronix.de -- Pengutronix e.K. | Wolfram Sang| Industrial Linux Solutions | http://www.pengutronix.de/ | signature.asc Description: Digital signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [net-next-2.6 PATCH 2/3] fs_enet: Add support for MPC512x to fs_enet driver
Wolfgang Grandegger wrote:
Hi David,
David Miller wrote:
From: Anatolij Gustschin ag...@denx.de
Date: Tue, 9 Feb 2010 15:23:17 +0100
In my understanding, in the ESP scsi driver the set of defines for
the register offsets is common for all chip drivers. The chip driver
methods for register access translate the offsets because the
registers on some chips are at different intervals (4-byte, 1-byte,
16-byte for mac_esp.c). But the register order is the same for
different chips.
In our case non only the register order is not the same for 8xx
FEC and 5121 FEC, but there are also other differences, different
reserved areas between several registers, some registers are
available only on 8xx and some only on 5121.
That only means you would need to use a table based register address
translation scheme, rather than a simple calculation. Something
like:
static unsigned int chip_xxx_table[] =
{
[GENERIC_REG_FOO]= CHIP_XXX_FOO,
...
};
static u32 chip_xxx_read_reg(struct chip *p, unsigned int reg)
{
unsigned int reg_off = chip_xxx_table[reg];
return readl(p-regs + reg_off);
}
And this table can have special tokens in entries for
registers which do not exist on a chip, so you can trap
attempted access to them in these read/write handlers.
Yes, that could be done, but to honest, I do not see any improvement in
respect to the previous patch where the register offset were defined via
pointers within a structure.
Please stop looking for excuses to fork this driver, a
unified driver I think can be done cleanly.
Other people suggested to fork the driver because it's getting too ugly.
That said, I think there is consensus that it does not make sense, and
it's even not possible, to provide a kernel image which runs on both,
the 8xx and the mpc512x. Therefore, there is also no need for sharing
this driver at run time. Compile time selection would allow a more
elegant and transparent implementation. Would that be an acceptable
solution?
Wolfgang.
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v4 1/3] i2c-mpc: use __devinit[data] for initialization functions and data
Hi Wolfgang, On Wed, 10 Feb 2010 11:09:25 +0100 Wolfgang Grandegger w...@grandegger.com wrote: __devinitdata goes at the end, immediately before the '='. Ditto throughout the file. This made a difference and revealed section mismatches. const seems to be incompatible with __devinitdata. Maybe try no const and __devinitconst (I am not sure if both will work). -- Cheers, Stephen Rothwells...@canb.auug.org.au http://www.canb.auug.org.au/~sfr/ pgpCf7SYAPc6f.pgp Description: PGP signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v4 1/3] i2c-mpc: use __devinit[data] for initialization functions and data
Stephen Rothwell wrote: Hi Wolfgang, On Wed, 10 Feb 2010 11:09:25 +0100 Wolfgang Grandegger w...@grandegger.com wrote: __devinitdata goes at the end, immediately before the '='. Ditto throughout the file. This made a difference and revealed section mismatches. const seems to be incompatible with __devinitdata. Maybe try no const and __devinitconst (I am not sure if both will work). Yes, that works, even together with const. To avoid rolling out the whole patch series again, I can prepare a follow-up patch fixing this issue. Wolfgang. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/6] powerpc: Use lwarx hint in spinlocks
Recent versions of the PowerPC architecture added a hint bit to the larx instructions to differentiate between an atomic operation and a lock operation: 0 Other programs might attempt to modify the word in storage addressed by EA even if the subsequent Store Conditional succeeds. 1 Other programs will not attempt to modify the word in storage addressed by EA until the program that has acquired the lock performs a subsequent store releasing the lock. To avoid a binutils dependency this patch create macros for the extended lwarx format and uses it in the spinlock code. To test this change I used a simple test case that acquires and releases a global pthread mutex: pthread_mutex_lock(mutex); pthread_mutex_unlock(mutex); On a 32 core POWER6, running 32 test threads we spend almost all our time in the futex spinlock code: 94.37% perf [kernel] [k] ._raw_spin_lock | |--99.95%-- ._raw_spin_lock | | | |--63.29%-- .futex_wake | | | |--36.64%-- .futex_wait_setup Which is a good test for this patch. The results (in lock/unlock operations per second) are: before: 1538203 ops/sec after: 2189219 ops/sec An improvement of 42% A 32 core POWER7 improves even more: before: 1279529 ops/sec after: 2282076 ops/sec An improvement of 78% Signed-off-by: Anton Blanchard an...@samba.org --- v2: We do this only for 64bit until we can verify all 32bit CPUs. Tested so far: 970 (thanks Ben), POWER5, POWER6, POWER7 Still to test: RS64, POWER3, POWER4 Index: powerpc.git/arch/powerpc/include/asm/ppc-opcode.h === --- powerpc.git.orig/arch/powerpc/include/asm/ppc-opcode.h 2010-02-10 15:28:58.453072362 +1100 +++ powerpc.git/arch/powerpc/include/asm/ppc-opcode.h 2010-02-10 15:33:08.963071793 +1100 @@ -24,6 +24,7 @@ #define PPC_INST_ISEL_MASK 0xfc3e #define PPC_INST_LSWI 0x7c0004aa #define PPC_INST_LSWX 0x7c00042a +#define PPC_INST_LWARX 0x7c29 #define PPC_INST_LWSYNC0x7c2004ac #define PPC_INST_LXVD2X0x7c000698 #define PPC_INST_MCRXR 0x7c000400 @@ -55,15 +56,28 @@ #define __PPC_RA(a)(((a) 0x1f) 16) #define __PPC_RB(b)(((b) 0x1f) 11) #define __PPC_RS(s)(((s) 0x1f) 21) +#define __PPC_RT(s)__PPC_RS(s) #define __PPC_XS(s)s) 0x1f) 21) | (((s) 0x20) 5)) #define __PPC_T_TLB(t) (((t) 0x3) 21) #define __PPC_WC(w)(((w) 0x3) 21) +/* + * Only use the larx hint bit on 64bit CPUs. Once we verify it doesn't have + * any side effects on all 32bit processors, we can do this all the time. + */ +#ifdef CONFIG_PPC64 +#define __PPC_EH(eh) (((eh) 0x1) 0) +#else +#define __PPC_EH(eh) 0 +#endif /* Deal with instructions that older assemblers aren't aware of */ #definePPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \ __PPC_RA(a) | __PPC_RB(b)) #definePPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \ __PPC_RA(a) | __PPC_RB(b)) +#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \ + __PPC_RT(t) | __PPC_RA(a) | \ + __PPC_RB(b) | __PPC_EH(eh)) #define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \ __PPC_RB(b)) #define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI) Index: powerpc.git/arch/powerpc/include/asm/spinlock.h === --- powerpc.git.orig/arch/powerpc/include/asm/spinlock.h2010-02-10 15:28:58.473072327 +1100 +++ powerpc.git/arch/powerpc/include/asm/spinlock.h 2010-02-10 15:29:29.454322618 +1100 @@ -27,6 +27,7 @@ #endif #include asm/asm-compat.h #include asm/synch.h +#include asm/ppc-opcode.h #define arch_spin_is_locked(x) ((x)-slock != 0) @@ -60,7 +61,7 @@ static inline unsigned long __arch_spin_ token = LOCK_TOKEN; __asm__ __volatile__( -1:lwarx %0,0,%2\n\ +1: PPC_LWARX(%0,0,%2,1) \n\ cmpwi 0,%0,0\n\ bne-2f\n\ stwcx. %1,0,%2\n\ @@ -186,7 +187,7 @@ static inline long __arch_read_trylock(a long tmp; __asm__ __volatile__( -1:lwarx %0,0,%1\n +1: PPC_LWARX(%0,0,%1,1) \n __DO_SIGN_EXTEND addic. %0,%0,1\n\ ble-2f\n @@ -211,7 +212,7 @@ static inline long __arch_write_trylock( token = WRLOCK_TOKEN; __asm__ __volatile__( -1:lwarx %0,0,%2\n\ +1: PPC_LWARX(%0,0,%2,1) \n\ cmpwi 0,%0,0\n\
[PATCH 3/6] powerpc: Convert open coded native hashtable bit lock
Now we have real bit locks use them instead of open coding it.
Signed-off-by: Anton Blanchard an...@samba.org
---
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 056d23a..9e1aa4f 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -122,7 +122,7 @@ static inline void native_lock_hpte(struct hash_pte *hptep)
unsigned long *word = hptep-v;
while (1) {
- if (!test_and_set_bit(HPTE_LOCK_BIT, word))
+ if (!test_and_set_bit_lock(HPTE_LOCK_BIT, word))
break;
while(test_bit(HPTE_LOCK_BIT, word))
cpu_relax();
@@ -133,8 +133,7 @@ static inline void native_unlock_hpte(struct hash_pte
*hptep)
{
unsigned long *word = hptep-v;
- asm volatile(lwsync:::memory);
- clear_bit(HPTE_LOCK_BIT, word);
+ clear_bit_unlock(HPTE_LOCK_BIT, word);
}
static long native_hpte_insert(unsigned long hpte_group, unsigned long va,
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/6] powerpc: Use lwarx/ldarx hint in bit locks
This patch implements the lwarx/ldarx hint bit for bit locks.
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: powerpc.git/arch/powerpc/include/asm/asm-compat.h
===
--- powerpc.git.orig/arch/powerpc/include/asm/asm-compat.h 2010-02-10
17:16:07.003090026 +1100
+++ powerpc.git/arch/powerpc/include/asm/asm-compat.h 2010-02-10
17:16:39.144321846 +1100
@@ -2,6 +2,7 @@
#define _ASM_POWERPC_ASM_COMPAT_H
#include asm/types.h
+#include asm/ppc-opcode.h
#ifdef __ASSEMBLY__
# define stringify_in_c(...) __VA_ARGS__
@@ -24,7 +25,7 @@
#define PPC_LONG stringify_in_c(.llong)
#define PPC_LONG_ALIGN stringify_in_c(.balign 8)
#define PPC_TLNEI stringify_in_c(tdnei)
-#define PPC_LLARX stringify_in_c(ldarx)
+#define PPC_LLARX(t, a, b, eh) PPC_LDARX(t, a, b, eh)
#define PPC_STLCX stringify_in_c(stdcx.)
#define PPC_CNTLZL stringify_in_c(cntlzd)
@@ -46,7 +47,7 @@
#define PPC_LONG stringify_in_c(.long)
#define PPC_LONG_ALIGN stringify_in_c(.balign 4)
#define PPC_TLNEI stringify_in_c(twnei)
-#define PPC_LLARX stringify_in_c(lwarx)
+#define PPC_LLARX(t, a, b, eh) PPC_LWARX(t, a, b, eh)
#define PPC_STLCX stringify_in_c(stwcx.)
#define PPC_CNTLZL stringify_in_c(cntlzw)
#define PPC_MTOCRF stringify_in_c(mtcrf)
Index: powerpc.git/arch/powerpc/include/asm/bitops.h
===
--- powerpc.git.orig/arch/powerpc/include/asm/bitops.h 2010-02-10
17:16:07.013074408 +1100
+++ powerpc.git/arch/powerpc/include/asm/bitops.h 2010-02-10
17:16:14.253072938 +1100
@@ -65,7 +65,7 @@ static __inline__ void fn(unsigned long
unsigned long *p = (unsigned long *)_p; \
__asm__ __volatile__ ( \
prefix \
-1: PPC_LLARX %0,0,%3\n \
+1: PPC_LLARX(%0,0,%3,0) \n \
stringify_in_c(op) %0,%0,%2\n \
PPC405_ERR77(0,%3) \
PPC_STLCX %0,0,%3\n \
@@ -103,31 +103,31 @@ static __inline__ void change_bit(int nr
/* Like DEFINE_BITOP(), with changes to the arguments to 'op' and the output
* operands. */
-#define DEFINE_TESTOP(fn, op, prefix, postfix) \
-static __inline__ unsigned long fn(\
- unsigned long mask, \
- volatile unsigned long *_p) \
-{ \
- unsigned long old, t; \
- unsigned long *p = (unsigned long *)_p; \
- __asm__ __volatile__ ( \
- prefix \
-1: PPC_LLARX %0,0,%3\n \
- stringify_in_c(op) %1,%0,%2\n \
- PPC405_ERR77(0,%3) \
- PPC_STLCX %1,0,%3\n \
- bne- 1b\n \
- postfix \
- : =r (old), =r (t)\
- : r (mask), r (p) \
- : cc, memory); \
- return (old mask);\
-}
-
-DEFINE_TESTOP(test_and_set_bits, or, LWSYNC_ON_SMP, ISYNC_ON_SMP)
-DEFINE_TESTOP(test_and_set_bits_lock, or, , ISYNC_ON_SMP)
-DEFINE_TESTOP(test_and_clear_bits, andc, LWSYNC_ON_SMP, ISYNC_ON_SMP)
-DEFINE_TESTOP(test_and_change_bits, xor, LWSYNC_ON_SMP, ISYNC_ON_SMP)
+#define DEFINE_TESTOP(fn, op, prefix, postfix, eh) \
+static __inline__ unsigned long fn(\
+ unsigned long mask, \
+ volatile unsigned long *_p) \
+{ \
+ unsigned long old, t; \
+ unsigned long *p = (unsigned long *)_p; \
+ __asm__ __volatile__ ( \
+ prefix \
+1: PPC_LLARX(%0,0,%3,eh) \n \
+ stringify_in_c(op) %1,%0,%2\n \
+ PPC405_ERR77(0,%3) \
+ PPC_STLCX %1,0,%3\n \
+ bne- 1b\n \
+ postfix \
+ : =r (old), =r (t)\
+ : r (mask), r (p) \
+ : cc, memory); \
+ return (old mask);\
+}
+
+DEFINE_TESTOP(test_and_set_bits, or, LWSYNC_ON_SMP, ISYNC_ON_SMP, 0)
+DEFINE_TESTOP(test_and_set_bits_lock, or, , ISYNC_ON_SMP, 1)
+DEFINE_TESTOP(test_and_clear_bits, andc, LWSYNC_ON_SMP, ISYNC_ON_SMP, 0)
+DEFINE_TESTOP(test_and_change_bits, xor, LWSYNC_ON_SMP, ISYNC_ON_SMP, 0)
static __inline__ int test_and_set_bit(unsigned long nr,
volatile unsigned long *addr)
Index:
[PATCH 5/6] powerpc: Fix lwsync patching code on 64bit
do_lwsync_fixups doesn't work on 64bit, we end up writing lwsyncs to the
wrong addresses:
0:mon di c001000bfacc
c001000bfacc 7c2004ac lwsync
Since the lwsync section has negative offsets we need to use a signed int
pointer so we sign extend the value.
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: powerpc.git/arch/powerpc/lib/feature-fixups.c
===
--- powerpc.git.orig/arch/powerpc/lib/feature-fixups.c 2010-02-10
18:34:32.645573355 +1100
+++ powerpc.git/arch/powerpc/lib/feature-fixups.c 2010-02-10
18:35:18.525571521 +1100
@@ -112,7 +112,7 @@ void do_feature_fixups(unsigned long val
void do_lwsync_fixups(unsigned long value, void *fixup_start, void *fixup_end)
{
- unsigned int *start, *end, *dest;
+ int *start, *end, *dest;
if (!(value CPU_FTR_LWSYNC))
return ;
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 4/6] powerpc: Rename LWSYNC_ON_SMP to PPC_RELEASE_BARRIER, ISYNC_ON_SMP to PPC_ACQUIRE_BARRIER
For performance reasons we are about to change ISYNC_ON_SMP to sometimes be lwsync. Now that the macro name doesn't make sense, change it and LWSYNC_ON_SMP to better explain what the barriers are doing. Signed-off-by: Anton Blanchard an...@samba.org --- Index: powerpc.git/arch/powerpc/include/asm/atomic.h === --- powerpc.git.orig/arch/powerpc/include/asm/atomic.h 2010-02-10 17:12:30.264322204 +1100 +++ powerpc.git/arch/powerpc/include/asm/atomic.h 2010-02-10 17:13:05.355571902 +1100 @@ -49,13 +49,13 @@ static __inline__ int atomic_add_return( int t; __asm__ __volatile__( - LWSYNC_ON_SMP + PPC_RELEASE_BARRIER 1:lwarx %0,0,%2 # atomic_add_return\n\ add %0,%1,%0\n PPC405_ERR77(0,%2) stwcx. %0,0,%2 \n\ bne-1b - ISYNC_ON_SMP + PPC_ACQUIRE_BARRIER : =r (t) : r (a), r (v-counter) : cc, memory); @@ -85,13 +85,13 @@ static __inline__ int atomic_sub_return( int t; __asm__ __volatile__( - LWSYNC_ON_SMP + PPC_RELEASE_BARRIER 1:lwarx %0,0,%2 # atomic_sub_return\n\ subf%0,%1,%0\n PPC405_ERR77(0,%2) stwcx. %0,0,%2 \n\ bne-1b - ISYNC_ON_SMP + PPC_ACQUIRE_BARRIER : =r (t) : r (a), r (v-counter) : cc, memory); @@ -119,13 +119,13 @@ static __inline__ int atomic_inc_return( int t; __asm__ __volatile__( - LWSYNC_ON_SMP + PPC_RELEASE_BARRIER 1:lwarx %0,0,%1 # atomic_inc_return\n\ addic %0,%0,1\n PPC405_ERR77(0,%1) stwcx. %0,0,%1 \n\ bne-1b - ISYNC_ON_SMP + PPC_ACQUIRE_BARRIER : =r (t) : r (v-counter) : cc, xer, memory); @@ -163,13 +163,13 @@ static __inline__ int atomic_dec_return( int t; __asm__ __volatile__( - LWSYNC_ON_SMP + PPC_RELEASE_BARRIER 1:lwarx %0,0,%1 # atomic_dec_return\n\ addic %0,%0,-1\n PPC405_ERR77(0,%1) stwcx. %0,0,%1\n\ bne-1b - ISYNC_ON_SMP + PPC_ACQUIRE_BARRIER : =r (t) : r (v-counter) : cc, xer, memory); @@ -194,7 +194,7 @@ static __inline__ int atomic_add_unless( int t; __asm__ __volatile__ ( - LWSYNC_ON_SMP + PPC_RELEASE_BARRIER 1:lwarx %0,0,%1 # atomic_add_unless\n\ cmpw0,%0,%3 \n\ beq-2f \n\ @@ -202,7 +202,7 @@ static __inline__ int atomic_add_unless( PPC405_ERR77(0,%2) stwcx. %0,0,%1 \n\ bne-1b \n - ISYNC_ON_SMP + PPC_ACQUIRE_BARRIER subf%0,%2,%0 \n\ 2: : =r (t) @@ -227,7 +227,7 @@ static __inline__ int atomic_dec_if_posi int t; __asm__ __volatile__( - LWSYNC_ON_SMP + PPC_RELEASE_BARRIER 1:lwarx %0,0,%1 # atomic_dec_if_positive\n\ cmpwi %0,1\n\ addi%0,%0,-1\n\ @@ -235,7 +235,7 @@ static __inline__ int atomic_dec_if_posi PPC405_ERR77(0,%1) stwcx. %0,0,%1\n\ bne-1b - ISYNC_ON_SMP + PPC_ACQUIRE_BARRIER \n\ 2:: =b (t) : r (v-counter) @@ -286,12 +286,12 @@ static __inline__ long atomic64_add_retu long t; __asm__ __volatile__( - LWSYNC_ON_SMP + PPC_RELEASE_BARRIER 1:ldarx %0,0,%2 # atomic64_add_return\n\ add %0,%1,%0\n\ stdcx. %0,0,%2 \n\ bne-1b - ISYNC_ON_SMP + PPC_ACQUIRE_BARRIER : =r (t) : r (a), r (v-counter) : cc, memory); @@ -320,12 +320,12 @@ static __inline__ long atomic64_sub_retu long t; __asm__ __volatile__( - LWSYNC_ON_SMP + PPC_RELEASE_BARRIER 1:ldarx %0,0,%2 # atomic64_sub_return\n\ subf%0,%1,%0\n\ stdcx. %0,0,%2 \n\ bne-1b - ISYNC_ON_SMP + PPC_ACQUIRE_BARRIER : =r (t) : r (a), r (v-counter) : cc, memory); @@ -352,12 +352,12 @@ static __inline__ long atomic64_inc_retu long t; __asm__ __volatile__( - LWSYNC_ON_SMP + PPC_RELEASE_BARRIER 1:ldarx %0,0,%1 # atomic64_inc_return\n\ addic %0,%0,1\n\ stdcx. %0,0,%1 \n\ bne-1b - ISYNC_ON_SMP + PPC_ACQUIRE_BARRIER : =r (t) : r (v-counter) : cc, xer, memory); @@ -394,12 +394,12 @@ static __inline__ long atomic64_dec_retu long t; __asm__ __volatile__( - LWSYNC_ON_SMP + PPC_RELEASE_BARRIER 1:ldarx %0,0,%1 # atomic64_dec_return\n\ addic %0,%0,-1\n\ stdcx. %0,0,%1\n\ bne-1b - ISYNC_ON_SMP + PPC_ACQUIRE_BARRIER : =r (t) : r (v-counter) : cc, xer, memory); @@ -419,13 +419,13 @@ static __inline__ long atomic64_dec_if_p
[PATCH] powerpc/40x: Add support for PPC40x boards with 512MB SDRAM
This patch adds support for boards with more that 512MByte RAM. Currently only 512MB of memory are enabled in the DCCR/ICCR real-mode cache control registers. This patch now enables caching in real-mode for 2GByte. Signed-off-by: Stefan Roese s...@denx.de Cc: Benjamin Herrenschmidt b...@kernel.crashing.org Cc: Josh Boyer jwbo...@linux.vnet.ibm.com --- arch/powerpc/mm/40x_mmu.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/mm/40x_mmu.c b/arch/powerpc/mm/40x_mmu.c index 08dfa8e..65abfcf 100644 --- a/arch/powerpc/mm/40x_mmu.c +++ b/arch/powerpc/mm/40x_mmu.c @@ -84,8 +84,8 @@ void __init MMU_init_hw(void) * vectors and the kernel live in real-mode. */ -mtspr(SPRN_DCCR, 0xF000); /* 512 MB of data space at 0x0. */ -mtspr(SPRN_ICCR, 0xF000); /* 512 MB of instr. space at 0x0. */ +mtspr(SPRN_DCCR, 0x); /* 2GByte of data space at 0x0. */ +mtspr(SPRN_ICCR, 0x); /* 2GByte of instr. space at 0x0. */ } #define LARGE_PAGE_SIZE_16M(124) -- 1.6.6.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v4 1/3] i2c-mpc: use __devinit[data] for initialization functions and data
On Wed, Feb 10, 2010 at 3:53 AM, Wolfgang Grandegger w...@grandegger.com wrote: Stephen Rothwell wrote: Hi Wolfgang, On Wed, 10 Feb 2010 11:09:25 +0100 Wolfgang Grandegger w...@grandegger.com wrote: __devinitdata goes at the end, immediately before the '='. Ditto throughout the file. This made a difference and revealed section mismatches. const seems to be incompatible with __devinitdata. Maybe try no const and __devinitconst (I am not sure if both will work). Yes, that works, even together with const. To avoid rolling out the whole patch series again, I can prepare a follow-up patch fixing this issue. Nah, just resend this one patch. g. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v4 1/3] i2c-mpc: use __devinit[data] for initialization functions and data
Grant Likely wrote: On Wed, Feb 10, 2010 at 3:53 AM, Wolfgang Grandegger w...@grandegger.com wrote: Stephen Rothwell wrote: Hi Wolfgang, On Wed, 10 Feb 2010 11:09:25 +0100 Wolfgang Grandegger w...@grandegger.com wrote: __devinitdata goes at the end, immediately before the '='. Ditto throughout the file. This made a difference and revealed section mismatches. const seems to be incompatible with __devinitdata. Maybe try no const and __devinitconst (I am not sure if both will work). Yes, that works, even together with const. To avoid rolling out the whole patch series again, I can prepare a follow-up patch fixing this issue. Nah, just resend this one patch. Even if it break the following patches? Will resend v7 in a second. Wolfgang. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v7 2/4] i2c-mpc: rename setclock initialization functions to setup
From: Wolfgang Grandegger w...@denx.de
To prepare support for the MPC512x processors from Freescale the
setclock initialization functions have been renamed to setup
because I2C interrupts must be enabled for the MPC512x by this
function as well.
Signed-off-by: Wolfgang Grandegger w...@denx.de
---
drivers/i2c/busses/i2c-mpc.c | 34 --
1 files changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index 9f0e203..370c342 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -67,9 +67,8 @@ struct mpc_i2c_divider {
};
struct mpc_i2c_data {
- void (*setclock)(struct device_node *node,
-struct mpc_i2c *i2c,
-u32 clock, u32 prescaler);
+ void (*setup)(struct device_node *node, struct mpc_i2c *i2c,
+ u32 clock, u32 prescaler);
u32 prescaler;
};
@@ -216,9 +215,9 @@ static int __devinit mpc_i2c_get_fdr_52xx(struct
device_node *node, u32 clock,
return div ? (int)div-fdr : -EINVAL;
}
-static void __devinit mpc_i2c_setclock_52xx(struct device_node *node,
- struct mpc_i2c *i2c,
- u32 clock, u32 prescaler)
+static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
+struct mpc_i2c *i2c,
+u32 clock, u32 prescaler)
{
int ret, fdr;
@@ -231,9 +230,9 @@ static void __devinit mpc_i2c_setclock_52xx(struct
device_node *node,
dev_info(i2c-dev, clock %d Hz (fdr=%d)\n, clock, fdr);
}
#else /* !CONFIG_PPC_MPC52xx */
-static void __devinit mpc_i2c_setclock_52xx(struct device_node *node,
- struct mpc_i2c *i2c,
- u32 clock, u32 prescaler)
+static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
+struct mpc_i2c *i2c,
+u32 clock, u32 prescaler)
{
}
#endif /* CONFIG_PPC_MPC52xx*/
@@ -322,9 +321,9 @@ static int __devinit mpc_i2c_get_fdr_8xxx(struct
device_node *node, u32 clock,
return div ? (int)div-fdr : -EINVAL;
}
-static void __devinit mpc_i2c_setclock_8xxx(struct device_node *node,
- struct mpc_i2c *i2c,
- u32 clock, u32 prescaler)
+static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
+struct mpc_i2c *i2c,
+u32 clock, u32 prescaler)
{
int ret, fdr;
@@ -340,9 +339,9 @@ static void __devinit mpc_i2c_setclock_8xxx(struct
device_node *node,
}
#else /* !CONFIG_FSL_SOC */
-static void __devinit mpc_i2c_setclock_8xxx(struct device_node *node,
- struct mpc_i2c *i2c,
- u32 clock, u32 prescaler)
+static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
+struct mpc_i2c *i2c,
+u32 clock, u32 prescaler)
{
}
#endif /* CONFIG_FSL_SOC */
@@ -533,12 +532,11 @@ static int __devinit fsl_i2c_probe(struct of_device *op,
if (match-data) {
struct mpc_i2c_data *data =
(struct mpc_i2c_data *)match-data;
- data-setclock(op-node, i2c, clock, data-prescaler);
+ data-setup(op-node, i2c, clock, data-prescaler);
} else {
/* Backwards compatibility */
if (of_get_property(op-node, dfsrr, NULL))
- mpc_i2c_setclock_8xxx(op-node, i2c,
- clock, 0);
+ mpc_i2c_setup_8xxx(op-node, i2c, clock, 0);
}
}
--
1.6.2.5
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v7 0/4] i2c-mpc: add support for the Freescale MPC512x and other fixes
From: Wolfgang Grandegger w...@denx.de This patch series adds support for the MPC512x from Freescale to the i2c-mpc driver. At that occasion, issues with __devinit[data] have been fixed and the doc of the FSL I2C dts bindings updated. It has been tested on a MPC5121ADS, TQM5200 and TQM8560 board Changes since v1: - use macro MPC_I2C_CLOCK_PRESERVE/SAFE for the special clock settings. - document the special DTS node fsl,mpc5121-i2c-ctrl. - update and correct the Kconfig help. - some other minor fixes as suggested by Wolfram. Changes since v2: - use __init[data] instead of __devinit[data] for this driver. Changes since v3: - switch back to __devinit[data] as pointed out by Ben. Changes since v4: - check MPC_I2C_CLOCK_SAFE instead of !clock as suggested by Wolfram. - update MODULE_DESCRIPTION(). Changes since v5 (suggested by Grant Likely): - various correctings for labling initialization functions and data (this is tricky because section mismatches are not always obvious). - add a separate patch for renaming the setclock into setup functions. - correct the doc of the I2C bindings, e.g. don't mention the legacy clock setting and remove obsolte parts. Changes since v6: - use __devinitconst for const data as suggested by Stephen Rothwell. Wolfgang Wolfgang Grandegger (4): i2c-mpc: use __devinit[data] for initialization functions and data i2c-mpc: rename setclock initialization functions to setup i2c-mpc: add support for the MPC512x processors from Freescale powerpc: doc/dts-bindings: update doc of FSL I2C bindings Documentation/powerpc/dts-bindings/fsl/i2c.txt | 30 +++- drivers/i2c/busses/Kconfig |7 +- drivers/i2c/busses/i2c-mpc.c | 194 +++- 3 files changed, 146 insertions(+), 85 deletions(-) ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v7 3/4] i2c-mpc: add support for the MPC512x processors from Freescale
From: Wolfgang Grandegger w...@denx.de
As I2C interrupts must be enabled for the MPC512x by the setup function
as well, fsl,preserve-clocking is handled in a slighly different way.
Also, the old settings are now reported calling dev_dbg(). For the
MPC512x the clock setup function of the MPC52xx can be re-used.
Furthermore, the Kconfig help has been updated and corrected.
Signed-off-by: Wolfgang Grandegger w...@denx.de
Reviewed-by: Wolfram Sang w.s...@pengutronix.de
---
drivers/i2c/busses/Kconfig |7 +--
drivers/i2c/busses/i2c-mpc.c | 93 +
2 files changed, 78 insertions(+), 22 deletions(-)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 5f318ce..5477e41 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -418,13 +418,12 @@ config I2C_IXP2000
instead.
config I2C_MPC
- tristate MPC107/824x/85xx/52xx/86xx
+ tristate MPC107/824x/85xx/512x/52xx/83xx/86xx
depends on PPC32
help
If you say yes to this option, support will be included for the
- built-in I2C interface on the MPC107/Tsi107/MPC8240/MPC8245 and
- MPC85xx/MPC8641 family processors. The driver may also work on 52xx
- family processors, though interrupts are known not to work.
+ built-in I2C interface on the MPC107, Tsi107, MPC512x, MPC52xx,
+ MPC8240, MPC8245, MPC83xx, MPC85xx and MPC8641 family processors.
This driver can also be built as a module. If so, the module
will be called i2c-mpc.
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index 370c342..78a15af 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -31,6 +31,9 @@
#define DRV_NAME mpc-i2c
+#define MPC_I2C_CLOCK_LEGACY 0
+#define MPC_I2C_CLOCK_PRESERVE (~0U)
+
#define MPC_I2C_FDR 0x04
#define MPC_I2C_CR0x08
#define MPC_I2C_SR0x0c
@@ -163,7 +166,7 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout,
int writing)
return 0;
}
-#ifdef CONFIG_PPC_MPC52xx
+#if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] __devinitconst = {
{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
{28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
@@ -193,7 +196,7 @@ static int __devinit mpc_i2c_get_fdr_52xx(struct
device_node *node, u32 clock,
u32 divider;
int i;
- if (!clock)
+ if (clock == MPC_I2C_CLOCK_LEGACY)
return -EINVAL;
/* Determine divider value */
@@ -221,6 +224,12 @@ static void __devinit mpc_i2c_setup_52xx(struct
device_node *node,
{
int ret, fdr;
+ if (clock == MPC_I2C_CLOCK_PRESERVE) {
+ dev_dbg(i2c-dev, using fdr %d\n,
+ readb(i2c-base + MPC_I2C_FDR));
+ return;
+ }
+
ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler);
fdr = (ret = 0) ? ret : 0x3f; /* backward compatibility */
@@ -229,13 +238,49 @@ static void __devinit mpc_i2c_setup_52xx(struct
device_node *node,
if (ret = 0)
dev_info(i2c-dev, clock %d Hz (fdr=%d)\n, clock, fdr);
}
-#else /* !CONFIG_PPC_MPC52xx */
+#else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
struct mpc_i2c *i2c,
u32 clock, u32 prescaler)
{
}
-#endif /* CONFIG_PPC_MPC52xx*/
+#endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
+
+#ifdef CONFIG_PPC_MPC512x
+static void __devinit mpc_i2c_setup_512x(struct device_node *node,
+struct mpc_i2c *i2c,
+u32 clock, u32 prescaler)
+{
+ struct device_node *node_ctrl;
+ void __iomem *ctrl;
+ const u32 *pval;
+ u32 idx;
+
+ /* Enable I2C interrupts for mpc5121 */
+ node_ctrl = of_find_compatible_node(NULL, NULL,
+ fsl,mpc5121-i2c-ctrl);
+ if (node_ctrl) {
+ ctrl = of_iomap(node_ctrl, 0);
+ if (ctrl) {
+ /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
+ pval = of_get_property(node, reg, NULL);
+ idx = (*pval 0xff) / 0x20;
+ setbits32(ctrl, 1 (24 + idx * 2));
+ iounmap(ctrl);
+ }
+ of_node_put(node_ctrl);
+ }
+
+ /* The clock setup for the 52xx works also fine for the 512x */
+ mpc_i2c_setup_52xx(node, i2c, clock, prescaler);
+}
+#else /* CONFIG_PPC_MPC512x */
+static void __devinit mpc_i2c_setup_512x(struct device_node *node,
+struct mpc_i2c *i2c,
+u32 clock, u32 prescaler)
+{
+}
+#endif /*
[PATCH v7 1/4] i2c-mpc: use __devinit[data] for initialization functions and data
From: Wolfgang Grandegger w...@denx.de
__devinit[data] has not yet been used for all initialization functions
and data. To avoid truncating lines, the struct mpc_i2c_match_data has
been renamed to mpc_i2c_data, which is even the better name.
Signed-off-by: Wolfgang Grandegger w...@denx.de
Tested-by: Wolfram Sang w.s...@pengutronix.de
---
drivers/i2c/busses/i2c-mpc.c | 99 +++--
1 files changed, 46 insertions(+), 53 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index f627001..9f0e203 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -66,7 +66,7 @@ struct mpc_i2c_divider {
u16 fdr;/* including dfsrr */
};
-struct mpc_i2c_match_data {
+struct mpc_i2c_data {
void (*setclock)(struct device_node *node,
struct mpc_i2c *i2c,
u32 clock, u32 prescaler);
@@ -165,7 +165,7 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout,
int writing)
}
#ifdef CONFIG_PPC_MPC52xx
-static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
+static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] __devinitconst = {
{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
{28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
{36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
@@ -186,7 +186,8 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[]
= {
{10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
};
-int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler)
+static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
+ int prescaler)
{
const struct mpc_i2c_divider *div = NULL;
unsigned int pvr = mfspr(SPRN_PVR);
@@ -215,9 +216,9 @@ int mpc_i2c_get_fdr_52xx(struct device_node *node, u32
clock, int prescaler)
return div ? (int)div-fdr : -EINVAL;
}
-static void mpc_i2c_setclock_52xx(struct device_node *node,
- struct mpc_i2c *i2c,
- u32 clock, u32 prescaler)
+static void __devinit mpc_i2c_setclock_52xx(struct device_node *node,
+ struct mpc_i2c *i2c,
+ u32 clock, u32 prescaler)
{
int ret, fdr;
@@ -230,15 +231,15 @@ static void mpc_i2c_setclock_52xx(struct device_node
*node,
dev_info(i2c-dev, clock %d Hz (fdr=%d)\n, clock, fdr);
}
#else /* !CONFIG_PPC_MPC52xx */
-static void mpc_i2c_setclock_52xx(struct device_node *node,
- struct mpc_i2c *i2c,
- u32 clock, u32 prescaler)
+static void __devinit mpc_i2c_setclock_52xx(struct device_node *node,
+ struct mpc_i2c *i2c,
+ u32 clock, u32 prescaler)
{
}
#endif /* CONFIG_PPC_MPC52xx*/
#ifdef CONFIG_FSL_SOC
-static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
+static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] __devinitconst = {
{160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
{288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
{416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
@@ -258,7 +259,7 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[]
= {
{49152, 0x011e}, {61440, 0x011f}
};
-u32 mpc_i2c_get_sec_cfg_8xxx(void)
+static u32 __devinit mpc_i2c_get_sec_cfg_8xxx(void)
{
struct device_node *node = NULL;
u32 __iomem *reg;
@@ -287,7 +288,8 @@ u32 mpc_i2c_get_sec_cfg_8xxx(void)
return val;
}
-int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler)
+static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
+ u32 prescaler)
{
const struct mpc_i2c_divider *div = NULL;
u32 divider;
@@ -320,9 +322,9 @@ int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32
clock, u32 prescaler)
return div ? (int)div-fdr : -EINVAL;
}
-static void mpc_i2c_setclock_8xxx(struct device_node *node,
- struct mpc_i2c *i2c,
- u32 clock, u32 prescaler)
+static void __devinit mpc_i2c_setclock_8xxx(struct device_node *node,
+ struct mpc_i2c *i2c,
+ u32 clock, u32 prescaler)
{
int ret, fdr;
@@ -338,9 +340,9 @@ static void mpc_i2c_setclock_8xxx(struct device_node *node,
}
#else /* !CONFIG_FSL_SOC */
-static void mpc_i2c_setclock_8xxx(struct device_node *node,
- struct mpc_i2c *i2c,
- u32 clock, u32 prescaler)
+static void __devinit mpc_i2c_setclock_8xxx(struct device_node *node,
+
[PATCH v7 4/4] powerpc: doc/dts-bindings: update doc of FSL I2C bindings
From: Wolfgang Grandegger w...@denx.de
This patch adds the MPC5121 to the list of supported devices,
enhances the doc of the clock-frequency property and removes
the obsolete cell-index, device_type and fsl-i2c property.
Furthermore an example for the MPC5121 has been added.
Signed-off-by: Wolfgang Grandegger w...@denx.de
Reviewed-by: Wolfram Sang w.s...@pengutronix.de
---
Documentation/powerpc/dts-bindings/fsl/i2c.txt | 30 +--
1 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/fsl/i2c.txt
b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
index b6d2e21..50da203 100644
--- a/Documentation/powerpc/dts-bindings/fsl/i2c.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
@@ -2,15 +2,14 @@
Required properties :
- - device_type : Should be i2c
- reg : Offset and length of the register set for the device
+ - compatible : should be fsl,CHIP-i2c where CHIP is the name of a
+ compatible processor, e.g. mpc8313, mpc8543, mpc8544, mpc5121,
+ mpc5200 or mpc5200b. For the mpc5121, an additional node
+ fsl,mpc5121-i2c-ctrl is required as shown in the example below.
Recommended properties :
- - compatible : compatibility list with 2 entries, the first should
- be fsl,CHIP-i2c where CHIP is the name of a compatible processor,
- e.g. mpc8313, mpc8543, mpc8544, mpc5200 or mpc5200b. The second one
- should be fsl-i2c.
- interrupts : a b where a is the interrupt number and b is a
field that represents an encoding of the sense and level
information for the interrupt. This should be encoded based on
@@ -24,25 +23,40 @@ Recommended properties :
Examples :
+ /* MPC5121 based board */
+ i...@1740 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,mpc5121-i2c, fsl-i2c;
+ reg = 0x1740 0x20;
+ interrupts = 11 0x8;
+ interrupt-parent = ipic;
+ clock-frequency = 10;
+ };
+
+ i2ccont...@1760 {
+ compatible = fsl,mpc5121-i2c-ctrl;
+ reg = 0x1760 0x8;
+ };
+
+ /* MPC5200B based board */
i...@3d00 {
#address-cells = 1;
#size-cells = 0;
compatible = fsl,mpc5200b-i2c,fsl,mpc5200-i2c,fsl-i2c;
- cell-index = 0;
reg = 0x3d00 0x40;
interrupts = 2 15 0;
interrupt-parent = mpc5200_pic;
fsl,preserve-clocking;
};
+ /* MPC8544 base board */
i...@3100 {
#address-cells = 1;
#size-cells = 0;
- cell-index = 1;
compatible = fsl,mpc8544-i2c, fsl-i2c;
reg = 0x3100 0x100;
interrupts = 43 2;
interrupt-parent = mpic;
clock-frequency = 40;
};
-
--
1.6.2.5
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: Use lwarx hint bit in spinlocks
On Feb 9, 2010, at 9:19 PM, Josh Boyer wrote: On Wed, Feb 10, 2010 at 01:50:11PM +1100, Anton Blanchard wrote: Recent versions of the PowerPC architecture added a hint bit to the larx instructions to differentiate between an atomic operation and a lock operation: 0 Other programs might attempt to modify the word in storage addressed by EA even if the subsequent Store Conditional succeeds. 1 Other programs will not attempt to modify the word in storage addressed by EA until the program that has acquired the lock performs a subsequent store releasing the lock. To avoid a binutils dependency this patch create macros for the extended lwarx format and uses it in the spinlock code. To test this change I used a simple test case that acquires and releases a global pthread mutex: pthread_mutex_lock(mutex); pthread_mutex_unlock(mutex); On a 32 core POWER6 running 32 test threads we spend almost all our time in the futex spinlock code (as expected): 94.37% perf [kernel] [k] ._raw_spin_lock | |--99.95%-- ._raw_spin_lock | | | |--63.29%-- .futex_wake | | | |--36.64%-- .futex_wait_setup which is a good test for this patch. The results (in lock/unlock operations per second) are: before: 1538203 ops/sec after: 2189219 ops/sec An improvement of 42% Signed-off-by: Anton Blanchard an...@samba.org --- We've had issues in the past with chips that do the wrong thing and don't ignore instruction reserved bits. One option might be to limit this change to 64bit and verify on that limited set of CPUs. In the off chance that someone actually does an SMP 44x, I think the hint bit here would just be ignored (I could test possibly if we want to verify). However, I thought the FSL parts didn't like toggling the reserved bits and those already are SMP in some cases. Kumar? josh Yeah, I need to test this on some older SMP parts that didn't treated reserved bits being set in the opcode as ignored but illegal. - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [rtc-linux] Re: [PATCH v3 03/11] rtc: Add MPC5121 Real time clock driver
On Tue, 9 Feb 2010 19:39:35 -0700 Grant Likely grant.lik...@secretlab.ca wrote: Acked-by: Grant Likely grant.lik...@secretlab.ca Alessandro, do you want me to carry this one in my powerpc tree along with the rest of the 5121 patches, or do you want to carry it? There aren't any commit ordering issues on this one. Yes please. thanks. Acked-by: Alessandro Zummo a.zu...@towertech.it -- Best regards, Alessandro Zummo, Tower Technologies - Torino, Italy http://www.towertech.it ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: Use lwarx hint bit in spinlocks
On Wed, Feb 10, 2010 at 09:40:34AM -0600, Kumar Gala wrote: In the off chance that someone actually does an SMP 44x, I think the hint bit here would just be ignored (I could test possibly if we want to verify). However, I thought the FSL parts didn't like toggling the reserved bits and those already are SMP in some cases. Kumar? josh Yeah, I need to test this on some older SMP parts that didn't treated reserved bits being set in the opcode as ignored but illegal. It looks like Anton just did a v2 of the patch targeted at ppc64 instead. josh ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] perf_event: e500 support
On Fri, Jan 15, 2010 at 03:43:51PM -0600, Scott Wood wrote:
This implements perf_event support for the Freescale embedded performance
monitor, based on the existing perf_event.c that supports server/classic
chips. Eventually we may want to factor out some of the common bits.
Cool! I agree we will want to factor out some things, such as
collect_events() for instance. We could create a perf_helper.c for
those bits.
Some limitations:
- No threshold support -- need to figure out how to represent it in
the event struct from userspace.
What does threshold support mean in this context? Does it mean
something different from getting an interrupt after N events have been
counted? Or does it mean counting instances where something takes
longer than a specific number of cycles?
- When trying to schedule multiple event groups at once, and using
restricted events, situations could arise where scheduling fails even
though it would be possible. Consider three groups, each with two events.
One group has restricted events, the others don't. The two non-restricted
groups are scheduled, then one is removed, which happens to occupy the two
counters that can't do restricted events. The remaining non-restricted
group will not be moved to the non-restricted-capable counters to make
room if the restricted group tries to be scheduled. Since thresholds are
not yet supported (though you can use the events with a threshold of
zero), and threshold events are the only restricted events, this seems
like a low priority issue.
Which way around are the restrictions? That some events can only be
counted on certain counters, or that some counters can only count a
subset of the available events?
Did you look at the constraint satisfaction code in the existing
perf_event.c and p*-pmu.c? That lets you express both sorts of
restrictions and automatically find the best solution (including
moving events from one counter to another like you describe).
Some specific comments:
diff --git a/arch/powerpc/include/asm/perf_event.h
b/arch/powerpc/include/asm/perf_event.h
index 3288ce3..2fd2781 100644
--- a/arch/powerpc/include/asm/perf_event.h
+++ b/arch/powerpc/include/asm/perf_event.h
@@ -2,6 +2,7 @@
* Performance event support - PowerPC-specific definitions.
*
* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
+ * Copyright 2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -12,6 +13,36 @@
#include asm/hw_irq.h
+#ifdef CONFIG_FSL_EMB_PERFMON
+#define MAX_HWEVENTS 4
+
+/* event flags */
+#define FSL_EMB_EVENT_VALID 1
+#define FSL_EMB_EVENT_RESTRICTED 2
+
+struct power_pmu {
I wonder if we should have just the stuff exported to the core in
asm/perf_event.h and move MAX_HWEVENTS, struct power_pmu etc. to
separate headers for fsl_embedded, classic, etc.?
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -98,7 +98,10 @@ obj64-$(CONFIG_AUDIT) += compat_audit.o
obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
-obj-$(CONFIG_PPC_PERF_CTRS) += perf_event.o perf_callchain.o
+obj-$(CONFIG_PPC_PERF_CTRS) += perf_event.o
+obj-$(CONFIG_FSL_EMB_PERF_EVENT) += perf_event_fsl_emb.o
+obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o
+obj-$(CONFIG_PERF_EVENTS)+= perf_callchain.o
This is because we want perf_callchain.o even if we don't have
hardware PMU support, is it? If so this is a separate fix that
deserves its own patch.
Paul.
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] perf_event: e500 support
Paul Mackerras wrote:
Some limitations:
- No threshold support -- need to figure out how to represent it in
the event struct from userspace.
What does threshold support mean in this context? Does it mean
something different from getting an interrupt after N events have been
counted? Or does it mean counting instances where something takes
longer than a specific number of cycles?
The latter.
- When trying to schedule multiple event groups at once, and using
restricted events, situations could arise where scheduling fails even
though it would be possible. Consider three groups, each with two events.
One group has restricted events, the others don't. The two non-restricted
groups are scheduled, then one is removed, which happens to occupy the two
counters that can't do restricted events. The remaining non-restricted
group will not be moved to the non-restricted-capable counters to make
room if the restricted group tries to be scheduled. Since thresholds are
not yet supported (though you can use the events with a threshold of
zero), and threshold events are the only restricted events, this seems
like a low priority issue.
Which way around are the restrictions? That some events can only be
counted on certain counters, or that some counters can only count a
subset of the available events?
You could look at it either way -- threshold-capable events can only go on
counters 0-1, or counters 2-3 can only count non-threshold-capable events.
Did you look at the constraint satisfaction code in the existing
perf_event.c and p*-pmu.c? That lets you express both sorts of
restrictions and automatically find the best solution (including
moving events from one counter to another like you describe).
I did look at it -- but I had a hard time understanding it, and went with the
simpler approach for now since the constraints are minimal on these chips. I'm
open to converting with a little help, if it doesn't add too much complexity or
if future chips need it.
+#ifdef CONFIG_FSL_EMB_PERFMON
+#define MAX_HWEVENTS 4
+
+/* event flags */
+#define FSL_EMB_EVENT_VALID 1
+#define FSL_EMB_EVENT_RESTRICTED 2
+
+struct power_pmu {
I wonder if we should have just the stuff exported to the core in
asm/perf_event.h and move MAX_HWEVENTS, struct power_pmu etc. to
separate headers for fsl_embedded, classic, etc.?
Maybe. We may also want to consider making it runtime selectable, as later
revisions of e300 have an e500-style performance counter. There's also a
separate platform-level performance counter on some of our chips; having arch
infrastructure that can delegate to multiple counter types would help there as well.
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -98,7 +98,10 @@ obj64-$(CONFIG_AUDIT)+= compat_audit.o
obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
obj-$(CONFIG_FUNCTION_GRAPH_TRACER)+= ftrace.o
-obj-$(CONFIG_PPC_PERF_CTRS)+= perf_event.o perf_callchain.o
+obj-$(CONFIG_PPC_PERF_CTRS)+= perf_event.o
+obj-$(CONFIG_FSL_EMB_PERF_EVENT) += perf_event_fsl_emb.o
+obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o
+obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o
This is because we want perf_callchain.o even if we don't have
hardware PMU support, is it? If so this is a separate fix that
deserves its own patch.
OK.
-Scott
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc: Improve 64bit copy_tofrom_user
Here is a patch from Paul Mackerras that improves the ppc64 copy_tofrom_user.
The loop now does 32 bytes at a time and as well as pairing loads and stores.
A quick test case that reads 8kB over and over shows the improvement:
POWER6: 53% faster
POWER7: 51% faster
#define _XOPEN_SOURCE 500
#include stdlib.h
#include stdio.h
#include unistd.h
#include fcntl.h
#include sys/types.h
#include sys/stat.h
#define BUFSIZE (8 * 1024)
#define ITERATIONS 1000
int main()
{
char tmpfile[] = /tmp/copy_to_user_testXX;
int fd;
char *buf[BUFSIZE];
unsigned long i;
fd = mkstemp(tmpfile);
if (fd 0) {
perror(open);
exit(1);
}
if (write(fd, buf, BUFSIZE) != BUFSIZE) {
perror(open);
exit(1);
}
for (i = 0; i 1000; i++) {
if (pread(fd, buf, BUFSIZE, 0) != BUFSIZE) {
perror(pread);
exit(1);
}
}
unlink(tmpfile);
return 0;
}
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: powerpc.git/arch/powerpc/lib/copyuser_64.S
===
--- powerpc.git.orig/arch/powerpc/lib/copyuser_64.S 2009-02-27
14:09:46.0 +1100
+++ powerpc.git/arch/powerpc/lib/copyuser_64.S 2010-02-11 11:12:37.646821713
+1100
@@ -44,37 +44,55 @@ BEGIN_FTR_SECTION
andi. r0,r4,7
bne .Lsrc_unaligned
END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
- srdir7,r5,4
-20:ld r9,0(r4)
- addir4,r4,-8
- mtctr r7
- andi. r5,r5,7
- bf cr7*4+0,22f
- addir3,r3,8
- addir4,r4,8
- mr r8,r9
- blt cr1,72f
-21:ld r9,8(r4)
-70:std r8,8(r3)
-22:ldu r8,16(r4)
-71:stdur9,16(r3)
+ blt cr1,.Ldo_tail /* if 16 bytes to copy */
+ srdir0,r5,5
+ cmpdi cr1,r0,0
+20:ld r7,0(r4)
+220: ld r6,8(r4)
+ addir4,r4,16
+ mtctr r0
+ andi. r0,r5,0x10
+ beq 22f
+ addir3,r3,16
+ addir4,r4,-16
+ mr r9,r7
+ mr r8,r6
+ beq cr1,72f
+21:ld r7,16(r4)
+221: ld r6,24(r4)
+ addir4,r4,32
+70:std r9,0(r3)
+270: std r8,8(r3)
+22:ld r9,0(r4)
+222: ld r8,8(r4)
+71:std r7,16(r3)
+271: std r6,24(r3)
+ addir3,r3,32
bdnz21b
-72:std r8,8(r3)
+72:std r9,0(r3)
+272: std r8,8(r3)
+ andi. r5,r5,0xf
beq+3f
- addir3,r3,16
+ addir4,r4,16
.Ldo_tail:
- bf cr7*4+1,1f
-23:lwz r9,8(r4)
+ addir3,r3,16
+ bf cr7*4+0,246f
+244: ld r9,0(r4)
+ addir4,r4,8
+245: std r9,0(r3)
+ addir3,r3,8
+246: bf cr7*4+1,1f
+23:lwz r9,0(r4)
addir4,r4,4
73:stw r9,0(r3)
addir3,r3,4
1: bf cr7*4+2,2f
-44:lhz r9,8(r4)
+44:lhz r9,0(r4)
addir4,r4,2
74:sth r9,0(r3)
addir3,r3,2
2: bf cr7*4+3,3f
-45:lbz r9,8(r4)
+45:lbz r9,0(r4)
75:stb r9,0(r3)
3: li r3,0
blr
@@ -220,7 +238,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_
131:
addir3,r3,8
120:
+320:
122:
+322:
124:
125:
126:
@@ -229,9 +249,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_
129:
133:
addir3,r3,8
-121:
132:
addir3,r3,8
+121:
+321:
+344:
134:
135:
138:
@@ -303,18 +325,22 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_
183:
add r3,r3,r7
b 1f
+371:
180:
addir3,r3,8
171:
177:
addir3,r3,8
-170:
-172:
+370:
+372:
176:
178:
addir3,r3,4
185:
addir3,r3,4
+170:
+172:
+345:
173:
174:
175:
@@ -341,11 +367,19 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_
.section __ex_table,a
.align 3
.llong 20b,120b
+ .llong 220b,320b
.llong 21b,121b
+ .llong 221b,321b
.llong 70b,170b
+ .llong 270b,370b
.llong 22b,122b
+ .llong 222b,322b
.llong 71b,171b
+ .llong 271b,371b
.llong 72b,172b
+ .llong 272b,372b
+ .llong 244b,344b
+ .llong 245b,345b
.llong 23b,123b
.llong 73b,173b
.llong 44b,144b
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/40x: Add support for PPC40x boards with 512MB SDRAM
On Wed, 2010-02-10 at 14:54 +0100, Stefan Roese wrote: This patch adds support for boards with more that 512MByte RAM. Currently only 512MB of memory are enabled in the DCCR/ICCR real-mode cache control registers. This patch now enables caching in real-mode for 2GByte. Should we make that conditional to how much memory is populated ? Or it doesn't matter ? I suppose we don't do IO accesses in real mode anyways so no big deal... Cheers, Ben. Signed-off-by: Stefan Roese s...@denx.de Cc: Benjamin Herrenschmidt b...@kernel.crashing.org Cc: Josh Boyer jwbo...@linux.vnet.ibm.com --- arch/powerpc/mm/40x_mmu.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/mm/40x_mmu.c b/arch/powerpc/mm/40x_mmu.c index 08dfa8e..65abfcf 100644 --- a/arch/powerpc/mm/40x_mmu.c +++ b/arch/powerpc/mm/40x_mmu.c @@ -84,8 +84,8 @@ void __init MMU_init_hw(void) * vectors and the kernel live in real-mode. */ -mtspr(SPRN_DCCR, 0xF000);/* 512 MB of data space at 0x0. */ -mtspr(SPRN_ICCR, 0xF000);/* 512 MB of instr. space at 0x0. */ +mtspr(SPRN_DCCR, 0x);/* 2GByte of data space at 0x0. */ +mtspr(SPRN_ICCR, 0x);/* 2GByte of instr. space at 0x0. */ } #define LARGE_PAGE_SIZE_16M (124) ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] perf_event: e500 support
On Wed, Feb 10, 2010 at 06:06:10PM -0600, Scott Wood wrote: Paul Mackerras wrote: Some limitations: - No threshold support -- need to figure out how to represent it in the event struct from userspace. What does threshold support mean in this context? Does it mean something different from getting an interrupt after N events have been counted? Or does it mean counting instances where something takes longer than a specific number of cycles? The latter. OK. I handled that on classic by using some extra high bits in the event config for the threshold value. If you have a single threshold value in hardware but more than one event that uses that threshold value, then you will need to add a constraint that all threshold events have to specify the same threshold. - When trying to schedule multiple event groups at once, and using restricted events, situations could arise where scheduling fails even though it would be possible. Consider three groups, each with two events. One group has restricted events, the others don't. The two non-restricted groups are scheduled, then one is removed, which happens to occupy the two counters that can't do restricted events. The remaining non-restricted group will not be moved to the non-restricted-capable counters to make room if the restricted group tries to be scheduled. Since thresholds are not yet supported (though you can use the events with a threshold of zero), and threshold events are the only restricted events, this seems like a low priority issue. Which way around are the restrictions? That some events can only be counted on certain counters, or that some counters can only count a subset of the available events? You could look at it either way -- threshold-capable events can only go on counters 0-1, or counters 2-3 can only count non-threshold-capable events. So, it sounds like you have a class of events which are the thresholding events, and two constraints: * at most two events in the thresholding event class * at most four events in total Are there other constraints? Apart from the thresholding events, can any event go on any counter, or can some events only be counted on one particular counter? Did you look at the constraint satisfaction code in the existing perf_event.c and p*-pmu.c? That lets you express both sorts of restrictions and automatically find the best solution (including moving events from one counter to another like you describe). I did look at it -- but I had a hard time understanding it, and went with the simpler approach for now since the constraints are minimal on these chips. I'm open to converting with a little help, if it doesn't add too much complexity or if future chips need it. Well, the first thing is that it separates out the question can the PMU handle this set of events? from the question which counter should each event go on?. The second question is handled by model-specific code, and turns out to be fairly straightforward once you know the answer to the first question is yes. In general you just work from the most constrained events to the least constrained. For the first question, you have to look at the specific hardware details of the PMU and turn its programming model into a set of constraints. The two main sorts of constraints I used were: * Some events require a particular hardware register bitfield to be programmed to a specific value, so if you have two such events, they must require the same value in that bitfield, or else they conflict. There can be several such bitfields, each with an associated class of events. * For some events, there is a limit on how many such events the PMU can support (for example, your threshold events, where you can have at most 2). For each such limit, there is a class of events which are subject to that limit. There is always the all events class, which is subject to the limit imposed by the number of PMCs. Now, obviously you can represent each such constraint with a variable and have a piece of code for each constraint that checks whether it is satisfied or not. What I did with the code for the POWER cpus was to work out a way to represent all the constraint information in a pair of unsigned long values (value and mask). This means that the constraint checking can be done with some simple integer arithmetic, and it can be done by generic code that doesn't need to know what the individual constraints are. If your constraints are just the two listed above (= 2 threshold events, = 4 events total), then doing it the obvious straightforward way is fine. If there are other constraints as well, such as certain events only being available on one specific PMC, then you should consider reusing the constraint checking machinery from ppc64. Paul. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 01/04] powerpc/booke: Introduce new CONFIG options for advanced debug registers
On Mon, Feb 08, 2010 at 02:50:57PM -0700, Dave Kleikamp wrote: powerpc/booke: Introduce new CONFIG options for advanced debug registers From: Dave Kleikamp sha...@linux.vnet.ibm.com Introduce new config options to simplify the ifdefs pertaining to the advanced debug registers for booke and 40x processors: CONFIG_PPC_ADV_DEBUG_REGS - boolean: true for dac-based processors CONFIG_PPC_ADV_DEBUG_IACS - number of IAC registers CONFIG_PPC_ADV_DEBUG_DACS - number of DAC registers CONFIG_PPC_ADV_DEBUG_DVCS - number of DVC registers CONFIG_PPC_ADV_DEBUG_DAC_RANGE - DAC ranges supported Beginning conservatively, since I only have the facilities to test 440 hardware. I believe all 40x and booke platforms support at least 2 IAC and 2 DAC registers. For 440, 4 IAC and 2 DVC registers are enabled, as well as the DAC ranges. Hrm. I'm not entirely convinced there aren't or won't be 44x chips with a different number of regs. Still we fix it up to do runtime checking later. Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com Acked-by: David Gibson d...@au1.ibm.com -- David Gibson| I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc: pair loads and stores in copy_4k_page
A number of our chips like loads and stores to be paired. A small kernel
module testcase shows the improvement of pairing loads and stores in
copy_4k_page:
POWER6: +9%
POWER7: +1.5%
#include linux/module.h
#include linux/mm.h
#define ITERATIONS 1000
static int __init copypage_init(void)
{
struct timespec before, after;
unsigned long i;
struct page *destpage, *srcpage;
char *dest, *src;
destpage = alloc_page(GFP_KERNEL);
srcpage = alloc_page(GFP_KERNEL);
dest = page_address(destpage);
src = page_address(srcpage);
getnstimeofday(before);
for (i = 0; i ITERATIONS; i++)
copy_4K_page(dest, src);
getnstimeofday(after);
free_page((unsigned long)dest);
free_page((unsigned long)src);
printk(KERN_DEBUG copy_4K_page loop took %lu ns\n,
(after.tv_sec - before.tv_sec) * NSEC_PER_SEC +
(after.tv_nsec - before.tv_nsec));
return 0;
}
static void __exit copypage_exit(void)
{
}
module_init(copypage_init)
module_exit(copypage_exit)
MODULE_LICENSE(GPL);
MODULE_AUTHOR(Anton Blanchard);
Signed-off-by: Anton Blanchard an...@samba.org
---
diff --git a/arch/powerpc/lib/copypage_64.S b/arch/powerpc/lib/copypage_64.S
index 75f3267..22b6c7b 100644
--- a/arch/powerpc/lib/copypage_64.S
+++ b/arch/powerpc/lib/copypage_64.S
@@ -43,62 +43,62 @@ END_FTR_SECTION_IFSET(CPU_FTR_CP_USE_DCBTZ)
ld r7,16(r4)
ldu r8,24(r4)
1: std r5,8(r3)
- ld r9,8(r4)
std r6,16(r3)
+ ld r9,8(r4)
ld r10,16(r4)
std r7,24(r3)
- ld r11,24(r4)
std r8,32(r3)
+ ld r11,24(r4)
ld r12,32(r4)
std r9,40(r3)
- ld r5,40(r4)
std r10,48(r3)
+ ld r5,40(r4)
ld r6,48(r4)
std r11,56(r3)
- ld r7,56(r4)
std r12,64(r3)
+ ld r7,56(r4)
ld r8,64(r4)
std r5,72(r3)
- ld r9,72(r4)
std r6,80(r3)
+ ld r9,72(r4)
ld r10,80(r4)
std r7,88(r3)
- ld r11,88(r4)
std r8,96(r3)
+ ld r11,88(r4)
ld r12,96(r4)
std r9,104(r3)
- ld r5,104(r4)
std r10,112(r3)
+ ld r5,104(r4)
ld r6,112(r4)
std r11,120(r3)
- ld r7,120(r4)
stdur12,128(r3)
+ ld r7,120(r4)
ldu r8,128(r4)
bdnz1b
std r5,8(r3)
- ld r9,8(r4)
std r6,16(r3)
+ ld r9,8(r4)
ld r10,16(r4)
std r7,24(r3)
- ld r11,24(r4)
std r8,32(r3)
+ ld r11,24(r4)
ld r12,32(r4)
std r9,40(r3)
- ld r5,40(r4)
std r10,48(r3)
+ ld r5,40(r4)
ld r6,48(r4)
std r11,56(r3)
- ld r7,56(r4)
std r12,64(r3)
+ ld r7,56(r4)
ld r8,64(r4)
std r5,72(r3)
- ld r9,72(r4)
std r6,80(r3)
+ ld r9,72(r4)
ld r10,80(r4)
std r7,88(r3)
- ld r11,88(r4)
std r8,96(r3)
+ ld r11,88(r4)
ld r12,96(r4)
std r9,104(r3)
std r10,112(r3)
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: register long sp asm(r1) incorrect
On Tue, 2010-02-09 at 16:24 +0100, Pavel Machek wrote: ...according to gcc docs, sp should be global, or placement in register is not guaranteed (except at asm boundaries, but there are none). Sorry I'm not sure I grok what you mean. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: pair loads and stores in copy_4k_page
Hi Anton, On Thursday 11 February 2010 15:07:54 Anton Blanchard wrote: A number of our chips like loads and stores to be paired. A small kernel module testcase shows the improvement of pairing loads and stores in copy_4k_page: POWER6: +9% POWER7: +1.5% I just tried this on one of our QS22 cell blades and it seems to cause about half a percent speedup but that looks like it's within the noise of the results that I'm getting. In any case it doesn't look like it has a negative effect for cell. Looks good! Mark ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/6] powerpc: Use lwarx hint in spinlocks
On Wed, Feb 10, 2010 at 09:57:28PM +1100, Anton Blanchard wrote: Recent versions of the PowerPC architecture added a hint bit to the larx instructions to differentiate between an atomic operation and a lock operation: 0 Other programs might attempt to modify the word in storage addressed by EA even if the subsequent Store Conditional succeeds. 1 Other programs will not attempt to modify the word in storage addressed by EA until the program that has acquired the lock performs a subsequent store releasing the lock. To avoid a binutils dependency this patch create macros for the extended lwarx format and uses it in the spinlock code. To test this change I used a simple test case that acquires and releases a global pthread mutex: pthread_mutex_lock(mutex); pthread_mutex_unlock(mutex); On a 32 core POWER6, running 32 test threads we spend almost all our time in the futex spinlock code: 94.37% perf [kernel] [k] ._raw_spin_lock | |--99.95%-- ._raw_spin_lock | | | |--63.29%-- .futex_wake | | | |--36.64%-- .futex_wait_setup Which is a good test for this patch. The results (in lock/unlock operations per second) are: before: 1538203 ops/sec after: 2189219 ops/sec An improvement of 42% A 32 core POWER7 improves even more: before: 1279529 ops/sec after: 2282076 ops/sec An improvement of 78% Cool. How does it go when there are significant amount of instructions between the lock and the unlock? A real(ish) workload, like dbench on ramdisk (which should hit the dcache lock). Signed-off-by: Anton Blanchard an...@samba.org --- v2: We do this only for 64bit until we can verify all 32bit CPUs. Tested so far: 970 (thanks Ben), POWER5, POWER6, POWER7 Still to test: RS64, POWER3, POWER4 Index: powerpc.git/arch/powerpc/include/asm/ppc-opcode.h === --- powerpc.git.orig/arch/powerpc/include/asm/ppc-opcode.h2010-02-10 15:28:58.453072362 +1100 +++ powerpc.git/arch/powerpc/include/asm/ppc-opcode.h 2010-02-10 15:33:08.963071793 +1100 @@ -24,6 +24,7 @@ #define PPC_INST_ISEL_MASK 0xfc3e #define PPC_INST_LSWI0x7c0004aa #define PPC_INST_LSWX0x7c00042a +#define PPC_INST_LWARX 0x7c29 #define PPC_INST_LWSYNC 0x7c2004ac #define PPC_INST_LXVD2X 0x7c000698 #define PPC_INST_MCRXR 0x7c000400 @@ -55,15 +56,28 @@ #define __PPC_RA(a) (((a) 0x1f) 16) #define __PPC_RB(b) (((b) 0x1f) 11) #define __PPC_RS(s) (((s) 0x1f) 21) +#define __PPC_RT(s) __PPC_RS(s) #define __PPC_XS(s) s) 0x1f) 21) | (((s) 0x20) 5)) #define __PPC_T_TLB(t) (((t) 0x3) 21) #define __PPC_WC(w) (((w) 0x3) 21) +/* + * Only use the larx hint bit on 64bit CPUs. Once we verify it doesn't have + * any side effects on all 32bit processors, we can do this all the time. + */ +#ifdef CONFIG_PPC64 +#define __PPC_EH(eh) (((eh) 0x1) 0) +#else +#define __PPC_EH(eh) 0 +#endif /* Deal with instructions that older assemblers aren't aware of */ #define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \ __PPC_RA(a) | __PPC_RB(b)) #define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \ __PPC_RA(a) | __PPC_RB(b)) +#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \ + __PPC_RT(t) | __PPC_RA(a) | \ + __PPC_RB(b) | __PPC_EH(eh)) #define PPC_MSGSND(b)stringify_in_c(.long PPC_INST_MSGSND | \ __PPC_RB(b)) #define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI) Index: powerpc.git/arch/powerpc/include/asm/spinlock.h === --- powerpc.git.orig/arch/powerpc/include/asm/spinlock.h 2010-02-10 15:28:58.473072327 +1100 +++ powerpc.git/arch/powerpc/include/asm/spinlock.h 2010-02-10 15:29:29.454322618 +1100 @@ -27,6 +27,7 @@ #endif #include asm/asm-compat.h #include asm/synch.h +#include asm/ppc-opcode.h #define arch_spin_is_locked(x) ((x)-slock != 0) @@ -60,7 +61,7 @@ static inline unsigned long __arch_spin_ token = LOCK_TOKEN; __asm__ __volatile__( -1: lwarx %0,0,%2\n\ +1: PPC_LWARX(%0,0,%2,1) \n\ cmpwi 0,%0,0\n\ bne-2f\n\ stwcx. %1,0,%2\n\ @@ -186,7 +187,7 @@ static inline long __arch_read_trylock(a long tmp; __asm__ __volatile__( -1: lwarx
Re: [PATCH 6/6] powerpc: Use lwsync for acquire barrier if CPU supports it
On Wed, Feb 10, 2010 at 10:10:25PM +1100, Anton Blanchard wrote: Nick Piggin discovered that lwsync barriers around locks were faster than isync on 970. That was a long time ago and I completely dropped the ball in testing his patches across other ppc64 processors. Turns out the idea helps on other chips. Using a microbenchmark that uses a lot of threads to contend on a global pthread mutex (and therefore a global futex), POWER6 improves 8% and POWER7 improves 2%. I checked POWER5 and while I couldn't measure an improvement, there was no regression. Ah, good to see this one come back. I also tested tbench over localhost btw which actually did show some speedup on the G5. BTW. this was the last thing left: http://www.mail-archive.com/linuxppc-dev@lists.ozlabs.org/msg29738.html Don't know if you took a look at that again, but maybe it's worth looking at. Hmm, we do actually seem to be growing number of smp_mb* calls in core kernel too. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
