[Patch 2/4] PPC64-HWBKPT: Implement hw-breakpoints for PowerPC Book III S
Implement perf-events based hw-breakpoint interfaces for PowerPC Book III S
processors. These interfaces help arbitrate requests from various users and
schedules them as appropriate.
Signed-off-by: K.Prasad pra...@linux.vnet.ibm.com
---
arch/powerpc/Kconfig |1
arch/powerpc/include/asm/cputable.h |4
arch/powerpc/include/asm/hw_breakpoint.h | 49
arch/powerpc/include/asm/processor.h |8
arch/powerpc/kernel/Makefile |1
arch/powerpc/kernel/hw_breakpoint.c | 345 +++
arch/powerpc/kernel/machine_kexec_64.c |3
arch/powerpc/kernel/process.c|6
arch/powerpc/kernel/ptrace.c | 64 +
arch/powerpc/lib/Makefile|1
include/linux/hw_breakpoint.h|1
11 files changed, 483 insertions(+)
Index: linux-2.6.ppc64_test/arch/powerpc/include/asm/hw_breakpoint.h
===
--- /dev/null
+++ linux-2.6.ppc64_test/arch/powerpc/include/asm/hw_breakpoint.h
@@ -0,0 +1,49 @@
+#ifndef _PPC_BOOK3S_64_HW_BREAKPOINT_H
+#define _PPC_BOOK3S_64_HW_BREAKPOINT_H
+
+#ifdef __KERNEL__
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+
+struct arch_hw_breakpoint {
+ u8 len; /* length of the target data symbol */
+ int type;
+ unsigned long address;
+};
+
+#include linux/kdebug.h
+#include asm/reg.h
+#include asm/system.h
+
+static inline int hw_breakpoint_slots(int type)
+{
+ return HBP_NUM;
+}
+struct perf_event;
+struct pmu;
+struct perf_sample_data;
+
+#define HW_BREAKPOINT_ALIGN 0x7
+/* Maximum permissible length of any HW Breakpoint */
+#define HW_BREAKPOINT_LEN 0x8
+
+extern int arch_bp_generic_fields(int type, int *gen_bp_type);
+extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
+extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
+extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
+ unsigned long val, void *data);
+int arch_install_hw_breakpoint(struct perf_event *bp);
+void arch_uninstall_hw_breakpoint(struct perf_event *bp);
+void hw_breakpoint_pmu_read(struct perf_event *bp);
+extern void flush_ptrace_hw_breakpoint(struct task_struct *tsk);
+
+extern struct pmu perf_ops_bp;
+extern void ptrace_triggered(struct perf_event *bp, int nmi,
+ struct perf_sample_data *data, struct pt_regs *regs);
+static inline void hw_breakpoint_disable(void)
+{
+ set_dabr(0);
+}
+
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
+#endif /* __KERNEL__ */
+#endif /* _PPC_BOOK3S_64_HW_BREAKPOINT_H */
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/hw_breakpoint.c
===
--- /dev/null
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/hw_breakpoint.c
@@ -0,0 +1,345 @@
+/*
+ * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
+ * using the CPU's debug registers. Derived from
+ * arch/x86/kernel/hw_breakpoint.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright 2010 IBM Corporation
+ * Author: K.Prasad pra...@linux.vnet.ibm.com
+ *
+ */
+
+#include linux/hw_breakpoint.h
+#include linux/notifier.h
+#include linux/kprobes.h
+#include linux/percpu.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/sched.h
+#include linux/init.h
+#include linux/smp.h
+
+#include asm/hw_breakpoint.h
+#include asm/processor.h
+#include asm/sstep.h
+
+/*
+ * Stores the breakpoints currently in use on each breakpoint address
+ * register for every cpu
+ */
+static DEFINE_PER_CPU(struct perf_event *, bp_per_reg);
+
+/*
+ * Install a perf counter breakpoint.
+ *
+ * We seek a free debug address register and use it for this
+ * breakpoint.
+ *
+ * Atomic: we hold the counter-ctx-lock and we only handle variables
+ * and registers local to this cpu.
+ */
+int arch_install_hw_breakpoint(struct perf_event *bp)
+{
+ struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+ struct perf_event **slot = __get_cpu_var(bp_per_reg);
+
+ *slot = bp;
+
+ /*
+* Do not install DABR values if the instruction must be single-stepped.
+* If so, DABR will be populated in single_step_dabr_instruction().
+
[Patch 3/4] PPC64-HWBKPT: Handle concurrent alignment interrupts
An alignment interrupt may intervene between a DSI/hw-breakpoint exception
and the single-step exception. Enable the alignment interrupt (through
modifications to emulate_single_step()) to notify the single-step exception
handler for proper restoration of hw-breakpoints.
Signed-off-by: K.Prasad pra...@linux.vnet.ibm.com
---
arch/powerpc/kernel/traps.c |7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/traps.c
===
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/traps.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/traps.c
@@ -602,7 +602,7 @@ void RunModeException(struct pt_regs *re
void __kprobes single_step_exception(struct pt_regs *regs)
{
- regs-msr = ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */
+ clear_single_step(regs);
if (notify_die(DIE_SSTEP, single_step, regs, 5,
5, SIGTRAP) == NOTIFY_STOP)
@@ -621,10 +621,7 @@ void __kprobes single_step_exception(str
*/
static void emulate_single_step(struct pt_regs *regs)
{
- if (single_stepping(regs)) {
- clear_single_step(regs);
- _exception(SIGTRAP, regs, TRAP_TRACE, 0);
- }
+ single_step_exception(regs);
}
static inline int __parse_fpscr(unsigned long fpscr)
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Re: [Patch 4/4] PPC64-HWBKPT: Enable hw-breakpoints while handling intervening signals
On Mon, May 24, 2010 at 04:04:19PM +0530, K.Prasad wrote: A signal delivered between a hw_breakpoint_handler() and the single_step_dabr_instruction() will not have the breakpoint active during signal handling (since breakpoint will not be restored through single-stepping due to absence of MSR_SE bit on the signal frame). Enable breakpoints before signal delivery and clear them during sigreturn() syscall. Limitation: Nested hw-breakpoint exceptions (where second exception is raised inside signal context) will cause a 'double-hit' i.e. the first breakpoint exception will be taken twice. I don't think this will actually cause a problem. In the case of a perf_event breakpoint, the semantics are trigger-after-execute, so the first hit won't cause a trigger, and perf_event won't double-count it. In the case of ptrace-style breakpoints, we don't single-step (it's up to the ptracer to do the single-stepping if needed) so the problem doesn't arise. In fact I don't think we even need to do anything on sigreturn. Yes, we are changing the NIP but we are changing it to a previous value as a result of an explicit action by the program, which is a bit different to what signal delivery and ptrace do. On signal delivery I was imagining that we would clear the MSR_SE bit before saving the MSR value in the signal frame, and reinstall the DABR value at the same time, and then essentially forget that we had already hit the breakpoint once and just wait for it to hit again. Paul. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[Patch 4/4] PPC64-HWBKPT: Enable hw-breakpoints while handling intervening signals
A signal delivered between a hw_breakpoint_handler() and the
single_step_dabr_instruction() will not have the breakpoint active during
signal handling (since breakpoint will not be restored through single-stepping
due to absence of MSR_SE bit on the signal frame). Enable breakpoints before
signal delivery and clear them during sigreturn() syscall.
Limitation: Nested hw-breakpoint exceptions (where second exception is raised
inside signal context) will cause a 'double-hit' i.e. the first breakpoint
exception will be taken twice.
Restore hw-breakpoints if the user-context is altered in the signal handler
(causing loss of MSR_SE). Side-effect: 'Double-hit' of breakpoint if the
instruction pointer is unaltered in the new context.
Signed-off-by: K.Prasad pra...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/hw_breakpoint.h |3 +++
arch/powerpc/kernel/hw_breakpoint.c | 28
arch/powerpc/kernel/signal.c |8
arch/powerpc/kernel/signal_32.c | 10 ++
arch/powerpc/kernel/signal_64.c |7 +++
5 files changed, 56 insertions(+)
Index: linux-2.6.ppc64_test/arch/powerpc/include/asm/hw_breakpoint.h
===
--- linux-2.6.ppc64_test.orig/arch/powerpc/include/asm/hw_breakpoint.h
+++ linux-2.6.ppc64_test/arch/powerpc/include/asm/hw_breakpoint.h
@@ -43,6 +43,9 @@ static inline void hw_breakpoint_disable
{
set_dabr(0);
}
+extern void sighandler_install_bp(struct task_struct *tsk);
+extern void sigreturn_uninstall_bp(struct task_struct *tsk);
+extern void thread_change_pc(struct task_struct *tsk, unsigned long msr);
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
#endif /* __KERNEL__ */
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/hw_breakpoint.c
===
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/hw_breakpoint.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/hw_breakpoint.c
@@ -175,6 +175,34 @@ int arch_validate_hwbkpt_settings(struct
return 0;
}
+void sighandler_install_bp(struct task_struct *tsk)
+{
+ struct arch_hw_breakpoint *info;
+
+ if (likely(!tsk-thread.last_hit_ubp))
+ return;
+
+ info = counter_arch_bp(tsk-thread.last_hit_ubp);
+ set_dabr(info-address | info-type | DABR_TRANSLATION);
+}
+
+void sigreturn_uninstall_bp(struct task_struct *tsk)
+{
+ if (unlikely(tsk-thread.last_hit_ubp))
+ set_dabr(0);
+}
+
+void thread_change_pc(struct task_struct *tsk, unsigned long new_msr)
+{
+ /*
+* Do not bother to restore breakpoints if single-stepping is not
+* cleared. single_step_dabr_instruction() will handle it if MSR_SE
+* is set.
+*/
+ if (!(new_msr MSR_SE))
+ sighandler_install_bp(tsk);
+}
+
/*
* Handle debug exception notifications.
*/
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/signal.c
===
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/signal.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/signal.c
@@ -11,6 +11,7 @@
#include linux/tracehook.h
#include linux/signal.h
+#include asm/hw_breakpoint.h
#include asm/uaccess.h
#include asm/unistd.h
@@ -149,6 +150,13 @@ static int do_signal_pending(sigset_t *o
if (current-thread.dabr)
set_dabr(current-thread.dabr);
#endif
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+ /*
+* Re-enable the breakpoints (if it was previously cleared in
+* hw_breakpoint_handler()) for the signal stack.
+*/
+ sighandler_install_bp(current);
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
if (is32) {
if (ka.sa.sa_flags SA_SIGINFO)
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/signal_64.c
===
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/signal_64.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/signal_64.c
@@ -33,6 +33,7 @@
#include asm/cacheflush.h
#include asm/syscalls.h
#include asm/vdso.h
+#include asm/hw_breakpoint.h
#include signal.h
@@ -312,6 +313,9 @@ int sys_swapcontext(struct ucontext __us
|| __copy_to_user(old_ctx-uc_sigmask,
current-blocked, sizeof(sigset_t)))
return -EFAULT;
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+ thread_change_pc(current, new_msr);
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
}
if (new_ctx == NULL)
return 0;
@@ -364,6 +368,9 @@ int sys_rt_sigreturn(unsigned long r3, u
if (__copy_from_user(set, uc-uc_sigmask, sizeof(set)))
goto badframe;
restore_sigmask(set);
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+ sigreturn_uninstall_bp(current);
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
if (restore_sigcontext(regs, NULL, 1, uc-uc_mcontext))
[Patch 0/4] PPC64-HWBKPT: Hardware Breakpoint interfaces - ver XX
Hi All, Here's a quick release of the next version of the patchset with a small, yet significant changelog. Please let me know the comments, if any. Changelog - ver XX (Version XIX: linuxppc-dev ref: 20100524040137.ga20...@in.ibm.com) - Non task-bound breakpoints will only be emulated. Breakpoint will be unregistered with a warning if emulation fails. Thanks, K.Prasad Changelog - ver XIX (Version XVIII: linuxppc-dev ref: 20100512033055.ga6...@in.ibm.com) - Increased coverage of breakpoints during concurrent alignment_exception and signal handling (which previously had 'blind-spots'). - Support for kernel-thread breakpoints and kernel-space breakpoints inside the context of a user-space process. - Patches re-based to commit f4b87dee923342505e1ddba8d34ce9de33e75050, thereby necessitating minor changes to arch_validate_hwbkpt_settings(). Changelog - ver XVIII (Version XVII: linuxppc-dev ref: 20100414034340.ga6...@in.ibm.com) - hw-breakpoint restoration variables are cleaned-up before unregistration through a new function hook arch_unregister_hw_breakpoint(). - emulate_single_step() now notifies DIE_SSTEP to registered handlers; causes single_step_dabr_instruction() to be invoked after alignment_exception. - SIGTRAP is no longer generated for non-ptrace user-space breakpoints. - Slight code restructuring for brevity and style corrections. Changelog - ver XVII (Version XVI: linuxppc-dev ref: 20100330095809.ga14...@in.ibm.com) - CONFIG_HAVE_HW_BREAKPOINT is now used to define the scope of the new code (in lieu of CONFIG_PPC_BOOK3S_64). - CONFIG_HAVE_HW_BREAKPOINT is now dependant upon CONFIG_PERF_EVENTS and CONFIG_PPC_BOOK3S_64 (to overcome build failures under certain configs). - Included a target in arch/powerpc/lib/Makefile to build sstep.o when HAVE_HW_BREAKPOINT. - Added a dummy definition for hw_breakpoint_disable() when !HAVE_HW_BREAKPOINT. - Tested builds under defconfigs for ppc64, cell and g5 (found no patch induced failures). Changelog - ver XVI (Version XV: linuxppc-dev ref: 20100323140639.ga21...@in.ibm.com) - Used a new config option CONFIG_PPC_BOOK3S_64 (in lieu of CONFIG_PPC64/CPU_FTR_HAS_DABR) to limit the scope of the new code. - Disabled breakpoints before kexec of the machine using hw_breakpoint_disable(). - Minor optimisation in exception-64s.S to check for data breakpoint exceptions in DSISR finally (after check for other causes) + changes in code comments and representation of DSISR_DABRMATCH constant. - Rebased to commit ae6be51ed01d6c4aaf249a207b4434bc7785853b of linux-2.6. Changelog - ver XV (Version XIV: linuxppc-dev ref: 20100308181232.ga3...@in.ibm.com) - Additional patch to disable interrupts during data breakpoint exception handling. - Moved HBP_NUM definition to cputable.h under a new CPU_FTR definition (CPU_FTR_HAS_DABR). - Filtering of extraneous exceptions (due to accesses outside symbol length) is by-passed for ptrace requests. - Removed flush_ptrace_hw_breakpoint() from __switch_to() due to incorrect coding placement. - Changes to code comments as per community reviews for previous version. - Minor coding-style changes in hw_breakpoint.c as per review comments. - Re-based to commit ae6be51ed01d6c4aaf249a207b4434bc7785853b of linux-2.6 Changelog - ver XIV (Version XIII: linuxppc-dev ref: 20100215055605.gb3...@in.ibm.com) - Removed the 'name' field from 'struct arch_hw_breakpoint'. - All callback invocations through bp-overflow_handler() are replaced with perf_bp_event(). - Removed the check for pre-existing single-stepping mode in hw_breakpoint_handler() as this check is unreliable while in kernel-space. Side effect of this change is the non-triggering of hw-breakpoints while single-stepping kernel through KGDB or Xmon. - Minor code-cleanups and addition of comments in hw_breakpoint_handler() and single_step_dabr_instruction(). - Re-based to commit 25cf84cf377c0aae5dbcf937ea89bc7893db5176 of linux-2.6 Changelog - ver XIII (Version XII: linuxppc-dev ref: 20100121084640.ga3...@in.ibm.com) - Fixed a bug for user-space breakpoints (triggered following the failure of a breakpoint request). - Re-based on commit 724e6d3fe8003c3f60bf404bf22e4e331327c596 of linux-2.6 Changelog - ver XII (Version XI: linuxppc-dev ref: 20100119091234.ga9...@in.ibm.com) - Unset MSR_SE only if kernel was not previously in single-step mode. - Pre-emption is now enabled before returning from the hw-breakpoint exception handler. - Variables to track the source of single-step exception (breakpoint from kernel, user-space vs single-stepping due to other requests) are added. - Extraneous hw-breakpoint exceptions (due to memory accesses lying outside monitored symbol length) is now done for both kernel and user-space (previously only
[Patch 1/4] Allow arch-specific cleanup before breakpoint unregistration
Certain architectures (such as PowerPC Book III S) have a need to cleanup
data-structures before the breakpoint is unregistered. This patch introduces
an arch-specific hook in release_bp_slot() along with a weak definition in
the form of a stub funciton.
Signed-off-by: K.Prasad pra...@linux.vnet.ibm.com
---
kernel/hw_breakpoint.c | 12
1 file changed, 12 insertions(+)
Index: linux-2.6.ppc64_test/kernel/hw_breakpoint.c
===
--- linux-2.6.ppc64_test.orig/kernel/hw_breakpoint.c
+++ linux-2.6.ppc64_test/kernel/hw_breakpoint.c
@@ -242,6 +242,17 @@ toggle_bp_slot(struct perf_event *bp, bo
}
/*
+ * Function to perform processor-specific cleanup during unregistration
+ */
+__weak void arch_unregister_hw_breakpoint(struct perf_event *bp)
+{
+ /*
+* A weak stub function here for those archs that don't define
+* it inside arch/.../kernel/hw_breakpoint.c
+*/
+}
+
+/*
* Contraints to check before allowing this new breakpoint counter:
*
* == Non-pinned counter == (Considered as pinned for now)
@@ -339,6 +350,7 @@ void release_bp_slot(struct perf_event *
{
mutex_lock(nr_bp_mutex);
+ arch_unregister_hw_breakpoint(bp);
__release_bp_slot(bp);
mutex_unlock(nr_bp_mutex);
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Re: [Patch 2/2] PPC64-HWBKPT: Implement hw-breakpoints for PPC64
On Thu, May 20, 2010 at 11:10:03PM +1000, Paul Mackerras wrote:
On Thu, May 20, 2010 at 09:36:03AM +0530, K.Prasad wrote:
(Had this mail composed along with the patchset...but mail server issues
caused delay in sending this...)
Hi Paul,
While we continue to discuss some of the design decisions, I
thought I'd ready up a patchset to capture the changes we agreed upon to
(lest we miss them). I have sent a new version of the patchset here:
linuxppc-dev message-id: 20100524040137.ga20...@in.ibm.com.
Please see more responses below.
Right. However, the thread is running the signal handler without the
DABR being set, which is unfortunate.
In order to keep the breakpoint active during signal handling, a
PowerPC specific signal handling code, say do_signal_pending() in
arch/powerpc/kernel/signal.c, must be tapped to check for/restore
the breakpoint for the process (if it exists).
What I would suggest is something slightly different: anything that
causes the thread to change where it's executing -- signal delivery,
modification of NIP with ptrace -- should cancel the single-step and
reinstall the breakpoint in the DABR. In other words we just forget
that we hit the breakpoint, and rely on hitting it again if we ever
get back to that instruction. I think that is by far the most
reliable approach.
That means that the hw-breakpoint code needs to export a function
called, say, thread_change_pc(), which is called whenever we're
changing a thread's userspace PC (NIP) value. If the hw-breakpoint
code has put that thread into single-step mode, we cancel the
single-step and if the thread is current, set DABR.
I have made changes to signal-handling code on the suggested lines (as
seen here: linuxppc-dev message-id:20100524040342.ge20...@in.ibm.com)
wherein the debug registers are populated before signal-delivery and
cleaned during signal-return.
However handling of nested interrupts, where second exception is taken
inside the signal handler is still flimsy and the system would experience
two hw-breakpoint exceptions. To overcome the same, we will need a flag in
'struct thread_struct' or perhaps in 'struct arch_hw_breakpoint' to
indicate a breakpoint previously taken in signal-handling context. Given
that the repurcussions of a double-hit are not dangerous, and unsure of
how an addition to thread_struct might be received, I've skipped those
changes for now.
I'm afraid if this is more complexity than we want to handle in the
first patchset. I agree that this will create a 'blind-spot' of code
which cannot not be monitored using breakpoints and may limit debugging
efforts (specially for memory corruption); however suspecting that signal
handlers (especially those that don't return to original instruction)
would be rare, I feel that this could be a 'feature' that can be brought
later-in. What do you think?
I think the thread_change_pc() approach is quite a bit simpler, and I
think it's better to get this right at the outset rather than have it
cause bugs later on, when we've all forgotten all the curly
details. :)
Yes, the details are mostly captured in the latest patchset. Had to make
some 'bold' changes to overcome the issues though :-)
Imagine this scenario: we get the DABR match, set MSR_SE and return to
the task. In the meantime another higher-priority task has become
runnable and our need_resched flag is set, so we call schedule() on
the way back out to usermode. The other task runs and then blocks and
our task gets scheduled again. As part of the context switch,
arch_install_hw_breakpoint() will get called and will set DABR. So
we'll return to usermode with both DABR and MSE_SE set.
I didn't foresee such a possibility. I think this can be handled by
putting a check in arch_install_hw_breakpoint() as shown below:
int arch_install_hw_breakpoint(struct perf_event *bp)
{
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
struct perf_event **slot = __get_cpu_var(bp_per_reg);
*slot = bp;
if (!current-thread.last_hit_ubp)
set_dabr(info-address | info-type | DABR_TRANSLATION);
return 0;
}
Yes, basically, but don't we need to handle per-cpu breakpoints as
well? That is, we only want the extra check if this breakpoint is a
per-task breakpoint. Or am I not seeing enough context here?
Until version XVIII of the patchset, the antiquated notion of user- and
kernel-space still existed to some extent. Through changes made here
(reference: linuxppc-dev message-id: 20100524040418.gf20...@in.ibm.com)
per-task (whose pid 0) and per-cpu breakpoints are suitably identified.
Now, per-task breakpoints can be one of the following
- User-space breakpoints bound to a process 'struct task_struct'.
- Kernel-space breakpoints bound to a process 'struct task_struct'.
- Kernel-thread breakpoint registered through
register_user_hw_breakpoint() and still identified
[PATCH v2] powerpc: Add i8042 keyboard and mouse irq parsing
Currently the irqs for the i8042, which historically provides keyboard and
mouse (aux) support, is hardwired in the driver rather than parsing the
dts. This patch modifies the powerpc legacy IO code to attempt to parse
the device tree for this information, failing back to the hardcoded values
if it fails.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
v2: This patch no longer requires the DTS files to be modified, reading the
interrupts from the current location as suggested by Grant.
arch/powerpc/kernel/setup-common.c | 49 ++--
drivers/input/serio/i8042-io.h |8 ++
2 files changed, 54 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/setup-common.c
b/arch/powerpc/kernel/setup-common.c
index 48f0a00..7f1bb99 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -94,6 +94,10 @@ struct screen_info screen_info = {
.orig_video_points = 16
};
+/* Variables required to store legacy IO irq routing */
+int of_i8042_kbd_irq;
+int of_i8042_aux_irq;
+
#ifdef __DO_IRQ_CANON
/* XXX should go elsewhere eventually */
int ppc_do_canonicalize_irqs;
@@ -558,13 +562,52 @@ void probe_machine(void)
/* Match a class of boards, not a specific device configuration. */
int check_legacy_ioport(unsigned long base_port)
{
- struct device_node *parent, *np = NULL;
+ struct device_node *parent, *np = NULL, *np_aux = NULL;
int ret = -ENODEV;
switch(base_port) {
case I8042_DATA_REG:
- if (!(np = of_find_compatible_node(NULL, NULL, pnpPNP,303)))
- np = of_find_compatible_node(NULL, NULL, pnpPNP,f03);
+ np = of_find_compatible_node(NULL, NULL, pnpPNP,303);
+ if (np) {
+ /* Interrupt routing in parent node */
+ parent = of_get_parent(np);
+ if (parent) {
+ /*
+* Attempt to parse DTS for keyboard irq,
+* fallback to standard.
+*/
+ of_i8042_kbd_irq = irq_of_parse_and_map(parent,
+ 0);
+ if (!of_i8042_kbd_irq)
+ of_i8042_kbd_irq = 1;
+
+ of_node_put(parent);
+ }
+ }
+
+ np_aux = of_find_compatible_node(NULL, NULL, pnpPNP,f03);
+ if (np_aux) {
+ if (!np) {
+ of_node_put(np);
+ np = np_aux;
+ }
+
+ /* Interrupt routing in parent node */
+ parent = of_get_parent(np_aux);
+ if (parent) {
+ /*
+* Attempt to parse DTS for mouse (aux) irq,
+* fallback to standard.
+*/
+ of_i8042_aux_irq = irq_of_parse_and_map(parent,
+ 1);
+ if (!of_i8042_aux_irq)
+ of_i8042_aux_irq = 12;
+
+ of_node_put(parent);
+ }
+ }
+
if (np) {
parent = of_get_parent(np);
of_node_put(np);
diff --git a/drivers/input/serio/i8042-io.h b/drivers/input/serio/i8042-io.h
index 847f4aa..8fc8753 100644
--- a/drivers/input/serio/i8042-io.h
+++ b/drivers/input/serio/i8042-io.h
@@ -19,6 +19,11 @@
* IRQs.
*/
+#if defined(CONFIG_PPC)
+extern int of_i8042_kbd_irq;
+extern int of_i8042_aux_irq;
+#endif
+
#ifdef __alpha__
# define I8042_KBD_IRQ 1
# define I8042_AUX_IRQ (RTC_PORT(0) == 0x170 ? 9 : 12) /* Jensen is special */
@@ -27,6 +32,9 @@
#include asm/irq.h
#elif defined(CONFIG_SH_CAYMAN)
#include asm/irq.h
+#elif defined(CONFIG_PPC)
+#define I8042_KBD_IRQ of_i8042_kbd_irq
+#define I8042_AUX_IRQ of_i8042_aux_irq
#else
# define I8042_KBD_IRQ 1
# define I8042_AUX_IRQ 12
--
Martyn Welch (Principal Software Engineer) | Registered in England and
GE Intelligent Platforms | Wales (3828642) at 100
T +44(0)127322748| Barbirolli Square, Manchester,
E martyn.we...@ge.com| M2 3AB VAT:GB 927559189
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Re: [PATCH v2] powerpc: Add i8042 keyboard and mouse irq parsing
On Mon, May 24, 2010 at 10:25 AM, Martyn Welch martyn.we...@ge.com wrote:
Currently the irqs for the i8042, which historically provides keyboard and
mouse (aux) support, is hardwired in the driver rather than parsing the
dts. This patch modifies the powerpc legacy IO code to attempt to parse
the device tree for this information, failing back to the hardcoded values
if it fails.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
v2: This patch no longer requires the DTS files to be modified, reading the
interrupts from the current location as suggested by Grant.
arch/powerpc/kernel/setup-common.c | 49
++--
drivers/input/serio/i8042-io.h | 8 ++
2 files changed, 54 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/setup-common.c
b/arch/powerpc/kernel/setup-common.c
index 48f0a00..7f1bb99 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -94,6 +94,10 @@ struct screen_info screen_info = {
.orig_video_points = 16
};
+/* Variables required to store legacy IO irq routing */
+int of_i8042_kbd_irq;
+int of_i8042_aux_irq;
+
#ifdef __DO_IRQ_CANON
/* XXX should go elsewhere eventually */
int ppc_do_canonicalize_irqs;
@@ -558,13 +562,52 @@ void probe_machine(void)
/* Match a class of boards, not a specific device configuration. */
int check_legacy_ioport(unsigned long base_port)
{
- struct device_node *parent, *np = NULL;
+ struct device_node *parent, *np = NULL, *np_aux = NULL;
int ret = -ENODEV;
switch(base_port) {
case I8042_DATA_REG:
- if (!(np = of_find_compatible_node(NULL, NULL, pnpPNP,303)))
- np = of_find_compatible_node(NULL, NULL,
pnpPNP,f03);
+ np = of_find_compatible_node(NULL, NULL, pnpPNP,303);
+ if (np) {
+ /* Interrupt routing in parent node */
+ parent = of_get_parent(np);
+ if (parent) {
+ /*
+ * Attempt to parse DTS for keyboard irq,
+ * fallback to standard.
+ */
+ of_i8042_kbd_irq =
irq_of_parse_and_map(parent,
+ 0);
+ if (!of_i8042_kbd_irq)
+ of_i8042_kbd_irq = 1;
+
+ of_node_put(parent);
+ }
+ }
+
+ np_aux = of_find_compatible_node(NULL, NULL, pnpPNP,f03);
+ if (np_aux) {
+ if (!np) {
+ of_node_put(np);
+ np = np_aux;
+ }
+
+ /* Interrupt routing in parent node */
+ parent = of_get_parent(np_aux);
+ if (parent) {
+ /*
+ * Attempt to parse DTS for mouse (aux) irq,
+ * fallback to standard.
+ */
+ of_i8042_aux_irq =
irq_of_parse_and_map(parent,
+ 1);
+ if (!of_i8042_aux_irq)
+ of_i8042_aux_irq = 12;
+
+ of_node_put(parent);
+ }
+ }
+
This seems to be a lot more code that you need. The existing code
already obtains a pointer to the parent node for you. All you really
should need to add is the two calls to irq_of_parse_and_map() for
obtaining the kbd and aux irq numbers.
if (np) {
parent = of_get_parent(np);
of_node_put(np);
diff --git a/drivers/input/serio/i8042-io.h b/drivers/input/serio/i8042-io.h
index 847f4aa..8fc8753 100644
--- a/drivers/input/serio/i8042-io.h
+++ b/drivers/input/serio/i8042-io.h
@@ -19,6 +19,11 @@
* IRQs.
*/
+#if defined(CONFIG_PPC)
+extern int of_i8042_kbd_irq;
+extern int of_i8042_aux_irq;
+#endif
Please fold these two extern definitions into the #elif
defined(CONFIG_PPC) block below.
+
#ifdef __alpha__
# define I8042_KBD_IRQ 1
# define I8042_AUX_IRQ (RTC_PORT(0) == 0x170 ? 9 : 12) /* Jensen is special
*/
@@ -27,6 +32,9 @@
#include asm/irq.h
#elif defined(CONFIG_SH_CAYMAN)
#include asm/irq.h
+#elif defined(CONFIG_PPC)
+#define I8042_KBD_IRQ of_i8042_kbd_irq
+#define I8042_AUX_IRQ of_i8042_aux_irq
#else
# define I8042_KBD_IRQ 1
# define I8042_AUX_IRQ 12
Cheers,
g.
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[PATCH] powerpc/fsl-booke: Fix InstructionTLBError execute permission check
From: Li Yang le...@freescale.com In CONFIG_PTE_64BIT the PTE format has unique permission bits for user and supervisor execute. However on !CONFIG_PTE_64BIT we overload the supervisor bit to imply user execute with _PAGE_USER set. This allows us to use the same permission check mask for user or supervisor code on !CONFIG_PTE_64BIT. However, on CONFIG_PTE_64BIT we map _PAGE_EXEC to _PAGE_BAP_UX so we need a different permission mask based on the fault coming from a kernel address or user space. Without unique permission masks we see issues like the following with modules: Unable to handle kernel paging request for instruction fetch Faulting instruction address: 0xf938d040 Oops: Kernel access of bad area, sig: 11 [#1] Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Jin Qing b24...@freescale.com Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- For 2.6.34 stable commit 78e2e68a2b79f394b7cd61e07987a8a89af907f7 arch/powerpc/kernel/head_fsl_booke.S | 13 ++--- 1 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index 7255265..edd4a57 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -639,6 +639,13 @@ interrupt_base: rlwinm r12,r12,0,16,1 mtspr SPRN_MAS1,r12 + /* Make up the required permissions for kernel code */ +#ifdef CONFIG_PTE_64BIT + li r13,_PAGE_PRESENT | _PAGE_BAP_SX + orisr13,r13,_page_acces...@h +#else + li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC +#endif b 4f /* Get the PGD for the current thread */ @@ -646,15 +653,15 @@ interrupt_base: mfspr r11,SPRN_SPRG_THREAD lwz r11,PGDIR(r11) -4: - /* Make up the required permissions */ + /* Make up the required permissions for user code */ #ifdef CONFIG_PTE_64BIT - li r13,_PAGE_PRESENT | _PAGE_EXEC + li r13,_PAGE_PRESENT | _PAGE_BAP_UX orisr13,r13,_page_acces...@h #else li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC #endif +4: FIND_PTE andc. r13,r13,r11 /* Check permission */ -- 1.6.0.6 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/fsl-booke: Move loadcam_entry back to asm code to fix SMP ftrace
When we build with ftrace enabled its possible that loadcam_entry would
have used the stack pointer (even though the code doesn't need it). We
call loadcam_entry in __secondary_start before the stack is setup. To
ensure that loadcam_entry doesn't use the stack pointer the easiest
solution is to just have it in asm code.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
For 2.6.34 stable commit 78f622377f7d31d988db350a43c5689dd5f31876
arch/powerpc/kernel/asm-offsets.c |8
arch/powerpc/mm/fsl_booke_mmu.c | 25 +++--
arch/powerpc/mm/mmu_decl.h| 10 +-
arch/powerpc/mm/tlb_nohash_low.S | 28
4 files changed, 48 insertions(+), 23 deletions(-)
diff --git a/arch/powerpc/kernel/asm-offsets.c
b/arch/powerpc/kernel/asm-offsets.c
index 957ceb7..0271b58 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -448,6 +448,14 @@ int main(void)
DEFINE(PGD_T_LOG2, PGD_T_LOG2);
DEFINE(PTE_T_LOG2, PTE_T_LOG2);
#endif
+#ifdef CONFIG_FSL_BOOKE
+ DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
+ DEFINE(TLBCAM_MAS0, offsetof(struct tlbcam, MAS0));
+ DEFINE(TLBCAM_MAS1, offsetof(struct tlbcam, MAS1));
+ DEFINE(TLBCAM_MAS2, offsetof(struct tlbcam, MAS2));
+ DEFINE(TLBCAM_MAS3, offsetof(struct tlbcam, MAS3));
+ DEFINE(TLBCAM_MAS7, offsetof(struct tlbcam, MAS7));
+#endif
#ifdef CONFIG_KVM_EXIT_TIMING
DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu,
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index 1ed6b52..cdc7526 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -2,7 +2,7 @@
* Modifications by Kumar Gala (ga...@kernel.crashing.org) to support
* E500 Book E processors.
*
- * Copyright 2004 Freescale Semiconductor, Inc
+ * Copyright 2004,2010 Freescale Semiconductor, Inc.
*
* This file contains the routines for initializing the MMU
* on the 4xx series of chips.
@@ -56,19 +56,13 @@
unsigned int tlbcam_index;
-#define NUM_TLBCAMS(64)
#if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) (CONFIG_LOWMEM_CAM_NUM =
NUM_TLBCAMS)
#error LOWMEM_CAM_NUM must be less than NUM_TLBCAMS
#endif
-struct tlbcam {
- u32 MAS0;
- u32 MAS1;
- unsigned long MAS2;
- u32 MAS3;
- u32 MAS7;
-} TLBCAM[NUM_TLBCAMS];
+#define NUM_TLBCAMS(64)
+struct tlbcam TLBCAM[NUM_TLBCAMS];
struct tlbcamrange {
unsigned long start;
@@ -109,19 +103,6 @@ unsigned long p_mapped_by_tlbcam(phys_addr_t pa)
return 0;
}
-void loadcam_entry(int idx)
-{
- mtspr(SPRN_MAS0, TLBCAM[idx].MAS0);
- mtspr(SPRN_MAS1, TLBCAM[idx].MAS1);
- mtspr(SPRN_MAS2, TLBCAM[idx].MAS2);
- mtspr(SPRN_MAS3, TLBCAM[idx].MAS3);
-
- if (mmu_has_feature(MMU_FTR_BIG_PHYS))
- mtspr(SPRN_MAS7, TLBCAM[idx].MAS7);
-
- asm volatile(isync;tlbwe;isync : : : memory);
-}
-
/*
* Set up one of the I/D BAT (block address translation) register pairs.
* The parameters are not checked; in particular size must be a power
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index eb11d5d..63b84a0 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -144,7 +144,15 @@ extern unsigned long mmu_mapin_ram(unsigned long top);
extern void MMU_init_hw(void);
extern unsigned long mmu_mapin_ram(unsigned long top);
extern void adjust_total_lowmem(void);
-
+extern void loadcam_entry(unsigned int index);
+
+struct tlbcam {
+ u32 MAS0;
+ u32 MAS1;
+ unsigned long MAS2;
+ u32 MAS3;
+ u32 MAS7;
+};
#elif defined(CONFIG_PPC32)
/* anything 32-bit except 4xx or 8xx */
extern void MMU_init_hw(void);
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index e925cb5..cfa7682 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -365,3 +365,31 @@ _GLOBAL(set_context)
#else
#error Unsupported processor type !
#endif
+
+#if defined(CONFIG_FSL_BOOKE)
+/*
+ * extern void loadcam_entry(unsigned int index)
+ *
+ * Load TLBCAM[index] entry in to the L2 CAM MMU
+ */
+_GLOBAL(loadcam_entry)
+ LOAD_REG_ADDR(r4, TLBCAM)
+ mulli r5,r3,TLBCAM_SIZE
+ add r3,r5,r4
+ lwz r4,TLBCAM_MAS0(r3)
+ mtspr SPRN_MAS0,r4
+ lwz r4,TLBCAM_MAS1(r3)
+ mtspr SPRN_MAS1,r4
+ PPC_LL r4,TLBCAM_MAS2(r3)
+ mtspr SPRN_MAS2,r4
+ lwz r4,TLBCAM_MAS3(r3)
+ mtspr SPRN_MAS3,r4
+BEGIN_MMU_FTR_SECTION
+ lwz r4,TLBCAM_MAS7(r3)
+ mtspr SPRN_MAS7,r4
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
+ isync
+ tlbwe
+ isync
+ blr
+#endif
--
1.6.0.6
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[PATCH] powerpc: Fix ioremap_flags() with book3e pte definition
From: Benjamin Herrenschmidt b...@kernel.crashing.org We can't just clear the user read permission in book3e pte, because that will also clear supervisor read permission. This surely isn't desired. Fix the problem by adding the supervisor read back. BenH: Slightly simplified the ifdef and applied to ppc64 too Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org --- For 2.6.34 stable commit 55052eeca6d71d76f7c3f156c0501814d8e5e6d3 arch/powerpc/mm/pgtable_32.c |8 arch/powerpc/mm/pgtable_64.c |8 2 files changed, 16 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c index b9243e7..767b0cf 100644 --- a/arch/powerpc/mm/pgtable_32.c +++ b/arch/powerpc/mm/pgtable_32.c @@ -146,6 +146,14 @@ ioremap_flags(phys_addr_t addr, unsigned long size, unsigned long flags) /* we don't want to let _PAGE_USER and _PAGE_EXEC leak out */ flags = ~(_PAGE_USER | _PAGE_EXEC); +#ifdef _PAGE_BAP_SR + /* _PAGE_USER contains _PAGE_BAP_SR on BookE using the new PTE format +* which means that we just cleared supervisor access... oops ;-) This +* restores it +*/ + flags |= _PAGE_BAP_SR; +#endif + return __ioremap_caller(addr, size, flags, __builtin_return_address(0)); } EXPORT_SYMBOL(ioremap_flags); diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c index d95679a..d050fc8 100644 --- a/arch/powerpc/mm/pgtable_64.c +++ b/arch/powerpc/mm/pgtable_64.c @@ -265,6 +265,14 @@ void __iomem * ioremap_flags(phys_addr_t addr, unsigned long size, /* we don't want to let _PAGE_USER and _PAGE_EXEC leak out */ flags = ~(_PAGE_USER | _PAGE_EXEC); +#ifdef _PAGE_BAP_SR + /* _PAGE_USER contains _PAGE_BAP_SR on BookE using the new PTE format +* which means that we just cleared supervisor access... oops ;-) This +* restores it +*/ + flags |= _PAGE_BAP_SR; +#endif + if (ppc_md.ioremap) return ppc_md.ioremap(addr, size, flags, caller); return __ioremap_caller(addr, size, flags, caller); -- 1.6.0.6 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/3] powerpc/fsl head: move the entry setup code into a seperate file
On Apr 4, 2010, at 3:19 PM, Sebastian Andrzej Siewior wrote: From: Sebastian Andrzej Siewior bige...@linutronix.de This patch only moves the initial entry code which setups the mapping from what ever to KERNELBASE into a seperate file. No code change has been made here. Signed-off-by: Sebastian Andrzej Siewior bige...@linutronix.de --- arch/powerpc/kernel/fsl_booke_entry_mapping.S | 200 + arch/powerpc/kernel/head_fsl_booke.S | 199 + 2 files changed, 201 insertions(+), 198 deletions(-) create mode 100644 arch/powerpc/kernel/fsl_booke_entry_mapping.S applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/3] powerpc/head fsl: fix the case where we are not in the first page
On Apr 4, 2010, at 3:19 PM, Sebastian Andrzej Siewior wrote: From: Sebastian Andrzej Siewior bige...@linutronix.de During boot we change the mapping a few times until we have a defined mapping. During this procedure a small 4KiB mapping is created and after that one a 64MiB. Currently the offset of the 4KiB page in that we run is zero because the complete startup up code is in first page which starts at RPN zero. If the code is recycled and moved to another location then its execution will fail because the start address in 64 MiB mapping is computed wrongly. It does not consider the offset to the page from the begin of the memory. This patch fixes this. Usually (system boot) r25 is zero so this does not change anything unless the code is recycled. Signed-off-by: Sebastian Andrzej Siewior bige...@linutronix.de --- arch/powerpc/kernel/head_fsl_booke.S |1 + 1 files changed, 1 insertions(+), 0 deletions(-) applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 3/3] powerpc/kexec: Add support for FSL-BookE
On Apr 4, 2010, at 3:19 PM, Sebastian Andrzej Siewior wrote: From: Sebastian Andrzej Siewior bige...@linutronix.de This adds support kexec on FSL-BookE where the MMU can not be simply switched off. The code borrows the initial MMU-setup code to create the identical mapping mapping. The only difference to the original boot code is the size of the mapping(s) and the executeable address. The kexec code maps the first 2 GiB of memory in 256 MiB steps. This should work also on e500v1 boxes. SMP support is still not available. Signed-off-by: Sebastian Andrzej Siewior bige...@linutronix.de --- arch/powerpc/Kconfig |2 +- arch/powerpc/include/asm/kexec.h | 13 + arch/powerpc/kernel/fsl_booke_entry_mapping.S | 37 + arch/powerpc/kernel/head_fsl_booke.S |2 + arch/powerpc/kernel/misc_32.S | 17 +++ 5 files changed, 70 insertions(+), 1 deletions(-) applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3 1/5] fsl_msi: fix the conflict of virt_msir's chip_data
On Apr 22, 2010, at 3:31 AM, Li Yang wrote: In fsl_of_msi_probe(), the virt_msir's chip_data have been stored the pointer to struct mpic. We add a struct fsl_msi_cascade_data to store the pointer to struct fsl_msi and msir_index in hanler_data. Otherwise, the pointer to struct mpic will be over-written, and will cause problem when calling eoi() of the irq. Signed-off-by: Zhao Chenhui b26...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- arch/powerpc/sysdev/fsl_msi.c | 33 +++-- 1 files changed, 27 insertions(+), 6 deletions(-) applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3 2/5] fsl_msi: enable msi allocation in all banks
On Apr 22, 2010, at 3:31 AM, Li Yang wrote: Put all fsl_msi banks in a linked list. The list of banks then can be traversed when allocating new msi interrupts. Also fix failing path of fsl_setup_msi_irqs(). Signed-off-by: Zhao Chenhui b26...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- arch/powerpc/sysdev/fsl_msi.c | 14 +++--- arch/powerpc/sysdev/fsl_msi.h |2 ++ 2 files changed, 13 insertions(+), 3 deletions(-) applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3 3/5] fsl_msi: enable msi sharing through AMP OSes
On Apr 22, 2010, at 3:31 AM, Li Yang wrote: Make a single PCIe MSI bank shareable through CAMP OSes. The number of MSI used by each core can be configured by dts file. Signed-off-by: Zhao Chenhui b26...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- arch/powerpc/sysdev/fsl_msi.c |8 +++- 1 files changed, 7 insertions(+), 1 deletions(-) applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3 4/5] mpc8572ds: change camp dtses for MSI sharing
On Apr 22, 2010, at 3:31 AM, Li Yang wrote: Enable the sharing of MSI interrupt through AMP OSes in the mpc8572ds dtses. Signed-off-by: Zhao Chenhui b26...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts | 15 +-- arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts |7 ++- 2 files changed, 15 insertions(+), 7 deletions(-) applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2] powerpc, kdump: Fix race in kdump shutdown
On May 14, 2010, at 12:40 AM, Michael Neuling wrote:
When we are crashing, the crashing/primary CPU IPIs the secondaries to
turn off IRQs, go into real mode and wait in kexec_wait. While this
is happening, the primary tears down all the MMU maps. Unfortunately
the primary doesn't check to make sure the secondaries have entered
real mode before doing this.
On PHYP machines, the secondaries can take a long time shutting down
the IRQ controller as RTAS calls are need. These RTAS calls need to
be serialised which resilts in the secondaries contending in
lock_rtas() and hence taking a long time to shut down.
We've hit this on large POWER7 machines, where some secondaries are
still waiting in lock_rtas(), when the primary tears down the HPTEs.
This patch makes sure all secondaries are in real mode before the
primary tears down the MMU. It uses the new kexec_state entry in the
paca. It times out if the secondaries don't reach real mode after
10sec.
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/kernel/crash.c | 27 +++
1 file changed, 27 insertions(+)
Index: linux-2.6-ozlabs/arch/powerpc/kernel/crash.c
===
--- linux-2.6-ozlabs.orig/arch/powerpc/kernel/crash.c
+++ linux-2.6-ozlabs/arch/powerpc/kernel/crash.c
@@ -162,6 +162,32 @@ static void crash_kexec_prepare_cpus(int
/* Leave the IPI callback set */
}
+/* wait for all the CPUs to hit real mode but timeout if they don't come in
*/
+static void crash_kexec_wait_realmode(int cpu)
+{
+ unsigned int msecs;
+ int i;
+
+ msecs = 1;
+ for (i=0; i NR_CPUS msecs 0; i++) {
+ if (i == cpu)
+ continue;
+
+ while (paca[i].kexec_state KEXEC_STATE_REAL_MODE) {
+ barrier();
+ if (!cpu_possible(i)) {
+ break;
+ }
+ if (!cpu_online(i)) {
+ break;
+ }
+ msecs--;
+ mdelay(1);
+ }
+ }
+ mb();
+}
+
/*
* This function will be called by secondary cpus or by kexec cpu
* if soft-reset is activated to stop some CPUs.
@@ -412,6 +438,7 @@ void default_machine_crash_shutdown(stru
crash_kexec_prepare_cpus(crashing_cpu);
cpu_set(crashing_cpu, cpus_in_crash);
crash_kexec_stop_spus();
should this be
#ifdef CONFIG_PPC_STD_MMU
+ crash_kexec_wait_realmode(crashing_cpu);
#endif
- k
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Re: [PATCH 2/2] powerpc, kdump: Fix race in kdump shutdown
On May 24, 2010, at 2:23 PM, Kumar Gala wrote:
On May 14, 2010, at 12:40 AM, Michael Neuling wrote:
When we are crashing, the crashing/primary CPU IPIs the secondaries to
turn off IRQs, go into real mode and wait in kexec_wait. While this
is happening, the primary tears down all the MMU maps. Unfortunately
the primary doesn't check to make sure the secondaries have entered
real mode before doing this.
On PHYP machines, the secondaries can take a long time shutting down
the IRQ controller as RTAS calls are need. These RTAS calls need to
be serialised which resilts in the secondaries contending in
lock_rtas() and hence taking a long time to shut down.
We've hit this on large POWER7 machines, where some secondaries are
still waiting in lock_rtas(), when the primary tears down the HPTEs.
This patch makes sure all secondaries are in real mode before the
primary tears down the MMU. It uses the new kexec_state entry in the
paca. It times out if the secondaries don't reach real mode after
10sec.
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/kernel/crash.c | 27 +++
1 file changed, 27 insertions(+)
Index: linux-2.6-ozlabs/arch/powerpc/kernel/crash.c
===
--- linux-2.6-ozlabs.orig/arch/powerpc/kernel/crash.c
+++ linux-2.6-ozlabs/arch/powerpc/kernel/crash.c
@@ -162,6 +162,32 @@ static void crash_kexec_prepare_cpus(int
/* Leave the IPI callback set */
}
+/* wait for all the CPUs to hit real mode but timeout if they don't come in
*/
+static void crash_kexec_wait_realmode(int cpu)
+{
+unsigned int msecs;
+int i;
+
+msecs = 1;
+for (i=0; i NR_CPUS msecs 0; i++) {
+if (i == cpu)
+continue;
+
+while (paca[i].kexec_state KEXEC_STATE_REAL_MODE) {
+barrier();
+if (!cpu_possible(i)) {
+break;
+}
+if (!cpu_online(i)) {
+break;
+}
+msecs--;
+mdelay(1);
+}
+}
+mb();
+}
+
/*
* This function will be called by secondary cpus or by kexec cpu
* if soft-reset is activated to stop some CPUs.
@@ -412,6 +438,7 @@ void default_machine_crash_shutdown(stru
crash_kexec_prepare_cpus(crashing_cpu);
cpu_set(crashing_cpu, cpus_in_crash);
crash_kexec_stop_spus();
should this be
#ifdef CONFIG_PPC_STD_MMU
+crash_kexec_wait_realmode(crashing_cpu);
#endif
I'm going to make it CONFIG_PPC_STD_MMU_64 as part of a Kexec book-e patch
- k
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[git pull] Please pull powerpc.git next branch
The following changes since commit 99ec28f183daa450faa7bdad6f932364ae325648: FUJITA Tomonori (1): powerpc: Remove unused 'protect4gb' boot parameter are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git next Andy Fleming (1): powerpc/85xx: Enable support for ports 3 and 4 on 8548 CDS Anton Vorontsov (1): powerpc/fsl-booke: Add hibernation support for FSL BookE processors Haiying Wang (1): powerpc/85xx: Add P1021MDS board support Lan Chunhe-B25806 (1): powerpc/fsl_msi: Add multiple MSI bank support Li Yang (5): powerpc/fsl_msi: fix the conflict of virt_msir's chip_data powerpc/fsl_msi: enable msi allocation in all banks powerpc/fsl_msi: enable msi sharing through AMP OSes powerpc/fsl_msi: add removal path and probe failing path powerpc/85xx: Change MPC8572DS camp dtses for MSI sharing Scott Wood (1): powerpc/e500mc: Implement machine check handler. Sebastian Andrzej Siewior (3): powerpc/fsl-booke: fix the case where we are not in the first page powerpc/fsl-booke: Move the entry setup code into a seperate file powerpc/kexec: Add support for FSL-BookE arch/powerpc/Kconfig |2 +- arch/powerpc/boot/dts/mpc8548cds.dts |4 - arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts | 15 +- arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts |7 +- arch/powerpc/boot/dts/p1021mds.dts | 698 arch/powerpc/include/asm/cputable.h|1 + arch/powerpc/include/asm/kexec.h | 13 + arch/powerpc/include/asm/reg_booke.h | 33 +- arch/powerpc/kernel/Makefile |8 +- arch/powerpc/kernel/cputable.c |2 +- arch/powerpc/kernel/crash.c|4 + arch/powerpc/kernel/fsl_booke_entry_mapping.S | 237 arch/powerpc/kernel/head_fsl_booke.S | 200 +--- arch/powerpc/kernel/misc_32.S | 17 + arch/powerpc/kernel/swsusp_booke.S | 193 +++ arch/powerpc/kernel/traps.c| 88 +++- arch/powerpc/platforms/85xx/mpc85xx_mds.c | 102 - arch/powerpc/sysdev/fsl_msi.c | 117 - arch/powerpc/sysdev/fsl_msi.h |3 + 19 files changed, 1494 insertions(+), 250 deletions(-) create mode 100644 arch/powerpc/boot/dts/p1021mds.dts create mode 100644 arch/powerpc/kernel/fsl_booke_entry_mapping.S create mode 100644 arch/powerpc/kernel/swsusp_booke.S ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
