[PATCH] USB: Fix USB Kconfig dependency problem on 85xx/QoirQ platforms
For FSL PPC SoCs USB_ARCH_HAS_EHCI currently on depends on PPC_83xx. However that excludes support for USB on 85xx & QorIQ devices. Use FSL_SOC insted which will get us 83xx, 85xx, QorIQ, and 5xxx which all have the same USB IP on them. Signed-off-by: Xulei Signed-off-by: Kumar Gala --- drivers/usb/Kconfig |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 6a58cb1..d513d3a 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -57,7 +57,7 @@ config USB_ARCH_HAS_OHCI # some non-PCI hcds implement EHCI config USB_ARCH_HAS_EHCI boolean - default y if PPC_83xx + default y if FSL_SOC default y if SOC_AU1200 default y if ARCH_IXP4XX default y if ARCH_W90X900 -- 1.7.0.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: PCI woes with 2.6.37
On 01/08/2011 06:07 AM, Gary Thomas wrote: On 01/08/2011 12:33 AM, Benjamin Herrenschmidt wrote: On Fri, 2011-01-07 at 16:06 -0700, Gary Thomas wrote: I just tried porting my target (MPC8347) from 2.6.28 (remember that one?) to 2.6.37. Recently I tried this with 2.6.32 without a lot of success, so I thought I'd try the latest :-) The changes are very simple, pretty much just the addition of my 8347 based platform DTS. Sadly, it fails even worse than it did on 2.6.32. For some reason, although everything seems to report that the PCI bus is alive, MEM access fails completely. If I try to access various PCI devices via their memory space (I only have memory peripherals so I can't test IO space access), I get what I assume are BUS timeouts - all 0x My PCI bus is defined in DTS like this: ranges =<0x0200 0x0 0xC000 0xC000 0x0 0x2000 What are the #address-cells and #size-cells properties of the parent of the PCI controller node ? PCI has 3 cells, so that accounts for the first 3 numbers of each of these. That leaves only 3 numbers, so either you have #address-cells = 1 and #size-cells = 2 or the other way around. The first sounds the most plausible and would mean that you are mapping c000 CPU space to c000 PCI space and the window is 512M long. Now of course, one needs to double check that the HW is configured that way (I suppose fsl_pci.c does the configuration based on the "ranges" property but I don't know for sure). So far nothing strikes me as totally odd. 0x0100 0x0 0x 0xB800 0x0 0x0010>; This looks reasonable too with the same assumption as above. PCI: Probing PCI hardware PCI: Scanning PHB /p...@ff008500 PCI: PHB IO resource = -000FF FFf [100] PCI: PHB MEM resource 0 = c000-dFF FFfff [200] Did you edit those by hand ? :-) They look correct tho as far as I can tell. Sorry, I did a little editing of the dump below (to make it more readable, no content changes) and "find & replace" went wild on me :-( It should have read: PCI: PHB MEM resource 0 = c000-dfff [200] PCI: PHB MEM offset = PCI: PHB IO offset = And that too. probe mode: 0 PCI::00:0b.0 Resource 0 1000-1007 [40101] fixup... PCI::00:0b.0 1000-1007 PCI::00:0b.0 Resource 1 1008-100b [40101] fixup... PCI::00:0b.0 1008-100b PCI::00:0b.0 Resource 2 1010-1017 [40101] fixup... PCI::00:0b.0 1010-1017 PCI::00:0b.0 Resource 3 1018-101b [40101] fixup... PCI::00:0b.0 1018-101b PCI::00:0b.0 Resource 4 1020-102f [40101] fixup... PCI::00:0b.0 1020-102f PCI::00:0b.0 Resource 5 0010-001001ff [40200] fixup... PCI::00:0b.0 0010-001001ff PCI::00:0b.0 Resource 6 -0007FF FF [4e200] is unassigned PCI::00:0c.0 Resource 0 0400-07FF FFff [40200] fixup... PCI::00:0c.0 0400-07FF FFff PCI: Fixup bus devices 0 (PHB) PCI: Try to map irq for :00:0b.0... Got one, spec 2 cells (0x0016 0x0008...) on /soc8...@ff00/p...@700 Mapped to linux irq 22 PCI: Try to map irq for :00:0c.0... Got one, spec 2 cells (0x0013 0x0008...) on /soc8...@ff00/p...@700 Mapped to linux irq 19 PCI: Allocating bus resources for :00... PCI: PHB (bus 0) bridge rsrc 0: -000FF FFf [0x100], parent c03b5740 (PCI IO) PCI: PHB (bus 0) bridge rsrc 1: c000-dFF FFfff [0x200], parent c03b5724 (PCI mem) PCI: Allocating :00:0b.0: Resource 0: 1000..1007 [40101] PCI: Allocating :00:0b.0: Resource 1: 1008..100b [40101] PCI: Allocating :00:0b.0: Resource 2: 1010..1017 [40101] PCI: Allocating :00:0b.0: Resource 3: 1018..101b [40101] PCI: Allocating :00:0b.0: Resource 4: 1020..102f [40101] PCI: Allocating :00:0b.0: Resource 5: 0010..001001ff [40200] PCI: Cannot allocate resource region 5 of device :00:0b.0, will remap PCI: Allocating :00:0c.0: Resource 0: 0400..07FF FFff [40200] That's huge, is this your "Coral" framebuffer ? It's clearly using a different address scheme which won't fit, so the kernel decides to remap it, so far so good. Indeed, the frame buffer takes 4MB PCI: Cannot allocate resource region 0 of device :00:0c.0, will remap Reserving legacy ranges for domain Candidate legacy IO: [io 0x-0x0fff] hose mem offset: hose mem res: [mem 0xc000-0xdFF FFfff] Local memory hole: [mem 0xc000-0xc01FF FFf] Now I can't grep the abo
Re: [PATCH] USB: Fix USB Kconfig dependency problem on 85xx/QoirQ platforms
On Jan 10, 2011, at 4:06 AM, Xulei wrote: > For FSL PPC SoCs USB_ARCH_HAS_EHCI currently on depends on PPC_83xx. > However that excludes support for USB on 85xx & QorIQ devices. Use > FSL_SOC insted which will get us 83xx, 85xx, QorIQ, and 5xxx which all > have the same USB IP on them. > > Signed-off-by: Xulei > Signed-off-by: Kumar Gala > --- > drivers/usb/Kconfig |2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig > index 6a58cb1..d513d3a 100644 > --- a/drivers/usb/Kconfig > +++ b/drivers/usb/Kconfig > @@ -57,7 +57,7 @@ config USB_ARCH_HAS_OHCI > # some non-PCI hcds implement EHCI > config USB_ARCH_HAS_EHCI > boolean > - default y if PPC_83xx > + default y if FSL_SOC > default y if SOC_AU1200 > default y if ARCH_IXP4XX > default y if ARCH_W90X900 > -- > 1.7.0.4 This really should have been CC'd to the USB list & maintainer. - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: mpc880 linux-2.6.32 slow running processes
> > Once you have tested it and it works, please send a patch to remove the 8xx > workaround. > Make sure Scott is cc:ed > > I tested linux-2.6.33 on my ppc880 board today, and even without the slowdown.patch applied, the board runs processes with good performance. It really seems that the problem is solved from linux-2.6.33 on. I'm not sure what you mean by sending a patch to remove the workaround. The only thing that I did in the 2.6.32 version was to apply the slowdown.patch attached in the message from Michael. Could you clarify please? Thanks for all the help so far, Rafael ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: mpc880 linux-2.6.32 slow running processes
Rafael Beims wrote on 2011/01/10 17:35:38: > > > > Once you have tested it and it works, please send a patch to remove the 8xx > > workaround. > > Make sure Scott is cc:ed > > > > > > I tested linux-2.6.33 on my ppc880 board today, and even without the > slowdown.patch applied, the board runs processes with good > performance. > It really seems that the problem is solved from linux-2.6.33 on. > > I'm not sure what you mean by sending a patch to remove the > workaround. The only thing that I did in the 2.6.32 version was to > apply the slowdown.patch attached in the message from Michael. > > Could you clarify please? Yes, this part in arch/powerpc/mm/pgtable.c: #ifdef CONFIG_8xx /* On 8xx, cache control instructions (particularly * "dcbst" from flush_dcache_icache) fault as write * operation if there is an unpopulated TLB entry * for the address in question. To workaround that, * we invalidate the TLB here, thus avoiding dcbst * misbehaviour. */ /* 8xx doesn't care about PID, size or ind args */ _tlbil_va(addr, 0, 0, 0); #endif /* CONFIG_8xx */ Should be removed in >= 2.6.33 kernels. My 8xx TLB work fixes this problem more efficiently. Jocke ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 0/4] De-couple sysfs memory directories from memory sections
This is a re-send of the remaining patches that did not make it into the last kernel release for de-coupling sysfs memory directories from memory sections. The first three patches of the previous set went in, and this is the remaining patches that need to be applied. The patches decouple the concept that a single memory section corresponds to a single directory in /sys/devices/system/memory/. On systems with large amounts of memory (1+ TB) there are performance issues related to creating the large number of sysfs directories. For a powerpc machine with 1 TB of memory we are creating 63,000+ directories. This is resulting in boot times of around 45-50 minutes for systems with 1 TB of memory and 8 hours for systems with 2 TB of memory. With this patch set applied I am now seeing boot times of 5 minutes or less. The root of this issue is in sysfs directory creation. Every time a directory is created a string compare is done against all sibling directories to ensure we do not create duplicates. The list of directory nodes in sysfs is kept as an unsorted list which results in this being an exponentially longer operation as the number of directories are created. The solution solved by this patch set is to allow a single directory in sysfs to span multiple memory sections. This is controlled by an optional architecturally defined function memory_block_size_bytes(). The default definition of this routine returns a memory block size equal to the memory section size. This maintains the current layout of sysfs memory directories as it appears to userspace to remain the same as it is today. For architectures that define their own version of this routine, as is done for powerpc and x86 in this patchset, the view in userspace would change such that each memoryXXX directory would span multiple memory sections. The number of sections spanned would depend on the value reported by memory_block_size_bytes. -Nathan Fontenot ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/4] allow memory blocks to span multiple memory sections
Update the memory sysfs code such that each sysfs memory directory is now considered a memory block that can span multiple memory sections per memory block. The default size of each memory block is SECTION_SIZE_BITS to maintain the current behavior of having a single memory section per memory block (i.e. one sysfs directory per memory section). For architectures that want to have memory blocks span multiple memory sections they need only define their own memory_block_size_bytes() routine. Update the memory hotplug documentation to reflect the new behaviors of memory blocks reflected in sysfs. Signed-off-by: Nathan Fontenot Reviewed-by: Robin Holt Reviewed-by: KAMEZAWA Hiroyuki --- Documentation/memory-hotplug.txt | 47 +++ drivers/base/memory.c| 155 +++ 2 files changed, 139 insertions(+), 63 deletions(-) Index: linux-2.6/Documentation/memory-hotplug.txt === --- linux-2.6.orig/Documentation/memory-hotplug.txt 2011-01-05 10:08:16.0 -0600 +++ linux-2.6/Documentation/memory-hotplug.txt 2011-01-05 10:17:37.0 -0600 @@ -126,36 +126,51 @@ config options. 4 sysfs files for memory hotplug -All sections have their device information under /sys/devices/system/memory as +All sections have their device information in sysfs. Each section is part of +a memory block under /sys/devices/system/memory as /sys/devices/system/memory/memoryXXX -(XXX is section id.) +(XXX is the section id.) -Now, XXX is defined as start_address_of_section / section_size. +Now, XXX is defined as (start_address_of_section / section_size) of the first +section contained in the memory block. The files 'phys_index' and +'end_phys_index' under each directory report the beginning and end section id's +for the memory block covered by the sysfs directory. It is expected that all +memory sections in this range are present and no memory holes exist in the +range. Currently there is no way to determine if there is a memory hole, but +the existence of one should not affect the hotplug capabilities of the memory +block. For example, assume 1GiB section size. A device for a memory starting at 0x1 is /sys/device/system/memory/memory4 (0x1 / 1Gib = 4) This device covers address range [0x1 ... 0x14000) -Under each section, you can see 4 files. +Under each section, you can see 4 or 5 files, the end_phys_index file being +a recent addition and not present on older kernels. -/sys/devices/system/memory/memoryXXX/phys_index +/sys/devices/system/memory/memoryXXX/start_phys_index +/sys/devices/system/memory/memoryXXX/end_phys_index /sys/devices/system/memory/memoryXXX/phys_device /sys/devices/system/memory/memoryXXX/state /sys/devices/system/memory/memoryXXX/removable -'phys_index' : read-only and contains section id, same as XXX. -'state' : read-write - at read: contains online/offline state of memory. - at write: user can specify "online", "offline" command -'phys_device': read-only: designed to show the name of physical memory device. - This is not well implemented now. -'removable' : read-only: contains an integer value indicating - whether the memory section is removable or not - removable. A value of 1 indicates that the memory - section is removable and a value of 0 indicates that - it is not removable. +'phys_index' : read-only and contains section id of the first section + in the memory block, same as XXX. +'end_phys_index' : read-only and contains section id of the last section + in the memory block. +'state' : read-write +at read: contains online/offline state of memory. +at write: user can specify "online", "offline" command +which will be performed on al sections in the block. +'phys_device' : read-only: designed to show the name of physical memory +device. This is not well implemented now. +'removable' : read-only: contains an integer value indicating +whether the memory block is removable or not +removable. A value of 1 indicates that the memory +block is removable and a value of 0 indicates that +it is not removable. A memory block is removable only if +every section in the block is removable. NOTE: These directories/files appear after physical memory hotplug phase. Index: linux-2.6/drivers/base/memory.c === --- linux-2.6.orig/drivers/base/memory.c2011-01-05 10:08:16.0 -0600 +++ linux-2.6/drivers/base/memory.c 2011-01-05 10:17:37.0 -0600 @@
[PATCH 2/4] Update phys_index to [start|end]_section_nr
Update the 'phys_index' property of a the memory_block struct to be
called start_section_nr, and add a end_section_nr property. The
data tracked here is the same but the updated naming is more in line
with what is stored here, namely the first and last section number
that the memory block spans.
The names presented to userspace remain the same, phys_index for
start_section_nr and end_phys_index for end_section_nr, to avoid breaking
anything in userspace.
This also updates the node sysfs code to be aware of the new capability for
a memory block to contain multiple memory sections and be aware of the memory
block structure name changes (start_section_nr). This requires an additional
parameter to unregister_mem_sect_under_nodes so that we know which memory
section of the memory block to unregister.
Signed-off-by: Nathan Fontenot
Reviewed-by: Robin Holt
Reviewed-by: KAMEZAWA Hiroyuki
---
drivers/base/memory.c | 41 +++--
drivers/base/node.c| 12
include/linux/memory.h |3 ++-
include/linux/node.h |6 --
4 files changed, 45 insertions(+), 17 deletions(-)
Index: linux-2.6/drivers/base/memory.c
===
--- linux-2.6.orig/drivers/base/memory.c2011-01-05 10:17:37.0
-0600
+++ linux-2.6/drivers/base/memory.c 2011-01-05 10:17:46.0 -0600
@@ -97,7 +97,7 @@ int register_memory(struct memory_block
int error;
memory->sysdev.cls = &memory_sysdev_class;
- memory->sysdev.id = memory->phys_index / sections_per_block;
+ memory->sysdev.id = memory->start_section_nr / sections_per_block;
error = sysdev_register(&memory->sysdev);
return error;
@@ -138,12 +138,26 @@ static unsigned long get_memory_block_si
* uses.
*/
-static ssize_t show_mem_phys_index(struct sys_device *dev,
+static ssize_t show_mem_start_phys_index(struct sys_device *dev,
struct sysdev_attribute *attr, char *buf)
{
struct memory_block *mem =
container_of(dev, struct memory_block, sysdev);
- return sprintf(buf, "%08lx\n", mem->phys_index / sections_per_block);
+ unsigned long phys_index;
+
+ phys_index = mem->start_section_nr / sections_per_block;
+ return sprintf(buf, "%08lx\n", phys_index);
+}
+
+static ssize_t show_mem_end_phys_index(struct sys_device *dev,
+ struct sysdev_attribute *attr, char *buf)
+{
+ struct memory_block *mem =
+ container_of(dev, struct memory_block, sysdev);
+ unsigned long phys_index;
+
+ phys_index = mem->end_section_nr / sections_per_block;
+ return sprintf(buf, "%08lx\n", phys_index);
}
/*
@@ -158,7 +172,7 @@ static ssize_t show_mem_removable(struct
container_of(dev, struct memory_block, sysdev);
for (i = 0; i < sections_per_block; i++) {
- pfn = section_nr_to_pfn(mem->phys_index + i);
+ pfn = section_nr_to_pfn(mem->start_section_nr + i);
ret &= is_mem_section_removable(pfn, PAGES_PER_SECTION);
}
@@ -275,14 +289,15 @@ static int memory_block_change_state(str
mem->state = MEM_GOING_OFFLINE;
for (i = 0; i < sections_per_block; i++) {
- ret = memory_section_action(mem->phys_index + i, to_state);
+ ret = memory_section_action(mem->start_section_nr + i,
+ to_state);
if (ret)
break;
}
if (ret) {
for (i = 0; i < sections_per_block; i++)
- memory_section_action(mem->phys_index + i,
+ memory_section_action(mem->start_section_nr + i,
from_state_req);
mem->state = from_state_req;
@@ -330,7 +345,8 @@ static ssize_t show_phys_device(struct s
return sprintf(buf, "%d\n", mem->phys_device);
}
-static SYSDEV_ATTR(phys_index, 0444, show_mem_phys_index, NULL);
+static SYSDEV_ATTR(phys_index, 0444, show_mem_start_phys_index, NULL);
+static SYSDEV_ATTR(end_phys_index, 0444, show_mem_end_phys_index, NULL);
static SYSDEV_ATTR(state, 0644, show_mem_state, store_mem_state);
static SYSDEV_ATTR(phys_device, 0444, show_phys_device, NULL);
static SYSDEV_ATTR(removable, 0444, show_mem_removable, NULL);
@@ -522,17 +538,21 @@ static int init_memory_block(struct memo
return -ENOMEM;
scn_nr = __section_nr(section);
- mem->phys_index = base_memory_block_id(scn_nr) * sections_per_block;
+ mem->start_section_nr =
+ base_memory_block_id(scn_nr) * sections_per_block;
+ mem->end_section_nr = mem->start_section_nr + sections_per_block - 1;
mem->state = state;
mem->section_count++;
mutex_init(&mem->state_mutex);
- start_pfn = section_nr_to_pfn(mem->phys_index);
[PATCH 3/4] Define memory_block_size_bytes for powerpc/pseries
Define a version of memory_block_size_bytes() for powerpc/pseries such that
a memory block spans an entire lmb.
Signed-off-by: Nathan Fontenot
Reviewed-by: Robin Holt
---
arch/powerpc/platforms/pseries/hotplug-memory.c | 66 +++-
1 file changed, 53 insertions(+), 13 deletions(-)
Index: linux-2.6/arch/powerpc/platforms/pseries/hotplug-memory.c
===
--- linux-2.6.orig/arch/powerpc/platforms/pseries/hotplug-memory.c
2011-01-05 10:08:14.0 -0600
+++ linux-2.6/arch/powerpc/platforms/pseries/hotplug-memory.c 2011-01-05
10:17:49.0 -0600
@@ -17,6 +17,54 @@
#include
#include
+static unsigned long get_memblock_size(void)
+{
+ struct device_node *np;
+ unsigned int memblock_size = 0;
+
+ np = of_find_node_by_path("/ibm,dynamic-reconfiguration-memory");
+ if (np) {
+ const unsigned long *size;
+
+ size = of_get_property(np, "ibm,lmb-size", NULL);
+ memblock_size = size ? *size : 0;
+
+ of_node_put(np);
+ } else {
+ unsigned int memzero_size = 0;
+ const unsigned int *regs;
+
+ np = of_find_node_by_path("/mem...@0");
+ if (np) {
+ regs = of_get_property(np, "reg", NULL);
+ memzero_size = regs ? regs[3] : 0;
+ of_node_put(np);
+ }
+
+ if (memzero_size) {
+ /* We now know the size of mem...@0, use this to find
+* the first memoryblock and get its size.
+*/
+ char buf[64];
+
+ sprintf(buf, "/mem...@%x", memzero_size);
+ np = of_find_node_by_path(buf);
+ if (np) {
+ regs = of_get_property(np, "reg", NULL);
+ memblock_size = regs ? regs[3] : 0;
+ of_node_put(np);
+ }
+ }
+ }
+
+ return memblock_size;
+}
+
+unsigned long memory_block_size_bytes(void)
+{
+ return get_memblock_size();
+}
+
static int pseries_remove_memblock(unsigned long base, unsigned int
memblock_size)
{
unsigned long start, start_pfn;
@@ -127,30 +175,22 @@ static int pseries_add_memory(struct dev
static int pseries_drconf_memory(unsigned long *base, unsigned int action)
{
- struct device_node *np;
- const unsigned long *lmb_size;
+ unsigned long memblock_size;
int rc;
- np = of_find_node_by_path("/ibm,dynamic-reconfiguration-memory");
- if (!np)
+ memblock_size = get_memblock_size();
+ if (!memblock_size)
return -EINVAL;
- lmb_size = of_get_property(np, "ibm,lmb-size", NULL);
- if (!lmb_size) {
- of_node_put(np);
- return -EINVAL;
- }
-
if (action == PSERIES_DRCONF_MEM_ADD) {
- rc = memblock_add(*base, *lmb_size);
+ rc = memblock_add(*base, memblock_size);
rc = (rc < 0) ? -EINVAL : 0;
} else if (action == PSERIES_DRCONF_MEM_REMOVE) {
- rc = pseries_remove_memblock(*base, *lmb_size);
+ rc = pseries_remove_memblock(*base, memblock_size);
} else {
rc = -EINVAL;
}
- of_node_put(np);
return rc;
}
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[PATCH 4/4] Define memory_block_size_bytes for x86_64 with CONFIG_X86_UV defined
Define a version of memory_block_size_bytes for x86_64 when CONFIG_X86_UV is
set.
Signed-off-by: Robin Holt
Signed-off-by: Jack Steiner
Signed-off-by: Nathan Fontenot
---
arch/x86/mm/init_64.c | 14 ++
1 file changed, 14 insertions(+)
Index: linux-2.6/arch/x86/mm/init_64.c
===
--- linux-2.6.orig/arch/x86/mm/init_64.c2011-01-05 10:08:13.0
-0600
+++ linux-2.6/arch/x86/mm/init_64.c 2011-01-05 10:17:51.0 -0600
@@ -51,6 +51,7 @@
#include
#include
#include
+#include
static int __init parse_direct_gbpages_off(char *arg)
{
@@ -908,6 +909,19 @@ const char *arch_vma_name(struct vm_area
return NULL;
}
+#ifdef CONFIG_X86_UV
+#define MIN_MEMORY_BLOCK_SIZE (1 << SECTION_SIZE_BITS)
+
+unsigned long memory_block_size_bytes(void)
+{
+ if (is_uv_system()) {
+ printk(KERN_INFO "UV: memory block size 2GB\n");
+ return 2UL * 1024 * 1024 * 1024;
+ }
+ return MIN_MEMORY_BLOCK_SIZE;
+}
+#endif
+
#ifdef CONFIG_SPARSEMEM_VMEMMAP
/*
* Initialise the sparsemem vmemmap using huge-pages at the PMD level.
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Re: [PATCH 0/4] De-couple sysfs memory directories from memory sections
On Mon, Jan 10, 2011 at 12:08:56PM -0600, Nathan Fontenot wrote: > This is a re-send of the remaining patches that did not make it > into the last kernel release for de-coupling sysfs memory > directories from memory sections. The first three patches of the > previous set went in, and this is the remaining patches that > need to be applied. Well, it's a bit late right now, as we are merging stuff that is already in our trees, and we are busy with that, so this is likely to be ignored until after .38-rc1 is out. So, care to resend this after .38-rc1 is out so people can pay attention to it? > The root of this issue is in sysfs directory creation. Every time > a directory is created a string compare is done against all sibling > directories to ensure we do not create duplicates. The list of > directory nodes in sysfs is kept as an unsorted list which results > in this being an exponentially longer operation as the number of > directories are created. Are you sure this is still an issue? I thought we solved this last kernel or so with a simple patch? thanks, greg k-h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 0/4] De-couple sysfs memory directories from memory sections
On 01/10/2011 12:44 PM, Greg KH wrote: > On Mon, Jan 10, 2011 at 12:08:56PM -0600, Nathan Fontenot wrote: >> This is a re-send of the remaining patches that did not make it >> into the last kernel release for de-coupling sysfs memory >> directories from memory sections. The first three patches of the >> previous set went in, and this is the remaining patches that >> need to be applied. > > Well, it's a bit late right now, as we are merging stuff that is already > in our trees, and we are busy with that, so this is likely to be ignored > until after .38-rc1 is out. > > So, care to resend this after .38-rc1 is out so people can pay attention > to it? I was afraid of this. I didn't get a chance to get it out sooner but thought I would send it out anyway. > > >> The root of this issue is in sysfs directory creation. Every time >> a directory is created a string compare is done against all sibling >> directories to ensure we do not create duplicates. The list of >> directory nodes in sysfs is kept as an unsorted list which results >> in this being an exponentially longer operation as the number of >> directories are created. > > Are you sure this is still an issue? I thought we solved this last > kernel or so with a simple patch? I'll go back and look at this again. thanks, -Nathan ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 0/4] De-couple sysfs memory directories from memory sections
> >> The root of this issue is in sysfs directory creation. Every time > >> a directory is created a string compare is done against all sibling > >> directories to ensure we do not create duplicates. The list of > >> directory nodes in sysfs is kept as an unsorted list which results > >> in this being an exponentially longer operation as the number of > >> directories are created. > > > > Are you sure this is still an issue? I thought we solved this last > > kernel or so with a simple patch? > > I'll go back and look at this again. What I recall fixing is the symbolic linking from the node* to the memory section. In that case, we cached the most recent mem section and since they always were added sequentially, the cache saved a rescan. Of course, I could be remembering something completely unrelated. Robin ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 00/13] powerpc: Backport 8xx TLB to 2.4
This is a backport from 2.6 which I did to overcome 8xx CPU bugs. 8xx does not update the DAR register when taking a TLB error caused by dcbX and icbi insns which makes it very tricky to use these insns. Also the dcbst wrongly sets the the store bit when faulting into DTLB error. A few more bugs very found during development. I know 2.4 is in strict maintenance mode and 8xx is obsolete but as it is still in use I wanted 8xx to age with grace. Joakim Tjernlund (13): 8xx: Use a macro to simpliy CPU6 errata code. 8xx: Tag DAR with 0x00f0 to catch buggy instructions. 8xx: invalidate non present TLBs 8xx: Fix CONFIG_PIN_TLB 8xx: Update TLB asm so it behaves as linux mm expects. 8xx: Always pin kernel instruction TLB 8xx: Fixup DAR from buggy dcbX instructions. 8xx: CPU6 errata make DTLB error too big to fit. 8xx: Add missing Guarded setting in DTLB Error. 8xx: Restore _PAGE_WRITETHRU 8xx: start using dcbX instructions in various copy routines 8xx: Optimize ITLBMiss handler. 8xx: Optimize TLB Miss handlers arch/ppc/kernel/head_8xx.S | 364 ++-- arch/ppc/kernel/misc.S | 18 --- arch/ppc/lib/string.S | 17 -- arch/ppc/mm/fault.c|8 +- include/asm-ppc/pgtable.h | 16 +- 5 files changed, 266 insertions(+), 157 deletions(-) -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 01/13] 8xx: Use a macro to simpliy CPU6 errata code.
Signed-off-by: Joakim Tjernlund --- arch/ppc/kernel/head_8xx.S | 84 +++ 1 files changed, 22 insertions(+), 62 deletions(-) diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index f9a30f3..ba05a57 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -31,6 +31,15 @@ #include #include "ppc_defs.h" +/* Macro to make the code more readable. */ +#ifdef CONFIG_8xx_CPU6 + #define DO_8xx_CPU6(val, reg) \ + li reg, val; \ + stw reg, 12(r0); \ + lwz reg, 12(r0); +#else + #define DO_8xx_CPU6(val, reg) +#endif .text .globl _stext _stext: @@ -310,20 +319,14 @@ SystemCall: InstructionTLBMiss: #ifdef CONFIG_8xx_CPU6 stw r3, 8(r0) - li r3, 0x3f80 - stw r3, 12(r0) - lwz r3, 12(r0) #endif + DO_8xx_CPU6(0x3f80, r3) mtspr M_TW, r20 /* Save a couple of working registers */ mfcrr20 stw r20, 0(r0) stw r21, 4(r0) mfspr r20, SRR0 /* Get effective address of fault */ -#ifdef CONFIG_8xx_CPU6 - li r3, 0x3780 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x3780, r3) mtspr MD_EPN, r20 /* Have to use MD_EPN for walk, MI_EPN can't */ mfspr r20, M_TWB /* Get level 1 table entry address */ @@ -345,17 +348,9 @@ InstructionTLBMiss: tophys(r21,r21) ori r21,r21,1 /* Set valid bit */ beq-2f /* If zero, don't try to find a pte */ -#ifdef CONFIG_8xx_CPU6 - li r3, 0x2b80 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x2b80, r3) mtspr MI_TWC, r21 /* Set segment attributes */ -#ifdef CONFIG_8xx_CPU6 - li r3, 0x3b80 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x3b80, r3) mtspr MD_TWC, r21 /* Load pte table base address */ mfspr r21, MD_TWC /* and get the pte address */ lwz r20, 0(r21) /* Get the pte */ @@ -371,12 +366,7 @@ InstructionTLBMiss: */ 2: li r21, 0x00f0 rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */ - -#ifdef CONFIG_8xx_CPU6 - li r3, 0x2d80 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x2d80, r3) mtspr MI_RPN, r20 /* Update TLB entry */ mfspr r20, M_TW /* Restore registers */ @@ -392,10 +382,8 @@ InstructionTLBMiss: DataStoreTLBMiss: #ifdef CONFIG_8xx_CPU6 stw r3, 8(r0) - li r3, 0x3f80 - stw r3, 12(r0) - lwz r3, 12(r0) #endif + DO_8xx_CPU6(0x3f80, r3) mtspr M_TW, r20 /* Save a couple of working registers */ mfcrr20 stw r20, 0(r0) @@ -419,11 +407,7 @@ DataStoreTLBMiss: tophys(r21, r21) ori r21, r21, 1 /* Set valid bit in physical L2 page */ beq-2f /* If zero, don't try to find a pte */ -#ifdef CONFIG_8xx_CPU6 - li r3, 0x3b80 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x3b80, r3) mtspr MD_TWC, r21 /* Load pte table base address */ mfspr r20, MD_TWC /* and get the pte address */ lwz r20, 0(r20) /* Get the pte */ @@ -435,11 +419,7 @@ DataStoreTLBMiss: * above. */ rlwimi r21, r20, 0, 27, 27 -#ifdef CONFIG_8xx_CPU6 - li r3, 0x3b80 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x3b80, r3) mtspr MD_TWC, r21 mfspr r21, MD_TWC /* get the pte address again */ @@ -454,12 +434,7 @@ DataStoreTLBMiss: */ 2: li r21, 0x00f0 rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */ - -#ifdef CONFIG_8xx_CPU6 - li r3, 0x3d80 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x3d80, r3) mtspr MD_RPN, r20 /* Update TLB entry */ mfspr r20, M_TW /* Restore registers */ @@ -491,10 +466,8 @@ InstructionTLBError: DataTLBError: #ifdef CONFIG_8xx_CPU6 stw r3, 8(r0) - li r3, 0x3f80 - stw r3, 12(r0) - lwz r3, 12(r0) #endif + DO_8xx_CPU6(0x3f80, r3) mtspr M_TW, r20 /* Save a couple of working registers */ mfcrr20 stw r20, 0(r0) @@ -527,11 +500,7 @@ DataTLBError: ori r21, r21, MD_EVALID mfspr r20, M_CASID rlwimi r21, r20, 0, 28, 31 -#ifdef CONFIG_8xx_CPU6 - li r3, 0x3780 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x3780, r3) mtspr MD_EPN, r21 mfspr r20, M_TWB /* Get level 1 table entry address */ @@ -553,11 +522,7 @@ DataTLBError: */ tophys(r21, r21)
[PATCH 02/13] 8xx: Tag DAR with 0x00f0 to catch buggy instructions.
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they cause a DTLB Error. Dectect this by tagging DAR with 0x00f0 at every exception exit that modifies DAR. This also fixes MachineCheck to pass DAR and DSISR as well. Signed-off-by: Joakim Tjernlund --- arch/ppc/kernel/head_8xx.S | 18 +- 1 files changed, 17 insertions(+), 1 deletions(-) diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index ba05a57..57858ce 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -197,7 +197,17 @@ label: \ STD_EXCEPTION(0x100, Reset, UnknownException) /* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) + . = 0x200 +MachineCheck: + EXCEPTION_PROLOG + mfspr r20,DSISR + stw r20,_DSISR(r21) + mfspr r20,DAR + stw r20,_DAR(r21) + li r20,0x00f0 + mtspr DAR,r20 /* Tag DAR */ + addir3,r1,STACK_FRAME_OVERHEAD + FINISH_EXCEPTION(MachineCheckException) /* Data access exception. * This is "never generated" by the MPC8xx. We jump to it for other @@ -211,6 +221,8 @@ DataAccess: mr r5,r20 mfspr r4,DAR stw r4,_DAR(r21) + li r20,0x00f0 + mtspr DAR,r20 /* Tag DAR */ addir3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ @@ -249,6 +261,8 @@ Alignment: EXCEPTION_PROLOG mfspr r4,DAR stw r4,_DAR(r21) + li r20,0x00f0 + mtspr DAR,r20 /* Tag DAR */ mfspr r5,DSISR stw r5,_DSISR(r21) addir3,r1,STACK_FRAME_OVERHEAD @@ -433,6 +447,7 @@ DataStoreTLBMiss: * of the MMU. */ 2: li r21, 0x00f0 + mtspr DAR, r21/* Tag DAR */ rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */ DO_8xx_CPU6(0x3d80, r3) mtspr MD_RPN, r20 /* Update TLB entry */ @@ -543,6 +558,7 @@ DataTLBError: * of the MMU. */ li r21, 0x00f0 + mtspr DAR, r21/* Tag DAR */ rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */ DO_8xx_CPU6(0x3d80, r3) mtspr MD_RPN, r20 /* Update TLB entry */ -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 03/13] 8xx: invalidate non present TLBs
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separaly as linux mm don't.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/mm/fault.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/ppc/mm/fault.c b/arch/ppc/mm/fault.c
index 9d3ce2d..874005a 100644
--- a/arch/ppc/mm/fault.c
+++ b/arch/ppc/mm/fault.c
@@ -116,7 +116,13 @@ void do_page_fault(struct pt_regs *regs, unsigned long
address,
else
is_write = error_code & 0x0200;
#endif /* CONFIG_4xx || CONFIG_BOOKE */
-
+#if defined(CONFIG_8xx)
+ /* 8xx does no invalidate TLBs that are ~PRESENT,
+* do it here.
+*/
+ if (error_code & 0x4000)
+ _tlbie(address);
+#endif
#if defined(CONFIG_XMON) || defined(CONFIG_KGDB)
if (debugger_fault_handler && regs->trap == 0x300) {
debugger_fault_handler(regs);
--
1.7.3.4
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[PATCH 04/13] 8xx: Fix CONFIG_PIN_TLB
The wrong register was loaded into MD_RPN. Signed-off-by: Joakim Tjernlund --- arch/ppc/kernel/head_8xx.S |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index 57858ce..5269e5b 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -840,13 +840,13 @@ initial_mmu: mtspr MD_TWC, r9 li r11, MI_BOOTINIT/* Create RPN for address 0 */ addis r11, r11, 0x0080/* Add 8M */ - mtspr MD_RPN, r8 + mtspr MD_RPN, r11 addis r8, r8, 0x0080 /* Add 8M */ mtspr MD_EPN, r8 mtspr MD_TWC, r9 addis r11, r11, 0x0080/* Add 8M */ - mtspr MD_RPN, r8 + mtspr MD_RPN, r11 #endif /* Since the cache is enabled according to the information we -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 05/13] 8xx: Update TLB asm so it behaves as linux mm expects.
Update the TLB asm to make proper use of _PAGE_DIRTY and _PAGE_ACCESSED. Get rid of _PAGE_HWWRITE too. Pros: - PRESENT is copied to ACCESSED, fixing accounting - DIRTY is mapped to 0x100, the changed bit, and is set directly when a page has been made dirty. - Proper RO/RW mapping of user space. - Free up 2 SW TLB bits in the linux pte(add back _PAGE_WRITETHRU ?) - kernel RO/user NA support. Not sure this is really needed, would save a few insn if not required. Cons: - A few more instructions in the DTLB Miss routine. Signed-off-by: Joakim Tjernlund --- arch/ppc/kernel/head_8xx.S | 53 ++- include/asm-ppc/pgtable.h | 15 +-- 2 files changed, 39 insertions(+), 29 deletions(-) diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index 5269e5b..9eb383b 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -361,25 +361,27 @@ InstructionTLBMiss: */ tophys(r21,r21) ori r21,r21,1 /* Set valid bit */ - beq-2f /* If zero, don't try to find a pte */ DO_8xx_CPU6(0x2b80, r3) mtspr MI_TWC, r21 /* Set segment attributes */ + beq-2f /* If zero, don't try to find a pte */ DO_8xx_CPU6(0x3b80, r3) mtspr MD_TWC, r21 /* Load pte table base address */ mfspr r21, MD_TWC /* and get the pte address */ lwz r20, 0(r21) /* Get the pte */ - ori r20, r20, _PAGE_ACCESSED - stw r20, 0(r21) - +#if 1 + /* if !swap, you can delete this */ + rlwimi r20, r20, 5, _PAGE_PRESENT<<5 /* Copy PRESENT to ACCESSED */ + stw r20, 0(r21) /* Update pte */ +#endif /* The Linux PTE won't go exactly into the MMU TLB. -* Software indicator bits 21, 22 and 28 must be clear. +* Software indicator bits 21 and 28 must be clear. * Software indicator bits 24, 25, 26, and 27 must be * set. All other Linux PTE bits control the behavior * of the MMU. */ 2: li r21, 0x00f0 - rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */ + rlwimi r20, r21, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */ DO_8xx_CPU6(0x2d80, r3) mtspr MI_RPN, r20 /* Update TLB entry */ @@ -436,12 +438,25 @@ DataStoreTLBMiss: DO_8xx_CPU6(0x3b80, r3) mtspr MD_TWC, r21 - mfspr r21, MD_TWC /* get the pte address again */ - ori r20, r20, _PAGE_ACCESSED - stw r20, 0(r21) +#if 1 + /* if !swap, you can delete this */ + mfspr r21, MD_TWC /* get the pte address */ + rlwimi r20, r20, 5, _PAGE_PRESENT<<5 /* Copy PRESENT to ACCESSED */ + stw r20, 0(r21) /* Update pte */ +#endif + + /* Honour kernel RO, User NA */ + /* 0x200 == Extended encoding, bit 22 */ + /* r20 |= (r20 & _PAGE_USER) >> 2 */ + rlwimi r20, r20, 32-2, 0x200 + /* r21 = (r20 & _PAGE_RW) >> 1 */ + rlwinm r21, r20, 32-1, 0x200 + or r20, r21, r20 + /* invert RW and 0x200 bits */ + xorir20, r20, _PAGE_RW | 0x200 /* The Linux PTE won't go exactly into the MMU TLB. -* Software indicator bits 21, 22 and 28 must be clear. +* Software indicator bits 22 and 28 must be clear. * Software indicator bits 24, 25, 26, and 27 must be * set. All other Linux PTE bits control the behavior * of the MMU. @@ -488,11 +503,12 @@ DataTLBError: stw r20, 0(r0) stw r21, 4(r0) - /* First, make sure this was a store operation. - */ mfspr r20, DSISR - andis. r21, r20, 0x0200/* If set, indicates store op */ - beq 2f + andis. r21, r20, 0x4800/* !translation or protection */ + bne-2f + /* Only Change bit left now, do it here as it is faster +* than trapping to the C fault handler. +*/ /* The EA of a data TLB miss is automatically stored in the MD_EPN * register. The EA of a data TLB error is automatically stored in @@ -542,17 +558,12 @@ DataTLBError: mfspr r21, MD_TWC /* and get the pte address */ lwz r20, 0(r21) /* Get the pte */ - andi. r21, r20, _PAGE_RW /* Is it writeable? */ - beq 2f /* Bail out if not */ - - /* Update 'changed', among others. - */ ori r20, r20, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE - mfspr r21, MD_TWC /* Get pte address again */ stw r20, 0(r21) /* and update pte in table */ + xorir20, r20, _PAGE_RW /* RW bit is inverted */ /* The Linux PTE won't go exactly into the MMU TLB. -* Software indicator bits 21, 22 and 28 must be clear. +* Software indicator bits 22 and 2
[PATCH 06/13] 8xx: Always pin kernel instruction TLB
Various kernel asm modifies SRR0/SRR1 just before executing a rfi. If such code crosses a page boundary you risk a TLB miss which will clobber SRR0/SRR1. Avoid this by always pinning kernel instruction TLB space. Signed-off-by: Joakim Tjernlund --- arch/ppc/kernel/head_8xx.S |9 + 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index 9eb383b..d992c24 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -777,12 +777,13 @@ start_here: */ initial_mmu: tlbia /* Invalidate all TLB entries */ -#ifdef CONFIG_PIN_TLB + +/* Always pin the first 8 MB ITLB to prevent ITLB + misses while mucking around with SRR0/SRR1 in asm +*/ lis r8, mi_rs...@h ori r8, r8, 0x1c00 -#else - li r8, 0 -#endif + mtspr MI_CTR, r8 /* Set instruction MMU control */ #ifdef CONFIG_PIN_TLB -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 07/13] 8xx: Fixup DAR from buggy dcbX instructions.
This is an assembler version to fixup DAR not being set by dcbX, icbi instructions. There are two versions, one uses selfmodifing code, the other uses a jump table but is much bigger(default). Signed-off-by: Joakim Tjernlund --- arch/ppc/kernel/head_8xx.S | 149 +++- 1 files changed, 146 insertions(+), 3 deletions(-) diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index d992c24..52ff914 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -503,8 +503,17 @@ DataTLBError: stw r20, 0(r0) stw r21, 4(r0) - mfspr r20, DSISR - andis. r21, r20, 0x4800/* !translation or protection */ + mfspr r20, DAR + cmpwi cr0, r20, 0x00f0 + beq-FixupDAR/* must be a buggy dcbX, icbi insn. */ +DARFixed: + /* As the DAR fixup may clear store we may have all 3 states zero. +* Make sure only 0x0200(store) falls down into DIRTY handling +*/ + mfspr r21, DSISR + andis. r21, r21, 0x4a00/* !translation, protection or store */ + srwir21, r21, 16 + cmpwi cr0, r21, 0x0200/* just store ? */ bne-2f /* Only Change bit left now, do it here as it is faster * than trapping to the C fault handler. @@ -526,7 +535,7 @@ DataTLBError: * are initialized in mapin_ram(). This will avoid the problem, * assuming we only use the dcbi instruction on kernel addresses. */ - mfspr r20, DAR + /* DAR is in r20 already */ rlwinm r21, r20, 0, 0, 19 ori r21, r21, MD_EVALID mfspr r20, M_CASID @@ -610,6 +619,140 @@ DataTLBError: STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) . = 0x2000 +/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions + * by decoding the registers used by the dcbx instruction and adding them. + * DAR is set to the calculated address and r10 also holds the EA on exit. + */ + /* define if you don't want to use self modifying code */ +#define NO_SELF_MODIFYING_CODE +FixupDAR:/* Entry point for dcbx workaround. */ + /* fetch instruction from memory. */ + mfspr r20, SRR0 + andis. r21, r20, 0x8000/* Address >= 0x8000 */ + DO_8xx_CPU6(0x3780, r3) + mtspr MD_EPN, r20 + mfspr r21, M_TWB /* Get level 1 table entry address */ + beq-3f /* Branch if user space */ + lis r21, (swapper_pg_dir-PAGE_OFFSET)@h + ori r21, r21, (swapper_pg_dir-PAGE_OFFSET)@l + rlwimi r21, r20, 32-20, 0xffc /* r21 = r21&~0xffc|(r20>>20)&0xffc */ +3: lwz r21, 0(r21) /* Get the level 1 entry */ + tophys (r21, r21) + DO_8xx_CPU6(0x3b80, r3) + mtspr MD_TWC, r21 /* Load pte table base address */ + mfspr r21, MD_TWC /* and get the pte address */ + lwz r21, 0(r21) /* Get the pte */ + /* concat physical page address(r21) and page offset(r20) */ + rlwimi r21, r20, 0, 20, 31 + lwz r21,0(r21) +/* Check if it really is a dcbx instruction. */ +/* dcbt and dcbtst does not generate DTLB Misses/Errors, + * no need to include them here */ + srwir20, r21, 26/* check if major OP code is 31 */ + cmpwi cr0, r20, 31 + bne-141f + rlwinm r20, r21, 0, 21, 30 + cmpwi cr0, r20, 2028 /* Is dcbz? */ + beq+142f + cmpwi cr0, r20, 940 /* Is dcbi? */ + beq+142f + cmpwi cr0, r20, 108 /* Is dcbst? */ + beq+144f/* Fix up store bit! */ + cmpwi cr0, r20, 172 /* Is dcbf? */ + beq+142f + cmpwi cr0, r20, 1964 /* Is icbi? */ + beq+142f +141: mfspr r20, DAR/* r20 must hold DAR at exit */ + b DARFixed/* Nope, go back to normal TLB processing */ + +144: mfspr r20, DSISR + rlwinm r20, r20,0,7,5 /* Clear store bit for buggy dcbst insn */ + mtspr DSISR, r20 +142: /* continue, it was a dcbx, dcbi instruction. */ +#ifdef CONFIG_8xx_CPU6 + lwz r3, 8(r0) /* restore r3 from memory */ +#endif +#ifndef NO_SELF_MODIFYING_CODE + andis. r20,r21,0x1f/* test if reg RA is r0 */ + li r20,modified_in...@l + dcbtst r0,r20 /* touch for store */ + rlwinm r21,r21,0,0,20 /* Zero lower 10 bits */ + orisr21,r21,640 /* Transform instr. to a "add r20,RA,RB" */ + ori r21,r21,532 + stw r21,0(r20) /* store add/and instruction */ + dcbf0,r20 /* flush new instr. to memory. */ + icbi0,r20 /* invalidate instr. cache line */ + lwz r21, 4(r0) /* restore r21 from memory */ + mfspr r20, M_TW /* restore r20 from M_TW */ + isync /* Wait until new instr is loaded from memory */ +modified_instr: +
[PATCH 08/13] 8xx: CPU6 errata make DTLB error too big to fit.
branch to common code in DTLB Miss instead. Signed-off-by: Joakim Tjernlund --- arch/ppc/kernel/head_8xx.S | 23 ++- 1 files changed, 2 insertions(+), 21 deletions(-) diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index 52ff914..0aab8ca 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -461,6 +461,7 @@ DataStoreTLBMiss: * set. All other Linux PTE bits control the behavior * of the MMU. */ +finish_DTLB: 2: li r21, 0x00f0 mtspr DAR, r21/* Tag DAR */ rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */ @@ -570,27 +571,7 @@ DARFixed: ori r20, r20, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE stw r20, 0(r21) /* and update pte in table */ xorir20, r20, _PAGE_RW /* RW bit is inverted */ - - /* The Linux PTE won't go exactly into the MMU TLB. -* Software indicator bits 22 and 28 must be clear. -* Software indicator bits 24, 25, 26, and 27 must be -* set. All other Linux PTE bits control the behavior -* of the MMU. -*/ - li r21, 0x00f0 - mtspr DAR, r21/* Tag DAR */ - rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */ - DO_8xx_CPU6(0x3d80, r3) - mtspr MD_RPN, r20 /* Update TLB entry */ - - mfspr r20, M_TW /* Restore registers */ - lwz r21, 0(r0) - mtcrr21 - lwz r21, 4(r0) -#ifdef CONFIG_8xx_CPU6 - lwz r3, 8(r0) -#endif - rfi + b finish_DTLB 2: mfspr r20, M_TW /* Restore registers */ lwz r21, 0(r0) -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 09/13] 8xx: Add missing Guarded setting in DTLB Error.
only DTLB Miss did set this bit, DTLB Error needs too otherwise the setting is lost when the page becomes dirty. Signed-off-by: Joakim Tjernlund --- arch/ppc/kernel/head_8xx.S | 12 +--- 1 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index 0aab8ca..2659a1e 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -565,9 +565,15 @@ DARFixed: ori r21, r21, 1 /* Set valid bit in physical L2 page */ DO_8xx_CPU6(0x3b80, r3) mtspr MD_TWC, r21 /* Load pte table base address */ - mfspr r21, MD_TWC /* and get the pte address */ - lwz r20, 0(r21) /* Get the pte */ - + mfspr r20, MD_TWC /* and get the pte address */ + lwz r20, 0(r20) /* Get the pte */ + /* Insert the Guarded flag into the TWC from the Linux PTE. +* It is bit 27 of both the Linux PTE and the TWC +*/ + rlwimi r21, r20, 0, 27, 27 + DO_8xx_CPU6(0x3b80, r3) + mtspr MD_TWC, r21 + mfspr r21, MD_TWC /* get the pte address again */ ori r20, r20, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE stw r20, 0(r21) /* and update pte in table */ xorir20, r20, _PAGE_RW /* RW bit is inverted */ -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 10/13] 8xx: Restore _PAGE_WRITETHRU
8xx has not had WRITETHRU due to lack of bits in the pte. After the recent rewrite of the 8xx TLB code, there are two bits left. Use one of them to WRITETHRU. Signed-off-by: Joakim Tjernlund --- arch/ppc/kernel/head_8xx.S |8 include/asm-ppc/pgtable.h |5 +++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index 2659a1e..43bccb1 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -435,6 +435,10 @@ DataStoreTLBMiss: * above. */ rlwimi r21, r20, 0, 27, 27 + /* Insert the WriteThru flag into the TWC from the Linux PTE. +* It is bit 25 in the Linux PTE and bit 30 in the TWC +*/ + rlwimi r21, r20, 32-5, 30, 30 DO_8xx_CPU6(0x3b80, r3) mtspr MD_TWC, r21 @@ -571,6 +575,10 @@ DARFixed: * It is bit 27 of both the Linux PTE and the TWC */ rlwimi r21, r20, 0, 27, 27 + /* Insert the WriteThru flag into the TWC from the Linux PTE. +* It is bit 25 in the Linux PTE and bit 30 in the TWC +*/ + rlwimi r21, r20, 32-5, 30, 30 DO_8xx_CPU6(0x3b80, r3) mtspr MD_TWC, r21 mfspr r21, MD_TWC /* get the pte address again */ diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index 2ba37d3..6cfc5fc 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h @@ -298,12 +298,13 @@ extern unsigned long vmalloc_start; #define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */ #define _PAGE_SHARED 0x0004 /* No ASID (context) compare */ -/* These three software bits must be masked out when the entry is loaded - * into the TLB, 2 SW bits free. +/* These four software bits must be masked out when the entry is loaded + * into the TLB, 1 SW bits left(0x0080). */ #define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */ #define _PAGE_GUARDED 0x0010 /* software: guarded access */ #define _PAGE_ACCESSED 0x0020 /* software: page referenced */ +#define _PAGE_WRITETHRU0x0040 /* software: caching is write through */ /* Setting any bits in the nibble with the follow two controls will * require a TLB exception handler change. It is assumed unused bits -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 11/13] 8xx: start using dcbX instructions in various copy routines
Now that 8xx can fixup dcbX instructions, start using them where possible like every other PowerPc arch do. Signed-off-by: Joakim Tjernlund --- arch/ppc/kernel/misc.S | 18 -- arch/ppc/lib/string.S | 17 - 2 files changed, 0 insertions(+), 35 deletions(-) diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S index c1c3178..6f57957 100644 --- a/arch/ppc/kernel/misc.S +++ b/arch/ppc/kernel/misc.S @@ -662,15 +662,7 @@ _GLOBAL(__flush_dcache_icache) _GLOBAL(clear_page) li r0,4096/L1_CACHE_LINE_SIZE mtctr r0 -#ifdef CONFIG_8xx - li r4, 0 -1: stw r4, 0(r3) - stw r4, 4(r3) - stw r4, 8(r3) - stw r4, 12(r3) -#else 1: dcbz0,r3 -#endif addir3,r3,L1_CACHE_LINE_SIZE bdnz1b blr @@ -695,15 +687,6 @@ _GLOBAL(copy_page) addir3,r3,-4 addir4,r4,-4 -#ifdef CONFIG_8xx - /* don't use prefetch on 8xx */ - li r0,4096/L1_CACHE_LINE_SIZE - mtctr r0 -1: COPY_16_BYTES - bdnz1b - blr - -#else /* not 8xx, we can prefetch */ li r5,4 #if MAX_COPY_PREFETCH > 1 @@ -744,7 +727,6 @@ _GLOBAL(copy_page) li r0,MAX_COPY_PREFETCH li r11,4 b 2b -#endif /* CONFIG_8xx */ /* * Atomic [test&set] exchange diff --git a/arch/ppc/lib/string.S b/arch/ppc/lib/string.S index 6ca54b4..b6ea44b 100644 --- a/arch/ppc/lib/string.S +++ b/arch/ppc/lib/string.S @@ -159,14 +159,7 @@ _GLOBAL(cacheable_memzero) bdnz4b 3: mtctr r9 li r7,4 -#if !defined(CONFIG_8xx) 10:dcbzr7,r6 -#else -10:stw r4, 4(r6) - stw r4, 8(r6) - stw r4, 12(r6) - stw r4, 16(r6) -#endif addir6,r6,CACHELINE_BYTES bdnz10b clrlwi r5,r8,32-LG_CACHELINE_BYTES @@ -261,9 +254,7 @@ _GLOBAL(cacheable_memcpy) mtctr r0 beq 63f 53: -#if !defined(CONFIG_8xx) dcbzr11,r6 -#endif COPY_16_BYTES #if L1_CACHE_LINE_SIZE >= 32 COPY_16_BYTES @@ -443,13 +434,6 @@ _GLOBAL(__copy_tofrom_user) li r11,4 beq 63f -#ifdef CONFIG_8xx - /* Don't use prefetch on 8xx */ - mtctr r0 -53:COPY_16_BYTES_WITHEX(0) - bdnz53b - -#else /* not CONFIG_8xx */ /* Here we decide how far ahead to prefetch the source */ li r3,4 cmpwi r0,1 @@ -502,7 +486,6 @@ _GLOBAL(__copy_tofrom_user) li r3,4 li r7,0 bne 114b -#endif /* CONFIG_8xx */ 63:srwi. r0,r5,2 mtctr r0 -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 12/13] 8xx: Optimize ITLBMiss handler.
Don't check for kernel space if no modules. Signed-off-by: Joakim Tjernlund --- arch/ppc/kernel/head_8xx.S |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index 43bccb1..5dbbdb4 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -347,12 +347,17 @@ InstructionTLBMiss: /* If we are faulting a kernel address, we have to use the * kernel page tables. */ +#ifdef CONFIG_MODULES + /* Since we PIN the first 8MB text, we only get ITLB misses +* for modules +*/ andi. r21, r20, 0x0800/* Address >= 0x8000 */ beq 3f lis r21, swapper_pg_...@h ori r21, r21, swapper_pg_...@l rlwimi r20, r21, 0, 2, 19 3: +#endif lwz r21, 0(r20) /* Get the level 1 entry */ rlwinm. r20, r21,0,0,19 /* Extract page descriptor page address */ -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 13/13] 8xx: Optimize TLB Miss handlers
Only update pte w.r.t ACCESSED if it isn't already set Signed-off-by: Joakim Tjernlund --- arch/ppc/kernel/head_8xx.S |7 +++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index 5dbbdb4..75acaa0 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -376,8 +376,12 @@ InstructionTLBMiss: #if 1 /* if !swap, you can delete this */ + andi. r21, r20, _PAGE_ACCESSED/* test ACCESSED bit */ + bne+4f /* Branch if set */ + mfspr r21, MD_TWC /* get the pte address */ rlwimi r20, r20, 5, _PAGE_PRESENT<<5 /* Copy PRESENT to ACCESSED */ stw r20, 0(r21) /* Update pte */ +4: #endif /* The Linux PTE won't go exactly into the MMU TLB. * Software indicator bits 21 and 28 must be clear. @@ -449,9 +453,12 @@ DataStoreTLBMiss: #if 1 /* if !swap, you can delete this */ + andi. r21, r20, _PAGE_ACCESSED/* test ACCESSED bit */ + bne+4f /* Branch if set */ mfspr r21, MD_TWC /* get the pte address */ rlwimi r20, r20, 5, _PAGE_PRESENT<<5 /* Copy PRESENT to ACCESSED */ stw r20, 0(r21) /* Update pte */ +4: #endif /* Honour kernel RO, User NA */ -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] ehci-fsl: Fix 'have_sysif_regs' detection
Previously a check was done on an ID register at the base of a CPU's
internal USB registers to determine if system interface regsiters were
present. The check looked for an ID register that had the format
ID[0:5] == ~ID[8:13] as described in the MPC5121 User's Manual to
determine if a MPC5121 or MPC83xx/85xx was being used.
There are two issues with this method:
- The ID register is not defined on the MPC83xx/85xx CPUs, so its
unclear what is being checked on them.
- Newer CPUs such as the P4080 also don't document the ID register, but
do share the same format as the MPC5121. Thus the previous code did
not set 'have_sysif_regs' properly which results in the P4080 not
properly initializing its USB ports.
Using the device tree 'compatible' node is a cleaner way to determine if
'have_sysif_regs' should be set and resolves the USB initialization issue
seen on the P4080.
Tested on a P4080-based system and compile tested on mpc512x_defconfig
with Freescale EHCI driver enabled.
Cc: Anatolij Gustschin
Cc: David Brownell
Cc: Kumar Gala
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Peter Tyser
---
drivers/usb/host/ehci-fsl.c | 13 -
drivers/usb/host/ehci-fsl.h |3 ---
drivers/usb/host/fsl-mph-dr-of.c | 11 ---
3 files changed, 8 insertions(+), 19 deletions(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 86e4289..5c761df 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -52,7 +52,6 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
struct resource *res;
int irq;
int retval;
- unsigned int temp;
pr_debug("initializing FSL-SOC USB Controller\n");
@@ -126,18 +125,6 @@ static int usb_hcd_fsl_probe(const struct hc_driver
*driver,
goto err3;
}
- /*
-* Check if it is MPC5121 SoC, otherwise set pdata->have_sysif_regs
-* flag for 83xx or 8536 system interface registers.
-*/
- if (pdata->big_endian_mmio)
- temp = in_be32(hcd->regs + FSL_SOC_USB_ID);
- else
- temp = in_le32(hcd->regs + FSL_SOC_USB_ID);
-
- if ((temp & ID_MSK) != (~((temp & NID_MSK) >> 8) & ID_MSK))
- pdata->have_sysif_regs = 1;
-
/* Enable USB controller, 83xx or 8536 */
if (pdata->have_sysif_regs)
setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index 2c83537..3fabed3 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -19,9 +19,6 @@
#define _EHCI_FSL_H
/* offsets for the non-ehci registers in the FSL SOC USB controller */
-#define FSL_SOC_USB_ID 0x0
-#define ID_MSK 0x3f
-#define NID_MSK0x3f00
#define FSL_SOC_USB_ULPIVP 0x170
#define FSL_SOC_USB_PORTSC10x184
#define PORT_PTS_MSK (3<<30)
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 574b99e..341fa81 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -262,19 +262,24 @@ static void fsl_usb2_mpc5121_exit(struct platform_device
*pdev)
}
}
-struct fsl_usb2_platform_data fsl_usb2_mpc5121_pd = {
+static struct fsl_usb2_platform_data fsl_usb2_mpc5121_pd = {
.big_endian_desc = 1,
.big_endian_mmio = 1,
.es = 1,
+ .have_sysif_regs = 0,
.le_setup_buf = 1,
.init = fsl_usb2_mpc5121_init,
.exit = fsl_usb2_mpc5121_exit,
};
#endif /* CONFIG_PPC_MPC512x */
+static struct fsl_usb2_platform_data fsl_usb2_mpc8xxx_pd = {
+ .have_sysif_regs = 1,
+};
+
static const struct of_device_id fsl_usb2_mph_dr_of_match[] = {
- { .compatible = "fsl-usb2-mph", },
- { .compatible = "fsl-usb2-dr", },
+ { .compatible = "fsl-usb2-mph", .data = &fsl_usb2_mpc8xxx_pd, },
+ { .compatible = "fsl-usb2-dr", .data = &fsl_usb2_mpc8xxx_pd, },
#ifdef CONFIG_PPC_MPC512x
{ .compatible = "fsl,mpc5121-usb2-dr", .data = &fsl_usb2_mpc5121_pd, },
#endif
--
1.7.0.4
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Re: PCI woes with 2.6.37
> I found the problem - a change I had in <2.6.32 that I hadn't > pushed forward. It seems to be related to how I have the PCI > controller setup (in RedBoot). Because of this, using these > settings in my DTS make things work properly: > ranges = <0x0200 0x0 0x 0xC000 0x0 0x2000 >0x0100 0x0 0x 0xB800 0x0 0x0010>; > Instead of > ranges = <0x0200 0x0 0xC000 0xC000 0x0 0x2000 >0x0100 0x0 0x 0xB800 0x0 0x0010>; Right so instead of a 1:1 mapping you have a N:1 mapping. We support both forms, tho it would have been nice if the fsl PCI code had properly reconfigured the controller based on the DT. > Sorry for the noise (wild goose chase), but discussing it did help > me to work out some PCI issues in general. > > Now that this is working, I'm trying to move to the next problem. > The system works fine, but only to a point. In this [embedded] > system, I have an SIL SATA controller on the PCI bus. Ok, those are pretty common and generally work fine. > On 2.6.28, > this device is rock solid. On 2.6.32 and now 2.6.37, I have issues. > Operations work on the device (connected to a SSD), but after some > arbitrary time, an operation will fail, causing the PCI bus (and > indeed the whole system) to hang. I've tried to peek in using a > BDI and once it hangs, even the BDI can't access the CPU any more. Ugh. Never hit a problem like this I'm afraid. > I'm pretty lost on this one - it will execute hundreds of SATA operations > properly and then die. Turning on SATA/SCSI traces, I can see the > final operation be issued and there seems to be no substantive difference > between this operation and the previous ones that all worked. In fact > if I reset and rerun the same program, it _will_ fail but never on > the same operation :-( > > Any ideas what could cause this failure? I have a similar system > that uses a different SATA controller that I'm going to try. Maybe > it's something peculiar to the SIL device as opposed to generic PCI > operations. Yes, definitely try different controllers. Also check your voltages just in case Other things you can do is double check the settings of things like max read request size, max payload size etc... in the PCIe config space of the device and the bridge. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 00/13] powerpc: Backport 8xx TLB to 2.4
Hi Joakim, On Mon, Jan 10, 2011 at 10:37:46PM +0100, Joakim Tjernlund wrote: > This is a backport from 2.6 which I did to overcome 8xx CPU > bugs. 8xx does not update the DAR register when taking a TLB > error caused by dcbX and icbi insns which makes it very > tricky to use these insns. Also the dcbst wrongly sets the > the store bit when faulting into DTLB error. > A few more bugs very found during development. > > I know 2.4 is in strict maintenance mode and 8xx is obsolete > but as it is still in use I wanted 8xx to age with grace. Thank you very much for taking care of this, that's very much appreciated. I'll look at this ASAP. Just a quick question in order to be certain, did you have the opportunity to test all of these changes on real hardware ? Thanks, Willy ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
