[PATCH] powerpc/p1023rds: Add nand flash node support in the dts
In the p1023rds, accessing exclusively nor flash or nand flash
device by BR0/OR0. When booting from nor flash, nand node is
disabled and nor node is enabled in the default dts. So, when
booting from nand flash, u-boot should do some operations:
o The status property of nand node should be enabled.
o The status property of nor node should be disabled.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
arch/powerpc/boot/dts/p1023rds.dts | 46 +--
1 files changed, 43 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/boot/dts/p1023rds.dts
b/arch/powerpc/boot/dts/p1023rds.dts
index d9b7767..aa63b81 100644
--- a/arch/powerpc/boot/dts/p1023rds.dts
+++ b/arch/powerpc/boot/dts/p1023rds.dts
@@ -58,6 +58,9 @@
rtic_b = rtic_b;
rtic_c = rtic_c;
rtic_d = rtic_d;
+
+ nor_flash = nor_flash;
+ nand_flash = nand_flash;
};
cpus {
@@ -378,11 +381,12 @@
interrupts = 19 2;
interrupt-parent = mpic;
- /* NOR Flash, BCSR */
+ /* NOR Flash, BCSR, NAND Flash */
ranges = 0x0 0x0 0x0 0xee00 0x0200
- 0x1 0x0 0x0 0xe000 0x8000;
+ 0x1 0x0 0x0 0xe000 0x8000
+ 0x2 0x0 0x0 0xffa0 0x0004;
- nor@0,0 {
+ nor_flash: nor@0,0 {
#address-cells = 1;
#size-cells = 1;
compatible = cfi-flash;
@@ -425,6 +429,42 @@
reg = 0x20 0x20;
};
};
+
+ nand_flash: nand@2,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,p1023-fcm-nand,
+fsl,elbc-fcm-nand;
+ reg = 0x2 0x0 0x0004;
+ status = disabled;
+
+ u-boot-nand@0 {
+ /* This location must not be altered */
+ /* 1MB for u-boot Bootloader Image */
+ reg = 0x0 0x0010;
+ read-only;
+ };
+
+ dtb-nand@10 {
+ /* 1MB for DTB Image */
+ reg = 0x0010 0x0010;
+ };
+
+ kernel-nand@20 {
+ /* 4MB for Linux Kernel Image */
+ reg = 0x0020 0x0040;
+ };
+
+ ramdisk-nand@60 {
+ /* 57MB for Compressed Root file System Image */
+ reg = 0x0060 0x0390;
+ };
+
+ empty-nand@3f0 {
+ /* 1MB for reserved space */
+ reg = 0x03f0 0x0010;
+ };
+ };
};
pci0: pcie@ff60a000 {
--
1.5.6.5
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[PATCH] mcu_mpc8349emitx.c: add shutdown request support
This patch add support for calling ctrl_alt_del() when the power button is
pressed for more than about 2 seconds on some freescale MPC83xx
evaluation boards and reference design.
The code uses a kthread to poll the CTRL_BTN bit each second.
Also change Kconfig entry of the driver to bool, as device's gpio
registration is broken when loading as module.
Tested on an MPC8315E RDB board.
Signed-off-by: Fabio Baltieri fabio.balti...@gmail.com
---
arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c | 58 +++-
arch/powerpc/platforms/Kconfig |2 +-
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
b/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
index 70798ac..ef6537b 100644
--- a/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
+++ b/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
@@ -21,6 +21,8 @@
#include linux/of.h
#include linux/of_gpio.h
#include linux/slab.h
+#include linux/kthread.h
+#include linux/reboot.h
#include asm/prom.h
#include asm/machdep.h
@@ -30,6 +32,7 @@
*/
#define MCU_REG_CTRL 0x20
#define MCU_CTRL_POFF 0x40
+#define MCU_CTRL_BTN 0x80
#define MCU_NUM_GPIO 2
@@ -42,13 +45,55 @@ struct mcu {
static struct mcu *glob_mcu;
+struct task_struct *shutdown_thread;
+static int shutdown_thread_fn(void *data)
+{
+ int ret;
+ struct mcu *mcu = glob_mcu;
+
+ while (!kthread_should_stop()) {
+ ret = i2c_smbus_read_byte_data(mcu-client, MCU_REG_CTRL);
+ if (ret 0)
+ pr_err(MCU status reg read failed.\n);
+ mcu-reg_ctrl = ret;
+
+
+ if (mcu-reg_ctrl MCU_CTRL_BTN) {
+ i2c_smbus_write_byte_data(mcu-client, MCU_REG_CTRL,
+ mcu-reg_ctrl
~MCU_CTRL_BTN);
+
+ ctrl_alt_del();
+ }
+
+ set_current_state(TASK_INTERRUPTIBLE);
+ schedule_timeout(HZ);
+ }
+
+ return 0;
+}
+
+static ssize_t show_status(struct device *d,
+ struct device_attribute *attr, char *buf)
+{
+ int ret;
+ struct mcu *mcu = glob_mcu;
+
+ ret = i2c_smbus_read_byte_data(mcu-client, MCU_REG_CTRL);
+ if (ret 0)
+ return -ENODEV;
+ mcu-reg_ctrl = ret;
+
+ return sprintf(buf, %02x\n, ret);
+}
+static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
+
static void mcu_power_off(void)
{
struct mcu *mcu = glob_mcu;
pr_info(Sending power-off request to the MCU...\n);
mutex_lock(mcu-lock);
- i2c_smbus_write_byte_data(glob_mcu-client, MCU_REG_CTRL,
+ i2c_smbus_write_byte_data(mcu-client, MCU_REG_CTRL,
mcu-reg_ctrl | MCU_CTRL_POFF);
mutex_unlock(mcu-lock);
}
@@ -130,6 +175,13 @@ static int __devinit mcu_probe(struct i2c_client *client,
dev_info(client-dev, will provide power-off service\n);
}
+ if (device_create_file(client-dev, dev_attr_status))
+ dev_err(client-dev,
+ couldn't create device file for status\n);
+
+ shutdown_thread = kthread_run(shutdown_thread_fn, NULL,
+ mcu-i2c-shdn);
+
return 0;
err:
kfree(mcu);
@@ -141,6 +193,10 @@ static int __devexit mcu_remove(struct i2c_client *client)
struct mcu *mcu = i2c_get_clientdata(client);
int ret;
+ kthread_stop(shutdown_thread);
+
+ device_remove_file(client-dev, dev_attr_status);
+
if (glob_mcu == mcu) {
ppc_md.power_off = NULL;
glob_mcu = NULL;
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index b9ba861..7bfd30e 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -355,7 +355,7 @@ config SIMPLE_GPIO
on-board peripherals.
config MCU_MPC8349EMITX
- tristate MPC8349E-mITX MCU driver
+ bool MPC8349E-mITX MCU driver
depends on I2C PPC_83xx
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
--
1.7.5.1
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Re: [PATCH v3] mtd: eLBC NAND: update ecc_stats.corrected when lteccr available
On Tue, 2011-07-26 at 15:07 -0500, Michael Hench wrote: update ecc_stats.corrected if LTECCR register is available. v2: kernel standard C formatting v3: kernel standard C formatting again, changed a comment to get under 80 chars Signed-off-by: Michael Hench michaelhe...@gmail.com Pushed to l2-mtd-2.6.git, thanks. -- Best Regards, Artem Bityutskiy ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v12 3/6] flexcan: Fix up fsl-flexcan device tree binding.
Grant,
Earlier, you had asked for a more specific name for the compatible
property of the Freescale flexcan device. I still have not gotten a
more specific answer. Hopefully Marc can give you more details about
the flexcan implementations.
Other than an agreement on the compatible property, I believe we have
agreement on all the other code changes in these patches. Is this change
acceptable as is and if we get a better resolution on the fsl,flexcan
name later, we can update the documentation and driver then?
Thanks,
Robin
On Fri, Aug 12, 2011 at 03:45:49AM -0500, Robin Holt wrote:
This patch cleans up the documentation of the device-tree binding for
the Flexcan devices on Freescale's PowerPC and ARM cores. Extra
properties are not used by the driver so we are removing them.
Signed-off-by: Robin Holt h...@sgi.com
Acked-by: Marc Kleine-Budde m...@pengutronix.de,
To: Wolfgang Grandegger w...@grandegger.com,
To: U Bhaskar-B22300 b22...@freescale.com
To: Scott Wood scottw...@freescale.com
To: Grant Likely grant.lik...@secretlab.ca
To: Kumar Gala ga...@kernel.crashing.org
Cc: socketcan-c...@lists.berlios.de,
Cc: net...@vger.kernel.org,
Cc: PPC list linuxppc-dev@lists.ozlabs.org
Cc: devicetree-disc...@lists.ozlabs.org
---
.../devicetree/bindings/net/can/fsl-flexcan.txt| 61
arch/powerpc/boot/dts/p1010rdb.dts | 10 +---
arch/powerpc/boot/dts/p1010si.dtsi | 10 +--
3 files changed, 17 insertions(+), 64 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
index 1a729f0..80a78a9 100644
--- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
+++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
@@ -1,61 +1,22 @@
-CAN Device Tree Bindings
-
-2011 Freescale Semiconductor, Inc.
+Flexcan CAN contoller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
-fsl,flexcan-v1.0 nodes
-In addition to the required compatible-, reg- and interrupt-properties, you
can
-also specify which clock source shall be used for the controller.
+Required properties:
-CPI Clock- Can Protocol Interface Clock
- This CLK_SRC bit of CTRL(control register) selects the clock source to
- the CAN Protocol Interface(CPI) to be either the peripheral clock
- (driven by the PLL) or the crystal oscillator clock. The selected clock
- is the one fed to the prescaler to generate the Serial Clock (Sclock).
- The PRESDIV field of CTRL(control register) controls a prescaler that
- generates the Serial Clock (Sclock), whose period defines the
- time quantum used to compose the CAN waveform.
+- compatible : Should be fsl,processor-flexcan and fsl,flexcan
-Can Engine Clock Source
- There are two sources for CAN clock
- - Platform Clock It represents the bus clock
- - Oscillator Clock
+ An implementation should also claim any of the following compatibles
+ that it is fully backwards compatible with:
- Peripheral Clock (PLL)
- --
- |
- - -
- | |CPI Clock| Prescaler | Sclock
- | || (1.. 256) |
- - -
- | |
- -- -CLK_SRC
- Oscillator Clock
+ - fsl,p1010-flexcan
-- fsl,flexcan-clock-source : CAN Engine Clock Source.This property selects
- the peripheral clock. PLL clock is fed to the
- prescaler to generate the Serial Clock (Sclock).
- Valid values are oscillator and platform
- oscillator: CAN engine clock source is
oscillator clock.
- platform The CAN engine clock source is the bus
clock
- (platform clock).
+- reg : Offset and length of the register set for this device
+- interrupts : Interrupt tuple for this device
-- fsl,flexcan-clock-divider : for the reference and system clock, an
additional
- clock divider can be specified.
-- clock-frequency: frequency required to calculate the bitrate for FlexCAN.
+Example:
-Note:
- - v1.0 of flexcan-v1.0 represent the IP block version for P1010 SOC.
- - P1010 does not have oscillator as the Clock Source.So the default
- Clock Source is platform clock.
-Examples:
-
- can0@1c000 {
- compatible = fsl,flexcan-v1.0;
+ can@1c000 {
+ compatible = fsl,p1010-flexcan, fsl,flexcan;
reg = 0x1c000 0x1000;
interrupts = 48 0x2;
interrupt-parent = mpic;
- fsl,flexcan-clock-source = platform;
-
Re: [PATCH v12 3/6] flexcan: Fix up fsl-flexcan device tree binding.
On Mon, Aug 15, 2011 at 9:03 AM, Robin Holt h...@sgi.com wrote: Grant, Earlier, you had asked for a more specific name for the compatible property of the Freescale flexcan device. I still have not gotten a more specific answer. Hopefully Marc can give you more details about the flexcan implementations. If there is no ip core version, then just stick with the fsl,soc-flexcan name and drop fsl,flexcan. Marketing may say flexcan is flexcan, but hardware engineers like to change things. Trying to be too generic in compatible values will just lead to problems in the future. g. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v12 3/6] flexcan: Fix up fsl-flexcan device tree binding.
On Mon, Aug 15, 2011 at 09:13:50AM -0600, Grant Likely wrote: On Mon, Aug 15, 2011 at 9:03 AM, Robin Holt h...@sgi.com wrote: Grant, Earlier, you had asked for a more specific name for the compatible property of the Freescale flexcan device. I still have not gotten a more specific answer. Hopefully Marc can give you more details about the flexcan implementations. If there is no ip core version, then just stick with the fsl,soc-flexcan name and drop fsl,flexcan. Marketing may say flexcan is flexcan, but hardware engineers like to change things. Trying to be too generic in compatible values will just lead to problems in the future. Thanks, Robin ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip
On Tue, 2011-07-12 at 12:48 +0800, b35...@freescale.com wrote:
+ /*
+ * Hack for supporting the flash chip whose writesize is
+ * larger than 2K bytes.
+ */
+ if (mtd-writesize 2048) {
+ elbc_fcm_ctrl-subpage_shift = ffs(mtd-writesize 11) - 1;
+ elbc_fcm_ctrl-subpage_mask =
+ (1 elbc_fcm_ctrl-subpage_shift) - 1;
+ /*
+ * Rewrite mtd-writesize, mtd-oobsize, chip-page_shift
+ * and chip-pagemask.
+ */
+ mtd-writesize = 2048;
+ mtd-oobsize = 64;
+ chip-page_shift = ffs(mtd-writesize) - 1;
+ chip-pagemask = (chip-chipsize chip-page_shift) - 1;
+ }
So basically if the flash has 4KiB NAND pages, you are considering it as
a flash with 2KiB NAND pages. But surely this will work only if the
underlying flash has NOP 2 at least. Or even, if you consider that JFFS2
and YAFFS want to write to OOB, you need NOP 4 (2 ECC writes and 2
writes from YAFFS/JFFS2) ? So this won't work for NOP1 flashes? Isn't it
an ugly hack?
--
Best Regards,
Artem Bityutskiy
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Re: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip
On 08/15/2011 10:59 AM, Artem Bityutskiy wrote:
On Tue, 2011-07-12 at 12:48 +0800, b35...@freescale.com wrote:
+/*
+ * Hack for supporting the flash chip whose writesize is
+ * larger than 2K bytes.
+ */
+if (mtd-writesize 2048) {
+elbc_fcm_ctrl-subpage_shift = ffs(mtd-writesize 11) - 1;
+elbc_fcm_ctrl-subpage_mask =
+(1 elbc_fcm_ctrl-subpage_shift) - 1;
+/*
+ * Rewrite mtd-writesize, mtd-oobsize, chip-page_shift
+ * and chip-pagemask.
+ */
+mtd-writesize = 2048;
+mtd-oobsize = 64;
+chip-page_shift = ffs(mtd-writesize) - 1;
+chip-pagemask = (chip-chipsize chip-page_shift) - 1;
+}
So basically if the flash has 4KiB NAND pages, you are considering it as
a flash with 2KiB NAND pages. But surely this will work only if the
underlying flash has NOP 2 at least. Or even, if you consider that JFFS2
and YAFFS want to write to OOB, you need NOP 4 (2 ECC writes and 2
writes from YAFFS/JFFS2) ? So this won't work for NOP1 flashes?
Right. The set of chips that work with this controller is still larger
with this than without this.
It looks like NOP1 tends to be MLC -- you probably wouldn't want to use
MLC with this controller anyway as it only does 1-bit ECC.
Isn't it an ugly hack?
Less ugly than some other approaches that were considered. :-)
But yes, it's a hack (even says so in the comment). The other option is
it doesn't work.
-Scott
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Re: [PATCH v12 3/6] flexcan: Fix up fsl-flexcan device tree binding.
On 08/15/2011 05:03 PM, Robin Holt wrote: Earlier, you had asked for a more specific name for the compatible property of the Freescale flexcan device. I still have not gotten a more specific answer. Hopefully Marc can give you more details about the flexcan implementations. There are at least 2 versions of the flexcan ip core in the wild. Due to lack of version numbers or other names I call them old and new here :). The newer one supports rx fifo mode, whereas the older one doesn't. The mainline flexcan driver just supports the new core [1]. The older core is found on coldfire processors. I don't know if there are coldfire cpus with the new flexcan core, too. The driver can be adopted to the old core if needed. The first cpus with the new core I got in touch with was the mx35 (arm11) and mx25 (arm9) both at the same time. Ask fsl which one was released first. After this there was mx28 (arm9) and there should be an mx53 (coretexa8) with flexcan too. Other than an agreement on the compatible property, I believe we have agreement on all the other code changes in these patches. Is this change acceptable as is and if we get a better resolution on the fsl,flexcan name later, we can update the documentation and driver then? cheers, Marc [1] http://lxr.linux.no/linux+v3.0.1/drivers/net/can/flexcan.c#L871 -- Pengutronix e.K. | Marc Kleine-Budde | Industrial Linux Solutions| Phone: +49-231-2826-924 | Vertretung West/Dortmund | Fax: +49-5121-206917- | Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de | signature.asc Description: OpenPGP digital signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip
On Mon, 2011-08-15 at 11:11 -0500, Scott Wood wrote:
On 08/15/2011 10:59 AM, Artem Bityutskiy wrote:
On Tue, 2011-07-12 at 12:48 +0800, b35...@freescale.com wrote:
+ /*
+ * Hack for supporting the flash chip whose writesize is
+ * larger than 2K bytes.
+ */
+ if (mtd-writesize 2048) {
+ elbc_fcm_ctrl-subpage_shift = ffs(mtd-writesize 11) - 1;
+ elbc_fcm_ctrl-subpage_mask =
+ (1 elbc_fcm_ctrl-subpage_shift) - 1;
+ /*
+ * Rewrite mtd-writesize, mtd-oobsize, chip-page_shift
+ * and chip-pagemask.
+ */
+ mtd-writesize = 2048;
+ mtd-oobsize = 64;
+ chip-page_shift = ffs(mtd-writesize) - 1;
+ chip-pagemask = (chip-chipsize chip-page_shift) - 1;
+ }
So basically if the flash has 4KiB NAND pages, you are considering it as
a flash with 2KiB NAND pages. But surely this will work only if the
underlying flash has NOP 2 at least. Or even, if you consider that JFFS2
and YAFFS want to write to OOB, you need NOP 4 (2 ECC writes and 2
writes from YAFFS/JFFS2) ? So this won't work for NOP1 flashes?
Right. The set of chips that work with this controller is still larger
with this than without this.
It looks like NOP1 tends to be MLC -- you probably wouldn't want to use
MLC with this controller anyway as it only does 1-bit ECC.
Isn't it an ugly hack?
Less ugly than some other approaches that were considered. :-)
But yes, it's a hack (even says so in the comment). The other option is
it doesn't work.
Could there be at least a fat comment that NANDs with 4KiB pages have to
be at least NOP4? And probably NANDs with 8KiB pages and larger should
simply be rejected?
--
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Artem Bityutskiy
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Re: [PATCH 8/9] arch/powerpc/sysdev/ehv_pic.c: add missing kfree
On Mon, Aug 8, 2011 at 7:18 AM, Julia Lawall ju...@diku.dk wrote:
diff --git a/arch/powerpc/sysdev/ehv_pic.c b/arch/powerpc/sysdev/ehv_pic.c
index af1a5df..b6731e4 100644
--- a/arch/powerpc/sysdev/ehv_pic.c
+++ b/arch/powerpc/sysdev/ehv_pic.c
@@ -280,6 +280,7 @@ void __init ehv_pic_init(void)
if (!ehv_pic-irqhost) {
of_node_put(np);
+ kfree(ehv_pic);
return;
}
Although the fix is correct, I think there is another bug in this
function. 'np' is not released when the function finishes
successfully. I've looked at other functions that use
irq_alloc_host(), and most of them do the same thing: they don't call
of_node_put() on the device node pointer. The only exception I've
found is mpc5121_ads_cpld_pic_init().
Ben, Kumar: am I missing something? irq_alloc_host() calls of_node_get():
host-of_node = of_node_get(of_node);
so doesn't that mean that the caller of irq_alloc_host() should
release the device node pointer?
--
Timur Tabi
Linux kernel developer at Freescale
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