Re: FW: P4080 device tree problems with fsl dpaa ... RESOLVED.
Hi Robert, On Tue, Oct 18, 2011 at 11:38 PM, Robert Sciuk robert.sc...@exfo.com wrote: [snip] How and what type of packets are you sending? Raw MAC frames, IP? Are you using custom code, or can you try things like ping? If you are using IP, I trust you checked the Linux configuration (like assigning a valid IP address to the interface and making sure the routing table is correct). Best regards, Thomas Thomas, I would like to thank you for your very kind assistance on the DPAA problem. We traced the problem to the connection between MAC and PHY, and we have resolved it by instrumenting code and comparing the TBI and PHY initialization from u-boot to the Linux DPA code, and replacing some of the magic numbers we found in the driver with magic numbers we know to work. OUCH! We spent an inordinate amount of effort in trying to understand the undocumented code/tree, but I am convinced that the device-tree approach to embedded boards is a very valuable approach, and will ultimately solve many more problems than it creates short term. Again, your information was of great assistance, and I look forward to being able to pay forward the same kind of assistance in the future. I'm very glad you found the issue (I was running out of ideas ;-) and that I was able to help you in some way. Thanks for posting back. Good luck with the rest of your project! Best regards, Thomas Cheers, Rob Sciuk. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/cpm: Clear muram before it is in use.
From: Hongjun Chen hong-jun.c...@freescale.com We need to ensure that MURAM is in a known and cleared out state before using it as the bootloader could have utilized it from its own purposes and left it in an unknown state. If we don't clear it out we've seen issues with UCC ethernet: * Multi ethernet interfaces can't work simultanously. * Multi up/down Ethernet interfaces will halt these ports. * UCC1 RGMII can't work when kernel boots from some hosts. Signed-off-by: Kai.Jiang kai.ji...@freescale.com Signed-off-by: Hongjun Chen hong-jun.c...@freescale.com Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- arch/powerpc/sysdev/cpm_common.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c index d55d0ad..8db10bb 100644 --- a/arch/powerpc/sysdev/cpm_common.c +++ b/arch/powerpc/sysdev/cpm_common.c @@ -3,7 +3,7 @@ * * Author: Scott Wood scottw...@freescale.com * - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007-2008,2010 Freescale Semiconductor, Inc. * * Some parts derived from commproc.c/cpm2_common.c, which is: * Copyright (c) 1997 Dan error_act (dma...@jlc.net) @@ -146,6 +146,7 @@ unsigned long cpm_muram_alloc(unsigned long size, unsigned long align) spin_lock_irqsave(cpm_muram_lock, flags); cpm_muram_info.alignment = align; start = rh_alloc(cpm_muram_info, size, commproc); + memset(cpm_muram_addr(start), 0, size); spin_unlock_irqrestore(cpm_muram_lock, flags); return start; -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 3/5][v2] fsl-rio: Add two ports and rapidio message units support
On Thu, Oct 13, 2011 at 10:09 AM, Kumar Gala wrote:
From: Liu Gang gang@freescale.com
Usually, freescale rapidio endpoint can support one 1X or two 4X LP-
Serial
link interfaces, and rapidio message transactions can be implemented
by
two
Is the number of 1x ports described correctly?
Can we have two 1x ports as well?
message units. This patch adds the support of two rapidio ports and
initializes message unit 0 and message unit 1. And these ports and
message
... skip ...
+
+ /* Probe the master port phy type */
+ ccsr = in_be32(priv-regs_win + RIO_CCSR + i*0x20);
+ port-phy_type = (ccsr 1) ? RIO_PHY_SERIAL :
RIO_PHY_PARALLEL;
+ dev_info(dev-dev, RapidIO PHY type: %s\n,
+ (port-phy_type == RIO_PHY_PARALLEL) ?
+ parallel :
+ ((port-phy_type == RIO_PHY_SERIAL) ?
serial
:
+ unknown));
+ /* Checking the port training status */
+ if (in_be32((priv-regs_win + RIO_ESCSR + i*0x20)) 1)
{
+ dev_err(dev-dev, Port %d is not ready.
+ Try to restart connection...\n, i);
+ switch (port-phy_type) {
+ case RIO_PHY_SERIAL:
+ /* Disable ports */
+ out_be32(priv-regs_win
+ + RIO_CCSR + i*0x20, 0);
+ /* Set 1x lane */
+ setbits32(priv-regs_win
+ + RIO_CCSR + i*0x20,
0x0200);
+ /* Enable ports */
+ setbits32(priv-regs_win
+ + RIO_CCSR + i*0x20,
0x0060);
+ break;
+ case RIO_PHY_PARALLEL:
+ /* Disable ports */
+ out_be32(priv-regs_win
+ + RIO_CCSR + i*0x20,
0x2200);
+ /* Enable ports */
+ out_be32(priv-regs_win
+ + RIO_CCSR + i*0x20,
0x4400);
+ break;
+ }
Probably this may be a good moment to drop the support for parallel
link.
Especially after you renamed controller to srio in the device tree.
+ msleep(100);
+ if (in_be32((priv-regs_win
+ + RIO_ESCSR + i*0x20)) 1) {
+ dev_err(dev-dev,
+ Port %d restart failed.\n, i);
+ release_resource(port-iores);
+ kfree(priv);
+ kfree(port);
+ continue;
+ }
+ dev_info(dev-dev, Port %d restart
success!\n, i);
+ }
+ fsl_rio_info(dev-dev, ccsr);
+
... skip ...
struct rio_msg_regs {
- u32 omr;/* 0xD_3000 - Outbound message 0 mode register
*/
- u32 osr;/* 0xD_3004 - Outbound message 0 status register
*/
+ u32 omr;
+ u32 osr;
u32 pad1;
- u32 odqdpar;/* 0xD_300C - Outbound message 0 descriptor
queue
-dequeue pointer address register */
+ u32 odqdpar;
u32 pad2;
- u32 osar; /* 0xD_3014 - Outbound message 0 source address
-register */
- u32 odpr; /* 0xD_3018 - Outbound message 0 destination
port
-register */
- u32 odatr; /* 0xD_301C - Outbound message 0 destination
attributes
-Register*/
- u32 odcr; /* 0xD_3020 - Outbound message 0 double-word
count
-register */
+ u32 osar;
+ u32 odpr;
+ u32 odatr;
+ u32 odcr;
u32 pad3;
- u32 odqepar;/* 0xD_3028 - Outbound message 0 descriptor
queue
-enqueue pointer address register */
+ u32 odqepar;
u32 pad4[13];
- u32 imr;/* 0xD_3060 - Inbound message 0 mode register */
- u32 isr;/* 0xD_3064 - Inbound message 0 status register
*/
+ u32 imr;
+ u32 isr;
u32 pad5;
- u32 ifqdpar;/* 0xD_306C - Inbound message 0 frame queue
dequeue
-pointer address register*/
+ u32 ifqdpar;
u32 pad6;
- u32 ifqepar;/* 0xD_3074 - Inbound message 0 frame queue
enqueue
-pointer address register */
- u32 pad7[226];
- u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */
- u32 odsr; /* 0xD_3404 - Outbound doorbell status register
*/
+ u32 ifqepar;
+ u32 pad7;
Do we need pad7 here?
+};
+
+struct rio_dbell_regs
RE: [PATCH] powerpc/85xx: Setup secondary cores PIR with hard SMP id
-Original Message- From: linuxppc-dev-bounces+bharat.bhushan=freescale@lists.ozlabs.org [mailto:linuxppc-dev- bounces+bharat.bhushan=freescale@lists.ozlabs.org] On Behalf Of Kumar Gala Sent: Friday, October 14, 2011 1:23 PM To: linuxppc-...@ozlabs.org Subject: [PATCH] powerpc/85xx: Setup secondary cores PIR with hard SMP id Normally logical and hard cpu ID are the same, however in same cases like on the P3060 they may differ. Where the logical is 0..5, the hard id goes 0,1,4..7. This can causes issues for places we utilize PIR to index into array like in debug exception handlers for finding the exception stack. Kumar, What should be the CONFIG_NR_CPUS for this? 8 or 6 ? Thanks -Bharat Move to setting up PIR with hard_smp_processor_id fixes the issue. Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- arch/powerpc/platforms/85xx/smp.c |9 + 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c index d6e4746..190d111 100644 --- a/arch/powerpc/platforms/85xx/smp.c +++ b/arch/powerpc/platforms/85xx/smp.c @@ -48,10 +48,11 @@ smp_85xx_kick_cpu(int nr) const u64 *cpu_rel_addr; __iomem u32 *bptr_vaddr; struct device_node *np; - int n = 0; + int n = 0, hw_cpu = get_hard_smp_processor_id(nr); int ioremappable; - WARN_ON (nr 0 || nr = NR_CPUS); + WARN_ON(nr 0 || nr = NR_CPUS); + WARN_ON(hw_cpu 0 || hw_cpu = NR_CPUS); pr_debug(smp_85xx_kick_cpu: kick CPU #%d\n, nr); @@ -79,7 +80,7 @@ smp_85xx_kick_cpu(int nr) local_irq_save(flags); - out_be32(bptr_vaddr + BOOT_ENTRY_PIR, nr); + out_be32(bptr_vaddr + BOOT_ENTRY_PIR, hw_cpu); #ifdef CONFIG_PPC32 out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start)); @@ -88,7 +89,7 @@ smp_85xx_kick_cpu(int nr) (ulong)(bptr_vaddr + SIZE_BOOT_ENTRY)); /* Wait a bit for the CPU to ack. */ - while ((__secondary_hold_acknowledge != nr) (++n 1000)) + while ((__secondary_hold_acknowledge != hw_cpu) (++n 1000)) mdelay(1); #else smp_generic_kick_cpu(nr); -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/85xx: Setup secondary cores PIR with hard SMP id
On Oct 19, 2011, at 10:53 PM, Bhushan Bharat-R65777 wrote: -Original Message- From: linuxppc-dev-bounces+bharat.bhushan=freescale@lists.ozlabs.org [mailto:linuxppc-dev- bounces+bharat.bhushan=freescale@lists.ozlabs.org] On Behalf Of Kumar Gala Sent: Friday, October 14, 2011 1:23 PM To: linuxppc-...@ozlabs.org Subject: [PATCH] powerpc/85xx: Setup secondary cores PIR with hard SMP id Normally logical and hard cpu ID are the same, however in same cases like on the P3060 they may differ. Where the logical is 0..5, the hard id goes 0,1,4..7. This can causes issues for places we utilize PIR to index into array like in debug exception handlers for finding the exception stack. Kumar, What should be the CONFIG_NR_CPUS for this? 8 or 6 ? 8. - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] powerpc/85xx: Setup secondary cores PIR with hard SMP id
-Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Thursday, October 20, 2011 9:32 AM To: Bhushan Bharat-R65777 Cc: linuxppc-...@ozlabs.org Subject: Re: [PATCH] powerpc/85xx: Setup secondary cores PIR with hard SMP id On Oct 19, 2011, at 10:53 PM, Bhushan Bharat-R65777 wrote: -Original Message- From: linuxppc-dev-bounces+bharat.bhushan=freescale@lists.ozlabs.org [mailto:linuxppc-dev- bounces+bharat.bhushan=freescale@lists.ozlabs.org] On Behalf Of bounces+Kumar Gala Sent: Friday, October 14, 2011 1:23 PM To: linuxppc-...@ozlabs.org Subject: [PATCH] powerpc/85xx: Setup secondary cores PIR with hard SMP id Normally logical and hard cpu ID are the same, however in same cases like on the P3060 they may differ. Where the logical is 0..5, the hard id goes 0,1,4..7. This can causes issues for places we utilize PIR to index into array like in debug exception handlers for finding the exception stack. Kumar, What should be the CONFIG_NR_CPUS for this? 8 or 6 ? 8. Kumar, I am just trying to understand the impact of setting NR_CPUS = 8 while actual cpus are 6 only. If I understood correctly, cpu_present, cpu_online are logical cpuid bit map. Also the PACA is allocated for nr_cpu_ids (NR_CPUS) and also indexed by logical cpuid. While they have knowledge of physical_cpuid. So in this case last two entries of PACA will not be used or wasted? I am not sure I am missing something here? Thanks -Bharat ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
