Re: [PATCH 00/14] Backport 8xx TLB to 2.4
Willy Tarreau w...@1wt.eu wrote on 2011/12/11 18:33:46: Hi Joakim, On Sun, Dec 11, 2011 at 06:19:54PM +0100, Joakim Tjernlund wrote: To: Joakim Tjernlund joakim.tjernl...@transmode.se From: Willy Tarreau w...@1wt.eu Hi Joakim, On Mon, Oct 10, 2011 at 01:30:06PM +0200, Joakim Tjernlund wrote: This is a backport from 2.6 which I did to overcome 8xx CPU bugs. 8xx does not update the DAR register when taking a TLB error caused by dcbX and icbi insns which makes it very tricky to use these insns. Also the dcbst wrongly sets the the store bit when faulting into DTLB error. A few more bugs very found during development.I know 2.4 is in strict maintenance mode and 8xx is obsolete but as it is still in use I wanted 8xx to age with grace. Thank you. I must admit I was hoping those patches would come in for a last release before the end of the year :-) Unless there is any objection from anyone, I'll merge them when kernel.org is back online. Cheers, Willy Did this go anywhere? Not yet, I just need to find some time to release another 2.4 with these patches. Ping? There should be a tree somewhere by now :) Jocke ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2] powerpc/85xx: Change style of partition nodes in dts for MPC8572DS
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Jia Hongtao b38...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/boot/dts/mpc8572ds.dtsi | 44 --
1 files changed, 26 insertions(+), 18 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dtsi
b/arch/powerpc/boot/dts/mpc8572ds.dtsi
index c3d4fac..e10fa61 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8572ds.dtsi
@@ -41,37 +41,41 @@
bank-width = 2;
device-width = 1;
- ramdisk@0 {
+ partition@0 {
reg = 0x0 0x0300;
- read-only;
+ label = ramdisk-nor;
};
- diagnostic@300 {
+ partition@300 {
reg = 0x0300 0x00e0;
+ label = diagnostic-nor;
read-only;
};
- dink@3e0 {
+ partition@3e0 {
reg = 0x03e0 0x0020;
+ label = dink-nor;
read-only;
};
- kernel@400 {
+ partition@400 {
reg = 0x0400 0x0040;
- read-only;
+ label = kernel-nor;
};
- jffs2@440 {
+ partition@440 {
reg = 0x0440 0x03b0;
+ label = fs-nor;
};
- dtb@7f0 {
+ partition@7f0 {
reg = 0x07f0 0x0008;
- read-only;
+ label = dtb-nor;
};
- u-boot@7f8 {
+ partition@7f8 {
reg = 0x07f8 0x0008;
+ label = u-boot-nor;
read-only;
};
};
@@ -83,31 +87,35 @@
fsl,elbc-fcm-nand;
reg = 0x2 0x0 0x4;
- u-boot@0 {
+ partition@0 {
reg = 0x0 0x0200;
+ label = u-boot-nand;
read-only;
};
- jffs2@200 {
+ partition@200 {
reg = 0x0200 0x1000;
+ label = fs-nand;
};
- ramdisk@1200 {
+ partition@1200 {
reg = 0x1200 0x0800;
- read-only;
+ label = ramdisk-nand;
};
- kernel@1a00 {
+ partition@1a00 {
reg = 0x1a00 0x0400;
+ label = kernel-nand;
};
- dtb@1e00 {
+ partition@1e00 {
reg = 0x1e00 0x0100;
- read-only;
+ label = dtb-nand;
};
- empty@1f00 {
+ partition@1f00 {
reg = 0x1f00 0x2100;
+ label = empty-nand;
};
};
--
1.7.5.1
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[PATCH 2/2] powerpc/85xx: update SEC node in dts for MPC8572DS
Add sec3.1 support Signed-off-by: Jin Qing b24...@freescale.com Signed-off-by: Zhao Chenhui b35...@freescale.com Signed-off-by: Jia Hongtao b38...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi index d44e25a..cdda34f 100644 --- a/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi @@ -184,7 +184,7 @@ /include/ pq3-etsec1-1.dtsi /include/ pq3-etsec1-2.dtsi /include/ pq3-etsec1-3.dtsi -/include/ pq3-sec3.0-0.dtsi +/include/ pq3-sec3.1-0.dtsi /include/ pq3-mpic.dtsi /include/ pq3-mpic-timer-B.dtsi -- 1.7.5.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/2 v2] powerpc: Abstract common define of signal multiplex control for qe
From: Zhicheng Fan b32...@freeescale.com
The mpc85xx_rdb and mpc85xx_mds have commom define of signal multiplex for qe
,so
they need to go in common header, the patch abstract them to fsl_guts.h
Signed-off-by: Zhicheng Fan b32...@freeescale.com
---
arch/powerpc/include/asm/fsl_guts.h | 19 +++
arch/powerpc/platforms/85xx/mpc85xx_mds.c |7 ++-
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_guts.h
b/arch/powerpc/include/asm/fsl_guts.h
index bebd124..efacfe3 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -114,6 +114,25 @@ struct ccsr_guts_86xx {
__be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
} __attribute__ ((packed));
+#ifdef CONFIG_PPC_85xx
+
+/* Alternate function signal multiplex control */
+#define MPC85xx_PMUXCR_OFFSET 0x60
+#define MPC85xx_PMUXCR_QE0 0x8000
+#define MPC85xx_PMUXCR_QE2 0x2000
+#define MPC85xx_PMUXCR_QE3 0x1000
+#define MPC85xx_PMUXCR_QE4 0x0800
+#define MPC85xx_PMUXCR_QE5 0x0400
+#define MPC85xx_PMUXCR_QE6 0x0200
+#define MPC85xx_PMUXCR_QE7 0x0100
+#define MPC85xx_PMUXCR_QE8 0x0080
+#define MPC85xx_PMUXCR_QE9 0x0040
+#define MPC85xx_PMUXCR_QE10 0x0020
+#define MPC85xx_PMUXCR_QE11 0x0010
+#define MPC85xx_PMUXCR_QE12 0x0008
+
+#endif
+
#ifdef CONFIG_PPC_86xx
#define CCSR_GUTS_DMACR_DEV_SSI0 /* DMA controller/channel set
to SSI */
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 1d15a0c..1bd339a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -51,6 +51,7 @@
#include asm/qe_ic.h
#include asm/mpic.h
#include asm/swiotlb.h
+#include asm/fsl_guts.h
#include smp.h
#include mpc85xx.h
@@ -268,11 +269,7 @@ static void __init mpc85xx_mds_qe_init(void)
mpc85xx_mds_reset_ucc_phys();
if (machine_is(p1021_mds)) {
-#define MPC85xx_PMUXCR_OFFSET 0x60
-#define MPC85xx_PMUXCR_QE0 0x8000
-#define MPC85xx_PMUXCR_QE3 0x1000
-#define MPC85xx_PMUXCR_QE9 0x0040
-#define MPC85xx_PMUXCR_QE12 0x0008
+
static __be32 __iomem *pmuxcr;
np = of_find_node_by_name(NULL, global-utilities);
--
1.7.0.4
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[PATCH 1/2 v2] P1025RDB: Add Quicc Engine support
From: Zhicheng Fan b32...@freeescale.com
Signed-off-by: Zhicheng Fan b32...@freeescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 80 -
1 files changed, 79 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 1950076..4c27b3b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -26,6 +26,9 @@
#include asm/prom.h
#include asm/udbg.h
#include asm/mpic.h
+#include asm/qe.h
+#include asm/qe_ic.h
+#include asm/fsl_guts.h
#include sysdev/fsl_soc.h
#include sysdev/fsl_pci.h
@@ -47,6 +50,10 @@ void __init mpc85xx_rdb_pic_init(void)
struct mpic *mpic;
unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_QUICC_ENGINE
+ struct device_node *np;
+#endif
+
if (of_flat_dt_is_compatible(root, fsl,MPC85XXRDB-CAMP)) {
mpic = mpic_alloc(NULL, 0,
MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
@@ -62,6 +69,18 @@ void __init mpc85xx_rdb_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
+ if (np) {
+ qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+ qe_ic_cascade_high_mpic);
+ of_node_put(np);
+
+ } else
+ pr_err(Could not find qe-ic node\n);
+#endif
+
}
/*
@@ -69,7 +88,7 @@ void __init mpc85xx_rdb_pic_init(void)
*/
static void __init mpc85xx_rdb_setup_arch(void)
{
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
struct device_node *np;
#endif
@@ -85,6 +104,65 @@ static void __init mpc85xx_rdb_setup_arch(void)
#endif
mpc85xx_smp_init();
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, fsl,qe);
+ if (!np) {
+ pr_err(Could not find Quicc Engine node\n);
+ goto qe_fail;
+ }
+
+ qe_reset();
+ of_node_put(np);
+
+ np = of_find_node_by_name(NULL, par_io);
+ if (np) {
+ struct device_node *ucc;
+
+ par_io_init(np);
+ of_node_put(np);
+
+ for_each_node_by_name(ucc, ucc)
+ par_io_of_config(ucc);
+
+ }
+ if (machine_is(p1025_rdb)) {
+
+ __be32 __iomem *pmuxcr;
+
+ np = of_find_node_by_name(NULL, global-utilities);
+
+ if (np) {
+ pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
+
+ if (!pmuxcr)
+ pr_err(KERN_EMERG Error: Alternate function
+signal multiplex control register not
+mapped!\n);
+ else {
+#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
+ /* P1025 has pins muxed for QE and other functions. To
+ * enable QE UEC mode, we need to set bit QE0 for UCC1
+ * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
+ * and QE12 for QE MII management singals in PMUXCR
+ * register.
+ */
+ setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
+ MPC85xx_PMUXCR_QE3 |
+ MPC85xx_PMUXCR_QE9 |
+ MPC85xx_PMUXCR_QE12);
+#endif
+ }
+
+ iounmap(pmuxcr);
+ of_node_put(np);
+ }
+
+ }
+
+qe_fail:
+#endif /* CONFIG_QUICC_ENGINE */
+
printk(KERN_INFO MPC85xx RDB board from Freescale Semiconductor\n);
}
--
1.7.0.4
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Re: [PATCH 00/14] Backport 8xx TLB to 2.4
Hi Joakim, On Wed, Feb 08, 2012 at 09:44:18AM +0100, Joakim Tjernlund wrote: Willy Tarreau w...@1wt.eu wrote on 2011/12/11 18:33:46: Hi Joakim, On Sun, Dec 11, 2011 at 06:19:54PM +0100, Joakim Tjernlund wrote: To: Joakim Tjernlund joakim.tjernl...@transmode.se From: Willy Tarreau w...@1wt.eu Hi Joakim, On Mon, Oct 10, 2011 at 01:30:06PM +0200, Joakim Tjernlund wrote: This is a backport from 2.6 which I did to overcome 8xx CPU bugs. 8xx does not update the DAR register when taking a TLB error caused by dcbX and icbi insns which makes it very tricky to use these insns. Also the dcbst wrongly sets the the store bit when faulting into DTLB error. A few more bugs very found during development.I know 2.4 is in strict maintenance mode and 8xx is obsolete but as it is still in use I wanted 8xx to age with grace. Thank you. I must admit I was hoping those patches would come in for a last release before the end of the year :-) Unless there is any objection from anyone, I'll merge them when kernel.org is back online. Cheers, Willy Did this go anywhere? Not yet, I just need to find some time to release another 2.4 with these patches. Ping? There should be a tree somewhere by now :) I'm planning on doing 2.4.37.12 once I'm finished with 2.6.27.60. However I'll have to find another place to host it, as the 2.4 tree was never completely recovered from master.kernel.org after the break-in, and admins there have many more important things to do than to spend their time restoring the 2.4 files. Probably that I'll put that into my account. BTW, since you're asking, you seem to still be using 2.4. Do you think it's worth pursuing maintenance over 2.4.37.12 and if so for how long ? I'm asking because until the break-in, I felt like almost nobody was using it anymore, but since the break-in, I received a number of mails asking where to download it. So now I assume that there are still users, but they're too much silent. Regards, Willy ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 00/14] Backport 8xx TLB to 2.4
Willy Tarreau w...@1wt.eu wrote on 2012/02/08 10:44:26: Hi Joakim, On Wed, Feb 08, 2012 at 09:44:18AM +0100, Joakim Tjernlund wrote: Willy Tarreau w...@1wt.eu wrote on 2011/12/11 18:33:46: Hi Joakim, On Sun, Dec 11, 2011 at 06:19:54PM +0100, Joakim Tjernlund wrote: To: Joakim Tjernlund joakim.tjernl...@transmode.se From: Willy Tarreau w...@1wt.eu Hi Joakim, On Mon, Oct 10, 2011 at 01:30:06PM +0200, Joakim Tjernlund wrote: This is a backport from 2.6 which I did to overcome 8xx CPU bugs. 8xx does not update the DAR register when taking a TLB error caused by dcbX and icbi insns which makes it very tricky to use these insns. Also the dcbst wrongly sets the the store bit when faulting into DTLB error. A few more bugs very found during development.I know 2.4 is in strict maintenance mode and 8xx is obsolete but as it is still in use I wanted 8xx to age with grace. Thank you. I must admit I was hoping those patches would come in for a last release before the end of the year :-) Unless there is any objection from anyone, I'll merge them when kernel.org is back online. Cheers, Willy Did this go anywhere? Not yet, I just need to find some time to release another 2.4 with these patches. Ping? There should be a tree somewhere by now :) I'm planning on doing 2.4.37.12 once I'm finished with 2.6.27.60. However I'll have to find another place to host it, as the 2.4 tree was never completely recovered from master.kernel.org after the break-in, and admins there have many more important things to do than to spend their time restoring the 2.4 files. Probably that I'll put that into my account. I see. BTW, since you're asking, you seem to still be using 2.4. Do you think it's worth pursuing maintenance over 2.4.37.12 and if so for how long ? I'm asking because until the break-in, I felt like almost nobody was using it anymore, but since the break-in, I received a number of mails asking where to download it. So now I assume that there are still users, but they're too much silent. yes, they are silent I guess. I figure, after 2.4.37.12, a public git tree on kernel org which still receives fixes would be enough. Jocke ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 00/14] Backport 8xx TLB to 2.4
On Wed, Feb 08, 2012 at 12:39:50PM +0100, Joakim Tjernlund wrote: BTW, since you're asking, you seem to still be using 2.4. Do you think it's worth pursuing maintenance over 2.4.37.12 and if so for how long ? I'm asking because until the break-in, I felt like almost nobody was using it anymore, but since the break-in, I received a number of mails asking where to download it. So now I assume that there are still users, but they're too much silent. yes, they are silent I guess. I figure, after 2.4.37.12, a public git tree on kernel org which still receives fixes would be enough. That's probably a good idea indeed. It avoids the need for a release for a single patch and still allows people to pick patches when they intend to build something. Regards, Willy ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2 ] Implement GET_IP/SET_IP for powerpc architecture.
With this change, helpers such as instruction_pointer() et al, get defined
in the generic header in terms of GET_IP
Removed the unnecessary definition of profile_pc in !CONFIG_SMP case as
suggested by Mike Frysinger.
Signed-off-by: Srikar Dronamraju sri...@linux.vnet.ibm.com
Signed-off-by: Ananth N Mavinakayanahalli ana...@in.ibm.com
---
arch/powerpc/include/asm/ptrace.h | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/ptrace.h
b/arch/powerpc/include/asm/ptrace.h
index 78a2051..84cc784 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -83,8 +83,18 @@ struct pt_regs {
#ifndef __ASSEMBLY__
-#define instruction_pointer(regs) ((regs)-nip)
-#define user_stack_pointer(regs) ((regs)-gpr[1])
+#define GET_IP(regs) ((regs)-nip)
+#define GET_USP(regs) ((regs)-gpr[1])
+#define GET_FP(regs) (0)
+#define SET_FP(regs, val)
+
+#ifdef CONFIG_SMP
+extern unsigned long profile_pc(struct pt_regs *regs);
+#define profile_pc profile_pc
+#endif
+
+#include asm-generic/ptrace.h
+
#define kernel_stack_pointer(regs) ((regs)-gpr[1])
static inline int is_syscall_success(struct pt_regs *regs)
{
@@ -99,12 +109,6 @@ static inline long regs_return_value(struct pt_regs *regs)
return -regs-gpr[3];
}
-#ifdef CONFIG_SMP
-extern unsigned long profile_pc(struct pt_regs *regs);
-#else
-#define profile_pc(regs) instruction_pointer(regs)
-#endif
-
#ifdef __powerpc64__
#define user_mode(regs) regs)-msr) MSR_PR_LG) 0x1)
#else
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Re: [PATCH 09/24] PCI, powerpc: Register busn_res for root buses
On Sat, Feb 4, 2012 at 10:57 PM, Yinghai Lu ying...@kernel.org wrote:
Signed-off-by: Yinghai Lu ying...@kernel.org
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Paul Mackerras pau...@samba.org
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/kernel/pci-common.c | 7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/pci-common.c
b/arch/powerpc/kernel/pci-common.c
index cce98d7..501f29b 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -1732,6 +1732,8 @@ void __devinit pcibios_scan_phb(struct pci_controller
*hose)
bus-secondary = hose-first_busno;
hose-bus = bus;
+ pci_bus_insert_busn_res(bus, hose-first_busno, hose-last_busno);
+
/* Get probe mode and perform scan */
mode = PCI_PROBE_NORMAL;
if (node ppc_md.pci_probe_mode)
@@ -1742,8 +1744,11 @@ void __devinit pcibios_scan_phb(struct pci_controller
*hose)
of_scan_bus(node, bus);
}
- if (mode == PCI_PROBE_NORMAL)
+ if (mode == PCI_PROBE_NORMAL) {
+ pci_bus_update_busn_res_end(bus, 255);
hose-last_busno = bus-subordinate = pci_scan_child_bus(bus);
+ pci_bus_update_busn_res_end(bus, bus-subordinate);
+ }
The only architecture-specific thing here is discovering the range of
bus numbers below a host bridge. The architecture should not have to
mess around with pci_bus_update_busn_res_end() like this. It should
be able to say here's my bus number range (and of course the PCI
core can default to 0-255 if the arch doesn't supply a range) and the
core should take care of the rest.
Bjorn
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Re: [linuxppc-release] [PATCH 1/2] powerpc/85xx: Change style of partition nodes in dts for MPC8572DS
Jia Hongtao wrote: - read-only; + label = ramdisk-nor; This is not a style change. Please explain this patch better. -- Timur Tabi Linux kernel developer at Freescale ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [linuxppc-release] [PATCH 2/2] powerpc/85xx: update SEC node in dts for MPC8572DS
Jia Hongtao wrote: Add sec3.1 support Signed-off-by: Jin Qing b24...@freescale.com Signed-off-by: Zhao Chenhui b35...@freescale.com Signed-off-by: Jia Hongtao b38...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi index d44e25a..cdda34f 100644 --- a/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi @@ -184,7 +184,7 @@ /include/ pq3-etsec1-1.dtsi /include/ pq3-etsec1-2.dtsi /include/ pq3-etsec1-3.dtsi -/include/ pq3-sec3.0-0.dtsi +/include/ pq3-sec3.1-0.dtsi This is not adding SEC 3.1 support. This patch is saying that the 8572 DTS was using the *wrong* SEC version. If that's true, you need to explain why it was wrong. -- Timur Tabi Linux kernel developer at Freescale ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 09/24] PCI, powerpc: Register busn_res for root buses
On Wed, Feb 8, 2012 at 7:58 AM, Bjorn Helgaas bhelg...@google.com wrote:
On Sat, Feb 4, 2012 at 10:57 PM, Yinghai Lu ying...@kernel.org wrote:
Signed-off-by: Yinghai Lu ying...@kernel.org
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Paul Mackerras pau...@samba.org
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/kernel/pci-common.c | 7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/pci-common.c
b/arch/powerpc/kernel/pci-common.c
index cce98d7..501f29b 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -1732,6 +1732,8 @@ void __devinit pcibios_scan_phb(struct pci_controller
*hose)
bus-secondary = hose-first_busno;
hose-bus = bus;
+ pci_bus_insert_busn_res(bus, hose-first_busno, hose-last_busno);
+
/* Get probe mode and perform scan */
mode = PCI_PROBE_NORMAL;
if (node ppc_md.pci_probe_mode)
@@ -1742,8 +1744,11 @@ void __devinit pcibios_scan_phb(struct pci_controller
*hose)
of_scan_bus(node, bus);
}
- if (mode == PCI_PROBE_NORMAL)
+ if (mode == PCI_PROBE_NORMAL) {
+ pci_bus_update_busn_res_end(bus, 255);
hose-last_busno = bus-subordinate = pci_scan_child_bus(bus);
+ pci_bus_update_busn_res_end(bus, bus-subordinate);
+ }
The only architecture-specific thing here is discovering the range of
bus numbers below a host bridge. The architecture should not have to
mess around with pci_bus_update_busn_res_end() like this. It should
be able to say here's my bus number range (and of course the PCI
core can default to 0-255 if the arch doesn't supply a range) and the
core should take care of the rest.
during the pci_scan_child_bus, child bus busn_res will be inserted
under parent bus busn_res.
So need to make sure parent busn_res.end is bigger enough.
Yinghai
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Re: tlb flushing on Power
Hey Ben, Thanks for responding. On 01/26/2012 03:39 PM, Benjamin Herrenschmidt wrote: On Thu, 2012-01-26 at 08:41 -0600, Brian King wrote: CC'ing linuxppc-dev... On 01/26/2012 08:18 AM, Seth Jennings wrote: Hey Dave, So I submitted the zsmalloc patches to lkml at the beginning of the year https://lkml.org/lkml/2012/1/9/389 I found there are two functions Nitin used in the mapping functions that are not supported in the powerpc arch: set_pte() and __flush_tlb_one(). .../... The arch management of page tables can be tricky indeed :-) I need to have a better understanding of what you are doing to see how I can try to adapt it to power. You can look at https://lkml.org/lkml/2012/1/9/389 in zsmalloc-main.c, zs_[un]map_object() functions for the currently uses of set_pte() and __flush_tlb_one(). set_pte() is long gone on all archs really (or if it's still there it's not meant to be used as is), use set_pte_at(). Problem with set_pte_at() for us is that we don't have an mm_struct to pass because the mapping is not for a userspace process but for the kernel itself. However, I do think this is the portable function we need to be using. Just need to figure out what to pass in for the mm_struct param. __flush_tlb_one() doesn't mean anything as an arch independent functionality. We have a local_flush_tlb_page() that -might- do what you want but why in hell is that patch not using proper existing interfaces ? flush_tlb_page() is the portable function we should be using. However, again, it requires a vma_area_struct. I'm not sure what we should be passing there. -- Seth ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [linuxppc-release] [PATCH 2/2] powerpc/85xx: update SEC node in dts for MPC8572DS
On Wed, 8 Feb 2012 10:39:43 -0600 Timur Tabi ti...@freescale.com wrote: Jia Hongtao wrote: -/include/ pq3-sec3.0-0.dtsi +/include/ pq3-sec3.1-0.dtsi This is not adding SEC 3.1 support. This patch is saying that the 8572 DTS was using the *wrong* SEC version. If that's true, you need to explain why it was wrong. especially since, and according to MPC8572E PowerQUICCTM III Integrated Host Processor Family Reference Manual, Rev. 2, the 8572 has a SEC 3.0. Kim ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: tlb flushing on Power
You can look at https://lkml.org/lkml/2012/1/9/389 in zsmalloc-main.c, zs_[un]map_object() functions for the currently uses of set_pte() and __flush_tlb_one(). set_pte() is long gone on all archs really (or if it's still there it's not meant to be used as is), use set_pte_at(). Problem with set_pte_at() for us is that we don't have an mm_struct to pass because the mapping is not for a userspace process but for the kernel itself. Then use init_mm However, I do think this is the portable function we need to be using. Just need to figure out what to pass in for the mm_struct param. __flush_tlb_one() doesn't mean anything as an arch independent functionality. We have a local_flush_tlb_page() that -might- do what you want but why in hell is that patch not using proper existing interfaces ? flush_tlb_page() is the portable function we should be using. However, again, it requires a vma_area_struct. I'm not sure what we should be passing there. Do you need this to be CPU local flush or global ? In the later, flush_tlb_kernel_range() is the right API. If you want per-cpu, we'll have to add a new arch hook. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 09/24] PCI, powerpc: Register busn_res for root buses
On Wed, 2012-02-08 at 07:58 -0800, Bjorn Helgaas wrote: The only architecture-specific thing here is discovering the range of bus numbers below a host bridge. The architecture should not have to mess around with pci_bus_update_busn_res_end() like this. It should be able to say here's my bus number range (and of course the PCI core can default to 0-255 if the arch doesn't supply a range) and the core should take care of the rest. So it's a bit messy in here because we deal with several things. What the firmware gives us is the range it assigned, but that isn't necessarily the HW limits (almost never is in fact). In some cases we honor it, for example when in probe only mode where we prevent any reassigning, and in some case, we ignore it and let the PCI core renumber things (typically because the FW forgot to set aside bus numbers for a cardbus slot for example, that sort of things). So it's a bit of a tricky situation. Off the top of my head, I'm pretty sure that most if not all of our PCI host bridges simply support a full 0...255 range and there is no sharing between bridges like on x86, they are just different domains. But I can't vouch 100% for some of the oddball cases like Pegasos or some freescale gear. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2 ] Implement GET_IP/SET_IP for powerpc architecture.
Acked-by: Mike Frysinger vap...@gentoo.org -mike signature.asc Description: This is a digitally signed message part. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/wsp: Fix IRQ affinity setting
We call the cache_hwirq_map() function with a linux IRQ number
but it expects a HW irq number. This triggers a BUG on multic-chip
setups in addition to not doing the right thing.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/platforms/wsp/ics.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/wsp/ics.c b/arch/powerpc/platforms/wsp/ics.c
index 5768743..97fe82e 100644
--- a/arch/powerpc/platforms/wsp/ics.c
+++ b/arch/powerpc/platforms/wsp/ics.c
@@ -346,7 +346,7 @@ static int wsp_chip_set_affinity(struct irq_data *d,
* For the moment only implement delivery to all cpus or one cpu.
* Get current irq_server for the given irq
*/
- ret = cache_hwirq_map(ics, d-irq, cpumask);
+ ret = cache_hwirq_map(ics, hw_irq, cpumask);
if (ret == -1) {
char cpulist[128];
cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask);
--
1.7.7.3
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[PATCH v2] powerpc: Rework lazy-interrupt handling
From 0ace17ba6960a8788b1bda3770df254cbbc6a244 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt b...@kernel.crashing.org Date: Thu, 9 Feb 2012 15:25:04 +1100 Subject: [PATCH] powerpc: Rework lazy-interrupt handling The current implementation of lazy interrupts handling has some issues that this tries to address. Except on iSeries, we don't do the various workarounds we need to do on re-enable when returning from an interrupt, which can do an implicit re-enable, and thus we may still lose or get delayed decrementer or doorbell interrupts. The current scheme also makes it much harder to handle the external edge interrupts provided by some BookE processors when using the EPR facility (External Proxy) and the Freescale Hypervisor. We also hard mask on decrementer interrupts which is sub-optimal. This is an attempt at fixing it all in one go by reworking the way we do the lazy interrupt disabling. The base idea is to replace the hard_enabled field with a irq_happened field in which we store a bit mask of what interrupt occurred while soft-disabled. When re-enabling, either via arch_local_irq_restore() or when returning from an interrupt, we can now decide what to do by testing bits in that field. We then implement re-emitting of the lost interrupts via either a re-use of the existing exception frame (exception exit case) or via the creation of a new one from assembly code (arch_local_irq_enable), without the need to trigger a fake one using set_dec() or similar. In addition, this adds a few refinements: - We no longer hard disable decrementer interrupts that occur while soft-disabled. We now simply bump the decrementer back to max (on BookS) or leave it stopped (on BookE) and continue with hard interrupts enabled, which means that we'll potentially get better sample quality from performance monitor interrupts. - Timer, decrementer and doorbell interrupts now hard-enable shortly after removing the source of the interrupt, which means they no longer run entirely hard disabled. Again, this will improve perf sample quality. - On Book3E 64-bit, we now make the performance monitor interrupt act as an NMI like Book3S (the necessary C code for that to work appear to already be present in the FSL perf code, notably calling nmi_enter instead of irq_enter). There are additional refinements that we can do on top of this patch: - We could remove the ps3 workaround from arch_local_irq_enable(), I believe that it should no longer be necessary - We could make masked decrementer interrupts act as NMIs when doing timer-based perf sampling to improve the sample quality. - There are additional simplifications of the exception entry/exit path that I've spotted along the way, such as merging fast_exception_return with the normal code path. This patch needs a LOT more testing review than it had so far !!! Not-signed-off-by-yet: Benjamin Herrenschmidt b...@kernel.crashing.org --- v2: - Add hard-enable to decrementer, timer and doorbells - Fix CR clobber in masked irq handling on BookE - Make embedded perf interrupt act as an NMI - Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want to retrigger an interrupt without preventing hard-enable Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org --- arch/powerpc/include/asm/exception-64s.h| 21 ++- arch/powerpc/include/asm/hw_irq.h | 51 +- arch/powerpc/include/asm/irqflags.h | 13 +- arch/powerpc/include/asm/paca.h |2 +- arch/powerpc/kernel/asm-offsets.c |2 +- arch/powerpc/kernel/dbell.c | 12 ++ arch/powerpc/kernel/entry_64.S | 96 ++- arch/powerpc/kernel/exceptions-64e.S| 210 --- arch/powerpc/kernel/exceptions-64s.S| 90 ++ arch/powerpc/kernel/head_64.S |9 - arch/powerpc/kernel/idle_book3e.S |8 +- arch/powerpc/kernel/idle_power4.S | 17 ++- arch/powerpc/kernel/idle_power7.S | 20 ++- arch/powerpc/kernel/irq.c | 187 ++-- arch/powerpc/kernel/time.c | 15 ++- arch/powerpc/platforms/iseries/Makefile |2 +- arch/powerpc/platforms/iseries/exception.S | 11 +- arch/powerpc/platforms/iseries/misc.S | 26 --- arch/powerpc/platforms/pseries/processor_idle.c | 24 +++- 19 files changed, 540 insertions(+), 276 deletions(-) delete mode 100644 arch/powerpc/platforms/iseries/misc.S diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index 8057f4f..b3f42e9 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -232,23 +232,24 @@ label##_hv: \ EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common,\ EXC_HV, KVMTEST, vec)
[PATCH] powerpc: Fix WARN_ON in decrementer_check_overflow
We use __get_cpu_var() which triggers a false positive warning
in smp_processor_id() thinking interrupts are enabled (at this
point, they are soft-enabled but hard-disabled).
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
I was initially planning to fix that with a more in-depth rework
of how we do lazy irq disabling on powerpc, but that patch is
becoming too complex for this release so I'll apply this as a
stop-gap and leave the full rework for -next
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 701d4ac..01e2877 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -118,10 +118,14 @@ static inline notrace void set_soft_enabled(unsigned long
enable)
static inline notrace void decrementer_check_overflow(void)
{
u64 now = get_tb_or_rtc();
- u64 *next_tb = __get_cpu_var(decrementers_next_tb);
+ u64 *next_tb;
+
+ preempt_disable();
+ next_tb = __get_cpu_var(decrementers_next_tb);
if (now = *next_tb)
set_dec(1);
+ preempt_enable();
}
notrace void arch_local_irq_restore(unsigned long en)
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[PATCH 1/2 v4] powerpc/85xx: Add p1020rdb-pc platform support
From: Zhicheng Fan b32...@freeescale.com
Signed-off-by: Zhicheng Fan b32...@freeescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 26 +-
1 files changed, 25 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index dce8aaf..a0b9c92 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -1,7 +1,7 @@
/*
* MPC85xx RDB Board Setup
*
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009,2012 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -168,10 +168,20 @@ qe_fail:
machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices);
machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices);
+machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
/*
* Called very early, device-tree isn't unflattened
*/
+static int __init p1020_rdb_pc_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, fsl,P1020RDB-PC))
+ return 1;
+ return 0;
+}
+
static int __init p2020_rdb_probe(void)
{
unsigned long root = of_get_flat_dt_root();
@@ -217,3 +227,17 @@ define_machine(p1020_rdb) {
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
+
+define_machine(p1020_rdb_pc) {
+ .name = P1020RDB-PC,
+ .probe = p1020_rdb_pc_probe,
+ .setup_arch = mpc85xx_rdb_setup_arch,
+ .init_IRQ = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq= mpic_get_irq,
+ .restart= fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.7.0.4
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[PATCH 2/2 v4] powerpc/dts: Add dts for p1020rdb-pc board
From: Zhicheng Fan b32...@freeescale.com
P1020RDB-PC Overview
--
1Gbyte DDR3 SDRAM
32 Mbyte NAND flash
10 16Mbyte NOR flash
16 Mbyte SPI flash
SD connector to interface with the SD memory card
Real-time clock on I2C bus
PCIe:
- x1 PCIe slot
- x1 mini-PCIe slot
10/100/1000 BaseT Ethernet ports:
- eTSEC1, RGMII: one 10/100/1000 port using VitesseTM VSC7385 L2 switch
- eTSEC2, SGMII: one 10/100/1000 port using VitesseTM VSC8221
- eTSEC3, RGMII: one 10/100/1000 port using AtherosTM AR8021
USB 2.0 port:
- Two USB2.0 Type A receptacles
- One USB2.0 signal to Mini PCIe slot
Dual RJ45 UART ports:
- DUART interface: supports two UARTs up to 115200 bps for console display
Signed-off-by: Zhicheng Fan b32...@freeescale.com
---
arch/powerpc/boot/dts/p1020rdb-pc.dts| 90
arch/powerpc/boot/dts/p1020rdb-pc.dtsi | 247 ++
arch/powerpc/boot/dts/p1020rdb-pc_36b.dts| 90
arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts | 64 ++
arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts | 142 +
5 files changed, 633 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc.dtsi
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_36b.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc.dts
b/arch/powerpc/boot/dts/p1020rdb-pc.dts
new file mode 100644
index 000..5c333b0
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc.dts
@@ -0,0 +1,90 @@
+/*
+ * P1020 RDB-PC Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/p1020si-pre.dtsi
+/ {
+ model = fsl,P1020RDB-PC;
+ compatible = fsl,P1020RDB-PC;
+
+ memory {
+ device_type = memory;
+ };
+
+ lbc: localbus@ffe05000 {
+ reg = 0 0xffe05000 0 0x1000;
+
+ /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
+ ranges = 0x0 0x0 0x0 0xef00 0x0100
+ 0x1 0x0 0x0 0xff80 0x0004
+ 0x2 0x0 0x0 0xffb0 0x0002
+ 0x3 0x0 0x0 0xffa0 0x0002;
+ };
+
+ soc: soc@ffe0 {
+ ranges = 0x0 0x0 0xffe0 0x10;
+ };
+
+ pci0: pcie@ffe09000 {
+ ranges = 0x200 0x0 0xa000 0 0xa000 0x0 0x2000
+ 0x100 0x0 0x 0 0xffc1 0x0 0x1;
+ reg = 0 0xffe09000 0 0x1000;
+ pcie@0 {
+ ranges = 0x200 0x0 0xa000
+ 0x200 0x0 0xa000
+ 0x0 0x2000
+
+ 0x100 0x0 0x0
+ 0x100 0x0 0x0
+ 0x0 0x10;
+ };
+ };
+
+ pci1: pcie@ffe0a000 {
+ reg = 0 0xffe0a000 0 0x1000;
+ ranges = 0x200 0x0 0x8000 0 0x8000 0x0 0x2000
+
